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  /external/swiftshader/third_party/LLVM/lib/Target/PTX/
PTXISelLowering.cpp 238 EVT RegVT = Ins[i].VT;
239 TargetRegisterClass* TRC = getRegClassFor(RegVT);
245 SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, RegVT, Chain,
299 EVT RegVT = Outs[i].VT;
303 if (RegVT == MVT::i1) {
306 else if (RegVT == MVT::i16) {
309 else if (RegVT == MVT::i32) {
312 else if (RegVT == MVT::i64) {
315 else if (RegVT == MVT::f32) {
318 else if (RegVT == MVT::f64)
    [all...]
  /external/llvm/lib/CodeGen/
CallingConvLower.cpp 241 for (MVT RegVT : RegParmTypes) {
243 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn);
245 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
248 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
  /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
MBlazeISelLowering.cpp 721 MVT RegVT = VA.getLocVT();
729 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
732 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
735 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp     [all...]
  /external/llvm/lib/Target/BPF/
BPFISelLowering.cpp 174 EVT RegVT = VA.getLocVT();
175 switch (RegVT.getSimpleVT().SimpleTy) {
178 << RegVT.getEVTString() << '\n';
184 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
  /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
BlackfinISelLowering.cpp 185 EVT RegVT = VA.getLocVT();
189 assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
193 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
199 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
202 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
  /external/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 444 EVT RegVT = VA.getLocVT();
445 switch (RegVT.getSimpleVT().SimpleTy) {
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
455 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
458 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
469 << RegVT.getEVTString() << "\n");
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 436 EVT RegVT = VA.getLocVT();
437 switch (RegVT.getSimpleVT().SimpleTy) {
442 << RegVT.getEVTString() << "\n";
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/MSP430/
MSP430ISelLowering.cpp 326 EVT RegVT = VA.getLocVT();
327 switch (RegVT.getSimpleVT().SimpleTy) {
332 << RegVT.getSimpleVT().SimpleTy << "\n";
340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
346 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
349 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
    [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.h 275 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
281 EVT RegVT;
SelectionDAGBuilder.cpp 577 EVT regvt, EVT valuevt)
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
    [all...]
LegalizeDAG.cpp 406 EVT RegVT =
411 unsigned RegBytes = RegVT.getSizeInBits() / 8;
415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
450 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
523 unsigned RegBytes = RegVT.getSizeInBits() / 8;
527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
554 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/Mips/
MipsISelLowering.cpp     [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp     [all...]
SelectionDAGBuilder.h 291 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
297 MVT RegVT;
    [all...]
SelectionDAGBuilder.cpp 618 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt,
620 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
    [all...]
LegalizeIntegerTypes.cpp     [all...]
  /external/llvm/lib/Target/XCore/
XCoreISelLowering.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/XCore/
XCoreISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/X86/
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMISelLowering.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMISelLowering.cpp     [all...]

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