1 /** @file 2 * 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #include "PcieInitLib.h" 17 #include <Library/DebugLib.h> 18 #include <Library/ArmLib.h> 19 #include <Library/BaseLib.h> 20 #include <Library/BaseMemoryLib.h> 21 #include <Library/IoLib.h> 22 #include <Library/TimerLib.h> 23 24 static PCIE_INIT_CFG mPcieIntCfg; 25 UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; 26 UINT64 pcie_serders_base[2][4] = {{0xB2080000,0xB2000000,0xB2100000,0xB2200000},{BASE_4TB + 0xB2080000,BASE_4TB + 0xB2000000,BASE_4TB + 0xB2100000,BASE_4TB + 0xB2200000}}; 27 UINT64 io_sub0_base = 0xa0000000; 28 UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000}; 29 #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000)) 30 UINT32 loop_test_flag[4] = {0,0,0,0}; 31 UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR; 32 #define PCIE_GEN1 0 /* PCIE 1.0 */ 33 #define PCIE_GEN2 1 /* PCIE 2.0 */ 34 #define PCIE_GEN3 2 /* PCIE 3.0 */ 35 #define DS_API(lane) ((0x1FF6c + 8*(15-lane))*2) 36 37 extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; 38 extern PCIE_IATU gastr_pcie_iatu_cfg; 39 extern PCIE_IATU_VA mPcieIatuTable; 40 41 VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value) 42 { 43 RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); 44 45 } 46 47 UINT32 PcieRegRead(UINT32 Port, UINTN Offset) 48 { 49 UINT32 Value = 0; 50 51 RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); 52 return Value; 53 } 54 55 VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value) 56 { 57 RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value); 58 } 59 60 UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1) 61 { 62 UINT32 Value = 0; 63 RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value); 64 return Value; 65 } 66 67 VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode) 68 { 69 u_sc_pcie0_clkreq pcie0; 70 u_sc_pcie1_clkreq pcie1; 71 u_sc_pcie2_clkreq pcie2; 72 u_sc_pcie3_clkreq pcie3; 73 74 switch(Port) 75 { 76 case 0: 77 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32); 78 pcie0.Bits.pcie0_apb_cfg_sel = Mode; 79 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32); 80 break; 81 case 1: 82 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32); 83 pcie1.Bits.pcie1_apb_cfg_sel = Mode; 84 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32); 85 break; 86 case 2: 87 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32); 88 pcie2.Bits.pcie2_apb_cfg_sel = Mode; 89 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32); 90 break; 91 case 3: 92 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32); 93 pcie3.Bits.pcie3_apb_cfg_sel = Mode; 94 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32); 95 break; 96 default: 97 break; 98 } 99 } 100 101 102 103 EFI_STATUS PcieEnableItssm(UINT32 HostBridgeNum, UINT32 Port) 104 { 105 PCIE_CTRL_7_U pcie_ctrl7; 106 107 if(Port >= PCIE_MAX_PORT_NUM) 108 { 109 return EFI_INVALID_PARAMETER; 110 } 111 112 if(mPcieIntCfg.PortIsInitilized[Port]) 113 { 114 return PCIE_ERR_ALREADY_INIT; 115 } 116 117 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 118 119 pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG); 120 pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1; 121 PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32); 122 123 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); 124 125 return EFI_SUCCESS; 126 } 127 128 EFI_STATUS PcieDisableItssm(UINT32 HostBridgeNum, UINT32 Port) 129 { 130 PCIE_CTRL_7_U pcie_ctrl7; 131 132 if(Port >= PCIE_MAX_PORT_NUM) 133 { 134 return PCIE_ERR_PARAM_INVALID; 135 } 136 137 138 if(mPcieIntCfg.PortIsInitilized[Port]) 139 { 140 return PCIE_ERR_ALREADY_INIT; 141 } 142 143 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 144 145 pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG); 146 pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0; 147 PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32); 148 149 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); 150 151 return EFI_SUCCESS; 152 } 153 154 155 EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed) 156 { 157 PCIE_EP_PCIE_CAP12_U pcie_cap12; 158 159 if(Port >= PCIE_MAX_PORT_NUM) 160 { 161 return EFI_INVALID_PARAMETER; 162 } 163 164 pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG); 165 pcie_cap12.Bits.targetlinkspeed = Speed; 166 PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32); 167 168 if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB || 169 mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP) 170 { 171 pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG); 172 pcie_cap12.Bits.targetlinkspeed = Speed; 173 PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32); 174 } 175 return EFI_SUCCESS; 176 } 177 178 EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width) 179 { 180 PCIE_EP_PORT_LOGIC4_U pcie_logic4; 181 PCIE_EP_PORT_LOGIC22_U logic22; 182 183 if(Port >= PCIE_MAX_PORT_NUM) 184 { 185 return PCIE_ERR_PARAM_INVALID; 186 } 187 188 pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG); 189 pcie_logic4.Bits.linkmodeenable = Width; 190 pcie_logic4.Bits.crosslinkenable = 0; 191 pcie_logic4.Bits.fastlinkmode = 1; 192 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32); 193 194 logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG); 195 logic22.Bits.n_fts = 0xff; 196 if(Width == PCIE_WITDH_X1) 197 { 198 logic22.Bits.pre_determ_num_of_lane = 1; 199 } 200 else if(Width == PCIE_WITDH_X2) 201 { 202 logic22.Bits.pre_determ_num_of_lane = 2; 203 } 204 else 205 { 206 logic22.Bits.pre_determ_num_of_lane = 3; 207 } 208 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32); 209 210 if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB || 211 mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP) 212 { 213 pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG); 214 pcie_logic4.Bits.linkmodeenable = Width; 215 pcie_logic4.Bits.crosslinkenable = 0; 216 pcie_logic4.Bits.fastlinkmode = 1; 217 PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32); 218 219 logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG); 220 logic22.Bits.n_fts = 0xff; 221 if(Width == PCIE_WITDH_X1) 222 { 223 logic22.Bits.pre_determ_num_of_lane = 1; 224 } 225 else if(Width == PCIE_WITDH_X2) 226 { 227 logic22.Bits.pre_determ_num_of_lane = 2; 228 } 229 else 230 { 231 logic22.Bits.pre_determ_num_of_lane = 3; 232 } 233 PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32); 234 } 235 return EFI_SUCCESS; 236 } 237 238 EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width) 239 { 240 PCIE_EP_PORT_LOGIC22_U logic22; 241 PCIE_EEP_PCI_CFG_HDR15_U hdr15; 242 UINT32 Value = 0; 243 if(Port >= PCIE_MAX_PORT_NUM) 244 { 245 return EFI_INVALID_PARAMETER; 246 } 247 248 Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG); 249 Value &= ~(0x3f<<16); 250 251 if(Width == PCIE_WITDH_X1) 252 { 253 Value |= (0x1 << 16); 254 } 255 else if(Width == PCIE_WITDH_X2) 256 { 257 Value |= (0x3 << 16); 258 } 259 else if(Width == PCIE_WITDH_X4) 260 { 261 Value |= (0x7 << 16); 262 } 263 else if(Width == PCIE_WITDH_X8) 264 { 265 Value |= (0xf << 16); 266 } 267 else 268 { 269 DEBUG((EFI_D_ERROR,"Width is not invalid\n")); 270 } 271 272 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value); 273 274 logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG); 275 logic22.UInt32 &= ~(0x1f<<8); 276 277 if(Width == PCIE_WITDH_X1) 278 { 279 logic22.Bits.pre_determ_num_of_lane = 1; 280 } 281 else if(Width == PCIE_WITDH_X2) 282 { 283 logic22.Bits.pre_determ_num_of_lane = 2; 284 } 285 else if(Width == PCIE_WITDH_X4) 286 { 287 logic22.Bits.pre_determ_num_of_lane = 4; 288 } 289 else if(Width == PCIE_WITDH_X8) 290 { 291 logic22.Bits.pre_determ_num_of_lane = 8; 292 } 293 else 294 { 295 DEBUG((EFI_D_ERROR,"Width is not invalid\n")); 296 } 297 298 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32); 299 300 /* setup RC BARs */ 301 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004); 302 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000); 303 304 /* setup interrupt pins */ 305 hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG); 306 hdr15.UInt32 &= 0xffff00ff; 307 hdr15.UInt32 |= 0x00000100; 308 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32); 309 310 /* setup bus numbers */ 311 Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG); 312 Value &= 0xff000000; 313 Value |= 0x00010100; 314 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value); 315 316 /* setup command register */ 317 Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG); 318 Value &= 0xffff0000; 319 Value |= 0x1|0x2|0x4|0x100; 320 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value); 321 322 return EFI_SUCCESS; 323 } 324 325 326 EFI_STATUS PcieModeSet(UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType) 327 { 328 PCIE_CTRL_0_U str_pcie_ctrl_0; 329 330 if(Port >= PCIE_MAX_PORT_NUM) 331 { 332 return EFI_INVALID_PARAMETER; 333 } 334 335 if(mPcieIntCfg.PortIsInitilized[Port]) 336 { 337 return PCIE_ERR_ALREADY_INIT; 338 } 339 340 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 341 342 str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG); 343 if(PcieType == PCIE_END_POINT) 344 { 345 str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE; 346 } 347 else 348 { 349 str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC; 350 } 351 PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32); 352 353 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); 354 355 return EFI_SUCCESS; 356 } 357 358 VOID PciePcsInit(UINT32 HostBridgeNum, UINT32 Port) 359 { 360 361 if(Port<=2) 362 { 363 RegWrite(pcie_serders_base[HostBridgeNum][Port] + 0xc088, 0x212); 364 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044); 365 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044); 366 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044); 367 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044); 368 369 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018); 370 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018); 371 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100); 372 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3); 373 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0); 374 } 375 else 376 377 { 378 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000); 379 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000); 380 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000); 381 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000); 382 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000); 383 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000); 384 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000); 385 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000); 386 387 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001); 388 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001); 389 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001); 390 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001); 391 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001); 392 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001); 393 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001); 394 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001); 395 396 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff); 397 } 398 399 } 400 401 VOID PcieEqualization(UINT32 Port) 402 { 403 UINT32 Value; 404 405 PcieRegWrite(Port, 0x890, 0x1400); 406 PcieRegWrite(Port, 0x894, 0xfd7); 407 408 PcieRegWrite(Port, 0x89c, 0x0); 409 PcieRegWrite(Port, 0x898, 0xfc00); 410 PcieRegWrite(Port, 0x89c, 0x1); 411 PcieRegWrite(Port, 0x898, 0xbd00); 412 PcieRegWrite(Port, 0x89c, 0x2); 413 PcieRegWrite(Port, 0x898, 0xccc0); 414 PcieRegWrite(Port, 0x89c, 0x3); 415 PcieRegWrite(Port, 0x898, 0x8dc0); 416 PcieRegWrite(Port, 0x89c, 0x4); 417 PcieRegWrite(Port, 0x898, 0xfc0); 418 PcieRegWrite(Port, 0x89c, 0x5); 419 PcieRegWrite(Port, 0x898, 0xe46); 420 PcieRegWrite(Port, 0x89c, 0x6); 421 PcieRegWrite(Port, 0x898, 0xdc8); 422 PcieRegWrite(Port, 0x89c, 0x7); 423 PcieRegWrite(Port, 0x898, 0xcb46); 424 PcieRegWrite(Port, 0x89c, 0x8); 425 PcieRegWrite(Port, 0x898, 0x8c07); 426 PcieRegWrite(Port, 0x89c, 0x9); 427 PcieRegWrite(Port, 0x898, 0xd0b); 428 PcieRegWrite(Port, 0x8a8, 0x103ff21); 429 430 Value = PcieRegRead(Port, 0x80); 431 Value |= 0x80; 432 PcieRegWrite(Port, 0x80, Value); 433 434 PcieRegWrite(Port, 0x184, 0x44444444); 435 PcieRegWrite(Port, 0x188, 0x44444444); 436 PcieRegWrite(Port, 0x18c, 0x44444444); 437 PcieRegWrite(Port, 0x190, 0x44444444); 438 439 } 440 441 442 EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port) 443 { 444 if(Port >= PCIE_MAX_PORT_NUM) 445 { 446 return EFI_INVALID_PARAMETER; 447 } 448 449 if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port]) 450 { 451 (VOID)PcieDisableItssm(HostBridgeNum, Port); 452 } 453 454 mPcieIntCfg.PortIsInitilized[Port] = FALSE; 455 mPcieIntCfg.DmaResource[Port] = (VOID *)NULL; 456 mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; 457 mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; 458 ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U)); 459 460 if(Port <= 2) 461 { 462 RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1); 463 MicroSecondDelay(0x1000); 464 465 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1); 466 MicroSecondDelay(0x1000); 467 } 468 else 469 { 470 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1); 471 MicroSecondDelay(0x1000); 472 473 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1); 474 MicroSecondDelay(0x1000); 475 } 476 return EFI_SUCCESS; 477 } 478 479 EFI_STATUS AssertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port) 480 { 481 if(Port >= PCIE_MAX_PORT_NUM) 482 { 483 return EFI_INVALID_PARAMETER; 484 } 485 486 if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port]) 487 { 488 (VOID)PcieDisableItssm(HostBridgeNum, Port); 489 } 490 491 mPcieIntCfg.PortIsInitilized[Port] = FALSE; 492 mPcieIntCfg.DmaResource[Port] = (VOID *)NULL; 493 mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; 494 mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; 495 ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U)); 496 497 if(Port <= 2) 498 { 499 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1); 500 MicroSecondDelay(0x1000); 501 } 502 else 503 { 504 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1); 505 MicroSecondDelay(0x1000); 506 } 507 return EFI_SUCCESS; 508 } 509 510 EFI_STATUS DeassertPcieCoreReset(UINT32 HostBridgeNum, UINT32 Port) 511 { 512 if(Port >= PCIE_MAX_PORT_NUM) 513 { 514 return EFI_INVALID_PARAMETER; 515 } 516 517 if(PcieIsLinkUp(HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port]) 518 { 519 (VOID)PcieDisableItssm(HostBridgeNum, Port); 520 } 521 522 mPcieIntCfg.PortIsInitilized[Port] = FALSE; 523 mPcieIntCfg.DmaResource[Port] = (VOID *)NULL; 524 mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0; 525 mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0; 526 ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U)); 527 528 if(Port <= 2) 529 { 530 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1); 531 MicroSecondDelay(0x1000); 532 } 533 else 534 { 535 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1); 536 MicroSecondDelay(0x1000); 537 } 538 return EFI_SUCCESS; 539 } 540 541 EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) 542 { 543 u_sc_pcie_hilink_pcs_reset_req reset_req; 544 UINT32 pcs_local_reset_status; 545 UINT32 pcs_local_status_checked; 546 UINT32 hilink_reset_status; 547 UINT32 hilink_status_checked; 548 UINT32 count = 0; 549 550 reset_req.UInt32 = 0; 551 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port); 552 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32); 553 554 reset_req.UInt32 = 0; 555 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port)); 556 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32); 557 MicroSecondDelay(0x1000); 558 559 /* read reset status, make sure pcs is reset */ 560 do { 561 MicroSecondDelay(1000); 562 count ++; 563 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_reset_status); 564 pcs_local_status_checked = 565 ((pcs_local_reset_status & (1 << Port)) != 566 (1 << Port)); 567 568 } while ((pcs_local_status_checked) && (count < 1000)); 569 570 if (pcs_local_status_checked) 571 DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n")); 572 573 count = 0; 574 do { 575 MicroSecondDelay(1000); 576 count ++; 577 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status); 578 hilink_status_checked = 579 ((hilink_reset_status & (0xff << (Port << 3))) != 580 (0xff << (Port << 3))); 581 } while ((hilink_status_checked) && (count < 1000)); 582 583 if (hilink_status_checked) 584 DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n")); 585 586 return EFI_SUCCESS; 587 } 588 589 EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) 590 { 591 u_sc_pcie_hilink_pcs_reset_req reset_req; 592 UINT32 pcs_local_status; 593 UINT32 pcs_local_status_checked; 594 UINT32 hilink_reset_status; 595 UINT32 hilink_status_checked; 596 UINT32 count = 0; 597 598 599 reset_req.UInt32 = 0; 600 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port); 601 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32); 602 603 reset_req.UInt32 = 0; 604 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port)); 605 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32); 606 607 /* read reset status, make sure pcs is deassert */ 608 do { 609 MicroSecondDelay(1000); 610 count ++; 611 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_ST_REG, pcs_local_status); 612 pcs_local_status_checked = (pcs_local_status & (1 << Port)); 613 } while ((pcs_local_status_checked) && (count < 1000)); 614 615 /* get a timeout error */ 616 if (pcs_local_status_checked) 617 DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); 618 619 count = 0; 620 do { 621 MicroSecondDelay(1000); 622 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status); 623 hilink_status_checked = (hilink_reset_status & 624 (0xff << (Port << 3))); 625 } while ((hilink_status_checked) && (count < 1000)); 626 627 if (hilink_status_checked) 628 DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); 629 630 return EFI_SUCCESS; 631 } 632 633 VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port) 634 { 635 UINT32 val; 636 UINT32 current_speed; 637 UINT32 ltssm_state; 638 UINT32 timeout = 0; 639 UINT32 eq = 0; 640 UINT32 loop = 100000; 641 U_SC_PCIE0_SYS_STATE4 PcieStat; 642 643 while (loop) 644 { 645 MicroSecondDelay(10); 646 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32); 647 val = PcieStat.UInt32; 648 current_speed = (val >> 6) & 0x3; 649 if (current_speed == PCIE_GEN3) 650 break; 651 loop--; 652 } 653 if (!loop) { 654 DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1)); 655 return; 656 } 657 658 ltssm_state = val & PCIE_LTSSM_STATE_MASK; 659 while ((current_speed == PCIE_GEN3) && 660 (ltssm_state != PCIE_LTSSM_LINKUP_STATE) && (timeout < 200)) { 661 if ((ltssm_state & 0x30) == 0x20) 662 eq = 1; 663 664 if ((ltssm_state == 0xd) && (eq == 1)) 665 { 666 MicroSecondDelay(5000); 667 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32); 668 val = PcieStat.UInt32; 669 ltssm_state = val & PCIE_LTSSM_STATE_MASK; 670 current_speed = (val >> 6) & 0x3; 671 if (ltssm_state == 0xd) 672 { 673 DEBUG((EFI_D_ERROR, "Do symbol align reset rate %d ltssm 0x%x\n",current_speed, ltssm_state)); 674 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x8000000); 675 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x8000000); 676 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x8000000); 677 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x8000000); 678 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x8000000); 679 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x8000000); 680 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x8000000); 681 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x8000000); 682 683 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0); 684 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0); 685 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0); 686 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0); 687 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0); 688 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0); 689 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0); 690 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0); 691 } 692 break; 693 } 694 695 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32); 696 val = PcieStat.UInt32; 697 ltssm_state = val & PCIE_LTSSM_STATE_MASK; 698 current_speed = (val >> 6) & 0x3; 699 700 MicroSecondDelay(1000); 701 timeout++; 702 } 703 704 if (timeout >= 200) { 705 DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1)); 706 return; 707 } 708 DEBUG((EFI_D_ERROR, "current_speed GEN%d\n",current_speed + 1)); 709 } 710 711 VOID Gen3DfeEnable(UINT32 HostBridgeNum, UINT32 Port) 712 { 713 UINT32 val; 714 UINT32 lane; 715 UINT32 current_speed; 716 U_SC_PCIE0_SYS_STATE4 PcieStat; 717 718 if (Port == 3) 719 return; 720 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32); 721 val = PcieStat.UInt32; 722 current_speed = (val >> 6) & 0x3; 723 if (current_speed != PCIE_GEN3) 724 return; 725 for (lane = 0; lane < 8; lane++) 726 RegWrite(pcie_serders_base[HostBridgeNum][Port] + (UINT32)DS_API(lane) + 4, 0x3851); 727 728 DEBUG((EFI_D_ERROR, "enable DFE success\n")); 729 } 730 731 EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock) 732 { 733 UINT32 reg_clock_disable; 734 UINT32 reg_clock_enable; 735 UINT32 reg_clock_status; 736 UINT32 clock_status; 737 UINT32 clock_status_checked; 738 UINT32 clock_ctrl; 739 UINT32 count = 0; 740 741 if (Port == 3) { 742 reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG; 743 reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG; 744 reg_clock_status = PCIE_SUBCTRL_SC_PCIE3_CLK_ST_REG; 745 } else { 746 reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(Port); 747 reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(Port); 748 reg_clock_status = PCIE_SUBCTRL_SC_PCIE0_2_CLK_ST_REG(Port); 749 } 750 751 if (0x1610 == soctype) 752 { 753 clock_ctrl = 0x7; 754 } 755 else 756 { 757 clock_ctrl = 0x3; 758 if (Clock) 759 RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, clock_ctrl); 760 else 761 RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, clock_ctrl); 762 } 763 764 do { 765 count ++; 766 MicroSecondDelay(1000); 767 RegRead(pcie_subctrl_base[HostBridgeNum] + reg_clock_status, clock_status); 768 if (Clock) 769 clock_status_checked = 770 ((clock_status & clock_ctrl) != clock_ctrl); 771 else 772 clock_status_checked = 773 ((clock_status & clock_ctrl) != 0); 774 } while ((clock_status_checked) && (count < 1000)); //1S 775 776 /* get a timeout error */ 777 if (clock_status_checked) 778 DEBUG((EFI_D_ERROR, "clock operation failed!\n")); 779 780 return EFI_SUCCESS; 781 } 782 783 VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) 784 { 785 UINT32 Value = 0; 786 787 if (0x1610 == soctype) 788 { 789 } 790 else 791 { 792 RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value); 793 Value &= ~(0xf); 794 Value |= Spd; 795 RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0xa0, Value); 796 return; 797 } 798 return; 799 } 800 801 VOID PcieSpdControl(UINT32 HostBridgeNum, UINT32 Port) 802 { 803 UINT32 Value = 0;; 804 805 /* set link width speed control register */ 806 RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value); 807 /* 808 * set the Directed Speed Change field of the Link Width and Speed 809 * Change Control register 810 */ 811 Value |= (1 << 17); 812 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x80c, Value); 813 } 814 815 VOID PcieSetDb2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 enable) 816 { 817 UINT32 dbi_ctrl; 818 819 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 820 821 RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl); 822 if (enable) 823 dbi_ctrl |= BIT0; 824 else 825 dbi_ctrl &= ~BIT0; 826 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, dbi_ctrl); 827 828 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); 829 } 830 831 VOID PcieDisabledBar0(UINT32 HostBridgeNum, UINT32 Port) 832 { 833 PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_ENABLE); 834 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + 0x10,0); 835 PcieSetDb2Enable(HostBridgeNum, Port, PCIE_DBI_CS2_DISABLE); 836 } 837 838 /* Configure vmid/asid table in PCIe host */ 839 VOID PcieConfigContextP660(UINT32 HostBridgeNum, UINT32 Port) 840 { 841 UINT32 i = 0; 842 UINTN val = 0;; 843 844 /* 845 * enable to clean vmid and asid tables though apb bus 846 * */ 847 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 848 RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val); 849 /* enable ar channel */ 850 val |= PCIE_RD_TAB_SEL | PCIE_RD_TAB_EN; 851 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val); 852 853 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE); 854 for (i = 0; i < 0x800; i++) 855 PcieRegWrite(Port, i * 4, 0); 856 857 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 858 /* enable aw channel */ 859 val &= (~PCIE_RD_TAB_SEL); 860 val |= PCIE_RD_TAB_EN; 861 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val); 862 863 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SLV_CONTENT_MODE); 864 865 /* 866 * init vmid and asid tables for all PCIe devices as 0 867 * vmid table: 0 ~ 0x3ff, asid table: 0x400 ~ 0x7ff 868 */ 869 for (i = 0; i < 0x800; i++) 870 PcieRegWrite(Port, i * 4, 0); 871 872 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 873 874 RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val); 875 /* disable ar channel */ 876 val |= PCIE_RD_TAB_SEL; 877 val &= (~PCIE_RD_TAB_EN); 878 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val); 879 /* disable aw channel */ 880 val &= ((~PCIE_RD_TAB_SEL) & (~PCIE_RD_TAB_EN)); 881 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL20_REG, val); 882 883 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL24_REG, 0xb7010040 & 0xffffffff); 884 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL28_REG, 0); 885 886 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL16_REG, (1<<12)|(1<<16)); 887 RegWrite( PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(Port * 0x10000) + PCIE_SYS_CTRL29_REG, (1<<12)); 888 889 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);; 890 } 891 892 EFI_STATUS PcieMaskLinkUpInit(UINT32 HostBridgeNum, UINT32 Port) 893 { 894 UINT32 Value = 0; 895 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 896 Value = PcieRegRead(Port, 0x1d0); 897 Value |= 1 << 12; 898 PcieRegWrite(Port,0x1d0, Value); 899 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); 900 return EFI_SUCCESS; 901 } 902 903 BOOLEAN PcieIsLinkUp(UINT32 HostBridgeNum, UINT32 Port) 904 { 905 UINT32 Value = 0; 906 U_SC_PCIE0_SYS_STATE4 PcieStat; 907 908 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32); 909 Value = PcieStat.UInt32; 910 if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE) 911 return TRUE; 912 913 return FALSE; 914 } 915 916 VOID PcieWriteOwnConfig(UINT32 Port, UINT32 Offset) 917 { 918 UINT32 Value = 0; 919 Value = PcieRegRead(Port,Offset & (~0x3)); 920 Value &= 0x0000ffff; 921 Value |= 0x06040000; 922 PcieRegWrite(Port, Offset & (~0x3), Value); 923 return; 924 } 925 926 EFI_STATUS 927 EFIAPI 928 PciePortInit ( 929 IN UINT32 HostBridgeNum, 930 IN PCIE_DRIVER_CFG *PcieCfg 931 ) 932 { 933 UINT32 Count = 0; 934 UINT32 PortIndex = PcieCfg->PortIndex; 935 UINT32 Value = 0; 936 937 938 if(PortIndex >= PCIE_MAX_PORT_NUM) 939 { 940 return EFI_INVALID_PARAMETER; 941 } 942 943 if(mPcieIntCfg.PortIsInitilized[PortIndex]) 944 { 945 return PCIE_ERR_ALREADY_INIT; 946 } 947 948 mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex); 949 950 /* assert reset signals */ 951 (VOID)AssertPcieCoreReset(HostBridgeNum, PortIndex); 952 (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 0); 953 (VOID)AssertPciePcsReset(HostBridgeNum, PortIndex); 954 955 /* de-assert phy reset */ 956 (VOID)DeassertPciePcsReset(HostBridgeNum, PortIndex); 957 958 /* de-assert core reset */ 959 (VOID)DeassertPcieCoreReset(HostBridgeNum, PortIndex); 960 (VOID)HisiPcieClockCtrl(0x660, HostBridgeNum, PortIndex, 1); 961 962 do { 963 RegRead(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(PortIndex * 0x10000) + 0x8108, Value); 964 if (Count == 10) { 965 DEBUG((EFI_D_ERROR, "PCIe Failed! PLL Locked: 0x%x\n\n",Value)); 966 return EFI_NOT_READY; 967 } 968 Count++; 969 MicroSecondDelay(100000); 970 } while ((Value & 0x3) == 0); 971 Count = 0; 972 973 /* initialize phy */ 974 (VOID)PciePcsInit(HostBridgeNum, PortIndex); 975 976 (VOID)PcieModeSet(HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType); 977 (VOID)PcieSpdSet(0x660, HostBridgeNum, PortIndex, 3); 978 (VOID)PcieSpdControl(HostBridgeNum, PortIndex); 979 /* setup root complex */ 980 (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth); 981 982 /* Pcie Equalization*/ 983 (VOID)PcieEqualization(PortIndex); 984 985 /* assert LTSSM enable */ 986 (VOID)PcieEnableItssm(HostBridgeNum, PortIndex); 987 988 /* 989 * This is a PCS hardware bug, we fix it by resetting 990 * PCS symalign module state machine 991 */ 992 (VOID)PcieGen3Config(HostBridgeNum, PortIndex); 993 PcieConfigContextP660(HostBridgeNum, PortIndex); 994 (VOID)PcieDisabledBar0(HostBridgeNum, PortIndex); 995 (VOID)PcieWriteOwnConfig(PortIndex, 0xa); 996 /* check if the link is up or not */ 997 while (!PcieIsLinkUp(HostBridgeNum, PortIndex)) { 998 MicroSecondDelay(1000); 999 Count++; 1000 if (Count >= 1000) { 1001 DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex)); 1002 return PCIE_ERR_LINK_OVER_TIME; 1003 } 1004 } 1005 DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex)); 1006 1007 /* dfe enable is just for 660 */ 1008 (VOID)Gen3DfeEnable(HostBridgeNum, PortIndex); 1009 1010 1011 PcieRegWrite(PortIndex, 0x80c, 0x208FF); 1012 1013 return EFI_SUCCESS; 1014 } 1015 1016 1017 1018 1019 EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable) 1020 { 1021 PCIE_SYS_CTRL20_U dbi_ro_enable; 1022 1023 if(Port >= PCIE_MAX_PORT_NUM) 1024 { 1025 return EFI_INVALID_PARAMETER; 1026 } 1027 1028 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL); 1029 dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG); 1030 dbi_ro_enable.Bits.ro_sel = Enable; 1031 PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32); 1032 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG); 1033 1034 return EFI_SUCCESS; 1035 1036 } 1037 1038 VOID PcieDelay(UINT32 dCount) 1039 { 1040 volatile UINT32 *uwCnt = &dCount; 1041 1042 while(*uwCnt > 0) 1043 { 1044 *uwCnt = *uwCnt - 1; 1045 } 1046 1047 } 1048 1049
