| /external/mesa3d/src/mesa/drivers/dri/common/xmlpool/ |
| de.po | 282 msgid "Only GART (AGP/PCIE) memory (if available)"
283 msgstr "Nur GART-Speicher (AGP/PCIE) (falls verfügbar)"
|
| es.po | 291 msgid "Only GART (AGP/PCIE) memory (if available)"
292 msgstr "Solo memoria GART (AGP/PCIE) (si está disponible)"
|
| fr.po | 278 msgid "Only GART (AGP/PCIE) memory (if available)"
279 msgstr "Utiliser uniquement la mémoire GART (AGP/PCIE) (si disponible)"
|
| nl.po | 279 msgid "Only GART (AGP/PCIE) memory (if available)"
280 msgstr "Alleen GART (AGP/PCIE) geheugen (als het aanwezig is)"
|
| sv.po | 271 msgid "Only GART (AGP/PCIE) memory (if available)"
272 msgstr "Endast GART-minne (AGP/PCIE) (om tillgängligt)"
|
| ca.po | 307 msgid "Only GART (AGP/PCIE) memory (if available)"
308 msgstr "Només memňria GART (AGP/PCIE) (si estŕ disponible)"
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Library/ |
| PlatformPciLib.h | 21 //The extern pcie addresses will be initialized by oemmisclib
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/ |
| Madt.aslc | 122 EFI_ACPI_6_0_GIC_ITS_INIT(3,0xB7000000) // pcie
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/ |
| Dsdt.asl | 502 // PCIe Root Bus
708 // Function 1: Return PCIe Slot Information
714 0x1, // x1 PCIe link
722 // Function 2: Return PCIe Slot Number.
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/ |
| SocConfiguration.h | 82 INT32 PcieEnabled; ///< Indicates PCIe enabled state. Zero if disabled; otherwise, enabled.
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/ |
| EarlyConfigPeimD03.c | 150 DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/ |
| PciHostBridge.h | 2 * Header containing the structure specific to the Xpress-RICH3 PCIe Root Complex
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Guid/ |
| Cper.h | [all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| mrc.h | 114 uint32_t uart_mmio_base; // pcie serial port base address (force 0 to disable debug)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PciPlatform/ |
| PciPlatform.c | 260 // WA for PCIe SATA card (SYBA SY-PEX400-40)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| ClockControl.c | 110 {SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH GPIO38:
|
| /external/autotest/client/common_lib/cros/network/ |
| interface.py | 30 NAME_MARVELL_88W8897_PCIE = 'Marvell 88W8897 PCIE'
31 NAME_MARVELL_88W8997_PCIE = 'Marvell 88W8997 PCIE'
42 NAME_BROADCOM_BCM4356_PCIE = 'Broadcom BCM4356 PCIE'
43 NAME_BROADCOM_BCM4371_PCIE = 'Broadcom BCM4371 PCIE'
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/ |
| PciHostBridge.c | 499 //Each Host Bridge have 8 Root Bridges max, every bits of 0xFF(8 bit) stands for the according PCIe Port
575 DEBUG((EFI_D_ERROR,"PCIE AddMemorySpace Error\n"));
[all...] |
| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/ |
| UefiShellDebug1CommandsLib.uni | 150 #string STR_MM_PCIE_ADDRESS_RANGE #language en-US "%H%s%N: Address parameter %016LX is not a valid PCI/PCIE address.\r\n"
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/ |
| styx-overdrive1000.dts | 267 pcie: pcie@f0000000 {
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/ |
| styx-overdrive.dts | 267 pcie: pcie@f0000000 {
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/ |
| IntelQNCLib.c | 176 EventDescStr = "PCIe WAKE";
180 EventDescStr = "PCIe";
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| I2cRegs.h | 2 Include file for I2C DXE Driver register definitions (PCIe config. space and memory space).
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 197 #define B_BOARD_FEATURES_NO_MINIPCIE BIT49 // Mini PCIe slot
|
| /external/autotest/client/cros/ |
| memory_bandwidth_logger.py | 19 IMC_DRAM_IO_REQUESTS = 0x5048 # PCIe, Display Engine, USB, etc.
|
