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      1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 /// \file
     10 /// This file a TargetTransformInfo::Concept conforming object specific to the
     11 /// ARM target machine. It uses the target's detailed information to
     12 /// provide more precise answers to certain TTI queries, while letting the
     13 /// target independent and default TTI implementations handle the rest.
     14 ///
     15 //===----------------------------------------------------------------------===//
     16 
     17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
     18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
     19 
     20 #include "ARM.h"
     21 #include "ARMTargetMachine.h"
     22 #include "llvm/Analysis/TargetTransformInfo.h"
     23 #include "llvm/CodeGen/BasicTTIImpl.h"
     24 #include "llvm/Target/TargetLowering.h"
     25 
     26 namespace llvm {
     27 
     28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
     29   typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
     30   typedef TargetTransformInfo TTI;
     31   friend BaseT;
     32 
     33   const ARMSubtarget *ST;
     34   const ARMTargetLowering *TLI;
     35 
     36   /// Estimate the overhead of scalarizing an instruction. Insert and Extract
     37   /// are set if the result needs to be inserted and/or extracted from vectors.
     38   unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
     39 
     40   const ARMSubtarget *getST() const { return ST; }
     41   const ARMTargetLowering *getTLI() const { return TLI; }
     42 
     43 public:
     44   explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
     45       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
     46         TLI(ST->getTargetLowering()) {}
     47 
     48   // Provide value semantics. MSVC requires that we spell all of these out.
     49   ARMTTIImpl(const ARMTTIImpl &Arg)
     50       : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
     51   ARMTTIImpl(ARMTTIImpl &&Arg)
     52       : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
     53         TLI(std::move(Arg.TLI)) {}
     54 
     55   bool enableInterleavedAccessVectorization() { return true; }
     56 
     57   /// Floating-point computation using ARMv8 AArch32 Advanced
     58   /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
     59   /// is IEEE-754 compliant, but it's not covered in this target.
     60   bool isFPVectorizationPotentiallyUnsafe() {
     61     return !ST->isTargetDarwin();
     62   }
     63 
     64   /// \name Scalar TTI Implementations
     65   /// @{
     66 
     67   int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
     68                             Type *Ty);
     69 
     70   using BaseT::getIntImmCost;
     71   int getIntImmCost(const APInt &Imm, Type *Ty);
     72 
     73   int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
     74 
     75   /// @}
     76 
     77   /// \name Vector TTI Implementations
     78   /// @{
     79 
     80   unsigned getNumberOfRegisters(bool Vector) {
     81     if (Vector) {
     82       if (ST->hasNEON())
     83         return 16;
     84       return 0;
     85     }
     86 
     87     if (ST->isThumb1Only())
     88       return 8;
     89     return 13;
     90   }
     91 
     92   unsigned getRegisterBitWidth(bool Vector) {
     93     if (Vector) {
     94       if (ST->hasNEON())
     95         return 128;
     96       return 0;
     97     }
     98 
     99     return 32;
    100   }
    101 
    102   unsigned getMaxInterleaveFactor(unsigned VF) {
    103     return ST->getMaxInterleaveFactor();
    104   }
    105 
    106   int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
    107 
    108   int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
    109 
    110   int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
    111 
    112   int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
    113 
    114   int getAddressComputationCost(Type *Val, bool IsComplex);
    115 
    116   int getFPOpCost(Type *Ty);
    117 
    118   int getArithmeticInstrCost(
    119       unsigned Opcode, Type *Ty,
    120       TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
    121       TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
    122       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
    123       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
    124 
    125   int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
    126                       unsigned AddressSpace);
    127 
    128   int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
    129                                  ArrayRef<unsigned> Indices, unsigned Alignment,
    130                                  unsigned AddressSpace);
    131   /// @}
    132 };
    133 
    134 } // end namespace llvm
    135 
    136 #endif
    137