1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb1 implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1FrameLowering.h" 15 #include "ARMMachineFunctionInfo.h" 16 #include "llvm/CodeGen/LivePhysRegs.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineModuleInfo.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 23 using namespace llvm; 24 25 Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti) 26 : ARMFrameLowering(sti) {} 27 28 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{ 29 const MachineFrameInfo *FFI = MF.getFrameInfo(); 30 unsigned CFSize = FFI->getMaxCallFrameSize(); 31 // It's not always a good idea to include the call frame as part of the 32 // stack frame. ARM (especially Thumb) has small immediate offset to 33 // address the stack frame. So a large call frame can cause poor codegen 34 // and may even makes it impossible to scavenge a register. 35 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 36 return false; 37 38 return !MF.getFrameInfo()->hasVarSizedObjects(); 39 } 40 41 static void emitSPUpdate(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator &MBBI, 43 const TargetInstrInfo &TII, const DebugLoc &dl, 44 const ThumbRegisterInfo &MRI, int NumBytes, 45 unsigned MIFlags = MachineInstr::NoFlags) { 46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 47 MRI, MIFlags); 48 } 49 50 51 MachineBasicBlock::iterator Thumb1FrameLowering:: 52 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 53 MachineBasicBlock::iterator I) const { 54 const Thumb1InstrInfo &TII = 55 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo()); 56 const ThumbRegisterInfo *RegInfo = 57 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo()); 58 if (!hasReservedCallFrame(MF)) { 59 // If we have alloca, convert as follows: 60 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 61 // ADJCALLSTACKUP -> add, sp, sp, amount 62 MachineInstr &Old = *I; 63 DebugLoc dl = Old.getDebugLoc(); 64 unsigned Amount = Old.getOperand(0).getImm(); 65 if (Amount != 0) { 66 // We need to keep the stack aligned properly. To do this, we round the 67 // amount of space needed for the outgoing arguments up to the next 68 // alignment boundary. 69 unsigned Align = getStackAlignment(); 70 Amount = (Amount+Align-1)/Align*Align; 71 72 // Replace the pseudo instruction with a new instruction... 73 unsigned Opc = Old.getOpcode(); 74 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); 76 } else { 77 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); 79 } 80 } 81 } 82 return MBB.erase(I); 83 } 84 85 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, 86 MachineBasicBlock &MBB) const { 87 MachineBasicBlock::iterator MBBI = MBB.begin(); 88 MachineFrameInfo *MFI = MF.getFrameInfo(); 89 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 90 MachineModuleInfo &MMI = MF.getMMI(); 91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 92 const ThumbRegisterInfo *RegInfo = 93 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo()); 94 const Thumb1InstrInfo &TII = 95 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo()); 96 97 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 98 unsigned NumBytes = MFI->getStackSize(); 99 assert(NumBytes >= ArgRegsSaveSize && 100 "ArgRegsSaveSize is included in NumBytes"); 101 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 102 103 // Debug location must be unknown since the first debug location is used 104 // to determine the end of the prologue. 105 DebugLoc dl; 106 107 unsigned FramePtr = RegInfo->getFrameRegister(MF); 108 unsigned BasePtr = RegInfo->getBaseRegister(); 109 int CFAOffset = 0; 110 111 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 112 NumBytes = (NumBytes + 3) & ~3; 113 MFI->setStackSize(NumBytes); 114 115 // Determine the sizes of each callee-save spill areas and record which frame 116 // belongs to which callee-save spill areas. 117 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 118 int FramePtrSpillFI = 0; 119 120 if (ArgRegsSaveSize) { 121 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, 122 MachineInstr::FrameSetup); 123 CFAOffset -= ArgRegsSaveSize; 124 unsigned CFIIndex = MMI.addFrameInst( 125 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 126 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 127 .addCFIIndex(CFIIndex) 128 .setMIFlags(MachineInstr::FrameSetup); 129 } 130 131 if (!AFI->hasStackFrame()) { 132 if (NumBytes - ArgRegsSaveSize != 0) { 133 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), 134 MachineInstr::FrameSetup); 135 CFAOffset -= NumBytes - ArgRegsSaveSize; 136 unsigned CFIIndex = MMI.addFrameInst( 137 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 138 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 139 .addCFIIndex(CFIIndex) 140 .setMIFlags(MachineInstr::FrameSetup); 141 } 142 return; 143 } 144 145 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 146 unsigned Reg = CSI[i].getReg(); 147 int FI = CSI[i].getFrameIdx(); 148 switch (Reg) { 149 case ARM::R8: 150 case ARM::R9: 151 case ARM::R10: 152 case ARM::R11: 153 if (STI.splitFramePushPop()) { 154 GPRCS2Size += 4; 155 break; 156 } 157 // fallthrough 158 case ARM::R4: 159 case ARM::R5: 160 case ARM::R6: 161 case ARM::R7: 162 case ARM::LR: 163 if (Reg == FramePtr) 164 FramePtrSpillFI = FI; 165 GPRCS1Size += 4; 166 break; 167 default: 168 DPRCSSize += 8; 169 } 170 } 171 172 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 173 ++MBBI; 174 } 175 176 // Determine starting offsets of spill areas. 177 unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize); 178 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 179 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 180 bool HasFP = hasFP(MF); 181 if (HasFP) 182 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 183 NumBytes); 184 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 185 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 186 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 187 NumBytes = DPRCSOffset; 188 189 int FramePtrOffsetInBlock = 0; 190 unsigned adjustedGPRCS1Size = GPRCS1Size; 191 if (tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) { 192 FramePtrOffsetInBlock = NumBytes; 193 adjustedGPRCS1Size += NumBytes; 194 NumBytes = 0; 195 } 196 197 if (adjustedGPRCS1Size) { 198 CFAOffset -= adjustedGPRCS1Size; 199 unsigned CFIIndex = MMI.addFrameInst( 200 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 201 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 202 .addCFIIndex(CFIIndex) 203 .setMIFlags(MachineInstr::FrameSetup); 204 } 205 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), 206 E = CSI.end(); I != E; ++I) { 207 unsigned Reg = I->getReg(); 208 int FI = I->getFrameIdx(); 209 switch (Reg) { 210 case ARM::R8: 211 case ARM::R9: 212 case ARM::R10: 213 case ARM::R11: 214 case ARM::R12: 215 if (STI.splitFramePushPop()) 216 break; 217 // fallthough 218 case ARM::R0: 219 case ARM::R1: 220 case ARM::R2: 221 case ARM::R3: 222 case ARM::R4: 223 case ARM::R5: 224 case ARM::R6: 225 case ARM::R7: 226 case ARM::LR: 227 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 228 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 229 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 230 .addCFIIndex(CFIIndex) 231 .setMIFlags(MachineInstr::FrameSetup); 232 break; 233 } 234 } 235 236 // Adjust FP so it point to the stack slot that contains the previous FP. 237 if (HasFP) { 238 FramePtrOffsetInBlock += 239 MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize; 240 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 241 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4) 242 .setMIFlags(MachineInstr::FrameSetup)); 243 if(FramePtrOffsetInBlock) { 244 CFAOffset += FramePtrOffsetInBlock; 245 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa( 246 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset)); 247 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 248 .addCFIIndex(CFIIndex) 249 .setMIFlags(MachineInstr::FrameSetup); 250 } else { 251 unsigned CFIIndex = 252 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( 253 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 255 .addCFIIndex(CFIIndex) 256 .setMIFlags(MachineInstr::FrameSetup); 257 } 258 if (NumBytes > 508) 259 // If offset is > 508 then sp cannot be adjusted in a single instruction, 260 // try restoring from fp instead. 261 AFI->setShouldRestoreSPFromFP(true); 262 } 263 264 if (NumBytes) { 265 // Insert it after all the callee-save spills. 266 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 267 MachineInstr::FrameSetup); 268 if (!HasFP) { 269 CFAOffset -= NumBytes; 270 unsigned CFIIndex = MMI.addFrameInst( 271 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 272 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 273 .addCFIIndex(CFIIndex) 274 .setMIFlags(MachineInstr::FrameSetup); 275 } 276 } 277 278 if (STI.isTargetELF() && HasFP) 279 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 280 AFI->getFramePtrSpillOffset()); 281 282 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 283 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 284 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 285 286 // Thumb1 does not currently support dynamic stack realignment. Report a 287 // fatal error rather then silently generate bad code. 288 if (RegInfo->needsStackRealignment(MF)) 289 report_fatal_error("Dynamic stack realignment not supported for thumb1."); 290 291 // If we need a base pointer, set it up here. It's whatever the value 292 // of the stack pointer is at this point. Any variable size objects 293 // will be allocated after this, so we can still use the base pointer 294 // to reference locals. 295 if (RegInfo->hasBasePointer(MF)) 296 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) 297 .addReg(ARM::SP)); 298 299 // If the frame has variable sized objects then the epilogue must restore 300 // the sp from fp. We can assume there's an FP here since hasFP already 301 // checks for hasVarSizedObjects. 302 if (MFI->hasVarSizedObjects()) 303 AFI->setShouldRestoreSPFromFP(true); 304 } 305 306 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) { 307 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() && 308 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs)) 309 return true; 310 else if (MI.getOpcode() == ARM::tPOP) { 311 // The first two operands are predicates. The last two are 312 // imp-def and imp-use of SP. Check everything in between. 313 for (int i = 2, e = MI.getNumOperands() - 2; i != e; ++i) 314 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs)) 315 return false; 316 return true; 317 } 318 return false; 319 } 320 321 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, 322 MachineBasicBlock &MBB) const { 323 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 324 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 325 MachineFrameInfo *MFI = MF.getFrameInfo(); 326 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 327 const ThumbRegisterInfo *RegInfo = 328 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo()); 329 const Thumb1InstrInfo &TII = 330 *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo()); 331 332 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 333 int NumBytes = (int)MFI->getStackSize(); 334 assert((unsigned)NumBytes >= ArgRegsSaveSize && 335 "ArgRegsSaveSize is included in NumBytes"); 336 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 337 unsigned FramePtr = RegInfo->getFrameRegister(MF); 338 339 if (!AFI->hasStackFrame()) { 340 if (NumBytes - ArgRegsSaveSize != 0) 341 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize); 342 } else { 343 // Unwind MBBI to point to first LDR / VLDRD. 344 if (MBBI != MBB.begin()) { 345 do 346 --MBBI; 347 while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs)); 348 if (!isCSRestore(*MBBI, CSRegs)) 349 ++MBBI; 350 } 351 352 // Move SP to start of FP callee save spill area. 353 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 354 AFI->getGPRCalleeSavedArea2Size() + 355 AFI->getDPRCalleeSavedAreaSize() + 356 ArgRegsSaveSize); 357 358 if (AFI->shouldRestoreSPFromFP()) { 359 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 360 // Reset SP based on frame pointer only if the stack frame extends beyond 361 // frame pointer stack slot, the target is ELF and the function has FP, or 362 // the target uses var sized objects. 363 if (NumBytes) { 364 assert(!MFI->getPristineRegs(MF).test(ARM::R4) && 365 "No scratch register to restore SP from FP!"); 366 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 367 TII, *RegInfo); 368 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 369 ARM::SP) 370 .addReg(ARM::R4)); 371 } else 372 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 373 ARM::SP) 374 .addReg(FramePtr)); 375 } else { 376 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET && 377 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) { 378 MachineBasicBlock::iterator PMBBI = std::prev(MBBI); 379 if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes)) 380 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes); 381 } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes)) 382 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 383 } 384 } 385 386 if (needPopSpecialFixUp(MF)) { 387 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true); 388 (void)Done; 389 assert(Done && "Emission of the special fixup failed!?"); 390 } 391 } 392 393 bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 394 if (!needPopSpecialFixUp(*MBB.getParent())) 395 return true; 396 397 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 398 return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false); 399 } 400 401 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const { 402 ARMFunctionInfo *AFI = 403 const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>(); 404 if (AFI->getArgRegsSaveSize()) 405 return true; 406 407 // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up. 408 for (const CalleeSavedInfo &CSI : MF.getFrameInfo()->getCalleeSavedInfo()) 409 if (CSI.getReg() == ARM::LR) 410 return true; 411 412 return false; 413 } 414 415 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB, 416 bool DoIt) const { 417 MachineFunction &MF = *MBB.getParent(); 418 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 419 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 420 const TargetInstrInfo &TII = *STI.getInstrInfo(); 421 const ThumbRegisterInfo *RegInfo = 422 static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo()); 423 424 // If MBBI is a return instruction, or is a tPOP followed by a return 425 // instruction in the successor BB, we may be able to directly restore 426 // LR in the PC. 427 // This is only possible with v5T ops (v4T can't change the Thumb bit via 428 // a POP PC instruction), and only if we do not need to emit any SP update. 429 // Otherwise, we need a temporary register to pop the value 430 // and copy that value into LR. 431 auto MBBI = MBB.getFirstTerminator(); 432 bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize; 433 if (CanRestoreDirectly) { 434 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB) 435 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET || 436 MBBI->getOpcode() == ARM::tPOP_RET); 437 else { 438 auto MBBI_prev = MBBI; 439 MBBI_prev--; 440 assert(MBBI_prev->getOpcode() == ARM::tPOP); 441 assert(MBB.succ_size() == 1); 442 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET) 443 MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET. 444 else 445 CanRestoreDirectly = false; 446 } 447 } 448 449 if (CanRestoreDirectly) { 450 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET) 451 return true; 452 MachineInstrBuilder MIB = 453 AddDefaultPred( 454 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))); 455 // Copy implicit ops and popped registers, if any. 456 for (auto MO: MBBI->operands()) 457 if (MO.isReg() && (MO.isImplicit() || MO.isDef())) 458 MIB.addOperand(MO); 459 MIB.addReg(ARM::PC, RegState::Define); 460 // Erase the old instruction (tBX_RET or tPOP). 461 MBB.erase(MBBI); 462 return true; 463 } 464 465 // Look for a temporary register to use. 466 // First, compute the liveness information. 467 LivePhysRegs UsedRegs(STI.getRegisterInfo()); 468 UsedRegs.addLiveOuts(MBB); 469 // The semantic of pristines changed recently and now, 470 // the callee-saved registers that are touched in the function 471 // are not part of the pristines set anymore. 472 // Add those callee-saved now. 473 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 474 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); 475 for (unsigned i = 0; CSRegs[i]; ++i) 476 UsedRegs.addReg(CSRegs[i]); 477 478 DebugLoc dl = DebugLoc(); 479 if (MBBI != MBB.end()) { 480 dl = MBBI->getDebugLoc(); 481 auto InstUpToMBBI = MBB.end(); 482 while (InstUpToMBBI != MBBI) 483 // The pre-decrement is on purpose here. 484 // We want to have the liveness right before MBBI. 485 UsedRegs.stepBackward(*--InstUpToMBBI); 486 } 487 488 // Look for a register that can be directly use in the POP. 489 unsigned PopReg = 0; 490 // And some temporary register, just in case. 491 unsigned TemporaryReg = 0; 492 BitVector PopFriendly = 493 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID)); 494 assert(PopFriendly.any() && "No allocatable pop-friendly register?!"); 495 // Rebuild the GPRs from the high registers because they are removed 496 // form the GPR reg class for thumb1. 497 BitVector GPRsNoLRSP = 498 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID)); 499 GPRsNoLRSP |= PopFriendly; 500 GPRsNoLRSP.reset(ARM::LR); 501 GPRsNoLRSP.reset(ARM::SP); 502 GPRsNoLRSP.reset(ARM::PC); 503 for (int Register = GPRsNoLRSP.find_first(); Register != -1; 504 Register = GPRsNoLRSP.find_next(Register)) { 505 if (!UsedRegs.contains(Register)) { 506 // Remember the first pop-friendly register and exit. 507 if (PopFriendly.test(Register)) { 508 PopReg = Register; 509 TemporaryReg = 0; 510 break; 511 } 512 // Otherwise, remember that the register will be available to 513 // save a pop-friendly register. 514 TemporaryReg = Register; 515 } 516 } 517 518 if (!DoIt && !PopReg && !TemporaryReg) 519 return false; 520 521 assert((PopReg || TemporaryReg) && "Cannot get LR"); 522 523 if (TemporaryReg) { 524 assert(!PopReg && "Unnecessary MOV is about to be inserted"); 525 PopReg = PopFriendly.find_first(); 526 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) 527 .addReg(TemporaryReg, RegState::Define) 528 .addReg(PopReg, RegState::Kill)); 529 } 530 531 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) { 532 // We couldn't use the direct restoration above, so 533 // perform the opposite conversion: tPOP_RET to tPOP. 534 MachineInstrBuilder MIB = 535 AddDefaultPred( 536 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))); 537 bool Popped = false; 538 for (auto MO: MBBI->operands()) 539 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) && 540 MO.getReg() != ARM::PC) { 541 MIB.addOperand(MO); 542 if (!MO.isImplicit()) 543 Popped = true; 544 } 545 // Is there anything left to pop? 546 if (!Popped) 547 MBB.erase(MIB.getInstr()); 548 // Erase the old instruction. 549 MBB.erase(MBBI); 550 MBBI = AddDefaultPred(BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))); 551 } 552 553 assert(PopReg && "Do not know how to get LR"); 554 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 555 .addReg(PopReg, RegState::Define); 556 557 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize); 558 559 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) 560 .addReg(ARM::LR, RegState::Define) 561 .addReg(PopReg, RegState::Kill)); 562 563 if (TemporaryReg) 564 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)) 565 .addReg(PopReg, RegState::Define) 566 .addReg(TemporaryReg, RegState::Kill)); 567 568 return true; 569 } 570 571 bool Thumb1FrameLowering:: 572 spillCalleeSavedRegisters(MachineBasicBlock &MBB, 573 MachineBasicBlock::iterator MI, 574 const std::vector<CalleeSavedInfo> &CSI, 575 const TargetRegisterInfo *TRI) const { 576 if (CSI.empty()) 577 return false; 578 579 DebugLoc DL; 580 const TargetInstrInfo &TII = *STI.getInstrInfo(); 581 582 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); 583 AddDefaultPred(MIB); 584 for (unsigned i = CSI.size(); i != 0; --i) { 585 unsigned Reg = CSI[i-1].getReg(); 586 bool isKill = true; 587 588 // Add the callee-saved register as live-in unless it's LR and 589 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 590 // then it's already added to the function and entry block live-in sets. 591 if (Reg == ARM::LR) { 592 MachineFunction &MF = *MBB.getParent(); 593 if (MF.getFrameInfo()->isReturnAddressTaken() && 594 MF.getRegInfo().isLiveIn(Reg)) 595 isKill = false; 596 } 597 598 if (isKill) 599 MBB.addLiveIn(Reg); 600 601 MIB.addReg(Reg, getKillRegState(isKill)); 602 } 603 MIB.setMIFlags(MachineInstr::FrameSetup); 604 return true; 605 } 606 607 bool Thumb1FrameLowering:: 608 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 609 MachineBasicBlock::iterator MI, 610 const std::vector<CalleeSavedInfo> &CSI, 611 const TargetRegisterInfo *TRI) const { 612 if (CSI.empty()) 613 return false; 614 615 MachineFunction &MF = *MBB.getParent(); 616 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 617 const TargetInstrInfo &TII = *STI.getInstrInfo(); 618 619 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 620 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 621 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); 622 AddDefaultPred(MIB); 623 624 bool NeedsPop = false; 625 for (unsigned i = CSI.size(); i != 0; --i) { 626 unsigned Reg = CSI[i-1].getReg(); 627 if (Reg == ARM::LR) { 628 if (MBB.succ_empty()) { 629 // Special epilogue for vararg functions. See emitEpilogue 630 if (isVarArg) 631 continue; 632 // ARMv4T requires BX, see emitEpilogue 633 if (!STI.hasV5TOps()) 634 continue; 635 Reg = ARM::PC; 636 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); 637 if (MI != MBB.end()) 638 MIB.copyImplicitOps(*MI); 639 MI = MBB.erase(MI); 640 } else 641 // LR may only be popped into PC, as part of return sequence. 642 // If this isn't the return sequence, we'll need emitPopSpecialFixUp 643 // to restore LR the hard way. 644 continue; 645 } 646 MIB.addReg(Reg, getDefRegState(true)); 647 NeedsPop = true; 648 } 649 650 // It's illegal to emit pop instruction without operands. 651 if (NeedsPop) 652 MBB.insert(MI, &*MIB); 653 else 654 MF.DeleteMachineInstr(MIB); 655 656 return true; 657 } 658