1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 16 17 #include "HexagonRegisterInfo.h" 18 #include "MCTargetDesc/HexagonBaseInfo.h" 19 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 20 #include "llvm/Target/TargetFrameLowering.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "HexagonGenInstrInfo.inc" 25 26 namespace llvm { 27 28 struct EVT; 29 class HexagonSubtarget; 30 31 class HexagonInstrInfo : public HexagonGenInstrInfo { 32 virtual void anchor(); 33 const HexagonRegisterInfo RI; 34 35 public: 36 explicit HexagonInstrInfo(HexagonSubtarget &ST); 37 38 /// TargetInstrInfo overrides. 39 /// 40 41 /// If the specified machine instruction is a direct 42 /// load from a stack slot, return the virtual or physical register number of 43 /// the destination along with the FrameIndex of the loaded stack slot. If 44 /// not, return 0. This predicate must return 0 if the instruction has 45 /// any side effects other than loading from the stack slot. 46 unsigned isLoadFromStackSlot(const MachineInstr &MI, 47 int &FrameIndex) const override; 48 49 /// If the specified machine instruction is a direct 50 /// store to a stack slot, return the virtual or physical register number of 51 /// the source reg along with the FrameIndex of the loaded stack slot. If 52 /// not, return 0. This predicate must return 0 if the instruction has 53 /// any side effects other than storing to the stack slot. 54 unsigned isStoreToStackSlot(const MachineInstr &MI, 55 int &FrameIndex) const override; 56 57 /// Analyze the branching code at the end of MBB, returning 58 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 59 /// implemented for a target). Upon success, this returns false and returns 60 /// with the following information in various cases: 61 /// 62 /// 1. If this block ends with no branches (it just falls through to its succ) 63 /// just return false, leaving TBB/FBB null. 64 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 65 /// the destination block. 66 /// 3. If this block ends with a conditional branch and it falls through to a 67 /// successor block, it sets TBB to be the branch destination block and a 68 /// list of operands that evaluate the condition. These operands can be 69 /// passed to other TargetInstrInfo methods to create new branches. 70 /// 4. If this block ends with a conditional branch followed by an 71 /// unconditional branch, it returns the 'true' destination in TBB, the 72 /// 'false' destination in FBB, and a list of operands that evaluate the 73 /// condition. These operands can be passed to other TargetInstrInfo 74 /// methods to create new branches. 75 /// 76 /// Note that RemoveBranch and InsertBranch must be implemented to support 77 /// cases where this method returns success. 78 /// 79 /// If AllowModify is true, then this routine is allowed to modify the basic 80 /// block (e.g. delete instructions after the unconditional branch). 81 /// 82 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 83 MachineBasicBlock *&FBB, 84 SmallVectorImpl<MachineOperand> &Cond, 85 bool AllowModify) const override; 86 87 /// Remove the branching code at the end of the specific MBB. 88 /// This is only invoked in cases where AnalyzeBranch returns success. It 89 /// returns the number of instructions that were removed. 90 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 91 92 /// Insert branch code into the end of the specified MachineBasicBlock. 93 /// The operands to this method are the same as those 94 /// returned by AnalyzeBranch. This is only invoked in cases where 95 /// AnalyzeBranch returns success. It returns the number of instructions 96 /// inserted. 97 /// 98 /// It is also invoked by tail merging to add unconditional branches in 99 /// cases where AnalyzeBranch doesn't apply because there was no original 100 /// branch to analyze. At least this much must be implemented, else tail 101 /// merging needs to be disabled. 102 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 103 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 104 const DebugLoc &DL) const override; 105 106 /// Analyze the loop code, return true if it cannot be understood. Upon 107 /// success, this function returns false and returns information about the 108 /// induction variable and compare instruction used at the end. 109 bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, 110 MachineInstr *&CmpInst) const override; 111 112 /// Generate code to reduce the loop iteration by one and check if the loop is 113 /// finished. Return the value/register of the the new loop count. We need 114 /// this function when peeling off one or more iterations of a loop. This 115 /// function assumes the nth iteration is peeled first. 116 unsigned reduceLoopCount(MachineBasicBlock &MBB, 117 MachineInstr *IndVar, MachineInstr *Cmp, 118 SmallVectorImpl<MachineOperand> &Cond, 119 SmallVectorImpl<MachineInstr *> &PrevInsts, 120 unsigned Iter, unsigned MaxIter) const override; 121 122 /// Return true if it's profitable to predicate 123 /// instructions with accumulated instruction latency of "NumCycles" 124 /// of the specified basic block, where the probability of the instructions 125 /// being executed is given by Probability, and Confidence is a measure 126 /// of our confidence that it will be properly predicted. 127 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 128 unsigned ExtraPredCycles, 129 BranchProbability Probability) const override; 130 131 /// Second variant of isProfitableToIfCvt. This one 132 /// checks for the case where two basic blocks from true and false path 133 /// of a if-then-else (diamond) are predicated on mutally exclusive 134 /// predicates, where the probability of the true path being taken is given 135 /// by Probability, and Confidence is a measure of our confidence that it 136 /// will be properly predicted. 137 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 138 unsigned NumTCycles, unsigned ExtraTCycles, 139 MachineBasicBlock &FMBB, 140 unsigned NumFCycles, unsigned ExtraFCycles, 141 BranchProbability Probability) const override; 142 143 /// Return true if it's profitable for if-converter to duplicate instructions 144 /// of specified accumulated instruction latencies in the specified MBB to 145 /// enable if-conversion. 146 /// The probability of the instructions being executed is given by 147 /// Probability, and Confidence is a measure of our confidence that it 148 /// will be properly predicted. 149 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 150 BranchProbability Probability) const override; 151 152 /// Emit instructions to copy a pair of physical registers. 153 /// 154 /// This function should support copies within any legal register class as 155 /// well as any cross-class copies created during instruction selection. 156 /// 157 /// The source and destination registers may overlap, which may require a 158 /// careful implementation when multiple copy instructions are required for 159 /// large registers. See for example the ARM target. 160 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 161 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 162 bool KillSrc) const override; 163 164 /// Store the specified register of the given register class to the specified 165 /// stack frame index. The store instruction is to be added to the given 166 /// machine basic block before the specified machine instruction. If isKill 167 /// is true, the register operand is the last use and must be marked kill. 168 void storeRegToStackSlot(MachineBasicBlock &MBB, 169 MachineBasicBlock::iterator MBBI, 170 unsigned SrcReg, bool isKill, int FrameIndex, 171 const TargetRegisterClass *RC, 172 const TargetRegisterInfo *TRI) const override; 173 174 /// Load the specified register of the given register class from the specified 175 /// stack frame index. The load instruction is to be added to the given 176 /// machine basic block before the specified machine instruction. 177 void loadRegFromStackSlot(MachineBasicBlock &MBB, 178 MachineBasicBlock::iterator MBBI, 179 unsigned DestReg, int FrameIndex, 180 const TargetRegisterClass *RC, 181 const TargetRegisterInfo *TRI) const override; 182 183 /// This function is called for all pseudo instructions 184 /// that remain after register allocation. Many pseudo instructions are 185 /// created to help register allocation. This is the place to convert them 186 /// into real instructions. The target can edit MI in place, or it can insert 187 /// new instructions and erase MI. The function should return true if 188 /// anything was changed. 189 bool expandPostRAPseudo(MachineInstr &MI) const override; 190 191 /// \brief Get the base register and byte offset of a load/store instr. 192 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, 193 int64_t &Offset, 194 const TargetRegisterInfo *TRI) const override; 195 196 /// Reverses the branch condition of the specified condition list, 197 /// returning false on success and true if it cannot be reversed. 198 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 199 const override; 200 201 /// Insert a noop into the instruction stream at the specified point. 202 void insertNoop(MachineBasicBlock &MBB, 203 MachineBasicBlock::iterator MI) const override; 204 205 /// Returns true if the instruction is already predicated. 206 bool isPredicated(const MachineInstr &MI) const override; 207 208 /// Convert the instruction into a predicated instruction. 209 /// It returns true if the operation was successful. 210 bool PredicateInstruction(MachineInstr &MI, 211 ArrayRef<MachineOperand> Cond) const override; 212 213 /// Returns true if the first specified predicate 214 /// subsumes the second, e.g. GE subsumes GT. 215 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 216 ArrayRef<MachineOperand> Pred2) const override; 217 218 /// If the specified instruction defines any predicate 219 /// or condition code register(s) used for predication, returns true as well 220 /// as the definition predicate(s) by reference. 221 bool DefinesPredicate(MachineInstr &MI, 222 std::vector<MachineOperand> &Pred) const override; 223 224 /// Return true if the specified instruction can be predicated. 225 /// By default, this returns true for every instruction with a 226 /// PredicateOperand. 227 bool isPredicable(MachineInstr &MI) const override; 228 229 /// Test if the given instruction should be considered a scheduling boundary. 230 /// This primarily includes labels and terminators. 231 bool isSchedulingBoundary(const MachineInstr &MI, 232 const MachineBasicBlock *MBB, 233 const MachineFunction &MF) const override; 234 235 /// Measure the specified inline asm to determine an approximation of its 236 /// length. 237 unsigned getInlineAsmLength(const char *Str, 238 const MCAsmInfo &MAI) const override; 239 240 /// Allocate and return a hazard recognizer to use for this target when 241 /// scheduling the machine instructions after register allocation. 242 ScheduleHazardRecognizer* 243 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 244 const ScheduleDAG *DAG) const override; 245 246 /// For a comparison instruction, return the source registers 247 /// in SrcReg and SrcReg2 if having two register operands, and the value it 248 /// compares against in CmpValue. Return true if the comparison instruction 249 /// can be analyzed. 250 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 251 unsigned &SrcReg2, int &Mask, int &Value) const override; 252 253 /// Compute the instruction latency of a given instruction. 254 /// If the instruction has higher cost when predicated, it's returned via 255 /// PredCost. 256 unsigned getInstrLatency(const InstrItineraryData *ItinData, 257 const MachineInstr &MI, 258 unsigned *PredCost = 0) const override; 259 260 /// Create machine specific model for scheduling. 261 DFAPacketizer * 262 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override; 263 264 // Sometimes, it is possible for the target 265 // to tell, even without aliasing information, that two MIs access different 266 // memory addresses. This function returns true if two MIs access different 267 // memory addresses and false otherwise. 268 bool 269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, 270 AliasAnalysis *AA = nullptr) const override; 271 272 /// For instructions with a base and offset, return the position of the 273 /// base register and offset operands. 274 bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos, 275 unsigned &OffsetPos) const override; 276 277 /// If the instruction is an increment of a constant value, return the amount. 278 bool getIncrementValue(const MachineInstr *MI, int &Value) const override; 279 280 /// HexagonInstrInfo specifics. 281 /// 282 283 const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 284 285 unsigned createVR(MachineFunction* MF, MVT VT) const; 286 287 bool isAbsoluteSet(const MachineInstr* MI) const; 288 bool isAccumulator(const MachineInstr *MI) const; 289 bool isComplex(const MachineInstr *MI) const; 290 bool isCompoundBranchInstr(const MachineInstr *MI) const; 291 bool isCondInst(const MachineInstr *MI) const; 292 bool isConditionalALU32 (const MachineInstr* MI) const; 293 bool isConditionalLoad(const MachineInstr* MI) const; 294 bool isConditionalStore(const MachineInstr* MI) const; 295 bool isConditionalTransfer(const MachineInstr* MI) const; 296 bool isConstExtended(const MachineInstr *MI) const; 297 bool isDeallocRet(const MachineInstr *MI) const; 298 bool isDependent(const MachineInstr *ProdMI, 299 const MachineInstr *ConsMI) const; 300 bool isDotCurInst(const MachineInstr* MI) const; 301 bool isDotNewInst(const MachineInstr* MI) const; 302 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const; 303 bool isEarlySourceInstr(const MachineInstr *MI) const; 304 bool isEndLoopN(unsigned Opcode) const; 305 bool isExpr(unsigned OpType) const; 306 bool isExtendable(const MachineInstr* MI) const; 307 bool isExtended(const MachineInstr* MI) const; 308 bool isFloat(const MachineInstr *MI) const; 309 bool isHVXMemWithAIndirect(const MachineInstr *I, 310 const MachineInstr *J) const; 311 bool isIndirectCall(const MachineInstr *MI) const; 312 bool isIndirectL4Return(const MachineInstr *MI) const; 313 bool isJumpR(const MachineInstr *MI) const; 314 bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const; 315 bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI, 316 const MachineInstr *ESMI) const; 317 bool isLateResultInstr(const MachineInstr *MI) const; 318 bool isLateSourceInstr(const MachineInstr *MI) const; 319 bool isLoopN(const MachineInstr *MI) const; 320 bool isMemOp(const MachineInstr *MI) const; 321 bool isNewValue(const MachineInstr* MI) const; 322 bool isNewValue(unsigned Opcode) const; 323 bool isNewValueInst(const MachineInstr* MI) const; 324 bool isNewValueJump(const MachineInstr* MI) const; 325 bool isNewValueJump(unsigned Opcode) const; 326 bool isNewValueStore(const MachineInstr* MI) const; 327 bool isNewValueStore(unsigned Opcode) const; 328 bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const; 329 bool isPostIncrement(const MachineInstr* MI) const override; 330 bool isPredicatedNew(const MachineInstr &MI) const; 331 bool isPredicatedNew(unsigned Opcode) const; 332 bool isPredicatedTrue(const MachineInstr &MI) const; 333 bool isPredicatedTrue(unsigned Opcode) const; 334 bool isPredicated(unsigned Opcode) const; 335 bool isPredicateLate(unsigned Opcode) const; 336 bool isPredictedTaken(unsigned Opcode) const; 337 bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const; 338 bool isSignExtendingLoad(const MachineInstr &MI) const; 339 bool isSolo(const MachineInstr* MI) const; 340 bool isSpillPredRegOp(const MachineInstr *MI) const; 341 bool isTailCall(const MachineInstr *MI) const; 342 bool isTC1(const MachineInstr *MI) const; 343 bool isTC2(const MachineInstr *MI) const; 344 bool isTC2Early(const MachineInstr *MI) const; 345 bool isTC4x(const MachineInstr *MI) const; 346 bool isV60VectorInstruction(const MachineInstr *MI) const; 347 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 348 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; 349 bool isVecAcc(const MachineInstr *MI) const; 350 bool isVecALU(const MachineInstr *MI) const; 351 bool isVecUsableNextPacket(const MachineInstr *ProdMI, 352 const MachineInstr *ConsMI) const; 353 bool isZeroExtendingLoad(const MachineInstr &MI) const; 354 355 bool canExecuteInBundle(const MachineInstr *First, 356 const MachineInstr *Second) const; 357 bool hasEHLabel(const MachineBasicBlock *B) const; 358 bool hasNonExtEquivalent(const MachineInstr *MI) const; 359 bool hasPseudoInstrPair(const MachineInstr *MI) const; 360 bool hasUncondBranch(const MachineBasicBlock *B) const; 361 bool mayBeCurLoad(const MachineInstr* MI) const; 362 bool mayBeNewStore(const MachineInstr* MI) const; 363 bool producesStall(const MachineInstr *ProdMI, 364 const MachineInstr *ConsMI) const; 365 bool producesStall(const MachineInstr *MI, 366 MachineBasicBlock::const_instr_iterator MII) const; 367 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const; 368 bool PredOpcodeHasJMP_c(unsigned Opcode) const; 369 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; 370 371 372 short getAbsoluteForm(const MachineInstr *MI) const; 373 unsigned getAddrMode(const MachineInstr* MI) const; 374 unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset, 375 unsigned &AccessSize) const; 376 short getBaseWithLongOffset(short Opcode) const; 377 short getBaseWithLongOffset(const MachineInstr *MI) const; 378 short getBaseWithRegOffset(const MachineInstr *MI) const; 379 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const; 380 unsigned getCExtOpNum(const MachineInstr *MI) const; 381 HexagonII::CompoundGroup 382 getCompoundCandidateGroup(const MachineInstr *MI) const; 383 unsigned getCompoundOpcode(const MachineInstr *GA, 384 const MachineInstr *GB) const; 385 int getCondOpcode(int Opc, bool sense) const; 386 int getDotCurOp(const MachineInstr* MI) const; 387 int getDotNewOp(const MachineInstr* MI) const; 388 int getDotNewPredJumpOp(const MachineInstr *MI, 389 const MachineBranchProbabilityInfo *MBPI) const; 390 int getDotNewPredOp(const MachineInstr *MI, 391 const MachineBranchProbabilityInfo *MBPI) const; 392 int getDotOldOp(const int opc) const; 393 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI) 394 const; 395 short getEquivalentHWInstr(const MachineInstr *MI) const; 396 MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const; 397 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, 398 const MachineInstr *MI) const; 399 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; 400 unsigned getInvertedPredicatedOpcode(const int Opc) const; 401 int getMaxValue(const MachineInstr *MI) const; 402 unsigned getMemAccessSize(const MachineInstr* MI) const; 403 int getMinValue(const MachineInstr *MI) const; 404 short getNonExtOpcode(const MachineInstr *MI) const; 405 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg, 406 unsigned &PredRegPos, unsigned &PredRegFlags) const; 407 short getPseudoInstrPair(const MachineInstr *MI) const; 408 short getRegForm(const MachineInstr *MI) const; 409 unsigned getSize(const MachineInstr *MI) const; 410 uint64_t getType(const MachineInstr* MI) const; 411 unsigned getUnits(const MachineInstr* MI) const; 412 unsigned getValidSubTargets(const unsigned Opcode) const; 413 414 415 /// getInstrTimingClassLatency - Compute the instruction latency of a given 416 /// instruction using Timing Class information, if available. 417 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const; 418 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const; 419 420 421 void immediateExtend(MachineInstr *MI) const; 422 bool invertAndChangeJumpTarget(MachineInstr* MI, 423 MachineBasicBlock* NewTarget) const; 424 void genAllInsnTimingClasses(MachineFunction &MF) const; 425 bool reversePredSense(MachineInstr* MI) const; 426 unsigned reversePrediction(unsigned Opcode) const; 427 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const; 428 short xformRegToImmOffset(const MachineInstr *MI) const; 429 }; 430 431 } 432 433 #endif 434
