1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Simple pass to fill delay slots with useful instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCNaCl.h" 15 #include "Mips.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsTargetMachine.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/SmallPtrSet.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/Analysis/AliasAnalysis.h" 22 #include "llvm/Analysis/ValueTracking.h" 23 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/PseudoSourceValue.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Target/TargetInstrInfo.h" 30 #include "llvm/Target/TargetMachine.h" 31 #include "llvm/Target/TargetRegisterInfo.h" 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "delay-slot-filler" 36 37 STATISTIC(FilledSlots, "Number of delay slots filled"); 38 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that" 39 " are not NOP."); 40 41 static cl::opt<bool> DisableDelaySlotFiller( 42 "disable-mips-delay-filler", 43 cl::init(false), 44 cl::desc("Fill all delay slots with NOPs."), 45 cl::Hidden); 46 47 static cl::opt<bool> DisableForwardSearch( 48 "disable-mips-df-forward-search", 49 cl::init(true), 50 cl::desc("Disallow MIPS delay filler to search forward."), 51 cl::Hidden); 52 53 static cl::opt<bool> DisableSuccBBSearch( 54 "disable-mips-df-succbb-search", 55 cl::init(true), 56 cl::desc("Disallow MIPS delay filler to search successor basic blocks."), 57 cl::Hidden); 58 59 static cl::opt<bool> DisableBackwardSearch( 60 "disable-mips-df-backward-search", 61 cl::init(false), 62 cl::desc("Disallow MIPS delay filler to search backward."), 63 cl::Hidden); 64 65 enum CompactBranchPolicy { 66 CB_Never, ///< The policy 'never' may in some circumstances or for some 67 ///< ISAs not be absolutely adhered to. 68 CB_Optimal, ///< Optimal is the default and will produce compact branches 69 ///< when delay slots cannot be filled. 70 CB_Always ///< 'always' may in some circumstances may not be 71 ///< absolutely adhered to there may not be a corresponding 72 ///< compact form of a branch. 73 }; 74 75 static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy( 76 "mips-compact-branches",cl::Optional, 77 cl::init(CB_Optimal), 78 cl::desc("MIPS Specific: Compact branch policy."), 79 cl::values( 80 clEnumValN(CB_Never, "never", "Do not use compact branches if possible."), 81 clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."), 82 clEnumValN(CB_Always, "always", "Always use compact branches if possible."), 83 clEnumValEnd 84 ) 85 ); 86 87 namespace { 88 typedef MachineBasicBlock::iterator Iter; 89 typedef MachineBasicBlock::reverse_iterator ReverseIter; 90 typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap; 91 92 class RegDefsUses { 93 public: 94 RegDefsUses(const TargetRegisterInfo &TRI); 95 void init(const MachineInstr &MI); 96 97 /// This function sets all caller-saved registers in Defs. 98 void setCallerSaved(const MachineInstr &MI); 99 100 /// This function sets all unallocatable registers in Defs. 101 void setUnallocatableRegs(const MachineFunction &MF); 102 103 /// Set bits in Uses corresponding to MBB's live-out registers except for 104 /// the registers that are live-in to SuccBB. 105 void addLiveOut(const MachineBasicBlock &MBB, 106 const MachineBasicBlock &SuccBB); 107 108 bool update(const MachineInstr &MI, unsigned Begin, unsigned End); 109 110 private: 111 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, 112 bool IsDef) const; 113 114 /// Returns true if Reg or its alias is in RegSet. 115 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const; 116 117 const TargetRegisterInfo &TRI; 118 BitVector Defs, Uses; 119 }; 120 121 /// Base class for inspecting loads and stores. 122 class InspectMemInstr { 123 public: 124 InspectMemInstr(bool ForbidMemInstr_) 125 : OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false), 126 SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {} 127 128 /// Return true if MI cannot be moved to delay slot. 129 bool hasHazard(const MachineInstr &MI); 130 131 virtual ~InspectMemInstr() {} 132 133 protected: 134 /// Flags indicating whether loads or stores have been seen. 135 bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore; 136 137 /// Memory instructions are not allowed to move to delay slot if this flag 138 /// is true. 139 bool ForbidMemInstr; 140 141 private: 142 virtual bool hasHazard_(const MachineInstr &MI) = 0; 143 }; 144 145 /// This subclass rejects any memory instructions. 146 class NoMemInstr : public InspectMemInstr { 147 public: 148 NoMemInstr() : InspectMemInstr(true) {} 149 private: 150 bool hasHazard_(const MachineInstr &MI) override { return true; } 151 }; 152 153 /// This subclass accepts loads from stacks and constant loads. 154 class LoadFromStackOrConst : public InspectMemInstr { 155 public: 156 LoadFromStackOrConst() : InspectMemInstr(false) {} 157 private: 158 bool hasHazard_(const MachineInstr &MI) override; 159 }; 160 161 /// This subclass uses memory dependence information to determine whether a 162 /// memory instruction can be moved to a delay slot. 163 class MemDefsUses : public InspectMemInstr { 164 public: 165 MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI); 166 167 private: 168 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType; 169 170 bool hasHazard_(const MachineInstr &MI) override; 171 172 /// Update Defs and Uses. Return true if there exist dependences that 173 /// disqualify the delay slot candidate between V and values in Uses and 174 /// Defs. 175 bool updateDefsUses(ValueType V, bool MayStore); 176 177 /// Get the list of underlying objects of MI's memory operand. 178 bool getUnderlyingObjects(const MachineInstr &MI, 179 SmallVectorImpl<ValueType> &Objects) const; 180 181 const MachineFrameInfo *MFI; 182 SmallPtrSet<ValueType, 4> Uses, Defs; 183 const DataLayout &DL; 184 185 /// Flags indicating whether loads or stores with no underlying objects have 186 /// been seen. 187 bool SeenNoObjLoad, SeenNoObjStore; 188 }; 189 190 class Filler : public MachineFunctionPass { 191 public: 192 Filler(TargetMachine &tm) 193 : MachineFunctionPass(ID), TM(tm) { } 194 195 const char *getPassName() const override { 196 return "Mips Delay Slot Filler"; 197 } 198 199 bool runOnMachineFunction(MachineFunction &F) override { 200 bool Changed = false; 201 for (MachineFunction::iterator FI = F.begin(), FE = F.end(); 202 FI != FE; ++FI) 203 Changed |= runOnMachineBasicBlock(*FI); 204 205 // This pass invalidates liveness information when it reorders 206 // instructions to fill delay slot. Without this, -verify-machineinstrs 207 // will fail. 208 if (Changed) 209 F.getRegInfo().invalidateLiveness(); 210 211 return Changed; 212 } 213 214 MachineFunctionProperties getRequiredProperties() const override { 215 return MachineFunctionProperties().set( 216 MachineFunctionProperties::Property::AllVRegsAllocated); 217 } 218 219 void getAnalysisUsage(AnalysisUsage &AU) const override { 220 AU.addRequired<MachineBranchProbabilityInfo>(); 221 MachineFunctionPass::getAnalysisUsage(AU); 222 } 223 224 private: 225 bool runOnMachineBasicBlock(MachineBasicBlock &MBB); 226 227 Iter replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch, 228 const DebugLoc &DL); 229 230 /// This function checks if it is valid to move Candidate to the delay slot 231 /// and returns true if it isn't. It also updates memory and register 232 /// dependence information. 233 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU, 234 InspectMemInstr &IM) const; 235 236 /// This function searches range [Begin, End) for an instruction that can be 237 /// moved to the delay slot. Returns true on success. 238 template<typename IterTy> 239 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, 240 RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot, 241 IterTy &Filler) const; 242 243 /// This function searches in the backward direction for an instruction that 244 /// can be moved to the delay slot. Returns true on success. 245 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const; 246 247 /// This function searches MBB in the forward direction for an instruction 248 /// that can be moved to the delay slot. Returns true on success. 249 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const; 250 251 /// This function searches one of MBB's successor blocks for an instruction 252 /// that can be moved to the delay slot and inserts clones of the 253 /// instruction into the successor's predecessor blocks. 254 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const; 255 256 /// Pick a successor block of MBB. Return NULL if MBB doesn't have a 257 /// successor block that is not a landing pad. 258 MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const; 259 260 /// This function analyzes MBB and returns an instruction with an unoccupied 261 /// slot that branches to Dst. 262 std::pair<MipsInstrInfo::BranchType, MachineInstr *> 263 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const; 264 265 /// Examine Pred and see if it is possible to insert an instruction into 266 /// one of its branches delay slot or its end. 267 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 268 RegDefsUses &RegDU, bool &HasMultipleSuccs, 269 BB2BrMap &BrMap) const; 270 271 bool terminateSearch(const MachineInstr &Candidate) const; 272 273 TargetMachine &TM; 274 275 static char ID; 276 }; 277 char Filler::ID = 0; 278 } // end of anonymous namespace 279 280 static bool hasUnoccupiedSlot(const MachineInstr *MI) { 281 return MI->hasDelaySlot() && !MI->isBundledWithSucc(); 282 } 283 284 /// This function inserts clones of Filler into predecessor blocks. 285 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) { 286 MachineFunction *MF = Filler->getParent()->getParent(); 287 288 for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) { 289 if (I->second) { 290 MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler)); 291 ++UsefulSlots; 292 } else { 293 I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler)); 294 } 295 } 296 } 297 298 /// This function adds registers Filler defines to MBB's live-in register list. 299 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) { 300 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) { 301 const MachineOperand &MO = Filler->getOperand(I); 302 unsigned R; 303 304 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg())) 305 continue; 306 307 #ifndef NDEBUG 308 const MachineFunction &MF = *MBB.getParent(); 309 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && 310 "Shouldn't move an instruction with unallocatable registers across " 311 "basic block boundaries."); 312 #endif 313 314 if (!MBB.isLiveIn(R)) 315 MBB.addLiveIn(R); 316 } 317 } 318 319 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI) 320 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} 321 322 void RegDefsUses::init(const MachineInstr &MI) { 323 // Add all register operands which are explicit and non-variadic. 324 update(MI, 0, MI.getDesc().getNumOperands()); 325 326 // If MI is a call, add RA to Defs to prevent users of RA from going into 327 // delay slot. 328 if (MI.isCall()) 329 Defs.set(Mips::RA); 330 331 // Add all implicit register operands of branch instructions except 332 // register AT. 333 if (MI.isBranch()) { 334 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands()); 335 Defs.reset(Mips::AT); 336 } 337 } 338 339 void RegDefsUses::setCallerSaved(const MachineInstr &MI) { 340 assert(MI.isCall()); 341 342 // Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into 343 // the delay slot. The reason is that RA/RA_64 must not be changed 344 // in the delay slot so that the callee can return to the caller. 345 if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) { 346 Defs.set(Mips::RA); 347 Defs.set(Mips::RA_64); 348 } 349 350 // If MI is a call, add all caller-saved registers to Defs. 351 BitVector CallerSavedRegs(TRI.getNumRegs(), true); 352 353 CallerSavedRegs.reset(Mips::ZERO); 354 CallerSavedRegs.reset(Mips::ZERO_64); 355 356 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent()); 357 *R; ++R) 358 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI) 359 CallerSavedRegs.reset(*AI); 360 361 Defs |= CallerSavedRegs; 362 } 363 364 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) { 365 BitVector AllocSet = TRI.getAllocatableSet(MF); 366 367 for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R)) 368 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI) 369 AllocSet.set(*AI); 370 371 AllocSet.set(Mips::ZERO); 372 AllocSet.set(Mips::ZERO_64); 373 374 Defs |= AllocSet.flip(); 375 } 376 377 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB, 378 const MachineBasicBlock &SuccBB) { 379 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), 380 SE = MBB.succ_end(); SI != SE; ++SI) 381 if (*SI != &SuccBB) 382 for (const auto &LI : (*SI)->liveins()) 383 Uses.set(LI.PhysReg); 384 } 385 386 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) { 387 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs()); 388 bool HasHazard = false; 389 390 for (unsigned I = Begin; I != End; ++I) { 391 const MachineOperand &MO = MI.getOperand(I); 392 393 if (MO.isReg() && MO.getReg()) 394 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef()); 395 } 396 397 Defs |= NewDefs; 398 Uses |= NewUses; 399 400 return HasHazard; 401 } 402 403 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, 404 unsigned Reg, bool IsDef) const { 405 if (IsDef) { 406 NewDefs.set(Reg); 407 // check whether Reg has already been defined or used. 408 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); 409 } 410 411 NewUses.set(Reg); 412 // check whether Reg has already been defined. 413 return isRegInSet(Defs, Reg); 414 } 415 416 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { 417 // Check Reg and all aliased Registers. 418 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) 419 if (RegSet.test(*AI)) 420 return true; 421 return false; 422 } 423 424 bool InspectMemInstr::hasHazard(const MachineInstr &MI) { 425 if (!MI.mayStore() && !MI.mayLoad()) 426 return false; 427 428 if (ForbidMemInstr) 429 return true; 430 431 OrigSeenLoad = SeenLoad; 432 OrigSeenStore = SeenStore; 433 SeenLoad |= MI.mayLoad(); 434 SeenStore |= MI.mayStore(); 435 436 // If MI is an ordered or volatile memory reference, disallow moving 437 // subsequent loads and stores to delay slot. 438 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) { 439 ForbidMemInstr = true; 440 return true; 441 } 442 443 return hasHazard_(MI); 444 } 445 446 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) { 447 if (MI.mayStore()) 448 return true; 449 450 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue()) 451 return true; 452 453 if (const PseudoSourceValue *PSV = 454 (*MI.memoperands_begin())->getPseudoValue()) { 455 if (isa<FixedStackPseudoSourceValue>(PSV)) 456 return false; 457 return !PSV->isConstant(nullptr) && !PSV->isStack(); 458 } 459 460 return true; 461 } 462 463 MemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_) 464 : InspectMemInstr(false), MFI(MFI_), DL(DL), SeenNoObjLoad(false), 465 SeenNoObjStore(false) {} 466 467 bool MemDefsUses::hasHazard_(const MachineInstr &MI) { 468 bool HasHazard = false; 469 SmallVector<ValueType, 4> Objs; 470 471 // Check underlying object list. 472 if (getUnderlyingObjects(MI, Objs)) { 473 for (SmallVectorImpl<ValueType>::const_iterator I = Objs.begin(); 474 I != Objs.end(); ++I) 475 HasHazard |= updateDefsUses(*I, MI.mayStore()); 476 477 return HasHazard; 478 } 479 480 // No underlying objects found. 481 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore); 482 HasHazard |= MI.mayLoad() || OrigSeenStore; 483 484 SeenNoObjLoad |= MI.mayLoad(); 485 SeenNoObjStore |= MI.mayStore(); 486 487 return HasHazard; 488 } 489 490 bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) { 491 if (MayStore) 492 return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore || 493 SeenNoObjLoad; 494 495 Uses.insert(V); 496 return Defs.count(V) || SeenNoObjStore; 497 } 498 499 bool MemDefsUses:: 500 getUnderlyingObjects(const MachineInstr &MI, 501 SmallVectorImpl<ValueType> &Objects) const { 502 if (!MI.hasOneMemOperand() || 503 (!(*MI.memoperands_begin())->getValue() && 504 !(*MI.memoperands_begin())->getPseudoValue())) 505 return false; 506 507 if (const PseudoSourceValue *PSV = 508 (*MI.memoperands_begin())->getPseudoValue()) { 509 if (!PSV->isAliased(MFI)) 510 return false; 511 Objects.push_back(PSV); 512 return true; 513 } 514 515 const Value *V = (*MI.memoperands_begin())->getValue(); 516 517 SmallVector<Value *, 4> Objs; 518 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL); 519 520 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end(); 521 I != E; ++I) { 522 if (!isIdentifiedObject(V)) 523 return false; 524 525 Objects.push_back(*I); 526 } 527 528 return true; 529 } 530 531 // Replace Branch with the compact branch instruction. 532 Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch, 533 const DebugLoc &DL) { 534 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 535 const MipsInstrInfo *TII = STI.getInstrInfo(); 536 537 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); 538 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); 539 540 std::next(Branch)->eraseFromParent(); 541 return Branch; 542 } 543 544 // For given opcode returns opcode of corresponding instruction with short 545 // delay slot. 546 static int getEquivalentCallShort(int Opcode) { 547 switch (Opcode) { 548 case Mips::BGEZAL: 549 return Mips::BGEZALS_MM; 550 case Mips::BLTZAL: 551 return Mips::BLTZALS_MM; 552 case Mips::JAL: 553 return Mips::JALS_MM; 554 case Mips::JALR: 555 return Mips::JALRS_MM; 556 case Mips::JALR16_MM: 557 return Mips::JALRS16_MM; 558 default: 559 llvm_unreachable("Unexpected call instruction for microMIPS."); 560 } 561 } 562 563 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block. 564 /// We assume there is only one delay slot per delayed instruction. 565 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { 566 bool Changed = false; 567 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 568 bool InMicroMipsMode = STI.inMicroMipsMode(); 569 const MipsInstrInfo *TII = STI.getInstrInfo(); 570 571 if (InMicroMipsMode && STI.hasMips32r6()) { 572 // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for 573 // branching instructions is not needed. 574 return Changed; 575 } 576 577 for (Iter I = MBB.begin(); I != MBB.end(); ++I) { 578 if (!hasUnoccupiedSlot(&*I)) 579 continue; 580 581 ++FilledSlots; 582 Changed = true; 583 584 // Delay slot filling is disabled at -O0. 585 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { 586 bool Filled = false; 587 588 if (MipsCompactBranchPolicy.getValue() != CB_Always || 589 !TII->getEquivalentCompactForm(I)) { 590 if (searchBackward(MBB, I)) { 591 Filled = true; 592 } else if (I->isTerminator()) { 593 if (searchSuccBBs(MBB, I)) { 594 Filled = true; 595 } 596 } else if (searchForward(MBB, I)) { 597 Filled = true; 598 } 599 } 600 601 if (Filled) { 602 // Get instruction with delay slot. 603 MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); 604 605 if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 && 606 DSI->isCall()) { 607 // If instruction in delay slot is 16b change opcode to 608 // corresponding instruction with short delay slot. 609 DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); 610 } 611 continue; 612 } 613 } 614 615 // For microMIPS if instruction is BEQ or BNE with one ZERO register, then 616 // instead of adding NOP replace this instruction with the corresponding 617 // compact branch instruction, i.e. BEQZC or BNEZC. Additionally 618 // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can 619 // be replaced with JRC16_MM. 620 621 // For MIPSR6 attempt to produce the corresponding compact (no delay slot) 622 // form of the CTI. For indirect jumps this will not require inserting a 623 // NOP and for branches will hopefully avoid requiring a NOP. 624 if ((InMicroMipsMode || 625 (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) && 626 TII->getEquivalentCompactForm(I)) { 627 I = replaceWithCompactBranch(MBB, I, I->getDebugLoc()); 628 continue; 629 } 630 631 // Bundle the NOP to the instruction with the delay slot. 632 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); 633 MIBundleBuilder(MBB, I, std::next(I, 2)); 634 } 635 636 return Changed; 637 } 638 639 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay 640 /// slots in Mips MachineFunctions 641 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) { 642 return new Filler(tm); 643 } 644 645 template<typename IterTy> 646 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, 647 RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot, 648 IterTy &Filler) const { 649 bool IsReverseIter = std::is_convertible<IterTy, ReverseIter>::value; 650 651 for (IterTy I = Begin; I != End;) { 652 IterTy CurrI = I; 653 ++I; 654 655 // skip debug value 656 if (CurrI->isDebugValue()) 657 continue; 658 659 if (terminateSearch(*CurrI)) 660 break; 661 662 assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) && 663 "Cannot put calls, returns or branches in delay slot."); 664 665 if (CurrI->isKill()) { 666 CurrI->eraseFromParent(); 667 668 // This special case is needed for reverse iterators, because when we 669 // erase an instruction, the iterators are updated to point to the next 670 // instruction. 671 if (IsReverseIter && I != End) 672 I = CurrI; 673 continue; 674 } 675 676 if (delayHasHazard(*CurrI, RegDU, IM)) 677 continue; 678 679 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 680 if (STI.isTargetNaCl()) { 681 // In NaCl, instructions that must be masked are forbidden in delay slots. 682 // We only check for loads, stores and SP changes. Calls, returns and 683 // branches are not checked because non-NaCl targets never put them in 684 // delay slots. 685 unsigned AddrIdx; 686 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) && 687 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) || 688 CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo())) 689 continue; 690 } 691 692 bool InMicroMipsMode = STI.inMicroMipsMode(); 693 const MipsInstrInfo *TII = STI.getInstrInfo(); 694 unsigned Opcode = (*Slot).getOpcode(); 695 if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 && 696 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || 697 Opcode == Mips::PseudoReturn)) 698 continue; 699 700 Filler = CurrI; 701 return true; 702 } 703 704 return false; 705 } 706 707 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const { 708 if (DisableBackwardSearch) 709 return false; 710 711 auto *Fn = MBB.getParent(); 712 RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo()); 713 MemDefsUses MemDU(Fn->getDataLayout(), Fn->getFrameInfo()); 714 ReverseIter Filler; 715 716 RegDU.init(*Slot); 717 718 if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Slot, 719 Filler)) 720 return false; 721 722 MBB.splice(std::next(Slot), &MBB, std::next(Filler).base()); 723 MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); 724 ++UsefulSlots; 725 return true; 726 } 727 728 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const { 729 // Can handle only calls. 730 if (DisableForwardSearch || !Slot->isCall()) 731 return false; 732 733 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 734 NoMemInstr NM; 735 Iter Filler; 736 737 RegDU.setCallerSaved(*Slot); 738 739 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler)) 740 return false; 741 742 MBB.splice(std::next(Slot), &MBB, Filler); 743 MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); 744 ++UsefulSlots; 745 return true; 746 } 747 748 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const { 749 if (DisableSuccBBSearch) 750 return false; 751 752 MachineBasicBlock *SuccBB = selectSuccBB(MBB); 753 754 if (!SuccBB) 755 return false; 756 757 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 758 bool HasMultipleSuccs = false; 759 BB2BrMap BrMap; 760 std::unique_ptr<InspectMemInstr> IM; 761 Iter Filler; 762 auto *Fn = MBB.getParent(); 763 764 // Iterate over SuccBB's predecessor list. 765 for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(), 766 PE = SuccBB->pred_end(); PI != PE; ++PI) 767 if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap)) 768 return false; 769 770 // Do not allow moving instructions which have unallocatable register operands 771 // across basic block boundaries. 772 RegDU.setUnallocatableRegs(*Fn); 773 774 // Only allow moving loads from stack or constants if any of the SuccBB's 775 // predecessors have multiple successors. 776 if (HasMultipleSuccs) { 777 IM.reset(new LoadFromStackOrConst()); 778 } else { 779 const MachineFrameInfo *MFI = Fn->getFrameInfo(); 780 IM.reset(new MemDefsUses(Fn->getDataLayout(), MFI)); 781 } 782 783 if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot, 784 Filler)) 785 return false; 786 787 insertDelayFiller(Filler, BrMap); 788 addLiveInRegs(Filler, *SuccBB); 789 Filler->eraseFromParent(); 790 791 return true; 792 } 793 794 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const { 795 if (B.succ_empty()) 796 return nullptr; 797 798 // Select the successor with the larget edge weight. 799 auto &Prob = getAnalysis<MachineBranchProbabilityInfo>(); 800 MachineBasicBlock *S = *std::max_element( 801 B.succ_begin(), B.succ_end(), 802 [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) { 803 return Prob.getEdgeProbability(&B, Dst0) < 804 Prob.getEdgeProbability(&B, Dst1); 805 }); 806 return S->isEHPad() ? nullptr : S; 807 } 808 809 std::pair<MipsInstrInfo::BranchType, MachineInstr *> 810 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const { 811 const MipsInstrInfo *TII = 812 MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo(); 813 MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr; 814 SmallVector<MachineInstr*, 2> BranchInstrs; 815 SmallVector<MachineOperand, 2> Cond; 816 817 MipsInstrInfo::BranchType R = 818 TII->analyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs); 819 820 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch)) 821 return std::make_pair(R, nullptr); 822 823 if (R != MipsInstrInfo::BT_CondUncond) { 824 if (!hasUnoccupiedSlot(BranchInstrs[0])) 825 return std::make_pair(MipsInstrInfo::BT_None, nullptr); 826 827 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst))); 828 829 return std::make_pair(R, BranchInstrs[0]); 830 } 831 832 assert((TrueBB == &Dst) || (FalseBB == &Dst)); 833 834 // Examine the conditional branch. See if its slot is occupied. 835 if (hasUnoccupiedSlot(BranchInstrs[0])) 836 return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]); 837 838 // If that fails, try the unconditional branch. 839 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst)) 840 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]); 841 842 return std::make_pair(MipsInstrInfo::BT_None, nullptr); 843 } 844 845 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 846 RegDefsUses &RegDU, bool &HasMultipleSuccs, 847 BB2BrMap &BrMap) const { 848 std::pair<MipsInstrInfo::BranchType, MachineInstr *> P = 849 getBranch(Pred, Succ); 850 851 // Return if either getBranch wasn't able to analyze the branches or there 852 // were no branches with unoccupied slots. 853 if (P.first == MipsInstrInfo::BT_None) 854 return false; 855 856 if ((P.first != MipsInstrInfo::BT_Uncond) && 857 (P.first != MipsInstrInfo::BT_NoBranch)) { 858 HasMultipleSuccs = true; 859 RegDU.addLiveOut(Pred, Succ); 860 } 861 862 BrMap[&Pred] = P.second; 863 return true; 864 } 865 866 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU, 867 InspectMemInstr &IM) const { 868 assert(!Candidate.isKill() && 869 "KILL instructions should have been eliminated at this point."); 870 871 bool HasHazard = Candidate.isImplicitDef(); 872 873 HasHazard |= IM.hasHazard(Candidate); 874 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands()); 875 876 return HasHazard; 877 } 878 879 bool Filler::terminateSearch(const MachineInstr &Candidate) const { 880 return (Candidate.isTerminator() || Candidate.isCall() || 881 Candidate.isPosition() || Candidate.isInlineAsm() || 882 Candidate.hasUnmodeledSideEffects()); 883 } 884