1 /* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm) 2 instructions. 3 4 Copyright (C) 2011-2016 Free Software Foundation, Inc. 5 Contributed by ARM Ltd. 6 7 This file is part of GAS. 8 9 GAS is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the license, or 12 (at your option) any later version. 13 14 GAS is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING3. If not, 21 see <http://www.gnu.org/licenses/>. */ 22 23 /* Prefetch memory instruction is not tested here. 24 25 Also note that as a programmer-friendly assembler, GAS generates 26 LDUR/STUR instructions in response to the standard LDR/STR mnemonics 27 when the immediate offset is unambiguous, i.e. when it is negative 28 or unaligned. Similarly a disassembler could display these 29 instructions using the standard LDR/STR mnemonics when the encoded 30 immediate is negative or unaligned. However this behaviour is not 31 required by the architectural assembly language. */ 32 33 .macro op2_no_imm op, reg 34 \op \reg\()7, [sp] 35 .endm 36 37 .macro op2 op, reg, simm 38 \op \reg\()7, [sp, #\simm] 39 .endm 40 41 // load to or store from core register 42 // size is the access size in byte 43 .macro ld_or_st op, suffix, reg, size 44 .irp simm, -256, -171 45 op2 \op\suffix, \reg, \simm 46 .endr 47 op2_no_imm \op\suffix, \reg 48 .irp simm, 0, 2, 4, 8, 16, 85, 255 49 op2 \op\suffix, \reg, \simm 50 .endr 51 op2 \op\suffix, \reg, "(4095*\size)" 52 .endm 53 54 // load to or store from FP/SIMD register 55 .macro ld_or_st_v op 56 .irp reg, b, h, s, d, q 57 .irp simm, -256, -171 58 op2 \op, \reg, \simm 59 .endr 60 op2_no_imm \op, \reg 61 .irp simm, 0, 2, 4, 8, 16, 85, 255 62 op2 \op, \reg, \simm 63 .endr 64 .ifc \reg, b 65 op2 \op, \reg, 4095 66 .endif 67 .ifc \reg, h 68 op2 \op, \reg, 8190 69 .endif 70 .ifc \reg, s 71 op2 \op, \reg, 16380 72 .endif 73 .ifc \reg, d 74 op2 \op, \reg, 32760 75 .endif 76 .ifc \reg, q 77 op2 \op, \reg, 65520 78 .endif 79 .endr 80 .endm 81 82 func: 83 // load to or store from FP/SIMD register 84 ld_or_st_v str 85 ld_or_st_v ldr 86 87 // load to or store from core register 88 // op, suffix, reg, size(in byte) 89 ld_or_st str, b, w, 1 90 ld_or_st str, h, w, 2 91 ld_or_st str, , w, 4 92 ld_or_st str, , x, 8 93 ld_or_st ldr, b, w, 1 94 ld_or_st ldr, h, w, 2 95 ld_or_st ldr, , w, 4 96 ld_or_st ldr, , x, 8 97 ld_or_st ldr, sb, x, 1 98 ld_or_st ldr, sh, x, 2 99 ld_or_st ldr, sw, x, 4 100 ld_or_st ldr, sb, w, 1 101 ld_or_st ldr, sh, w, 2 102 103
