1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * BSC9132 QDS board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_MISC_INIT_R 14 15 #ifdef CONFIG_SDCARD 16 #define CONFIG_RAMBOOT_SDCARD 17 #define CONFIG_SYS_RAMBOOT 18 #define CONFIG_SYS_EXTRA_ENV_RELOC 19 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 20 #endif 21 #ifdef CONFIG_SPIFLASH 22 #define CONFIG_RAMBOOT_SPIFLASH 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 #ifdef CONFIG_NAND_SECBOOT 28 #define CONFIG_RAMBOOT_NAND 29 #define CONFIG_SYS_RAMBOOT 30 #define CONFIG_SYS_EXTRA_ENV_RELOC 31 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 32 #endif 33 34 #ifdef CONFIG_NAND 35 #define CONFIG_SPL_INIT_MINIMAL 36 #define CONFIG_SPL_NAND_BOOT 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 39 40 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 41 #define CONFIG_SPL_MAX_SIZE 8192 42 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 43 #define CONFIG_SPL_RELOC_STACK 0x00100000 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 45 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 53 #endif 54 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 57 #else 58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59 #endif 60 61 /* High Level Configuration Options */ 62 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 63 64 #if defined(CONFIG_PCI) 65 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 66 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 67 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 68 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 70 71 /* 72 * PCI Windows 73 * Memory space is mapped 1-1, but I/O space must start from 0. 74 */ 75 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 76 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 77 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 78 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 79 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 80 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 81 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 82 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 83 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 84 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 85 86 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 87 #endif 88 89 #define CONFIG_ENV_OVERWRITE 90 91 #if defined(CONFIG_SYS_CLK_100_DDR_100) 92 #define CONFIG_SYS_CLK_FREQ 100000000 93 #define CONFIG_DDR_CLK_FREQ 100000000 94 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 95 #define CONFIG_SYS_CLK_FREQ 100000000 96 #define CONFIG_DDR_CLK_FREQ 133000000 97 #endif 98 99 #define CONFIG_MP 100 101 #define CONFIG_HWCONFIG 102 /* 103 * These can be toggled for performance analysis, otherwise use default. 104 */ 105 #define CONFIG_L2_CACHE /* toggle L2 cache */ 106 #define CONFIG_BTB /* enable branch predition */ 107 108 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 109 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 110 111 /* DDR Setup */ 112 #define CONFIG_SYS_SPD_BUS_NUM 0 113 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 114 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 115 #define CONFIG_FSL_DDR_INTERACTIVE 116 117 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 118 119 #define CONFIG_SYS_SDRAM_SIZE (1024) 120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 123 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 124 125 /* DDR3 Controller Settings */ 126 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 127 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 128 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 129 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 130 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 131 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 132 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 133 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 134 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 135 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 136 137 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 138 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 139 #define CONFIG_SYS_DDR_RCW_1 0x00000000 140 #define CONFIG_SYS_DDR_RCW_2 0x00000000 141 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 142 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 143 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 144 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 145 146 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 147 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 148 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 149 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 150 151 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 152 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 153 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 154 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 155 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 156 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 157 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 158 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 159 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 160 161 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 162 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 163 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 164 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 165 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 166 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 167 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 168 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 169 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 170 171 /*FIXME: the following params are constant w.r.t diff freq 172 combinations. this should be removed later 173 */ 174 #if CONFIG_DDR_CLK_FREQ == 100000000 175 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 176 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 177 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 178 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 179 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 180 #elif CONFIG_DDR_CLK_FREQ == 133000000 181 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 182 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 183 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 184 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 185 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 186 #else 187 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 188 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 189 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 190 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 191 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 192 #endif 193 194 /* relocated CCSRBAR */ 195 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 196 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 197 198 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 199 200 /* DSP CCSRBAR */ 201 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 202 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 203 204 /* 205 * IFC Definitions 206 */ 207 /* NOR Flash on IFC */ 208 209 #define CONFIG_SYS_FLASH_BASE 0x88000000 210 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 211 212 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 213 214 #define CONFIG_SYS_NOR_CSPR 0x88000101 215 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 216 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 217 /* NOR Flash Timing Params */ 218 219 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 220 | FTIM0_NOR_TEADC(0x03) \ 221 | FTIM0_NOR_TAVDS(0x00) \ 222 | FTIM0_NOR_TEAHC(0x0f)) 223 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 224 | FTIM1_NOR_TRAD_NOR(0x09) \ 225 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 226 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 227 | FTIM2_NOR_TCH(0x4) \ 228 | FTIM2_NOR_TWPH(0x7) \ 229 | FTIM2_NOR_TWP(0x1e)) 230 #define CONFIG_SYS_NOR_FTIM3 0x0 231 232 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 233 #define CONFIG_SYS_FLASH_QUIET_TEST 234 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 235 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 236 237 #undef CONFIG_SYS_FLASH_CHECKSUM 238 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 239 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 240 241 /* CFI for NOR Flash */ 242 #define CONFIG_FLASH_CFI_DRIVER 243 #define CONFIG_SYS_FLASH_CFI 244 #define CONFIG_SYS_FLASH_EMPTY_INFO 245 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 246 247 /* NAND Flash on IFC */ 248 #define CONFIG_SYS_NAND_BASE 0xff800000 249 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 250 251 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 252 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 253 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 254 | CSPR_V) 255 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 256 257 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 258 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 259 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 260 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 261 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 262 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 263 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 264 265 /* NAND Flash Timing Params */ 266 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 267 | FTIM0_NAND_TWP(0x05) \ 268 | FTIM0_NAND_TWCHT(0x02) \ 269 | FTIM0_NAND_TWH(0x04)) 270 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 271 | FTIM1_NAND_TWBE(0x1e) \ 272 | FTIM1_NAND_TRR(0x07) \ 273 | FTIM1_NAND_TRP(0x05)) 274 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 275 | FTIM2_NAND_TREH(0x04) \ 276 | FTIM2_NAND_TWHRE(0x11)) 277 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 278 279 #define CONFIG_SYS_NAND_DDR_LAW 11 280 281 /* NAND */ 282 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 283 #define CONFIG_SYS_MAX_NAND_DEVICE 1 284 285 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 286 287 #ifndef CONFIG_SPL_BUILD 288 #define CONFIG_FSL_QIXIS 289 #endif 290 #ifdef CONFIG_FSL_QIXIS 291 #define CONFIG_SYS_FPGA_BASE 0xffb00000 292 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 293 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 294 #define QIXIS_LBMAP_SWITCH 9 295 #define QIXIS_LBMAP_MASK 0x07 296 #define QIXIS_LBMAP_SHIFT 0 297 #define QIXIS_LBMAP_DFLTBANK 0x00 298 #define QIXIS_LBMAP_ALTBANK 0x04 299 #define QIXIS_RST_CTL_RESET 0x83 300 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 301 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 302 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 303 304 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 305 306 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 307 | CSPR_PORT_SIZE_8 \ 308 | CSPR_MSEL_GPCM \ 309 | CSPR_V) 310 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 311 #define CONFIG_SYS_CSOR2 0x0 312 /* CPLD Timing parameters for IFC CS3 */ 313 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 314 FTIM0_GPCM_TEADC(0x0e) | \ 315 FTIM0_GPCM_TEAHC(0x0e)) 316 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 317 FTIM1_GPCM_TRAD(0x1f)) 318 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 319 FTIM2_GPCM_TCH(0x8) | \ 320 FTIM2_GPCM_TWP(0x1f)) 321 #define CONFIG_SYS_CS2_FTIM3 0x0 322 #endif 323 324 /* Set up IFC registers for boot location NOR/NAND */ 325 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 326 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 327 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 328 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 329 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 330 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 331 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 332 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #else 341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 349 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 350 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 351 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 352 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 353 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 354 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 355 #endif 356 357 #define CONFIG_SYS_INIT_RAM_LOCK 358 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 359 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 360 361 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 362 - GENERATED_GBL_DATA_SIZE) 363 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 364 365 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 366 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 367 368 /* Serial Port */ 369 #undef CONFIG_SERIAL_SOFTWARE_FIFO 370 #define CONFIG_SYS_NS16550_SERIAL 371 #define CONFIG_SYS_NS16550_REG_SIZE 1 372 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 373 #ifdef CONFIG_SPL_BUILD 374 #define CONFIG_NS16550_MIN_FUNCTIONS 375 #endif 376 377 #define CONFIG_SYS_BAUDRATE_TABLE \ 378 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 379 380 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 381 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 382 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 383 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 384 385 #define CONFIG_SYS_I2C 386 #define CONFIG_SYS_I2C_FSL 387 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 388 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 389 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 390 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 391 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 392 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 393 394 /* I2C EEPROM */ 395 #define CONFIG_ID_EEPROM 396 #ifdef CONFIG_ID_EEPROM 397 #define CONFIG_SYS_I2C_EEPROM_NXID 398 #endif 399 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 400 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 401 #define CONFIG_SYS_EEPROM_BUS_NUM 0 402 403 /* enable read and write access to EEPROM */ 404 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 405 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 406 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 407 408 /* I2C FPGA */ 409 #define CONFIG_I2C_FPGA 410 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 411 412 #define CONFIG_RTC_DS3231 413 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 414 415 /* 416 * SPI interface will not be available in case of NAND boot SPI CS0 will be 417 * used for SLIC 418 */ 419 /* eSPI - Enhanced SPI */ 420 #ifdef CONFIG_FSL_ESPI 421 #define CONFIG_SF_DEFAULT_SPEED 10000000 422 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 423 #endif 424 425 #if defined(CONFIG_TSEC_ENET) 426 427 #define CONFIG_MII /* MII PHY management */ 428 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 429 #define CONFIG_TSEC1 1 430 #define CONFIG_TSEC1_NAME "eTSEC1" 431 #define CONFIG_TSEC2 1 432 #define CONFIG_TSEC2_NAME "eTSEC2" 433 434 #define TSEC1_PHY_ADDR 0 435 #define TSEC2_PHY_ADDR 1 436 437 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 438 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 439 440 #define TSEC1_PHYIDX 0 441 #define TSEC2_PHYIDX 0 442 443 #define CONFIG_ETHPRIME "eTSEC1" 444 445 /* TBI PHY configuration for SGMII mode */ 446 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 447 TBICR_PHY_RESET \ 448 | TBICR_ANEG_ENABLE \ 449 | TBICR_FULL_DUPLEX \ 450 | TBICR_SPEED1_SET \ 451 ) 452 453 #endif /* CONFIG_TSEC_ENET */ 454 455 #ifdef CONFIG_MMC 456 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 457 #endif 458 459 #ifdef CONFIG_USB_EHCI_HCD 460 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 461 #define CONFIG_USB_EHCI_FSL 462 #define CONFIG_HAS_FSL_DR_USB 463 #endif 464 465 /* 466 * Environment 467 */ 468 #if defined(CONFIG_RAMBOOT_SDCARD) 469 #define CONFIG_FSL_FIXED_MMC_LOCATION 470 #define CONFIG_SYS_MMC_ENV_DEV 0 471 #define CONFIG_ENV_SIZE 0x2000 472 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 473 #define CONFIG_ENV_SPI_BUS 0 474 #define CONFIG_ENV_SPI_CS 0 475 #define CONFIG_ENV_SPI_MAX_HZ 10000000 476 #define CONFIG_ENV_SPI_MODE 0 477 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 478 #define CONFIG_ENV_SECT_SIZE 0x10000 479 #define CONFIG_ENV_SIZE 0x2000 480 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 481 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 482 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 483 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 484 #elif defined(CONFIG_SYS_RAMBOOT) 485 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 486 #define CONFIG_ENV_SIZE 0x2000 487 #else 488 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 489 #define CONFIG_ENV_SIZE 0x2000 490 #define CONFIG_ENV_SECT_SIZE 0x20000 491 #endif 492 493 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 494 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 495 496 /* 497 * Miscellaneous configurable options 498 */ 499 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 500 501 /* 502 * For booting Linux, the board info and command line data 503 * have to be in the first 64 MB of memory, since this is 504 * the maximum mapped by the Linux kernel during initialization. 505 */ 506 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 507 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 508 509 #if defined(CONFIG_CMD_KGDB) 510 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 511 #endif 512 513 /* 514 * Dynamic MTD Partition support with mtdparts 515 */ 516 #ifdef CONFIG_MTD_NOR_FLASH 517 #define CONFIG_MTD_DEVICE 518 #define CONFIG_MTD_PARTITIONS 519 #define CONFIG_FLASH_CFI_MTD 520 #endif 521 /* 522 * Environment Configuration 523 */ 524 525 #if defined(CONFIG_TSEC_ENET) 526 #define CONFIG_HAS_ETH0 527 #define CONFIG_HAS_ETH1 528 #endif 529 530 #define CONFIG_HOSTNAME "BSC9132qds" 531 #define CONFIG_ROOTPATH "/opt/nfsroot" 532 #define CONFIG_BOOTFILE "uImage" 533 #define CONFIG_UBOOTPATH "u-boot.bin" 534 535 #ifdef CONFIG_SDCARD 536 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 537 #else 538 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 539 #endif 540 541 #define CONFIG_EXTRA_ENV_SETTINGS \ 542 "netdev=eth0\0" \ 543 "uboot=" CONFIG_UBOOTPATH "\0" \ 544 "loadaddr=1000000\0" \ 545 "bootfile=uImage\0" \ 546 "consoledev=ttyS0\0" \ 547 "ramdiskaddr=2000000\0" \ 548 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 549 "fdtaddr=1e00000\0" \ 550 "fdtfile=bsc9132qds.dtb\0" \ 551 "bdev=sda1\0" \ 552 CONFIG_DEF_HWCONFIG\ 553 "othbootargs=mem=880M ramdisk_size=600000 " \ 554 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 555 "isolcpus=0\0" \ 556 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 557 "console=$consoledev,$baudrate $othbootargs; " \ 558 "usb start;" \ 559 "ext2load usb 0:4 $loadaddr $bootfile;" \ 560 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 561 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 562 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 563 "debug_halt_off=mw ff7e0e30 0xf0000000;" 564 565 #define CONFIG_NFSBOOTCOMMAND \ 566 "setenv bootargs root=/dev/nfs rw " \ 567 "nfsroot=$serverip:$rootpath " \ 568 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 569 "console=$consoledev,$baudrate $othbootargs;" \ 570 "tftp $loadaddr $bootfile;" \ 571 "tftp $fdtaddr $fdtfile;" \ 572 "bootm $loadaddr - $fdtaddr" 573 574 #define CONFIG_HDBOOT \ 575 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 576 "console=$consoledev,$baudrate $othbootargs;" \ 577 "usb start;" \ 578 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 579 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 580 "bootm $loadaddr - $fdtaddr" 581 582 #define CONFIG_RAMBOOTCOMMAND \ 583 "setenv bootargs root=/dev/ram rw " \ 584 "console=$consoledev,$baudrate $othbootargs; " \ 585 "tftp $ramdiskaddr $ramdiskfile;" \ 586 "tftp $loadaddr $bootfile;" \ 587 "tftp $fdtaddr $fdtfile;" \ 588 "bootm $loadaddr $ramdiskaddr $fdtaddr" 589 590 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 591 592 #include <asm/fsl_secure_boot.h> 593 594 #endif /* __CONFIG_H */ 595
