| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRAsmPrinter.cpp | 119 unsigned RegIdx = ByteNumber / BytesPerReg;
120 assert(RegIdx < NumOpRegs && "Multibyte index out of range.");
122 Reg = MI->getOperand(OpNum + RegIdx).getReg();
|
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 210 unsigned RegIdx = State.getFirstUnallocated(RegList);
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
216 State.AllocateReg(RegList[RegIdx++]);
251 unsigned RegIdx = State.getFirstUnallocated(RegList);
253 if (RegIdx >= RegList.size())
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
|
| ARMISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 503 int RegIdx = mapRegToGPRIndex(LI.PhysReg);
504 if (RegIdx >= 0)
505 LOHInfos[RegIdx].OneUser = true;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 210 unsigned RegIdx = State.getFirstUnallocated(RegList);
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
216 State.AllocateReg(RegList[RegIdx++]);
254 unsigned RegIdx = State.getFirstUnallocated(RegList);
256 if (RegIdx >= RegList.size())
259 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| DetectDeadLanes.cpp | 114 void PutInWorklist(unsigned RegIdx) {
115 if (WorklistMembers.test(RegIdx))
117 WorklistMembers.set(RegIdx);
118 Worklist.push_back(RegIdx);
366 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
367 DefinedByCopy.set(RegIdx);
368 PutInWorklist(RegIdx);
499 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
[all...] |
| SplitKit.cpp | 384 VNInfo *SplitEditor::defValue(unsigned RegIdx,
390 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
397 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
400 // This was the first time (RegIdx, ParentVNI) was mapped.
420 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
422 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
435 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
441 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
448 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
451 // so always begin RegIdx 0 early and all others late
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 615 int RegIdx = BaseRegIdx + Offset;
616 if (RegIdx < 0) {
617 Offset = RegIdx;
618 RegIdx = 0;
623 unsigned Reg = RC->getRegister(RegIdx);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| DetectDeadLanes.cpp | 113 void PutInWorklist(unsigned RegIdx) {
114 if (WorklistMembers.test(RegIdx))
116 WorklistMembers.set(RegIdx);
117 Worklist.push_back(RegIdx);
364 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
365 DefinedByCopy.set(RegIdx);
366 PutInWorklist(RegIdx);
497 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
[all...] |
| SplitKit.cpp | 457 VNInfo *SplitEditor::defValue(unsigned RegIdx,
464 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
473 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP));
475 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not
494 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) {
495 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)];
507 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false);
540 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
553 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx));
627 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 236 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
275 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen.
279 RegIdx -= 112; // Trap temps start at offset 112. TODO: Get this from tablegen.
286 O << RegIdx;
290 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 72 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
73 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
821 SDValue RegIdx = Node->getOperand(2);
823 getMSACtrlReg(RegIdx), MVT::i32);
854 SDValue RegIdx = Node->getOperand(2);
857 getMSACtrlReg(RegIdx), Value);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| SplitKit.cpp | 345 VNInfo *SplitEditor::defValue(unsigned RegIdx,
351 LiveInterval *LI = Edit->get(RegIdx);
358 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
361 // This was the first time (RegIdx, ParentVNI) was mapped.
381 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
383 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
396 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
401 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
408 LiveInterval *LI = Edit->get(RegIdx);
411 // so always begin RegIdx 0 early and all others late
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 325 unsigned RegIdx = MRI.getEncodingValue(RegNo) & ((1 << 8) - 1);
367 O << RegIdx;
371 O << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
79 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
876 SDValue RegIdx = Node->getOperand(2);
878 getMSACtrlReg(RegIdx), MVT::i32);
909 SDValue RegIdx = Node->getOperand(2);
912 getMSACtrlReg(RegIdx), Value);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 722 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
724 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 626 struct RegIdxOp RegIdx;
640 Op->RegIdx.Index = Index;
641 Op->RegIdx.RegInfo = RegInfo;
642 Op->RegIdx.Kind = RegKind;
652 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
653 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
655 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
661 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
663 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 817 struct RegIdxOp RegIdx;
832 Op->RegIdx.Index = Index;
833 Op->RegIdx.RegInfo = RegInfo;
834 Op->RegIdx.Kind = RegKind;
835 Op->RegIdx.Tok.Data = Str.data();
836 Op->RegIdx.Tok.Length = Str.size();
846 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
847 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
849 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
