| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| VectorUtils.h | 129 /// This function creates a shuffle mask for interleaving \p NumVecs vectors of
133 /// <0, VF, VF * 2, ..., VF * (NumVecs - 1), 1, VF + 1, VF * 2 + 1, ...>
135 /// For example, the mask for VF = 4 and NumVecs = 2 is:
139 unsigned NumVecs);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| VectorUtils.cpp | 495 unsigned NumVecs) {
498 for (unsigned j = 0; j < NumVecs; j++)
553 unsigned NumVecs = Vecs.size();
554 assert(NumVecs > 1 && "Should be at least two vectors");
560 for (unsigned i = 0; i < NumVecs - 1; i += 2) {
562 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
569 if (NumVecs % 2 != 0)
570 TmpList.push_back(ResList[NumVecs - 1]);
573 NumVecs = ResList.size();
574 } while (NumVecs > 1)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 208 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
216 /// SelectVST - Select NEON store intrinsics. NumVecs should
219 /// For NumVecs <= 2, QOpcodes1 is not used.
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
228 bool isUpdating, unsigned NumVecs,
231 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 200 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
203 /// For NumVecs <= 2, QOpcodes1 is not used.
204 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
208 /// SelectVST - Select NEON store intrinsics. NumVecs should
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
216 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
220 unsigned NumVecs, const uint16_t *DOpcodes,
223 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
226 void SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 181 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
184 /// For NumVecs <= 2, QOpcodes1 is not used.
185 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
189 /// SelectVST - Select NEON store intrinsics. NumVecs should
192 /// For NumVecs <= 2, QOpcodes1 is not used.
193 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
197 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
201 unsigned NumVecs, const uint16_t *DOpcodes,
204 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
208 unsigned NumVecs, const uint16_t *DOpcodes
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 150 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 151 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
155 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
157 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
159 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
160 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
165 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
[all...] |
| AArch64ISelLowering.cpp | [all...] |
