1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86INSTRUCTIONINFO_H 15 #define X86INSTRUCTIONINFO_H 16 17 #include "llvm/Target/TargetInstrInfo.h" 18 #include "X86.h" 19 #include "X86RegisterInfo.h" 20 #include "llvm/ADT/DenseMap.h" 21 22 #define GET_INSTRINFO_HEADER 23 #include "X86GenInstrInfo.inc" 24 25 namespace llvm { 26 class X86RegisterInfo; 27 class X86TargetMachine; 28 29 namespace X86 { 30 // Enums for memory operand decoding. Each memory operand is represented with 31 // a 5 operand sequence in the form: 32 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 33 // These enums help decode this. 34 enum { 35 AddrBaseReg = 0, 36 AddrScaleAmt = 1, 37 AddrIndexReg = 2, 38 AddrDisp = 3, 39 40 /// AddrSegmentReg - The operand # of the segment in the memory operand. 41 AddrSegmentReg = 4, 42 43 /// AddrNumOperands - Total number of operands in a memory reference. 44 AddrNumOperands = 5 45 }; 46 47 48 // X86 specific condition code. These correspond to X86_*_COND in 49 // X86InstrInfo.td. They must be kept in synch. 50 enum CondCode { 51 COND_A = 0, 52 COND_AE = 1, 53 COND_B = 2, 54 COND_BE = 3, 55 COND_E = 4, 56 COND_G = 5, 57 COND_GE = 6, 58 COND_L = 7, 59 COND_LE = 8, 60 COND_NE = 9, 61 COND_NO = 10, 62 COND_NP = 11, 63 COND_NS = 12, 64 COND_O = 13, 65 COND_P = 14, 66 COND_S = 15, 67 68 // Artificial condition codes. These are used by AnalyzeBranch 69 // to indicate a block terminated with two conditional branches to 70 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 71 // which can't be represented on x86 with a single condition. These 72 // are never used in MachineInstrs. 73 COND_NE_OR_P, 74 COND_NP_OR_E, 75 76 COND_INVALID 77 }; 78 79 // Turn condition code into conditional branch opcode. 80 unsigned GetCondBranchFromCond(CondCode CC); 81 82 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 83 /// e.g. turning COND_E to COND_NE. 84 CondCode GetOppositeBranchCondition(X86::CondCode CC); 85 86 } 87 88 /// X86II - This namespace holds all of the target specific flags that 89 /// instruction info tracks. 90 /// 91 namespace X86II { 92 /// Target Operand Flag enum. 93 enum TOF { 94 //===------------------------------------------------------------------===// 95 // X86 Specific MachineOperand flags. 96 97 MO_NO_FLAG, 98 99 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 100 /// relocation of: 101 /// SYMBOL_LABEL + [. - PICBASELABEL] 102 MO_GOT_ABSOLUTE_ADDRESS, 103 104 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 105 /// immediate should get the value of the symbol minus the PIC base label: 106 /// SYMBOL_LABEL - PICBASELABEL 107 MO_PIC_BASE_OFFSET, 108 109 /// MO_GOT - On a symbol operand this indicates that the immediate is the 110 /// offset to the GOT entry for the symbol name from the base of the GOT. 111 /// 112 /// See the X86-64 ELF ABI supplement for more details. 113 /// SYMBOL_LABEL @GOT 114 MO_GOT, 115 116 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 117 /// the offset to the location of the symbol name from the base of the GOT. 118 /// 119 /// See the X86-64 ELF ABI supplement for more details. 120 /// SYMBOL_LABEL @GOTOFF 121 MO_GOTOFF, 122 123 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 124 /// offset to the GOT entry for the symbol name from the current code 125 /// location. 126 /// 127 /// See the X86-64 ELF ABI supplement for more details. 128 /// SYMBOL_LABEL @GOTPCREL 129 MO_GOTPCREL, 130 131 /// MO_PLT - On a symbol operand this indicates that the immediate is 132 /// offset to the PLT entry of symbol name from the current code location. 133 /// 134 /// See the X86-64 ELF ABI supplement for more details. 135 /// SYMBOL_LABEL @PLT 136 MO_PLT, 137 138 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 139 /// some TLS offset. 140 /// 141 /// See 'ELF Handling for Thread-Local Storage' for more details. 142 /// SYMBOL_LABEL @TLSGD 143 MO_TLSGD, 144 145 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 146 /// some TLS offset. 147 /// 148 /// See 'ELF Handling for Thread-Local Storage' for more details. 149 /// SYMBOL_LABEL @GOTTPOFF 150 MO_GOTTPOFF, 151 152 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 153 /// some TLS offset. 154 /// 155 /// See 'ELF Handling for Thread-Local Storage' for more details. 156 /// SYMBOL_LABEL @INDNTPOFF 157 MO_INDNTPOFF, 158 159 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 160 /// some TLS offset. 161 /// 162 /// See 'ELF Handling for Thread-Local Storage' for more details. 163 /// SYMBOL_LABEL @TPOFF 164 MO_TPOFF, 165 166 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 167 /// some TLS offset. 168 /// 169 /// See 'ELF Handling for Thread-Local Storage' for more details. 170 /// SYMBOL_LABEL @NTPOFF 171 MO_NTPOFF, 172 173 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 174 /// reference is actually to the "__imp_FOO" symbol. This is used for 175 /// dllimport linkage on windows. 176 MO_DLLIMPORT, 177 178 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 179 /// reference is actually to the "FOO$stub" symbol. This is used for calls 180 /// and jumps to external functions on Tiger and earlier. 181 MO_DARWIN_STUB, 182 183 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 184 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 185 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 186 MO_DARWIN_NONLAZY, 187 188 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 189 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 190 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 191 MO_DARWIN_NONLAZY_PIC_BASE, 192 193 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 194 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 195 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 196 /// stub. 197 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 198 199 /// MO_TLVP - On a symbol operand this indicates that the immediate is 200 /// some TLS offset. 201 /// 202 /// This is the TLS offset for the Darwin TLS mechanism. 203 MO_TLVP, 204 205 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 206 /// is some TLS offset from the picbase. 207 /// 208 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 209 MO_TLVP_PIC_BASE 210 }; 211 } 212 213 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 214 /// a reference to a stub for a global, not the global itself. 215 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 216 switch (TargetFlag) { 217 case X86II::MO_DLLIMPORT: // dllimport stub. 218 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 219 case X86II::MO_GOT: // normal GOT reference. 220 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 221 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 222 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 223 return true; 224 default: 225 return false; 226 } 227 } 228 229 /// isGlobalRelativeToPICBase - Return true if the specified global value 230 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 231 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 232 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 233 switch (TargetFlag) { 234 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 235 case X86II::MO_GOT: // isPICStyleGOT: other global. 236 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 237 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 238 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 239 case X86II::MO_TLVP: // ??? Pretty sure.. 240 return true; 241 default: 242 return false; 243 } 244 } 245 246 /// X86II - This namespace holds all of the target specific flags that 247 /// instruction info tracks. 248 /// 249 namespace X86II { 250 enum { 251 //===------------------------------------------------------------------===// 252 // Instruction encodings. These are the standard/most common forms for X86 253 // instructions. 254 // 255 256 // PseudoFrm - This represents an instruction that is a pseudo instruction 257 // or one that has not been implemented yet. It is illegal to code generate 258 // it, but tolerated for intermediate implementation stages. 259 Pseudo = 0, 260 261 /// Raw - This form is for instructions that don't have any operands, so 262 /// they are just a fixed opcode value, like 'leave'. 263 RawFrm = 1, 264 265 /// AddRegFrm - This form is used for instructions like 'push r32' that have 266 /// their one register operand added to their opcode. 267 AddRegFrm = 2, 268 269 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 270 /// to specify a destination, which in this case is a register. 271 /// 272 MRMDestReg = 3, 273 274 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 275 /// to specify a destination, which in this case is memory. 276 /// 277 MRMDestMem = 4, 278 279 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 280 /// to specify a source, which in this case is a register. 281 /// 282 MRMSrcReg = 5, 283 284 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 285 /// to specify a source, which in this case is memory. 286 /// 287 MRMSrcMem = 6, 288 289 /// MRM[0-7][rm] - These forms are used to represent instructions that use 290 /// a Mod/RM byte, and use the middle field to hold extended opcode 291 /// information. In the intel manual these are represented as /0, /1, ... 292 /// 293 294 // First, instructions that operate on a register r/m operand... 295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 297 298 // Next, instructions that operate on a memory r/m operand... 299 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 300 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 301 302 // MRMInitReg - This form is used for instructions whose source and 303 // destinations are the same register. 304 MRMInitReg = 32, 305 306 //// MRM_C1 - A mod/rm byte of exactly 0xC1. 307 MRM_C1 = 33, 308 MRM_C2 = 34, 309 MRM_C3 = 35, 310 MRM_C4 = 36, 311 MRM_C8 = 37, 312 MRM_C9 = 38, 313 MRM_E8 = 39, 314 MRM_F0 = 40, 315 MRM_F8 = 41, 316 MRM_F9 = 42, 317 MRM_D0 = 45, 318 MRM_D1 = 46, 319 320 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 321 /// immediates, the first of which is a 16-bit immediate (specified by 322 /// the imm encoding) and the second is a 8-bit fixed value. 323 RawFrmImm8 = 43, 324 325 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 326 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 327 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 328 /// manual, this operand is described as pntr16:32 and pntr16:16 329 RawFrmImm16 = 44, 330 331 FormMask = 63, 332 333 //===------------------------------------------------------------------===// 334 // Actual flags... 335 336 // OpSize - Set if this instruction requires an operand size prefix (0x66), 337 // which most often indicates that the instruction operates on 16 bit data 338 // instead of 32 bit data. 339 OpSize = 1 << 6, 340 341 // AsSize - Set if this instruction requires an operand size prefix (0x67), 342 // which most often indicates that the instruction address 16 bit address 343 // instead of 32 bit address (or 32 bit address in 64 bit mode). 344 AdSize = 1 << 7, 345 346 //===------------------------------------------------------------------===// 347 // Op0Mask - There are several prefix bytes that are used to form two byte 348 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 349 // used to obtain the setting of this field. If no bits in this field is 350 // set, there is no prefix byte for obtaining a multibyte opcode. 351 // 352 Op0Shift = 8, 353 Op0Mask = 0x1F << Op0Shift, 354 355 // TB - TwoByte - Set if this instruction has a two byte opcode, which 356 // starts with a 0x0F byte before the real opcode. 357 TB = 1 << Op0Shift, 358 359 // REP - The 0xF3 prefix byte indicating repetition of the following 360 // instruction. 361 REP = 2 << Op0Shift, 362 363 // D8-DF - These escape opcodes are used by the floating point unit. These 364 // values must remain sequential. 365 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 366 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 367 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 368 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 369 370 // XS, XD - These prefix codes are for single and double precision scalar 371 // floating point operations performed in the SSE registers. 372 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 373 374 // T8, TA, A6, A7 - Prefix after the 0x0F prefix. 375 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 376 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, 377 378 // TF - Prefix before and after 0x0F 379 TF = 17 << Op0Shift, 380 381 //===------------------------------------------------------------------===// 382 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 383 // They are used to specify GPRs and SSE registers, 64-bit operand size, 384 // etc. We only cares about REX.W and REX.R bits and only the former is 385 // statically determined. 386 // 387 REXShift = Op0Shift + 5, 388 REX_W = 1 << REXShift, 389 390 //===------------------------------------------------------------------===// 391 // This three-bit field describes the size of an immediate operand. Zero is 392 // unused so that we can tell if we forgot to set a value. 393 ImmShift = REXShift + 1, 394 ImmMask = 7 << ImmShift, 395 Imm8 = 1 << ImmShift, 396 Imm8PCRel = 2 << ImmShift, 397 Imm16 = 3 << ImmShift, 398 Imm16PCRel = 4 << ImmShift, 399 Imm32 = 5 << ImmShift, 400 Imm32PCRel = 6 << ImmShift, 401 Imm64 = 7 << ImmShift, 402 403 //===------------------------------------------------------------------===// 404 // FP Instruction Classification... Zero is non-fp instruction. 405 406 // FPTypeMask - Mask for all of the FP types... 407 FPTypeShift = ImmShift + 3, 408 FPTypeMask = 7 << FPTypeShift, 409 410 // NotFP - The default, set for instructions that do not use FP registers. 411 NotFP = 0 << FPTypeShift, 412 413 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 414 ZeroArgFP = 1 << FPTypeShift, 415 416 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 417 OneArgFP = 2 << FPTypeShift, 418 419 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 420 // result back to ST(0). For example, fcos, fsqrt, etc. 421 // 422 OneArgFPRW = 3 << FPTypeShift, 423 424 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 425 // explicit argument, storing the result to either ST(0) or the implicit 426 // argument. For example: fadd, fsub, fmul, etc... 427 TwoArgFP = 4 << FPTypeShift, 428 429 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 430 // explicit argument, but have no destination. Example: fucom, fucomi, ... 431 CompareFP = 5 << FPTypeShift, 432 433 // CondMovFP - "2 operand" floating point conditional move instructions. 434 CondMovFP = 6 << FPTypeShift, 435 436 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 437 SpecialFP = 7 << FPTypeShift, 438 439 // Lock prefix 440 LOCKShift = FPTypeShift + 3, 441 LOCK = 1 << LOCKShift, 442 443 // Segment override prefixes. Currently we just need ability to address 444 // stuff in gs and fs segments. 445 SegOvrShift = LOCKShift + 1, 446 SegOvrMask = 3 << SegOvrShift, 447 FS = 1 << SegOvrShift, 448 GS = 2 << SegOvrShift, 449 450 // Execution domain for SSE instructions in bits 23, 24. 451 // 0 in bits 23-24 means normal, non-SSE instruction. 452 SSEDomainShift = SegOvrShift + 2, 453 454 OpcodeShift = SSEDomainShift + 2, 455 456 //===------------------------------------------------------------------===// 457 /// VEX - The opcode prefix used by AVX instructions 458 VEXShift = OpcodeShift + 8, 459 VEX = 1U << 0, 460 461 /// VEX_W - Has a opcode specific functionality, but is used in the same 462 /// way as REX_W is for regular SSE instructions. 463 VEX_W = 1U << 1, 464 465 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 466 /// address instructions in SSE are represented as 3 address ones in AVX 467 /// and the additional register is encoded in VEX_VVVV prefix. 468 VEX_4V = 1U << 2, 469 470 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 471 /// must be encoded in the i8 immediate field. This usually happens in 472 /// instructions with 4 operands. 473 VEX_I8IMM = 1U << 3, 474 475 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 476 /// instruction uses 256-bit wide registers. This is usually auto detected 477 /// if a VR256 register is used, but some AVX instructions also have this 478 /// field marked when using a f256 memory references. 479 VEX_L = 1U << 4, 480 481 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 482 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 483 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 484 /// storing a classifier in the imm8 field. To simplify our implementation, 485 /// we handle this by storeing the classifier in the opcode field and using 486 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 487 Has3DNow0F0FOpcode = 1U << 5 488 }; 489 490 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 491 // specified machine instruction. 492 // 493 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 494 return TSFlags >> X86II::OpcodeShift; 495 } 496 497 static inline bool hasImm(uint64_t TSFlags) { 498 return (TSFlags & X86II::ImmMask) != 0; 499 } 500 501 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 502 /// of the specified instruction. 503 static inline unsigned getSizeOfImm(uint64_t TSFlags) { 504 switch (TSFlags & X86II::ImmMask) { 505 default: assert(0 && "Unknown immediate size"); 506 case X86II::Imm8: 507 case X86II::Imm8PCRel: return 1; 508 case X86II::Imm16: 509 case X86II::Imm16PCRel: return 2; 510 case X86II::Imm32: 511 case X86II::Imm32PCRel: return 4; 512 case X86II::Imm64: return 8; 513 } 514 } 515 516 /// isImmPCRel - Return true if the immediate of the specified instruction's 517 /// TSFlags indicates that it is pc relative. 518 static inline unsigned isImmPCRel(uint64_t TSFlags) { 519 switch (TSFlags & X86II::ImmMask) { 520 default: assert(0 && "Unknown immediate size"); 521 case X86II::Imm8PCRel: 522 case X86II::Imm16PCRel: 523 case X86II::Imm32PCRel: 524 return true; 525 case X86II::Imm8: 526 case X86II::Imm16: 527 case X86II::Imm32: 528 case X86II::Imm64: 529 return false; 530 } 531 } 532 533 /// getMemoryOperandNo - The function returns the MCInst operand # for the 534 /// first field of the memory operand. If the instruction doesn't have a 535 /// memory operand, this returns -1. 536 /// 537 /// Note that this ignores tied operands. If there is a tied register which 538 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 539 /// counted as one operand. 540 /// 541 static inline int getMemoryOperandNo(uint64_t TSFlags) { 542 switch (TSFlags & X86II::FormMask) { 543 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); 544 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); 545 case X86II::Pseudo: 546 case X86II::RawFrm: 547 case X86II::AddRegFrm: 548 case X86II::MRMDestReg: 549 case X86II::MRMSrcReg: 550 case X86II::RawFrmImm8: 551 case X86II::RawFrmImm16: 552 return -1; 553 case X86II::MRMDestMem: 554 return 0; 555 case X86II::MRMSrcMem: { 556 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 557 unsigned FirstMemOp = 1; 558 if (HasVEX_4V) 559 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 560 561 // FIXME: Maybe lea should have its own form? This is a horrible hack. 562 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 563 // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 564 return FirstMemOp; 565 } 566 case X86II::MRM0r: case X86II::MRM1r: 567 case X86II::MRM2r: case X86II::MRM3r: 568 case X86II::MRM4r: case X86II::MRM5r: 569 case X86II::MRM6r: case X86II::MRM7r: 570 return -1; 571 case X86II::MRM0m: case X86II::MRM1m: 572 case X86II::MRM2m: case X86II::MRM3m: 573 case X86II::MRM4m: case X86II::MRM5m: 574 case X86II::MRM6m: case X86II::MRM7m: 575 return 0; 576 case X86II::MRM_C1: 577 case X86II::MRM_C2: 578 case X86II::MRM_C3: 579 case X86II::MRM_C4: 580 case X86II::MRM_C8: 581 case X86II::MRM_C9: 582 case X86II::MRM_E8: 583 case X86II::MRM_F0: 584 case X86II::MRM_F8: 585 case X86II::MRM_F9: 586 case X86II::MRM_D0: 587 case X86II::MRM_D1: 588 return -1; 589 } 590 } 591 } 592 593 inline static bool isScale(const MachineOperand &MO) { 594 return MO.isImm() && 595 (MO.getImm() == 1 || MO.getImm() == 2 || 596 MO.getImm() == 4 || MO.getImm() == 8); 597 } 598 599 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 600 if (MI->getOperand(Op).isFI()) return true; 601 return Op+4 <= MI->getNumOperands() && 602 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && 603 MI->getOperand(Op+2).isReg() && 604 (MI->getOperand(Op+3).isImm() || 605 MI->getOperand(Op+3).isGlobal() || 606 MI->getOperand(Op+3).isCPI() || 607 MI->getOperand(Op+3).isJTI()); 608 } 609 610 inline static bool isMem(const MachineInstr *MI, unsigned Op) { 611 if (MI->getOperand(Op).isFI()) return true; 612 return Op+5 <= MI->getNumOperands() && 613 MI->getOperand(Op+4).isReg() && 614 isLeaMem(MI, Op); 615 } 616 617 class X86InstrInfo : public X86GenInstrInfo { 618 X86TargetMachine &TM; 619 const X86RegisterInfo RI; 620 621 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 622 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 623 /// 624 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr; 625 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable0; 626 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable1; 627 DenseMap<unsigned, std::pair<unsigned,unsigned> > RegOp2MemOpTable2; 628 629 /// MemOp2RegOpTable - Load / store unfolding opcode map. 630 /// 631 DenseMap<unsigned, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 632 633 public: 634 explicit X86InstrInfo(X86TargetMachine &tm); 635 636 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 637 /// such, whenever a client has an instance of instruction info, it should 638 /// always be able to get register info as well (through this method). 639 /// 640 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 641 642 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 643 /// extension instruction. That is, it's like a copy where it's legal for the 644 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 645 /// true, then it's expected the pre-extension value is available as a subreg 646 /// of the result register. This also returns the sub-register index in 647 /// SubIdx. 648 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 649 unsigned &SrcReg, unsigned &DstReg, 650 unsigned &SubIdx) const; 651 652 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 653 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 654 /// stack locations as well. This uses a heuristic so it isn't 655 /// reliable for correctness. 656 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 657 int &FrameIndex) const; 658 659 /// hasLoadFromStackSlot - If the specified machine instruction has 660 /// a load from a stack slot, return true along with the FrameIndex 661 /// of the loaded stack slot and the machine mem operand containing 662 /// the reference. If not, return false. Unlike 663 /// isLoadFromStackSlot, this returns true for any instructions that 664 /// loads from the stack. This is a hint only and may not catch all 665 /// cases. 666 bool hasLoadFromStackSlot(const MachineInstr *MI, 667 const MachineMemOperand *&MMO, 668 int &FrameIndex) const; 669 670 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; 671 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 672 /// stack locations as well. This uses a heuristic so it isn't 673 /// reliable for correctness. 674 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 675 int &FrameIndex) const; 676 677 /// hasStoreToStackSlot - If the specified machine instruction has a 678 /// store to a stack slot, return true along with the FrameIndex of 679 /// the loaded stack slot and the machine mem operand containing the 680 /// reference. If not, return false. Unlike isStoreToStackSlot, 681 /// this returns true for any instructions that loads from the 682 /// stack. This is a hint only and may not catch all cases. 683 bool hasStoreToStackSlot(const MachineInstr *MI, 684 const MachineMemOperand *&MMO, 685 int &FrameIndex) const; 686 687 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 688 AliasAnalysis *AA) const; 689 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 690 unsigned DestReg, unsigned SubIdx, 691 const MachineInstr *Orig, 692 const TargetRegisterInfo &TRI) const; 693 694 /// convertToThreeAddress - This method must be implemented by targets that 695 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 696 /// may be able to convert a two-address instruction into a true 697 /// three-address instruction on demand. This allows the X86 target (for 698 /// example) to convert ADD and SHL instructions into LEA instructions if they 699 /// would require register copies due to two-addressness. 700 /// 701 /// This method returns a null pointer if the transformation cannot be 702 /// performed, otherwise it returns the new instruction. 703 /// 704 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 705 MachineBasicBlock::iterator &MBBI, 706 LiveVariables *LV) const; 707 708 /// commuteInstruction - We have a few instructions that must be hacked on to 709 /// commute them. 710 /// 711 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 712 713 // Branch analysis. 714 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; 715 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 716 MachineBasicBlock *&FBB, 717 SmallVectorImpl<MachineOperand> &Cond, 718 bool AllowModify) const; 719 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 720 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 721 MachineBasicBlock *FBB, 722 const SmallVectorImpl<MachineOperand> &Cond, 723 DebugLoc DL) const; 724 virtual void copyPhysReg(MachineBasicBlock &MBB, 725 MachineBasicBlock::iterator MI, DebugLoc DL, 726 unsigned DestReg, unsigned SrcReg, 727 bool KillSrc) const; 728 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 729 MachineBasicBlock::iterator MI, 730 unsigned SrcReg, bool isKill, int FrameIndex, 731 const TargetRegisterClass *RC, 732 const TargetRegisterInfo *TRI) const; 733 734 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 735 SmallVectorImpl<MachineOperand> &Addr, 736 const TargetRegisterClass *RC, 737 MachineInstr::mmo_iterator MMOBegin, 738 MachineInstr::mmo_iterator MMOEnd, 739 SmallVectorImpl<MachineInstr*> &NewMIs) const; 740 741 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 742 MachineBasicBlock::iterator MI, 743 unsigned DestReg, int FrameIndex, 744 const TargetRegisterClass *RC, 745 const TargetRegisterInfo *TRI) const; 746 747 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 748 SmallVectorImpl<MachineOperand> &Addr, 749 const TargetRegisterClass *RC, 750 MachineInstr::mmo_iterator MMOBegin, 751 MachineInstr::mmo_iterator MMOEnd, 752 SmallVectorImpl<MachineInstr*> &NewMIs) const; 753 virtual 754 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 755 int FrameIx, uint64_t Offset, 756 const MDNode *MDPtr, 757 DebugLoc DL) const; 758 759 /// foldMemoryOperand - If this target supports it, fold a load or store of 760 /// the specified stack slot into the specified machine instruction for the 761 /// specified operand(s). If this is possible, the target should perform the 762 /// folding and return true, otherwise it should return false. If it folds 763 /// the instruction, it is likely that the MachineInstruction the iterator 764 /// references has been changed. 765 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 766 MachineInstr* MI, 767 const SmallVectorImpl<unsigned> &Ops, 768 int FrameIndex) const; 769 770 /// foldMemoryOperand - Same as the previous version except it allows folding 771 /// of any load and store from / to any address, not just from a specific 772 /// stack slot. 773 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 774 MachineInstr* MI, 775 const SmallVectorImpl<unsigned> &Ops, 776 MachineInstr* LoadMI) const; 777 778 /// canFoldMemoryOperand - Returns true if the specified load / store is 779 /// folding is possible. 780 virtual bool canFoldMemoryOperand(const MachineInstr*, 781 const SmallVectorImpl<unsigned> &) const; 782 783 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 784 /// a store or a load and a store into two or more instruction. If this is 785 /// possible, returns true as well as the new instructions by reference. 786 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 787 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 788 SmallVectorImpl<MachineInstr*> &NewMIs) const; 789 790 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 791 SmallVectorImpl<SDNode*> &NewNodes) const; 792 793 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 794 /// instruction after load / store are unfolded from an instruction of the 795 /// specified opcode. It returns zero if the specified unfolding is not 796 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 797 /// index of the operand which will hold the register holding the loaded 798 /// value. 799 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 800 bool UnfoldLoad, bool UnfoldStore, 801 unsigned *LoadRegIndex = 0) const; 802 803 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 804 /// to determine if two loads are loading from the same base address. It 805 /// should only return true if the base pointers are the same and the 806 /// only differences between the two addresses are the offset. It also returns 807 /// the offsets by reference. 808 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 809 int64_t &Offset1, int64_t &Offset2) const; 810 811 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 812 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 813 /// be scheduled togther. On some targets if two loads are loading from 814 /// addresses in the same cache line, it's better if they are scheduled 815 /// together. This function takes two integers that represent the load offsets 816 /// from the common base address. It returns true if it decides it's desirable 817 /// to schedule the two loads together. "NumLoads" is the number of loads that 818 /// have already been scheduled after Load1. 819 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 820 int64_t Offset1, int64_t Offset2, 821 unsigned NumLoads) const; 822 823 virtual void getNoopForMachoTarget(MCInst &NopInst) const; 824 825 virtual 826 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 827 828 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 829 /// instruction that defines the specified register class. 830 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 831 832 static bool isX86_64NonExtLowByteReg(unsigned reg) { 833 return (reg == X86::SPL || reg == X86::BPL || 834 reg == X86::SIL || reg == X86::DIL); 835 } 836 837 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 838 if (!MO.isReg()) return false; 839 return isX86_64ExtendedReg(MO.getReg()); 840 } 841 842 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 843 /// higher) register? e.g. r8, xmm8, xmm13, etc. 844 static bool isX86_64ExtendedReg(unsigned RegNo); 845 846 /// getGlobalBaseReg - Return a virtual register initialized with the 847 /// the global base register value. Output instructions required to 848 /// initialize the register in the function entry block, if necessary. 849 /// 850 unsigned getGlobalBaseReg(MachineFunction *MF) const; 851 852 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 853 /// and a bitmask of possible arguments to SetSSEDomain ase the second. 854 std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const; 855 856 /// SetSSEDomain - Set the SSEDomain of MI. 857 void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; 858 859 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 860 MachineInstr* MI, 861 unsigned OpNum, 862 const SmallVectorImpl<MachineOperand> &MOs, 863 unsigned Size, unsigned Alignment) const; 864 865 bool isHighLatencyDef(int opc) const; 866 867 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 868 const MachineRegisterInfo *MRI, 869 const MachineInstr *DefMI, unsigned DefIdx, 870 const MachineInstr *UseMI, unsigned UseIdx) const; 871 872 private: 873 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 874 MachineFunction::iterator &MFI, 875 MachineBasicBlock::iterator &MBBI, 876 LiveVariables *LV) const; 877 878 /// isFrameOperand - Return true and the FrameIndex if the specified 879 /// operand and follow operands form a reference to the stack frame. 880 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 881 int &FrameIndex) const; 882 }; 883 884 } // End llvm namespace 885 886 #endif 887
