1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "mips-lower" 16 #include "MipsISelLowering.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "MipsTargetObjectFile.h" 20 #include "MipsSubtarget.h" 21 #include "llvm/DerivedTypes.h" 22 #include "llvm/Function.h" 23 #include "llvm/GlobalVariable.h" 24 #include "llvm/Intrinsics.h" 25 #include "llvm/CallingConv.h" 26 #include "InstPrinter/MipsInstPrinter.h" 27 #include "llvm/CodeGen/CallingConvLower.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineInstrBuilder.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 using namespace llvm; 37 38 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 39 switch (Opcode) { 40 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 41 case MipsISD::Hi: return "MipsISD::Hi"; 42 case MipsISD::Lo: return "MipsISD::Lo"; 43 case MipsISD::GPRel: return "MipsISD::GPRel"; 44 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 45 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 46 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 47 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 48 case MipsISD::Ret: return "MipsISD::Ret"; 49 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 50 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 51 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 52 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 53 case MipsISD::FPRound: return "MipsISD::FPRound"; 54 case MipsISD::MAdd: return "MipsISD::MAdd"; 55 case MipsISD::MAddu: return "MipsISD::MAddu"; 56 case MipsISD::MSub: return "MipsISD::MSub"; 57 case MipsISD::MSubu: return "MipsISD::MSubu"; 58 case MipsISD::DivRem: return "MipsISD::DivRem"; 59 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 60 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 61 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 62 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 63 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 64 case MipsISD::Sync: return "MipsISD::Sync"; 65 default: return NULL; 66 } 67 } 68 69 MipsTargetLowering:: 70 MipsTargetLowering(MipsTargetMachine &TM) 71 : TargetLowering(TM, new MipsTargetObjectFile()) { 72 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 73 74 // Mips does not have i1 type, so use i32 for 75 // setcc operations results (slt, sgt, ...). 76 setBooleanContents(ZeroOrOneBooleanContent); 77 78 // Set up the register classes 79 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 80 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 81 82 // When dealing with single precision only, use libcalls 83 if (!Subtarget->isSingleFloat()) 84 if (!Subtarget->isFP64bit()) 85 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 86 87 // Load extented operations for i1 types must be promoted 88 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 91 92 // MIPS doesn't have extending float->double load/store 93 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 94 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 95 96 // Used by legalize types to correctly generate the setcc result. 97 // Without this, every float setcc comes with a AND/OR with the result, 98 // we don't want this, since the fpcmp result goes to a flag register, 99 // which is used implicitly by brcond and select operations. 100 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 101 102 // Mips Custom Operations 103 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 104 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 105 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 106 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 107 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 108 setOperationAction(ISD::SELECT, MVT::f32, Custom); 109 setOperationAction(ISD::SELECT, MVT::f64, Custom); 110 setOperationAction(ISD::SELECT, MVT::i32, Custom); 111 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 112 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 113 setOperationAction(ISD::VASTART, MVT::Other, Custom); 114 115 setOperationAction(ISD::SDIV, MVT::i32, Expand); 116 setOperationAction(ISD::SREM, MVT::i32, Expand); 117 setOperationAction(ISD::UDIV, MVT::i32, Expand); 118 setOperationAction(ISD::UREM, MVT::i32, Expand); 119 120 // Operations not directly supported by Mips. 121 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 122 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 123 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 124 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 125 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 127 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 128 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 129 setOperationAction(ISD::ROTL, MVT::i32, Expand); 130 131 if (!Subtarget->isMips32r2()) 132 setOperationAction(ISD::ROTR, MVT::i32, Expand); 133 134 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 135 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 136 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 137 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 138 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 139 setOperationAction(ISD::FSIN, MVT::f32, Expand); 140 setOperationAction(ISD::FSIN, MVT::f64, Expand); 141 setOperationAction(ISD::FCOS, MVT::f32, Expand); 142 setOperationAction(ISD::FCOS, MVT::f64, Expand); 143 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 144 setOperationAction(ISD::FPOW, MVT::f32, Expand); 145 setOperationAction(ISD::FPOW, MVT::f64, Expand); 146 setOperationAction(ISD::FLOG, MVT::f32, Expand); 147 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 148 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 149 setOperationAction(ISD::FEXP, MVT::f32, Expand); 150 setOperationAction(ISD::FMA, MVT::f32, Expand); 151 setOperationAction(ISD::FMA, MVT::f64, Expand); 152 153 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 154 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 155 156 setOperationAction(ISD::VAARG, MVT::Other, Expand); 157 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 158 setOperationAction(ISD::VAEND, MVT::Other, Expand); 159 160 // Use the default for now 161 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 162 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 163 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 164 165 if (Subtarget->isSingleFloat()) 166 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 167 168 if (!Subtarget->hasSEInReg()) { 169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 171 } 172 173 if (!Subtarget->hasBitCount()) 174 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 175 176 if (!Subtarget->hasSwap()) 177 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 178 179 setTargetDAGCombine(ISD::ADDE); 180 setTargetDAGCombine(ISD::SUBE); 181 setTargetDAGCombine(ISD::SDIVREM); 182 setTargetDAGCombine(ISD::UDIVREM); 183 setTargetDAGCombine(ISD::SETCC); 184 185 setMinFunctionAlignment(2); 186 187 setStackPointerRegisterToSaveRestore(Mips::SP); 188 computeRegisterProperties(); 189 190 setExceptionPointerRegister(Mips::A0); 191 setExceptionSelectorRegister(Mips::A1); 192 } 193 194 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const { 195 return MVT::i32; 196 } 197 198 // SelectMadd - 199 // Transforms a subgraph in CurDAG if the following pattern is found: 200 // (addc multLo, Lo0), (adde multHi, Hi0), 201 // where, 202 // multHi/Lo: product of multiplication 203 // Lo0: initial value of Lo register 204 // Hi0: initial value of Hi register 205 // Return true if pattern matching was successful. 206 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 207 // ADDENode's second operand must be a flag output of an ADDC node in order 208 // for the matching to be successful. 209 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 210 211 if (ADDCNode->getOpcode() != ISD::ADDC) 212 return false; 213 214 SDValue MultHi = ADDENode->getOperand(0); 215 SDValue MultLo = ADDCNode->getOperand(0); 216 SDNode* MultNode = MultHi.getNode(); 217 unsigned MultOpc = MultHi.getOpcode(); 218 219 // MultHi and MultLo must be generated by the same node, 220 if (MultLo.getNode() != MultNode) 221 return false; 222 223 // and it must be a multiplication. 224 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 225 return false; 226 227 // MultLo amd MultHi must be the first and second output of MultNode 228 // respectively. 229 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 230 return false; 231 232 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 233 // of the values of MultNode, in which case MultNode will be removed in later 234 // phases. 235 // If there exist users other than ADDENode or ADDCNode, this function returns 236 // here, which will result in MultNode being mapped to a single MULT 237 // instruction node rather than a pair of MULT and MADD instructions being 238 // produced. 239 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 240 return false; 241 242 SDValue Chain = CurDAG->getEntryNode(); 243 DebugLoc dl = ADDENode->getDebugLoc(); 244 245 // create MipsMAdd(u) node 246 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 247 248 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 249 MVT::Glue, 250 MultNode->getOperand(0),// Factor 0 251 MultNode->getOperand(1),// Factor 1 252 ADDCNode->getOperand(1),// Lo0 253 ADDENode->getOperand(1));// Hi0 254 255 // create CopyFromReg nodes 256 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 257 MAdd); 258 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 259 Mips::HI, MVT::i32, 260 CopyFromLo.getValue(2)); 261 262 // replace uses of adde and addc here 263 if (!SDValue(ADDCNode, 0).use_empty()) 264 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 265 266 if (!SDValue(ADDENode, 0).use_empty()) 267 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 268 269 return true; 270 } 271 272 // SelectMsub - 273 // Transforms a subgraph in CurDAG if the following pattern is found: 274 // (addc Lo0, multLo), (sube Hi0, multHi), 275 // where, 276 // multHi/Lo: product of multiplication 277 // Lo0: initial value of Lo register 278 // Hi0: initial value of Hi register 279 // Return true if pattern matching was successful. 280 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 281 // SUBENode's second operand must be a flag output of an SUBC node in order 282 // for the matching to be successful. 283 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 284 285 if (SUBCNode->getOpcode() != ISD::SUBC) 286 return false; 287 288 SDValue MultHi = SUBENode->getOperand(1); 289 SDValue MultLo = SUBCNode->getOperand(1); 290 SDNode* MultNode = MultHi.getNode(); 291 unsigned MultOpc = MultHi.getOpcode(); 292 293 // MultHi and MultLo must be generated by the same node, 294 if (MultLo.getNode() != MultNode) 295 return false; 296 297 // and it must be a multiplication. 298 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 299 return false; 300 301 // MultLo amd MultHi must be the first and second output of MultNode 302 // respectively. 303 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 304 return false; 305 306 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 307 // of the values of MultNode, in which case MultNode will be removed in later 308 // phases. 309 // If there exist users other than SUBENode or SUBCNode, this function returns 310 // here, which will result in MultNode being mapped to a single MULT 311 // instruction node rather than a pair of MULT and MSUB instructions being 312 // produced. 313 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 314 return false; 315 316 SDValue Chain = CurDAG->getEntryNode(); 317 DebugLoc dl = SUBENode->getDebugLoc(); 318 319 // create MipsSub(u) node 320 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 321 322 SDValue MSub = CurDAG->getNode(MultOpc, dl, 323 MVT::Glue, 324 MultNode->getOperand(0),// Factor 0 325 MultNode->getOperand(1),// Factor 1 326 SUBCNode->getOperand(0),// Lo0 327 SUBENode->getOperand(0));// Hi0 328 329 // create CopyFromReg nodes 330 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 331 MSub); 332 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 333 Mips::HI, MVT::i32, 334 CopyFromLo.getValue(2)); 335 336 // replace uses of sube and subc here 337 if (!SDValue(SUBCNode, 0).use_empty()) 338 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 339 340 if (!SDValue(SUBENode, 0).use_empty()) 341 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 342 343 return true; 344 } 345 346 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 347 TargetLowering::DAGCombinerInfo &DCI, 348 const MipsSubtarget* Subtarget) { 349 if (DCI.isBeforeLegalize()) 350 return SDValue(); 351 352 if (Subtarget->isMips32() && SelectMadd(N, &DAG)) 353 return SDValue(N, 0); 354 355 return SDValue(); 356 } 357 358 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 359 TargetLowering::DAGCombinerInfo &DCI, 360 const MipsSubtarget* Subtarget) { 361 if (DCI.isBeforeLegalize()) 362 return SDValue(); 363 364 if (Subtarget->isMips32() && SelectMsub(N, &DAG)) 365 return SDValue(N, 0); 366 367 return SDValue(); 368 } 369 370 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 371 TargetLowering::DAGCombinerInfo &DCI, 372 const MipsSubtarget* Subtarget) { 373 if (DCI.isBeforeLegalizeOps()) 374 return SDValue(); 375 376 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 377 MipsISD::DivRemU; 378 DebugLoc dl = N->getDebugLoc(); 379 380 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 381 N->getOperand(0), N->getOperand(1)); 382 SDValue InChain = DAG.getEntryNode(); 383 SDValue InGlue = DivRem; 384 385 // insert MFLO 386 if (N->hasAnyUseOfValue(0)) { 387 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, 388 InGlue); 389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 390 InChain = CopyFromLo.getValue(1); 391 InGlue = CopyFromLo.getValue(2); 392 } 393 394 // insert MFHI 395 if (N->hasAnyUseOfValue(1)) { 396 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 397 Mips::HI, MVT::i32, InGlue); 398 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 399 } 400 401 return SDValue(); 402 } 403 404 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 405 switch (CC) { 406 default: llvm_unreachable("Unknown fp condition code!"); 407 case ISD::SETEQ: 408 case ISD::SETOEQ: return Mips::FCOND_OEQ; 409 case ISD::SETUNE: return Mips::FCOND_UNE; 410 case ISD::SETLT: 411 case ISD::SETOLT: return Mips::FCOND_OLT; 412 case ISD::SETGT: 413 case ISD::SETOGT: return Mips::FCOND_OGT; 414 case ISD::SETLE: 415 case ISD::SETOLE: return Mips::FCOND_OLE; 416 case ISD::SETGE: 417 case ISD::SETOGE: return Mips::FCOND_OGE; 418 case ISD::SETULT: return Mips::FCOND_ULT; 419 case ISD::SETULE: return Mips::FCOND_ULE; 420 case ISD::SETUGT: return Mips::FCOND_UGT; 421 case ISD::SETUGE: return Mips::FCOND_UGE; 422 case ISD::SETUO: return Mips::FCOND_UN; 423 case ISD::SETO: return Mips::FCOND_OR; 424 case ISD::SETNE: 425 case ISD::SETONE: return Mips::FCOND_ONE; 426 case ISD::SETUEQ: return Mips::FCOND_UEQ; 427 } 428 } 429 430 431 // Returns true if condition code has to be inverted. 432 static bool InvertFPCondCode(Mips::CondCode CC) { 433 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 434 return false; 435 436 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 437 return true; 438 439 assert(false && "Illegal Condition Code"); 440 return false; 441 } 442 443 // Creates and returns an FPCmp node from a setcc node. 444 // Returns Op if setcc is not a floating point comparison. 445 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 446 // must be a SETCC node 447 if (Op.getOpcode() != ISD::SETCC) 448 return Op; 449 450 SDValue LHS = Op.getOperand(0); 451 452 if (!LHS.getValueType().isFloatingPoint()) 453 return Op; 454 455 SDValue RHS = Op.getOperand(1); 456 DebugLoc dl = Op.getDebugLoc(); 457 458 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 459 // node if necessary. 460 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 461 462 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 463 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 464 } 465 466 // Creates and returns a CMovFPT/F node. 467 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 468 SDValue False, DebugLoc DL) { 469 bool invert = InvertFPCondCode((Mips::CondCode) 470 cast<ConstantSDNode>(Cond.getOperand(2)) 471 ->getSExtValue()); 472 473 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 474 True.getValueType(), True, False, Cond); 475 } 476 477 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 478 TargetLowering::DAGCombinerInfo &DCI, 479 const MipsSubtarget* Subtarget) { 480 if (DCI.isBeforeLegalizeOps()) 481 return SDValue(); 482 483 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 484 485 if (Cond.getOpcode() != MipsISD::FPCmp) 486 return SDValue(); 487 488 SDValue True = DAG.getConstant(1, MVT::i32); 489 SDValue False = DAG.getConstant(0, MVT::i32); 490 491 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 492 } 493 494 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 495 const { 496 SelectionDAG &DAG = DCI.DAG; 497 unsigned opc = N->getOpcode(); 498 499 switch (opc) { 500 default: break; 501 case ISD::ADDE: 502 return PerformADDECombine(N, DAG, DCI, Subtarget); 503 case ISD::SUBE: 504 return PerformSUBECombine(N, DAG, DCI, Subtarget); 505 case ISD::SDIVREM: 506 case ISD::UDIVREM: 507 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 508 case ISD::SETCC: 509 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 510 } 511 512 return SDValue(); 513 } 514 515 SDValue MipsTargetLowering:: 516 LowerOperation(SDValue Op, SelectionDAG &DAG) const 517 { 518 switch (Op.getOpcode()) 519 { 520 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 521 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 522 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 523 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 524 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 525 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 526 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 527 case ISD::SELECT: return LowerSELECT(Op, DAG); 528 case ISD::VASTART: return LowerVASTART(Op, DAG); 529 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 530 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 531 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 532 } 533 return SDValue(); 534 } 535 536 //===----------------------------------------------------------------------===// 537 // Lower helper functions 538 //===----------------------------------------------------------------------===// 539 540 // AddLiveIn - This helper function adds the specified physical register to the 541 // MachineFunction as a live in value. It also creates a corresponding 542 // virtual register for it. 543 static unsigned 544 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 545 { 546 assert(RC->contains(PReg) && "Not the correct regclass!"); 547 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 548 MF.getRegInfo().addLiveIn(PReg, VReg); 549 return VReg; 550 } 551 552 // Get fp branch code (not opcode) from condition code. 553 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 554 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 555 return Mips::BRANCH_T; 556 557 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 558 return Mips::BRANCH_F; 559 560 return Mips::BRANCH_INVALID; 561 } 562 563 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 564 DebugLoc dl, 565 const MipsSubtarget* Subtarget, 566 const TargetInstrInfo *TII, 567 bool isFPCmp, unsigned Opc) { 568 // There is no need to expand CMov instructions if target has 569 // conditional moves. 570 if (Subtarget->hasCondMov()) 571 return BB; 572 573 // To "insert" a SELECT_CC instruction, we actually have to insert the 574 // diamond control-flow pattern. The incoming instruction knows the 575 // destination vreg to set, the condition code register to branch on, the 576 // true/false values to select between, and a branch opcode to use. 577 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 578 MachineFunction::iterator It = BB; 579 ++It; 580 581 // thisMBB: 582 // ... 583 // TrueVal = ... 584 // setcc r1, r2, r3 585 // bNE r1, r0, copy1MBB 586 // fallthrough --> copy0MBB 587 MachineBasicBlock *thisMBB = BB; 588 MachineFunction *F = BB->getParent(); 589 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 590 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 591 F->insert(It, copy0MBB); 592 F->insert(It, sinkMBB); 593 594 // Transfer the remainder of BB and its successor edges to sinkMBB. 595 sinkMBB->splice(sinkMBB->begin(), BB, 596 llvm::next(MachineBasicBlock::iterator(MI)), 597 BB->end()); 598 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 599 600 // Next, add the true and fallthrough blocks as its successors. 601 BB->addSuccessor(copy0MBB); 602 BB->addSuccessor(sinkMBB); 603 604 // Emit the right instruction according to the type of the operands compared 605 if (isFPCmp) 606 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 607 else 608 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 609 .addReg(Mips::ZERO).addMBB(sinkMBB); 610 611 // copy0MBB: 612 // %FalseValue = ... 613 // # fallthrough to sinkMBB 614 BB = copy0MBB; 615 616 // Update machine-CFG edges 617 BB->addSuccessor(sinkMBB); 618 619 // sinkMBB: 620 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 621 // ... 622 BB = sinkMBB; 623 624 if (isFPCmp) 625 BuildMI(*BB, BB->begin(), dl, 626 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 627 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 628 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 629 else 630 BuildMI(*BB, BB->begin(), dl, 631 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 632 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 633 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 634 635 MI->eraseFromParent(); // The pseudo instruction is gone now. 636 return BB; 637 } 638 639 MachineBasicBlock * 640 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 641 MachineBasicBlock *BB) const { 642 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 643 DebugLoc dl = MI->getDebugLoc(); 644 645 switch (MI->getOpcode()) { 646 default: 647 assert(false && "Unexpected instr type to insert"); 648 return NULL; 649 case Mips::MOVT: 650 case Mips::MOVT_S: 651 case Mips::MOVT_D: 652 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F); 653 case Mips::MOVF: 654 case Mips::MOVF_S: 655 case Mips::MOVF_D: 656 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T); 657 case Mips::MOVZ_I: 658 case Mips::MOVZ_S: 659 case Mips::MOVZ_D: 660 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE); 661 case Mips::MOVN_I: 662 case Mips::MOVN_S: 663 case Mips::MOVN_D: 664 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ); 665 666 case Mips::ATOMIC_LOAD_ADD_I8: 667 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 668 case Mips::ATOMIC_LOAD_ADD_I16: 669 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 670 case Mips::ATOMIC_LOAD_ADD_I32: 671 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 672 673 case Mips::ATOMIC_LOAD_AND_I8: 674 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 675 case Mips::ATOMIC_LOAD_AND_I16: 676 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 677 case Mips::ATOMIC_LOAD_AND_I32: 678 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 679 680 case Mips::ATOMIC_LOAD_OR_I8: 681 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 682 case Mips::ATOMIC_LOAD_OR_I16: 683 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 684 case Mips::ATOMIC_LOAD_OR_I32: 685 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 686 687 case Mips::ATOMIC_LOAD_XOR_I8: 688 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 689 case Mips::ATOMIC_LOAD_XOR_I16: 690 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 691 case Mips::ATOMIC_LOAD_XOR_I32: 692 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 693 694 case Mips::ATOMIC_LOAD_NAND_I8: 695 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 696 case Mips::ATOMIC_LOAD_NAND_I16: 697 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 698 case Mips::ATOMIC_LOAD_NAND_I32: 699 return EmitAtomicBinary(MI, BB, 4, 0, true); 700 701 case Mips::ATOMIC_LOAD_SUB_I8: 702 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 703 case Mips::ATOMIC_LOAD_SUB_I16: 704 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 705 case Mips::ATOMIC_LOAD_SUB_I32: 706 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 707 708 case Mips::ATOMIC_SWAP_I8: 709 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 710 case Mips::ATOMIC_SWAP_I16: 711 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 712 case Mips::ATOMIC_SWAP_I32: 713 return EmitAtomicBinary(MI, BB, 4, 0); 714 715 case Mips::ATOMIC_CMP_SWAP_I8: 716 return EmitAtomicCmpSwapPartword(MI, BB, 1); 717 case Mips::ATOMIC_CMP_SWAP_I16: 718 return EmitAtomicCmpSwapPartword(MI, BB, 2); 719 case Mips::ATOMIC_CMP_SWAP_I32: 720 return EmitAtomicCmpSwap(MI, BB, 4); 721 } 722 } 723 724 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 725 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 726 MachineBasicBlock * 727 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 728 unsigned Size, unsigned BinOpcode, 729 bool Nand) const { 730 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 731 732 MachineFunction *MF = BB->getParent(); 733 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 734 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 735 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 736 DebugLoc dl = MI->getDebugLoc(); 737 738 unsigned OldVal = MI->getOperand(0).getReg(); 739 unsigned Ptr = MI->getOperand(1).getReg(); 740 unsigned Incr = MI->getOperand(2).getReg(); 741 742 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 743 unsigned AndRes = RegInfo.createVirtualRegister(RC); 744 unsigned Success = RegInfo.createVirtualRegister(RC); 745 746 // insert new blocks after the current block 747 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 748 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 749 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 750 MachineFunction::iterator It = BB; 751 ++It; 752 MF->insert(It, loopMBB); 753 MF->insert(It, exitMBB); 754 755 // Transfer the remainder of BB and its successor edges to exitMBB. 756 exitMBB->splice(exitMBB->begin(), BB, 757 llvm::next(MachineBasicBlock::iterator(MI)), 758 BB->end()); 759 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 760 761 // thisMBB: 762 // ... 763 // fallthrough --> loopMBB 764 BB->addSuccessor(loopMBB); 765 loopMBB->addSuccessor(loopMBB); 766 loopMBB->addSuccessor(exitMBB); 767 768 // loopMBB: 769 // ll oldval, 0(ptr) 770 // <binop> storeval, oldval, incr 771 // sc success, storeval, 0(ptr) 772 // beq success, $0, loopMBB 773 BB = loopMBB; 774 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); 775 if (Nand) { 776 // and andres, oldval, incr 777 // nor storeval, $0, andres 778 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); 779 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) 780 .addReg(Mips::ZERO).addReg(AndRes); 781 } else if (BinOpcode) { 782 // <binop> storeval, oldval, incr 783 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 784 } else { 785 StoreVal = Incr; 786 } 787 BuildMI(BB, dl, TII->get(Mips::SC), Success) 788 .addReg(StoreVal).addReg(Ptr).addImm(0); 789 BuildMI(BB, dl, TII->get(Mips::BEQ)) 790 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 791 792 MI->eraseFromParent(); // The instruction is gone now. 793 794 return exitMBB; 795 } 796 797 MachineBasicBlock * 798 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 799 MachineBasicBlock *BB, 800 unsigned Size, unsigned BinOpcode, 801 bool Nand) const { 802 assert((Size == 1 || Size == 2) && 803 "Unsupported size for EmitAtomicBinaryPartial."); 804 805 MachineFunction *MF = BB->getParent(); 806 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 807 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 808 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 809 DebugLoc dl = MI->getDebugLoc(); 810 811 unsigned Dest = MI->getOperand(0).getReg(); 812 unsigned Ptr = MI->getOperand(1).getReg(); 813 unsigned Incr = MI->getOperand(2).getReg(); 814 815 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 816 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 817 unsigned Mask = RegInfo.createVirtualRegister(RC); 818 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 819 unsigned NewVal = RegInfo.createVirtualRegister(RC); 820 unsigned OldVal = RegInfo.createVirtualRegister(RC); 821 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 822 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 823 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 824 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 825 unsigned AndRes = RegInfo.createVirtualRegister(RC); 826 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 827 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 828 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 829 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 830 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 831 unsigned SllRes = RegInfo.createVirtualRegister(RC); 832 unsigned Success = RegInfo.createVirtualRegister(RC); 833 834 // insert new blocks after the current block 835 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 836 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 837 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 838 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 839 MachineFunction::iterator It = BB; 840 ++It; 841 MF->insert(It, loopMBB); 842 MF->insert(It, sinkMBB); 843 MF->insert(It, exitMBB); 844 845 // Transfer the remainder of BB and its successor edges to exitMBB. 846 exitMBB->splice(exitMBB->begin(), BB, 847 llvm::next(MachineBasicBlock::iterator(MI)), 848 BB->end()); 849 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 850 851 BB->addSuccessor(loopMBB); 852 loopMBB->addSuccessor(loopMBB); 853 loopMBB->addSuccessor(sinkMBB); 854 sinkMBB->addSuccessor(exitMBB); 855 856 // thisMBB: 857 // addiu masklsb2,$0,-4 # 0xfffffffc 858 // and alignedaddr,ptr,masklsb2 859 // andi ptrlsb2,ptr,3 860 // sll shiftamt,ptrlsb2,3 861 // ori maskupper,$0,255 # 0xff 862 // sll mask,maskupper,shiftamt 863 // nor mask2,$0,mask 864 // sll incr2,incr,shiftamt 865 866 int64_t MaskImm = (Size == 1) ? 255 : 65535; 867 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 868 .addReg(Mips::ZERO).addImm(-4); 869 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 870 .addReg(Ptr).addReg(MaskLSB2); 871 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 872 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 873 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 874 .addReg(Mips::ZERO).addImm(MaskImm); 875 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 876 .addReg(ShiftAmt).addReg(MaskUpper); 877 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 878 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 879 880 881 // atomic.load.binop 882 // loopMBB: 883 // ll oldval,0(alignedaddr) 884 // binop binopres,oldval,incr2 885 // and newval,binopres,mask 886 // and maskedoldval0,oldval,mask2 887 // or storeval,maskedoldval0,newval 888 // sc success,storeval,0(alignedaddr) 889 // beq success,$0,loopMBB 890 891 // atomic.swap 892 // loopMBB: 893 // ll oldval,0(alignedaddr) 894 // and newval,incr2,mask 895 // and maskedoldval0,oldval,mask2 896 // or storeval,maskedoldval0,newval 897 // sc success,storeval,0(alignedaddr) 898 // beq success,$0,loopMBB 899 900 BB = loopMBB; 901 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 902 if (Nand) { 903 // and andres, oldval, incr2 904 // nor binopres, $0, andres 905 // and newval, binopres, mask 906 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 907 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 908 .addReg(Mips::ZERO).addReg(AndRes); 909 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 910 } else if (BinOpcode) { 911 // <binop> binopres, oldval, incr2 912 // and newval, binopres, mask 913 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 914 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 915 } else {// atomic.swap 916 // and newval, incr2, mask 917 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 918 } 919 920 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 921 .addReg(OldVal).addReg(Mask2); 922 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 923 .addReg(MaskedOldVal0).addReg(NewVal); 924 BuildMI(BB, dl, TII->get(Mips::SC), Success) 925 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 926 BuildMI(BB, dl, TII->get(Mips::BEQ)) 927 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 928 929 // sinkMBB: 930 // and maskedoldval1,oldval,mask 931 // srl srlres,maskedoldval1,shiftamt 932 // sll sllres,srlres,24 933 // sra dest,sllres,24 934 BB = sinkMBB; 935 int64_t ShiftImm = (Size == 1) ? 24 : 16; 936 937 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 938 .addReg(OldVal).addReg(Mask); 939 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 940 .addReg(ShiftAmt).addReg(MaskedOldVal1); 941 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 942 .addReg(SrlRes).addImm(ShiftImm); 943 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 944 .addReg(SllRes).addImm(ShiftImm); 945 946 MI->eraseFromParent(); // The instruction is gone now. 947 948 return exitMBB; 949 } 950 951 MachineBasicBlock * 952 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 953 MachineBasicBlock *BB, 954 unsigned Size) const { 955 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 956 957 MachineFunction *MF = BB->getParent(); 958 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 959 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 960 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 961 DebugLoc dl = MI->getDebugLoc(); 962 963 unsigned Dest = MI->getOperand(0).getReg(); 964 unsigned Ptr = MI->getOperand(1).getReg(); 965 unsigned OldVal = MI->getOperand(2).getReg(); 966 unsigned NewVal = MI->getOperand(3).getReg(); 967 968 unsigned Success = RegInfo.createVirtualRegister(RC); 969 970 // insert new blocks after the current block 971 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 972 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 973 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 974 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 975 MachineFunction::iterator It = BB; 976 ++It; 977 MF->insert(It, loop1MBB); 978 MF->insert(It, loop2MBB); 979 MF->insert(It, exitMBB); 980 981 // Transfer the remainder of BB and its successor edges to exitMBB. 982 exitMBB->splice(exitMBB->begin(), BB, 983 llvm::next(MachineBasicBlock::iterator(MI)), 984 BB->end()); 985 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 986 987 // thisMBB: 988 // ... 989 // fallthrough --> loop1MBB 990 BB->addSuccessor(loop1MBB); 991 loop1MBB->addSuccessor(exitMBB); 992 loop1MBB->addSuccessor(loop2MBB); 993 loop2MBB->addSuccessor(loop1MBB); 994 loop2MBB->addSuccessor(exitMBB); 995 996 // loop1MBB: 997 // ll dest, 0(ptr) 998 // bne dest, oldval, exitMBB 999 BB = loop1MBB; 1000 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 1001 BuildMI(BB, dl, TII->get(Mips::BNE)) 1002 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1003 1004 // loop2MBB: 1005 // sc success, newval, 0(ptr) 1006 // beq success, $0, loop1MBB 1007 BB = loop2MBB; 1008 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1009 .addReg(NewVal).addReg(Ptr).addImm(0); 1010 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1011 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1012 1013 MI->eraseFromParent(); // The instruction is gone now. 1014 1015 return exitMBB; 1016 } 1017 1018 MachineBasicBlock * 1019 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1020 MachineBasicBlock *BB, 1021 unsigned Size) const { 1022 assert((Size == 1 || Size == 2) && 1023 "Unsupported size for EmitAtomicCmpSwapPartial."); 1024 1025 MachineFunction *MF = BB->getParent(); 1026 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1027 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1028 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1029 DebugLoc dl = MI->getDebugLoc(); 1030 1031 unsigned Dest = MI->getOperand(0).getReg(); 1032 unsigned Ptr = MI->getOperand(1).getReg(); 1033 unsigned CmpVal = MI->getOperand(2).getReg(); 1034 unsigned NewVal = MI->getOperand(3).getReg(); 1035 1036 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1037 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1038 unsigned Mask = RegInfo.createVirtualRegister(RC); 1039 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1040 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1041 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1042 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1043 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1044 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1045 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1046 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1047 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1048 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1049 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1050 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1051 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1052 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1053 unsigned Success = RegInfo.createVirtualRegister(RC); 1054 1055 // insert new blocks after the current block 1056 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1057 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1058 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1059 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1060 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1061 MachineFunction::iterator It = BB; 1062 ++It; 1063 MF->insert(It, loop1MBB); 1064 MF->insert(It, loop2MBB); 1065 MF->insert(It, sinkMBB); 1066 MF->insert(It, exitMBB); 1067 1068 // Transfer the remainder of BB and its successor edges to exitMBB. 1069 exitMBB->splice(exitMBB->begin(), BB, 1070 llvm::next(MachineBasicBlock::iterator(MI)), 1071 BB->end()); 1072 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1073 1074 BB->addSuccessor(loop1MBB); 1075 loop1MBB->addSuccessor(sinkMBB); 1076 loop1MBB->addSuccessor(loop2MBB); 1077 loop2MBB->addSuccessor(loop1MBB); 1078 loop2MBB->addSuccessor(sinkMBB); 1079 sinkMBB->addSuccessor(exitMBB); 1080 1081 // FIXME: computation of newval2 can be moved to loop2MBB. 1082 // thisMBB: 1083 // addiu masklsb2,$0,-4 # 0xfffffffc 1084 // and alignedaddr,ptr,masklsb2 1085 // andi ptrlsb2,ptr,3 1086 // sll shiftamt,ptrlsb2,3 1087 // ori maskupper,$0,255 # 0xff 1088 // sll mask,maskupper,shiftamt 1089 // nor mask2,$0,mask 1090 // andi maskedcmpval,cmpval,255 1091 // sll shiftedcmpval,maskedcmpval,shiftamt 1092 // andi maskednewval,newval,255 1093 // sll shiftednewval,maskednewval,shiftamt 1094 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1095 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1096 .addReg(Mips::ZERO).addImm(-4); 1097 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1098 .addReg(Ptr).addReg(MaskLSB2); 1099 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1100 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1101 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1102 .addReg(Mips::ZERO).addImm(MaskImm); 1103 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1104 .addReg(ShiftAmt).addReg(MaskUpper); 1105 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1106 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1107 .addReg(CmpVal).addImm(MaskImm); 1108 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1109 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1110 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1111 .addReg(NewVal).addImm(MaskImm); 1112 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1113 .addReg(ShiftAmt).addReg(MaskedNewVal); 1114 1115 // loop1MBB: 1116 // ll oldval,0(alginedaddr) 1117 // and maskedoldval0,oldval,mask 1118 // bne maskedoldval0,shiftedcmpval,sinkMBB 1119 BB = loop1MBB; 1120 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1121 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1122 .addReg(OldVal).addReg(Mask); 1123 BuildMI(BB, dl, TII->get(Mips::BNE)) 1124 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1125 1126 // loop2MBB: 1127 // and maskedoldval1,oldval,mask2 1128 // or storeval,maskedoldval1,shiftednewval 1129 // sc success,storeval,0(alignedaddr) 1130 // beq success,$0,loop1MBB 1131 BB = loop2MBB; 1132 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1133 .addReg(OldVal).addReg(Mask2); 1134 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1135 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1136 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1137 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1138 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1139 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1140 1141 // sinkMBB: 1142 // srl srlres,maskedoldval0,shiftamt 1143 // sll sllres,srlres,24 1144 // sra dest,sllres,24 1145 BB = sinkMBB; 1146 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1147 1148 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1149 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1150 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1151 .addReg(SrlRes).addImm(ShiftImm); 1152 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1153 .addReg(SllRes).addImm(ShiftImm); 1154 1155 MI->eraseFromParent(); // The instruction is gone now. 1156 1157 return exitMBB; 1158 } 1159 1160 //===----------------------------------------------------------------------===// 1161 // Misc Lower Operation implementation 1162 //===----------------------------------------------------------------------===// 1163 SDValue MipsTargetLowering:: 1164 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1165 { 1166 MachineFunction &MF = DAG.getMachineFunction(); 1167 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1168 1169 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1170 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1171 "Cannot lower if the alignment of the allocated space is larger than \ 1172 that of the stack."); 1173 1174 SDValue Chain = Op.getOperand(0); 1175 SDValue Size = Op.getOperand(1); 1176 DebugLoc dl = Op.getDebugLoc(); 1177 1178 // Get a reference from Mips stack pointer 1179 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 1180 1181 // Subtract the dynamic size from the actual stack size to 1182 // obtain the new stack size. 1183 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 1184 1185 // The Sub result contains the new stack start address, so it 1186 // must be placed in the stack pointer register. 1187 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 1188 SDValue()); 1189 1190 // This node always has two return values: a new stack pointer 1191 // value and a chain 1192 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); 1193 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1194 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1195 1196 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1197 } 1198 1199 SDValue MipsTargetLowering:: 1200 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1201 { 1202 // The first operand is the chain, the second is the condition, the third is 1203 // the block to branch to if the condition is true. 1204 SDValue Chain = Op.getOperand(0); 1205 SDValue Dest = Op.getOperand(2); 1206 DebugLoc dl = Op.getDebugLoc(); 1207 1208 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1209 1210 // Return if flag is not set by a floating point comparison. 1211 if (CondRes.getOpcode() != MipsISD::FPCmp) 1212 return Op; 1213 1214 SDValue CCNode = CondRes.getOperand(2); 1215 Mips::CondCode CC = 1216 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1217 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1218 1219 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1220 Dest, CondRes); 1221 } 1222 1223 SDValue MipsTargetLowering:: 1224 LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1225 { 1226 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1227 1228 // Return if flag is not set by a floating point comparison. 1229 if (Cond.getOpcode() != MipsISD::FPCmp) 1230 return Op; 1231 1232 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1233 Op.getDebugLoc()); 1234 } 1235 1236 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1237 SelectionDAG &DAG) const { 1238 // FIXME there isn't actually debug info here 1239 DebugLoc dl = Op.getDebugLoc(); 1240 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1241 1242 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1243 SDVTList VTs = DAG.getVTList(MVT::i32); 1244 1245 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1246 1247 // %gp_rel relocation 1248 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1249 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1250 MipsII::MO_GPREL); 1251 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1252 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1253 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1254 } 1255 // %hi/%lo relocation 1256 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1257 MipsII::MO_ABS_HI); 1258 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1259 MipsII::MO_ABS_LO); 1260 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1261 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1262 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1263 } 1264 1265 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1266 MipsII::MO_GOT); 1267 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA); 1268 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 1269 DAG.getEntryNode(), GA, MachinePointerInfo(), 1270 false, false, 0); 1271 // On functions and global targets not internal linked only 1272 // a load from got/GP is necessary for PIC to work. 1273 if (!GV->hasInternalLinkage() && 1274 (!GV->hasLocalLinkage() || isa<Function>(GV))) 1275 return ResNode; 1276 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1277 MipsII::MO_ABS_LO); 1278 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1279 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 1280 } 1281 1282 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1283 SelectionDAG &DAG) const { 1284 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1285 // FIXME there isn't actually debug info here 1286 DebugLoc dl = Op.getDebugLoc(); 1287 1288 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1289 // %hi/%lo relocation 1290 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1291 MipsII::MO_ABS_HI); 1292 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1293 MipsII::MO_ABS_LO); 1294 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1295 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1296 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1297 } 1298 1299 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1300 MipsII::MO_GOT); 1301 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1302 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1303 MipsII::MO_ABS_LO); 1304 SDValue Load = DAG.getLoad(MVT::i32, dl, 1305 DAG.getEntryNode(), BAGOTOffset, 1306 MachinePointerInfo(), false, false, 0); 1307 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1308 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1309 } 1310 1311 SDValue MipsTargetLowering:: 1312 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1313 { 1314 // If the relocation model is PIC, use the General Dynamic TLS Model, 1315 // otherwise use the Initial Exec or Local Exec TLS Model. 1316 // TODO: implement Local Dynamic TLS model 1317 1318 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1319 DebugLoc dl = GA->getDebugLoc(); 1320 const GlobalValue *GV = GA->getGlobal(); 1321 EVT PtrVT = getPointerTy(); 1322 1323 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1324 // General Dynamic TLS Model 1325 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1326 0, MipsII::MO_TLSGD); 1327 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1328 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1329 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1330 1331 ArgListTy Args; 1332 ArgListEntry Entry; 1333 Entry.Node = Argument; 1334 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1335 Args.push_back(Entry); 1336 std::pair<SDValue, SDValue> CallResult = 1337 LowerCallTo(DAG.getEntryNode(), 1338 (Type *) Type::getInt32Ty(*DAG.getContext()), 1339 false, false, false, false, 0, CallingConv::C, false, true, 1340 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1341 dl); 1342 1343 return CallResult.first; 1344 } 1345 1346 SDValue Offset; 1347 if (GV->isDeclaration()) { 1348 // Initial Exec TLS Model 1349 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1350 MipsII::MO_GOTTPREL); 1351 Offset = DAG.getLoad(MVT::i32, dl, 1352 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1353 false, false, 0); 1354 } else { 1355 // Local Exec TLS Model 1356 SDVTList VTs = DAG.getVTList(MVT::i32); 1357 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1358 MipsII::MO_TPREL_HI); 1359 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1360 MipsII::MO_TPREL_LO); 1361 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1362 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1363 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1364 } 1365 1366 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1367 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1368 } 1369 1370 SDValue MipsTargetLowering:: 1371 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1372 { 1373 SDValue ResNode; 1374 SDValue HiPart; 1375 // FIXME there isn't actually debug info here 1376 DebugLoc dl = Op.getDebugLoc(); 1377 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1378 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1379 1380 EVT PtrVT = Op.getValueType(); 1381 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1382 1383 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1384 1385 if (!IsPIC) { 1386 SDValue Ops[] = { JTI }; 1387 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1388 } else {// Emit Load from Global Pointer 1389 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1390 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1391 MachinePointerInfo(), 1392 false, false, 0); 1393 } 1394 1395 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1396 MipsII::MO_ABS_LO); 1397 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1398 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1399 1400 return ResNode; 1401 } 1402 1403 SDValue MipsTargetLowering:: 1404 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1405 { 1406 SDValue ResNode; 1407 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1408 const Constant *C = N->getConstVal(); 1409 // FIXME there isn't actually debug info here 1410 DebugLoc dl = Op.getDebugLoc(); 1411 1412 // gp_rel relocation 1413 // FIXME: we should reference the constant pool using small data sections, 1414 // but the asm printer currently doesn't support this feature without 1415 // hacking it. This feature should come soon so we can uncomment the 1416 // stuff below. 1417 //if (IsInSmallSection(C->getType())) { 1418 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1419 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1420 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1421 1422 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1423 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1424 N->getOffset(), MipsII::MO_ABS_HI); 1425 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1426 N->getOffset(), MipsII::MO_ABS_LO); 1427 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1428 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1429 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1430 } else { 1431 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1432 N->getOffset(), MipsII::MO_GOT); 1433 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1434 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1435 CP, MachinePointerInfo::getConstantPool(), 1436 false, false, 0); 1437 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1438 N->getOffset(), MipsII::MO_ABS_LO); 1439 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1440 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1441 } 1442 1443 return ResNode; 1444 } 1445 1446 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1447 MachineFunction &MF = DAG.getMachineFunction(); 1448 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1449 1450 DebugLoc dl = Op.getDebugLoc(); 1451 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1452 getPointerTy()); 1453 1454 // vastart just stores the address of the VarArgsFrameIndex slot into the 1455 // memory location argument. 1456 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1457 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1458 MachinePointerInfo(SV), 1459 false, false, 0); 1460 } 1461 1462 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1463 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1464 DebugLoc dl = Op.getDebugLoc(); 1465 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1466 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1467 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1468 DAG.getConstant(0x7fffffff, MVT::i32)); 1469 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1470 DAG.getConstant(0x80000000, MVT::i32)); 1471 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1472 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1473 } 1474 1475 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1476 // FIXME: 1477 // Use ext/ins instructions if target architecture is Mips32r2. 1478 // Eliminate redundant mfc1 and mtc1 instructions. 1479 unsigned LoIdx = 0, HiIdx = 1; 1480 1481 if (!isLittle) 1482 std::swap(LoIdx, HiIdx); 1483 1484 DebugLoc dl = Op.getDebugLoc(); 1485 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1486 Op.getOperand(0), 1487 DAG.getConstant(LoIdx, MVT::i32)); 1488 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1489 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1490 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1491 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1492 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1493 DAG.getConstant(0x7fffffff, MVT::i32)); 1494 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1495 DAG.getConstant(0x80000000, MVT::i32)); 1496 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1497 1498 if (!isLittle) 1499 std::swap(Word0, Word1); 1500 1501 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1502 } 1503 1504 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1505 const { 1506 EVT Ty = Op.getValueType(); 1507 1508 assert(Ty == MVT::f32 || Ty == MVT::f64); 1509 1510 if (Ty == MVT::f32) 1511 return LowerFCOPYSIGN32(Op, DAG); 1512 else 1513 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1514 } 1515 1516 SDValue MipsTargetLowering:: 1517 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1518 // check the depth 1519 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1520 "Frame address can only be determined for current frame."); 1521 1522 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1523 MFI->setFrameAddressIsTaken(true); 1524 EVT VT = Op.getValueType(); 1525 DebugLoc dl = Op.getDebugLoc(); 1526 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); 1527 return FrameAddr; 1528 } 1529 1530 // TODO: set SType according to the desired memory barrier behavior. 1531 SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, 1532 SelectionDAG& DAG) const { 1533 unsigned SType = 0; 1534 DebugLoc dl = Op.getDebugLoc(); 1535 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1536 DAG.getConstant(SType, MVT::i32)); 1537 } 1538 1539 //===----------------------------------------------------------------------===// 1540 // Calling Convention Implementation 1541 //===----------------------------------------------------------------------===// 1542 1543 #include "MipsGenCallingConv.inc" 1544 1545 //===----------------------------------------------------------------------===// 1546 // TODO: Implement a generic logic using tblgen that can support this. 1547 // Mips O32 ABI rules: 1548 // --- 1549 // i32 - Passed in A0, A1, A2, A3 and stack 1550 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 1551 // an argument. Otherwise, passed in A1, A2, A3 and stack. 1552 // f64 - Only passed in two aliased f32 registers if no int reg has been used 1553 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1554 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 1555 // go to stack. 1556 // 1557 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1558 //===----------------------------------------------------------------------===// 1559 1560 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1561 MVT LocVT, CCValAssign::LocInfo LocInfo, 1562 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1563 1564 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1565 1566 static const unsigned IntRegs[] = { 1567 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1568 }; 1569 static const unsigned F32Regs[] = { 1570 Mips::F12, Mips::F14 1571 }; 1572 static const unsigned F64Regs[] = { 1573 Mips::D6, Mips::D7 1574 }; 1575 1576 // ByVal Args 1577 if (ArgFlags.isByVal()) { 1578 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1579 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1580 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1581 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1582 r < std::min(IntRegsSize, NextReg); ++r) 1583 State.AllocateReg(IntRegs[r]); 1584 return false; 1585 } 1586 1587 // Promote i8 and i16 1588 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1589 LocVT = MVT::i32; 1590 if (ArgFlags.isSExt()) 1591 LocInfo = CCValAssign::SExt; 1592 else if (ArgFlags.isZExt()) 1593 LocInfo = CCValAssign::ZExt; 1594 else 1595 LocInfo = CCValAssign::AExt; 1596 } 1597 1598 unsigned Reg; 1599 1600 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1601 // is true: function is vararg, argument is 3rd or higher, there is previous 1602 // argument which is not f32 or f64. 1603 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1604 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1605 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1606 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1607 1608 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1609 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1610 // If this is the first part of an i64 arg, 1611 // the allocated register must be either A0 or A2. 1612 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1613 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1614 LocVT = MVT::i32; 1615 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1616 // Allocate int register and shadow next int register. If first 1617 // available register is Mips::A1 or Mips::A3, shadow it too. 1618 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1619 if (Reg == Mips::A1 || Reg == Mips::A3) 1620 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1621 State.AllocateReg(IntRegs, IntRegsSize); 1622 LocVT = MVT::i32; 1623 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1624 // we are guaranteed to find an available float register 1625 if (ValVT == MVT::f32) { 1626 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1627 // Shadow int register 1628 State.AllocateReg(IntRegs, IntRegsSize); 1629 } else { 1630 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1631 // Shadow int registers 1632 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1633 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1634 State.AllocateReg(IntRegs, IntRegsSize); 1635 State.AllocateReg(IntRegs, IntRegsSize); 1636 } 1637 } else 1638 llvm_unreachable("Cannot handle this ValVT."); 1639 1640 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1641 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1642 1643 if (!Reg) 1644 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1645 else 1646 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1647 1648 return false; // CC must always match 1649 } 1650 1651 //===----------------------------------------------------------------------===// 1652 // Call Calling Convention Implementation 1653 //===----------------------------------------------------------------------===// 1654 1655 static const unsigned O32IntRegsSize = 4; 1656 1657 static const unsigned O32IntRegs[] = { 1658 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1659 }; 1660 1661 // Write ByVal Arg to arg registers and stack. 1662 static void 1663 WriteByValArg(SDValue& Chain, DebugLoc dl, 1664 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1665 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1666 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1667 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1668 MVT PtrType) { 1669 unsigned FirstWord = VA.getLocMemOffset() / 4; 1670 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 1671 unsigned LastWord = FirstWord + NumWords; 1672 unsigned CurWord; 1673 1674 // copy the first 4 words of byval arg to registers A0 - A3 1675 for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize); 1676 ++CurWord) { 1677 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1678 DAG.getConstant((CurWord - FirstWord) * 4, 1679 MVT::i32)); 1680 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1681 MachinePointerInfo(), 1682 false, false, 0); 1683 MemOpChains.push_back(LoadVal.getValue(1)); 1684 unsigned DstReg = O32IntRegs[CurWord]; 1685 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1686 } 1687 1688 // copy remaining part of byval arg to stack. 1689 if (CurWord < LastWord) { 1690 unsigned SizeInBytes = (LastWord - CurWord) * 4; 1691 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1692 DAG.getConstant((CurWord - FirstWord) * 4, 1693 MVT::i32)); 1694 LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true); 1695 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1696 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 1697 DAG.getConstant(SizeInBytes, MVT::i32), 1698 /*Align*/4, 1699 /*isVolatile=*/false, /*AlwaysInline=*/false, 1700 MachinePointerInfo(0), MachinePointerInfo(0)); 1701 MemOpChains.push_back(Chain); 1702 } 1703 } 1704 1705 /// LowerCall - functions arguments are copied from virtual regs to 1706 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1707 /// TODO: isTailCall. 1708 SDValue 1709 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1710 CallingConv::ID CallConv, bool isVarArg, 1711 bool &isTailCall, 1712 const SmallVectorImpl<ISD::OutputArg> &Outs, 1713 const SmallVectorImpl<SDValue> &OutVals, 1714 const SmallVectorImpl<ISD::InputArg> &Ins, 1715 DebugLoc dl, SelectionDAG &DAG, 1716 SmallVectorImpl<SDValue> &InVals) const { 1717 // MIPs target does not yet support tail call optimization. 1718 isTailCall = false; 1719 1720 MachineFunction &MF = DAG.getMachineFunction(); 1721 MachineFrameInfo *MFI = MF.getFrameInfo(); 1722 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1723 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1724 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1725 1726 // Analyze operands of the call, assigning locations to each operand. 1727 SmallVector<CCValAssign, 16> ArgLocs; 1728 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1729 getTargetMachine(), ArgLocs, *DAG.getContext()); 1730 1731 if (Subtarget->isABI_O32()) 1732 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1733 else 1734 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1735 1736 // Get a count of how many bytes are to be pushed on the stack. 1737 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1738 1739 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NextStackOffset, 1740 true)); 1741 1742 // If this is the first call, create a stack frame object that points to 1743 // a location to which .cprestore saves $gp. 1744 if (IsPIC && !MipsFI->getGPFI()) 1745 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1746 1747 // Get the frame index of the stack frame object that points to the location 1748 // of dynamically allocated area on the stack. 1749 int DynAllocFI = MipsFI->getDynAllocFI(); 1750 1751 // Update size of the maximum argument space. 1752 // For O32, a minimum of four words (16 bytes) of argument space is 1753 // allocated. 1754 if (Subtarget->isABI_O32()) 1755 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1756 1757 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1758 1759 if (MaxCallFrameSize < NextStackOffset) { 1760 MipsFI->setMaxCallFrameSize(NextStackOffset); 1761 1762 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1763 // allocated stack space. These offsets must be aligned to a boundary 1764 // determined by the stack alignment of the ABI. 1765 unsigned StackAlignment = TFL->getStackAlignment(); 1766 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1767 StackAlignment * StackAlignment; 1768 1769 if (IsPIC) 1770 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1771 1772 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1773 } 1774 1775 // With EABI is it possible to have 16 args on registers. 1776 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1777 SmallVector<SDValue, 8> MemOpChains; 1778 1779 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1780 1781 // Walk the register/memloc assignments, inserting copies/loads. 1782 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1783 SDValue Arg = OutVals[i]; 1784 CCValAssign &VA = ArgLocs[i]; 1785 1786 // Promote the value if needed. 1787 switch (VA.getLocInfo()) { 1788 default: llvm_unreachable("Unknown loc info!"); 1789 case CCValAssign::Full: 1790 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 1791 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 1792 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 1793 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 1794 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1795 Arg, DAG.getConstant(0, MVT::i32)); 1796 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1797 Arg, DAG.getConstant(1, MVT::i32)); 1798 if (!Subtarget->isLittle()) 1799 std::swap(Lo, Hi); 1800 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); 1801 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); 1802 continue; 1803 } 1804 } 1805 break; 1806 case CCValAssign::SExt: 1807 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1808 break; 1809 case CCValAssign::ZExt: 1810 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1811 break; 1812 case CCValAssign::AExt: 1813 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1814 break; 1815 } 1816 1817 // Arguments that can be passed on register must be kept at 1818 // RegsToPass vector 1819 if (VA.isRegLoc()) { 1820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1821 continue; 1822 } 1823 1824 // Register can't get to this point... 1825 assert(VA.isMemLoc()); 1826 1827 // ByVal Arg. 1828 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1829 if (Flags.isByVal()) { 1830 assert(Subtarget->isABI_O32() && 1831 "No support for ByVal args by ABIs other than O32 yet."); 1832 assert(Flags.getByValSize() && 1833 "ByVal args of size 0 should have been ignored by front-end."); 1834 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg, 1835 VA, Flags, getPointerTy()); 1836 continue; 1837 } 1838 1839 // Create the frame index object for this incoming parameter 1840 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1841 VA.getLocMemOffset(), true); 1842 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 1843 1844 // emit ISD::STORE whichs stores the 1845 // parameter value to a stack Location 1846 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 1847 MachinePointerInfo(), 1848 false, false, 0)); 1849 } 1850 1851 // Extend range of indices of frame objects for outgoing arguments that were 1852 // created during this function call. Skip this step if no such objects were 1853 // created. 1854 if (LastFI) 1855 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 1856 1857 // Transform all store nodes into one single node because all store 1858 // nodes are independent of each other. 1859 if (!MemOpChains.empty()) 1860 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1861 &MemOpChains[0], MemOpChains.size()); 1862 1863 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1864 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1865 // node so that legalize doesn't hack it. 1866 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 1867 bool LoadSymAddr = false; 1868 SDValue CalleeLo; 1869 1870 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1871 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 1872 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1873 getPointerTy(), 0,MipsII:: MO_GOT); 1874 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 1875 0, MipsII::MO_ABS_LO); 1876 } else { 1877 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1878 getPointerTy(), 0, OpFlag); 1879 } 1880 1881 LoadSymAddr = true; 1882 } 1883 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1884 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 1885 getPointerTy(), OpFlag); 1886 LoadSymAddr = true; 1887 } 1888 1889 SDValue InFlag; 1890 1891 // Create nodes that load address of callee and copy it to T9 1892 if (IsPIC) { 1893 if (LoadSymAddr) { 1894 // Load callee address 1895 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee); 1896 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee, 1897 MachinePointerInfo::getGOT(), 1898 false, false, 0); 1899 1900 // Use GOT+LO if callee has internal linkage. 1901 if (CalleeLo.getNode()) { 1902 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 1903 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 1904 } else 1905 Callee = LoadValue; 1906 } 1907 1908 // copy to T9 1909 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 1910 InFlag = Chain.getValue(1); 1911 Callee = DAG.getRegister(Mips::T9, MVT::i32); 1912 } 1913 1914 // Build a sequence of copy-to-reg nodes chained together with token 1915 // chain and flag operands which copy the outgoing args into registers. 1916 // The InFlag in necessary since all emitted instructions must be 1917 // stuck together. 1918 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1919 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1920 RegsToPass[i].second, InFlag); 1921 InFlag = Chain.getValue(1); 1922 } 1923 1924 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 1925 // = Chain, Callee, Reg#1, Reg#2, ... 1926 // 1927 // Returns a chain & a flag for retval copy to use. 1928 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1929 SmallVector<SDValue, 8> Ops; 1930 Ops.push_back(Chain); 1931 Ops.push_back(Callee); 1932 1933 // Add argument registers to the end of the list so that they are 1934 // known live into the call. 1935 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1936 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1937 RegsToPass[i].second.getValueType())); 1938 1939 if (InFlag.getNode()) 1940 Ops.push_back(InFlag); 1941 1942 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 1943 InFlag = Chain.getValue(1); 1944 1945 // Create the CALLSEQ_END node. 1946 Chain = DAG.getCALLSEQ_END(Chain, 1947 DAG.getIntPtrConstant(NextStackOffset, true), 1948 DAG.getIntPtrConstant(0, true), InFlag); 1949 InFlag = Chain.getValue(1); 1950 1951 // Handle result values, copying them out of physregs into vregs that we 1952 // return. 1953 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 1954 Ins, dl, DAG, InVals); 1955 } 1956 1957 /// LowerCallResult - Lower the result values of a call into the 1958 /// appropriate copies out of appropriate physical registers. 1959 SDValue 1960 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1961 CallingConv::ID CallConv, bool isVarArg, 1962 const SmallVectorImpl<ISD::InputArg> &Ins, 1963 DebugLoc dl, SelectionDAG &DAG, 1964 SmallVectorImpl<SDValue> &InVals) const { 1965 // Assign locations to each value returned by this call. 1966 SmallVector<CCValAssign, 16> RVLocs; 1967 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1968 getTargetMachine(), RVLocs, *DAG.getContext()); 1969 1970 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 1971 1972 // Copy all of the result registers out of their specified physreg. 1973 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1974 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 1975 RVLocs[i].getValVT(), InFlag).getValue(1); 1976 InFlag = Chain.getValue(2); 1977 InVals.push_back(Chain.getValue(0)); 1978 } 1979 1980 return Chain; 1981 } 1982 1983 //===----------------------------------------------------------------------===// 1984 // Formal Arguments Calling Convention Implementation 1985 //===----------------------------------------------------------------------===// 1986 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 1987 std::vector<SDValue>& OutChains, 1988 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 1989 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 1990 unsigned LocMem = VA.getLocMemOffset(); 1991 unsigned FirstWord = LocMem / 4; 1992 1993 // copy register A0 - A3 to frame object 1994 for (unsigned i = 0; i < NumWords; ++i) { 1995 unsigned CurWord = FirstWord + i; 1996 if (CurWord >= O32IntRegsSize) 1997 break; 1998 1999 unsigned SrcReg = O32IntRegs[CurWord]; 2000 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2001 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2002 DAG.getConstant(i * 4, MVT::i32)); 2003 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2004 StorePtr, MachinePointerInfo(), false, 2005 false, 0); 2006 OutChains.push_back(Store); 2007 } 2008 } 2009 2010 /// LowerFormalArguments - transform physical registers into virtual registers 2011 /// and generate load operations for arguments places on the stack. 2012 SDValue 2013 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2014 CallingConv::ID CallConv, 2015 bool isVarArg, 2016 const SmallVectorImpl<ISD::InputArg> 2017 &Ins, 2018 DebugLoc dl, SelectionDAG &DAG, 2019 SmallVectorImpl<SDValue> &InVals) 2020 const { 2021 MachineFunction &MF = DAG.getMachineFunction(); 2022 MachineFrameInfo *MFI = MF.getFrameInfo(); 2023 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2024 2025 MipsFI->setVarArgsFrameIndex(0); 2026 2027 // Used with vargs to acumulate store chains. 2028 std::vector<SDValue> OutChains; 2029 2030 // Assign locations to all of the incoming arguments. 2031 SmallVector<CCValAssign, 16> ArgLocs; 2032 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2033 getTargetMachine(), ArgLocs, *DAG.getContext()); 2034 2035 if (Subtarget->isABI_O32()) 2036 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2037 else 2038 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2039 2040 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2041 2042 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2043 CCValAssign &VA = ArgLocs[i]; 2044 2045 // Arguments stored on registers 2046 if (VA.isRegLoc()) { 2047 EVT RegVT = VA.getLocVT(); 2048 unsigned ArgReg = VA.getLocReg(); 2049 TargetRegisterClass *RC = 0; 2050 2051 if (RegVT == MVT::i32) 2052 RC = Mips::CPURegsRegisterClass; 2053 else if (RegVT == MVT::f32) 2054 RC = Mips::FGR32RegisterClass; 2055 else if (RegVT == MVT::f64) { 2056 if (!Subtarget->isSingleFloat()) 2057 RC = Mips::AFGR64RegisterClass; 2058 } else 2059 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2060 2061 // Transform the arguments stored on 2062 // physical registers into virtual ones 2063 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2064 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2065 2066 // If this is an 8 or 16-bit value, it has been passed promoted 2067 // to 32 bits. Insert an assert[sz]ext to capture this, then 2068 // truncate to the right size. 2069 if (VA.getLocInfo() != CCValAssign::Full) { 2070 unsigned Opcode = 0; 2071 if (VA.getLocInfo() == CCValAssign::SExt) 2072 Opcode = ISD::AssertSext; 2073 else if (VA.getLocInfo() == CCValAssign::ZExt) 2074 Opcode = ISD::AssertZext; 2075 if (Opcode) 2076 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2077 DAG.getValueType(VA.getValVT())); 2078 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2079 } 2080 2081 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 2082 if (Subtarget->isABI_O32()) { 2083 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 2084 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 2085 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 2086 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2087 VA.getLocReg()+1, RC); 2088 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2089 if (!Subtarget->isLittle()) 2090 std::swap(ArgValue, ArgValue2); 2091 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2092 ArgValue, ArgValue2); 2093 } 2094 } 2095 2096 InVals.push_back(ArgValue); 2097 } else { // VA.isRegLoc() 2098 2099 // sanity check 2100 assert(VA.isMemLoc()); 2101 2102 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2103 2104 if (Flags.isByVal()) { 2105 assert(Subtarget->isABI_O32() && 2106 "No support for ByVal args by ABIs other than O32 yet."); 2107 assert(Flags.getByValSize() && 2108 "ByVal args of size 0 should have been ignored by front-end."); 2109 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2110 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2111 true); 2112 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2113 InVals.push_back(FIN); 2114 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2115 2116 continue; 2117 } 2118 2119 // The stack pointer offset is relative to the caller stack frame. 2120 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2121 VA.getLocMemOffset(), true); 2122 2123 // Create load nodes to retrieve arguments from the stack 2124 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2125 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2126 MachinePointerInfo::getFixedStack(LastFI), 2127 false, false, 0)); 2128 } 2129 } 2130 2131 // The mips ABIs for returning structs by value requires that we copy 2132 // the sret argument into $v0 for the return. Save the argument into 2133 // a virtual register so that we can access it from the return points. 2134 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2135 unsigned Reg = MipsFI->getSRetReturnReg(); 2136 if (!Reg) { 2137 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2138 MipsFI->setSRetReturnReg(Reg); 2139 } 2140 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2141 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2142 } 2143 2144 if (isVarArg && Subtarget->isABI_O32()) { 2145 // Record the frame index of the first variable argument 2146 // which is a value necessary to VASTART. 2147 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2148 assert(NextStackOffset % 4 == 0 && 2149 "NextStackOffset must be aligned to 4-byte boundaries."); 2150 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2151 MipsFI->setVarArgsFrameIndex(LastFI); 2152 2153 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2154 // copy the integer registers that have not been used for argument passing 2155 // to the caller's stack frame. 2156 for (; NextStackOffset < 16; NextStackOffset += 4) { 2157 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2158 unsigned Idx = NextStackOffset / 4; 2159 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2160 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2161 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2162 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2163 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2164 MachinePointerInfo(), 2165 false, false, 0)); 2166 } 2167 } 2168 2169 MipsFI->setLastInArgFI(LastFI); 2170 2171 // All stores are grouped in one node to allow the matching between 2172 // the size of Ins and InVals. This only happens when on varg functions 2173 if (!OutChains.empty()) { 2174 OutChains.push_back(Chain); 2175 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2176 &OutChains[0], OutChains.size()); 2177 } 2178 2179 return Chain; 2180 } 2181 2182 //===----------------------------------------------------------------------===// 2183 // Return Value Calling Convention Implementation 2184 //===----------------------------------------------------------------------===// 2185 2186 SDValue 2187 MipsTargetLowering::LowerReturn(SDValue Chain, 2188 CallingConv::ID CallConv, bool isVarArg, 2189 const SmallVectorImpl<ISD::OutputArg> &Outs, 2190 const SmallVectorImpl<SDValue> &OutVals, 2191 DebugLoc dl, SelectionDAG &DAG) const { 2192 2193 // CCValAssign - represent the assignment of 2194 // the return value to a location 2195 SmallVector<CCValAssign, 16> RVLocs; 2196 2197 // CCState - Info about the registers and stack slot. 2198 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2199 getTargetMachine(), RVLocs, *DAG.getContext()); 2200 2201 // Analize return values. 2202 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2203 2204 // If this is the first return lowered for this function, add 2205 // the regs to the liveout set for the function. 2206 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2207 for (unsigned i = 0; i != RVLocs.size(); ++i) 2208 if (RVLocs[i].isRegLoc()) 2209 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2210 } 2211 2212 SDValue Flag; 2213 2214 // Copy the result values into the output registers. 2215 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2216 CCValAssign &VA = RVLocs[i]; 2217 assert(VA.isRegLoc() && "Can only return in registers!"); 2218 2219 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2220 OutVals[i], Flag); 2221 2222 // guarantee that all emitted copies are 2223 // stuck together, avoiding something bad 2224 Flag = Chain.getValue(1); 2225 } 2226 2227 // The mips ABIs for returning structs by value requires that we copy 2228 // the sret argument into $v0 for the return. We saved the argument into 2229 // a virtual register in the entry block, so now we copy the value out 2230 // and into $v0. 2231 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2232 MachineFunction &MF = DAG.getMachineFunction(); 2233 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2234 unsigned Reg = MipsFI->getSRetReturnReg(); 2235 2236 if (!Reg) 2237 llvm_unreachable("sret virtual register not created in the entry block"); 2238 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2239 2240 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2241 Flag = Chain.getValue(1); 2242 } 2243 2244 // Return on Mips is always a "jr $ra" 2245 if (Flag.getNode()) 2246 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2247 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2248 else // Return Void 2249 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2250 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2251 } 2252 2253 //===----------------------------------------------------------------------===// 2254 // Mips Inline Assembly Support 2255 //===----------------------------------------------------------------------===// 2256 2257 /// getConstraintType - Given a constraint letter, return the type of 2258 /// constraint it is for this target. 2259 MipsTargetLowering::ConstraintType MipsTargetLowering:: 2260 getConstraintType(const std::string &Constraint) const 2261 { 2262 // Mips specific constrainy 2263 // GCC config/mips/constraints.md 2264 // 2265 // 'd' : An address register. Equivalent to r 2266 // unless generating MIPS16 code. 2267 // 'y' : Equivalent to r; retained for 2268 // backwards compatibility. 2269 // 'f' : Floating Point registers. 2270 if (Constraint.size() == 1) { 2271 switch (Constraint[0]) { 2272 default : break; 2273 case 'd': 2274 case 'y': 2275 case 'f': 2276 return C_RegisterClass; 2277 break; 2278 } 2279 } 2280 return TargetLowering::getConstraintType(Constraint); 2281 } 2282 2283 /// Examine constraint type and operand type and determine a weight value. 2284 /// This object must already have been set up with the operand type 2285 /// and the current alternative constraint selected. 2286 TargetLowering::ConstraintWeight 2287 MipsTargetLowering::getSingleConstraintMatchWeight( 2288 AsmOperandInfo &info, const char *constraint) const { 2289 ConstraintWeight weight = CW_Invalid; 2290 Value *CallOperandVal = info.CallOperandVal; 2291 // If we don't have a value, we can't do a match, 2292 // but allow it at the lowest weight. 2293 if (CallOperandVal == NULL) 2294 return CW_Default; 2295 Type *type = CallOperandVal->getType(); 2296 // Look at the constraint type. 2297 switch (*constraint) { 2298 default: 2299 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2300 break; 2301 case 'd': 2302 case 'y': 2303 if (type->isIntegerTy()) 2304 weight = CW_Register; 2305 break; 2306 case 'f': 2307 if (type->isFloatTy()) 2308 weight = CW_Register; 2309 break; 2310 } 2311 return weight; 2312 } 2313 2314 /// Given a register class constraint, like 'r', if this corresponds directly 2315 /// to an LLVM register class, return a register of 0 and the register class 2316 /// pointer. 2317 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2318 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2319 { 2320 if (Constraint.size() == 1) { 2321 switch (Constraint[0]) { 2322 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2323 case 'y': // Same as 'r'. Exists for compatibility. 2324 case 'r': 2325 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2326 case 'f': 2327 if (VT == MVT::f32) 2328 return std::make_pair(0U, Mips::FGR32RegisterClass); 2329 if (VT == MVT::f64) 2330 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2331 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2332 break; 2333 } 2334 } 2335 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2336 } 2337 2338 bool 2339 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2340 // The Mips target isn't yet aware of offsets. 2341 return false; 2342 } 2343 2344 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2345 if (VT != MVT::f32 && VT != MVT::f64) 2346 return false; 2347 if (Imm.isNegZero()) 2348 return false; 2349 return Imm.isZero(); 2350 } 2351
