1 //======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb1 implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb1FrameLowering.h" 15 #include "ARMBaseInstrInfo.h" 16 #include "ARMMachineFunctionInfo.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 22 using namespace llvm; 23 24 bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{ 25 const MachineFrameInfo *FFI = MF.getFrameInfo(); 26 unsigned CFSize = FFI->getMaxCallFrameSize(); 27 // It's not always a good idea to include the call frame as part of the 28 // stack frame. ARM (especially Thumb) has small immediate offset to 29 // address the stack frame. So a large call frame can cause poor codegen 30 // and may even makes it impossible to scavenge a register. 31 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 32 return false; 33 34 return !MF.getFrameInfo()->hasVarSizedObjects(); 35 } 36 37 static void 38 emitSPUpdate(MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator &MBBI, 40 const TargetInstrInfo &TII, DebugLoc dl, 41 const Thumb1RegisterInfo &MRI, 42 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 43 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, 44 MRI, MIFlags); 45 } 46 47 void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { 48 MachineBasicBlock &MBB = MF.front(); 49 MachineBasicBlock::iterator MBBI = MBB.begin(); 50 MachineFrameInfo *MFI = MF.getFrameInfo(); 51 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 52 const Thumb1RegisterInfo *RegInfo = 53 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 54 const Thumb1InstrInfo &TII = 55 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 56 57 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 58 unsigned NumBytes = MFI->getStackSize(); 59 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 60 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 61 unsigned FramePtr = RegInfo->getFrameRegister(MF); 62 unsigned BasePtr = RegInfo->getBaseRegister(); 63 64 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. 65 NumBytes = (NumBytes + 3) & ~3; 66 MFI->setStackSize(NumBytes); 67 68 // Determine the sizes of each callee-save spill areas and record which frame 69 // belongs to which callee-save spill areas. 70 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 71 int FramePtrSpillFI = 0; 72 73 if (VARegSaveSize) 74 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize, 75 MachineInstr::FrameSetup); 76 77 if (!AFI->hasStackFrame()) { 78 if (NumBytes != 0) 79 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 80 MachineInstr::FrameSetup); 81 return; 82 } 83 84 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 85 unsigned Reg = CSI[i].getReg(); 86 int FI = CSI[i].getFrameIdx(); 87 switch (Reg) { 88 case ARM::R4: 89 case ARM::R5: 90 case ARM::R6: 91 case ARM::R7: 92 case ARM::LR: 93 if (Reg == FramePtr) 94 FramePtrSpillFI = FI; 95 AFI->addGPRCalleeSavedArea1Frame(FI); 96 GPRCS1Size += 4; 97 break; 98 case ARM::R8: 99 case ARM::R9: 100 case ARM::R10: 101 case ARM::R11: 102 if (Reg == FramePtr) 103 FramePtrSpillFI = FI; 104 if (STI.isTargetDarwin()) { 105 AFI->addGPRCalleeSavedArea2Frame(FI); 106 GPRCS2Size += 4; 107 } else { 108 AFI->addGPRCalleeSavedArea1Frame(FI); 109 GPRCS1Size += 4; 110 } 111 break; 112 default: 113 AFI->addDPRCalleeSavedAreaFrame(FI); 114 DPRCSSize += 8; 115 } 116 } 117 118 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { 119 ++MBBI; 120 if (MBBI != MBB.end()) 121 dl = MBBI->getDebugLoc(); 122 } 123 124 // Determine starting offsets of spill areas. 125 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 126 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 127 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 128 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 129 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 130 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 131 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 132 NumBytes = DPRCSOffset; 133 134 // Adjust FP so it point to the stack slot that contains the previous FP. 135 if (hasFP(MF)) { 136 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) 137 .addFrameIndex(FramePtrSpillFI).addImm(0) 138 .setMIFlags(MachineInstr::FrameSetup)); 139 if (NumBytes > 508) 140 // If offset is > 508 then sp cannot be adjusted in a single instruction, 141 // try restoring from fp instead. 142 AFI->setShouldRestoreSPFromFP(true); 143 } 144 145 if (NumBytes) 146 // Insert it after all the callee-save spills. 147 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, 148 MachineInstr::FrameSetup); 149 150 if (STI.isTargetELF() && hasFP(MF)) 151 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 152 AFI->getFramePtrSpillOffset()); 153 154 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 155 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 156 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 157 158 // If we need dynamic stack realignment, do it here. Be paranoid and make 159 // sure if we also have VLAs, we have a base pointer for frame access. 160 if (RegInfo->needsStackRealignment(MF)) { 161 // We cannot use sp as source/dest register here, thus we're emitting the 162 // following sequence: 163 // mov r4, sp 164 // lsrs r4, r4, Log2MaxAlign 165 // lsls r4, r4, Log2MaxAlign 166 // mov sp, r4 167 unsigned MaxAlign = MFI->getMaxAlignment(); 168 unsigned Log2MaxAlign = Log2_32(MaxAlign); 169 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 170 .addReg(ARM::SP, RegState::Kill)); 171 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), 172 ARM::R4)) 173 .addReg(ARM::R4, RegState::Kill) 174 .addImm(Log2MaxAlign)); 175 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), 176 ARM::R4)) 177 .addReg(ARM::R4, RegState::Kill) 178 .addImm(Log2MaxAlign)); 179 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 180 .addReg(ARM::R4, RegState::Kill)); 181 182 AFI->setShouldRestoreSPFromFP(true); 183 } 184 185 // If we need a base pointer, set it up here. It's whatever the value 186 // of the stack pointer is at this point. Any variable size objects 187 // will be allocated after this, so we can still use the base pointer 188 // to reference locals. 189 if (RegInfo->hasBasePointer(MF)) 190 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) 191 .addReg(ARM::SP)); 192 193 // If the frame has variable sized objects then the epilogue must restore 194 // the sp from fp. We can assume there's an FP here since hasFP already 195 // checks for hasVarSizedObjects. 196 if (MFI->hasVarSizedObjects()) 197 AFI->setShouldRestoreSPFromFP(true); 198 } 199 200 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 201 for (unsigned i = 0; CSRegs[i]; ++i) 202 if (Reg == CSRegs[i]) 203 return true; 204 return false; 205 } 206 207 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { 208 if (MI->getOpcode() == ARM::tLDRspi && 209 MI->getOperand(1).isFI() && 210 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) 211 return true; 212 else if (MI->getOpcode() == ARM::tPOP) { 213 // The first two operands are predicates. The last two are 214 // imp-def and imp-use of SP. Check everything in between. 215 for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) 216 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 217 return false; 218 return true; 219 } 220 return false; 221 } 222 223 void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, 224 MachineBasicBlock &MBB) const { 225 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 226 assert((MBBI->getOpcode() == ARM::tBX_RET || 227 MBBI->getOpcode() == ARM::tPOP_RET) && 228 "Can only insert epilog into returning blocks"); 229 DebugLoc dl = MBBI->getDebugLoc(); 230 MachineFrameInfo *MFI = MF.getFrameInfo(); 231 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 232 const Thumb1RegisterInfo *RegInfo = 233 static_cast<const Thumb1RegisterInfo*>(MF.getTarget().getRegisterInfo()); 234 const Thumb1InstrInfo &TII = 235 *static_cast<const Thumb1InstrInfo*>(MF.getTarget().getInstrInfo()); 236 237 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 238 int NumBytes = (int)MFI->getStackSize(); 239 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 240 unsigned FramePtr = RegInfo->getFrameRegister(MF); 241 242 if (!AFI->hasStackFrame()) { 243 if (NumBytes != 0) 244 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 245 } else { 246 // Unwind MBBI to point to first LDR / VLDRD. 247 if (MBBI != MBB.begin()) { 248 do 249 --MBBI; 250 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); 251 if (!isCSRestore(MBBI, CSRegs)) 252 ++MBBI; 253 } 254 255 // Move SP to start of FP callee save spill area. 256 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 257 AFI->getGPRCalleeSavedArea2Size() + 258 AFI->getDPRCalleeSavedAreaSize()); 259 260 if (AFI->shouldRestoreSPFromFP()) { 261 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 262 // Reset SP based on frame pointer only if the stack frame extends beyond 263 // frame pointer stack slot, the target is ELF and the function has FP, or 264 // the target uses var sized objects. 265 if (NumBytes) { 266 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 267 "No scratch register to restore SP from FP!"); 268 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 269 TII, *RegInfo); 270 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 271 ARM::SP) 272 .addReg(ARM::R4)); 273 } else 274 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 275 ARM::SP) 276 .addReg(FramePtr)); 277 } else { 278 if (MBBI->getOpcode() == ARM::tBX_RET && 279 &MBB.front() != MBBI && 280 prior(MBBI)->getOpcode() == ARM::tPOP) { 281 MachineBasicBlock::iterator PMBBI = prior(MBBI); 282 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes); 283 } else 284 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); 285 } 286 } 287 288 if (VARegSaveSize) { 289 // Unlike T2 and ARM mode, the T1 pop instruction cannot restore 290 // to LR, and we can't pop the value directly to the PC since 291 // we need to update the SP after popping the value. Therefore, we 292 // pop the old LR into R3 as a temporary. 293 294 // Move back past the callee-saved register restoration 295 while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs)) 296 ++MBBI; 297 // Epilogue for vararg functions: pop LR to R3 and branch off it. 298 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) 299 .addReg(ARM::R3, RegState::Define); 300 301 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize); 302 303 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) 304 .addReg(ARM::R3, RegState::Kill)); 305 // erase the old tBX_RET instruction 306 MBB.erase(MBBI); 307 } 308 } 309 310 bool Thumb1FrameLowering:: 311 spillCalleeSavedRegisters(MachineBasicBlock &MBB, 312 MachineBasicBlock::iterator MI, 313 const std::vector<CalleeSavedInfo> &CSI, 314 const TargetRegisterInfo *TRI) const { 315 if (CSI.empty()) 316 return false; 317 318 DebugLoc DL; 319 MachineFunction &MF = *MBB.getParent(); 320 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 321 322 if (MI != MBB.end()) DL = MI->getDebugLoc(); 323 324 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); 325 AddDefaultPred(MIB); 326 for (unsigned i = CSI.size(); i != 0; --i) { 327 unsigned Reg = CSI[i-1].getReg(); 328 bool isKill = true; 329 330 // Add the callee-saved register as live-in unless it's LR and 331 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress 332 // then it's already added to the function and entry block live-in sets. 333 if (Reg == ARM::LR) { 334 MachineFunction &MF = *MBB.getParent(); 335 if (MF.getFrameInfo()->isReturnAddressTaken() && 336 MF.getRegInfo().isLiveIn(Reg)) 337 isKill = false; 338 } 339 340 if (isKill) 341 MBB.addLiveIn(Reg); 342 343 MIB.addReg(Reg, getKillRegState(isKill)); 344 } 345 MIB.setMIFlags(MachineInstr::FrameSetup); 346 return true; 347 } 348 349 bool Thumb1FrameLowering:: 350 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 351 MachineBasicBlock::iterator MI, 352 const std::vector<CalleeSavedInfo> &CSI, 353 const TargetRegisterInfo *TRI) const { 354 if (CSI.empty()) 355 return false; 356 357 MachineFunction &MF = *MBB.getParent(); 358 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 359 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 360 361 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 362 DebugLoc DL = MI->getDebugLoc(); 363 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); 364 AddDefaultPred(MIB); 365 366 bool NumRegs = false; 367 for (unsigned i = CSI.size(); i != 0; --i) { 368 unsigned Reg = CSI[i-1].getReg(); 369 if (Reg == ARM::LR) { 370 // Special epilogue for vararg functions. See emitEpilogue 371 if (isVarArg) 372 continue; 373 Reg = ARM::PC; 374 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); 375 MI = MBB.erase(MI); 376 } 377 MIB.addReg(Reg, getDefRegState(true)); 378 NumRegs = true; 379 } 380 381 // It's illegal to emit pop instruction without operands. 382 if (NumRegs) 383 MBB.insert(MI, &*MIB); 384 else 385 MF.DeleteMachineInstr(MIB); 386 387 return true; 388 } 389
