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      1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the X86 implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef X86INSTRUCTIONINFO_H
     15 #define X86INSTRUCTIONINFO_H
     16 
     17 #include "X86.h"
     18 #include "X86RegisterInfo.h"
     19 #include "llvm/ADT/DenseMap.h"
     20 #include "llvm/Target/TargetInstrInfo.h"
     21 
     22 #define GET_INSTRINFO_HEADER
     23 #include "X86GenInstrInfo.inc"
     24 
     25 namespace llvm {
     26   class X86RegisterInfo;
     27   class X86TargetMachine;
     28 
     29 namespace X86 {
     30   // X86 specific condition code. These correspond to X86_*_COND in
     31   // X86InstrInfo.td. They must be kept in synch.
     32   enum CondCode {
     33     COND_A  = 0,
     34     COND_AE = 1,
     35     COND_B  = 2,
     36     COND_BE = 3,
     37     COND_E  = 4,
     38     COND_G  = 5,
     39     COND_GE = 6,
     40     COND_L  = 7,
     41     COND_LE = 8,
     42     COND_NE = 9,
     43     COND_NO = 10,
     44     COND_NP = 11,
     45     COND_NS = 12,
     46     COND_O  = 13,
     47     COND_P  = 14,
     48     COND_S  = 15,
     49 
     50     // Artificial condition codes. These are used by AnalyzeBranch
     51     // to indicate a block terminated with two conditional branches to
     52     // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
     53     // which can't be represented on x86 with a single condition. These
     54     // are never used in MachineInstrs.
     55     COND_NE_OR_P,
     56     COND_NP_OR_E,
     57 
     58     COND_INVALID
     59   };
     60 
     61   // Turn condition code into conditional branch opcode.
     62   unsigned GetCondBranchFromCond(CondCode CC);
     63 
     64   /// GetOppositeBranchCondition - Return the inverse of the specified cond,
     65   /// e.g. turning COND_E to COND_NE.
     66   CondCode GetOppositeBranchCondition(X86::CondCode CC);
     67 }  // end namespace X86;
     68 
     69 
     70 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
     71 /// a reference to a stub for a global, not the global itself.
     72 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
     73   switch (TargetFlag) {
     74   case X86II::MO_DLLIMPORT: // dllimport stub.
     75   case X86II::MO_GOTPCREL:  // rip-relative GOT reference.
     76   case X86II::MO_GOT:       // normal GOT reference.
     77   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Normal $non_lazy_ptr ref.
     78   case X86II::MO_DARWIN_NONLAZY:                 // Normal $non_lazy_ptr ref.
     79   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
     80     return true;
     81   default:
     82     return false;
     83   }
     84 }
     85 
     86 /// isGlobalRelativeToPICBase - Return true if the specified global value
     87 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).  If this
     88 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
     89 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
     90   switch (TargetFlag) {
     91   case X86II::MO_GOTOFF:                         // isPICStyleGOT: local global.
     92   case X86II::MO_GOT:                            // isPICStyleGOT: other global.
     93   case X86II::MO_PIC_BASE_OFFSET:                // Darwin local global.
     94   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Darwin/32 external global.
     95   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
     96   case X86II::MO_TLVP:                           // ??? Pretty sure..
     97     return true;
     98   default:
     99     return false;
    100   }
    101 }
    102 
    103 inline static bool isScale(const MachineOperand &MO) {
    104   return MO.isImm() &&
    105     (MO.getImm() == 1 || MO.getImm() == 2 ||
    106      MO.getImm() == 4 || MO.getImm() == 8);
    107 }
    108 
    109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
    110   if (MI->getOperand(Op).isFI()) return true;
    111   return Op+4 <= MI->getNumOperands() &&
    112     MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
    113     MI->getOperand(Op+2).isReg() &&
    114     (MI->getOperand(Op+3).isImm() ||
    115      MI->getOperand(Op+3).isGlobal() ||
    116      MI->getOperand(Op+3).isCPI() ||
    117      MI->getOperand(Op+3).isJTI());
    118 }
    119 
    120 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
    121   if (MI->getOperand(Op).isFI()) return true;
    122   return Op+5 <= MI->getNumOperands() &&
    123     MI->getOperand(Op+4).isReg() &&
    124     isLeaMem(MI, Op);
    125 }
    126 
    127 class X86InstrInfo : public X86GenInstrInfo {
    128   X86TargetMachine &TM;
    129   const X86RegisterInfo RI;
    130 
    131   /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
    132   /// RegOp2MemOpTable2 - Load / store folding opcode maps.
    133   ///
    134   typedef DenseMap<unsigned,
    135                    std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
    136   RegOp2MemOpTableType RegOp2MemOpTable2Addr;
    137   RegOp2MemOpTableType RegOp2MemOpTable0;
    138   RegOp2MemOpTableType RegOp2MemOpTable1;
    139   RegOp2MemOpTableType RegOp2MemOpTable2;
    140 
    141   /// MemOp2RegOpTable - Load / store unfolding opcode map.
    142   ///
    143   typedef DenseMap<unsigned,
    144                    std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
    145   MemOp2RegOpTableType MemOp2RegOpTable;
    146 
    147   void AddTableEntry(RegOp2MemOpTableType &R2MTable,
    148                      MemOp2RegOpTableType &M2RTable,
    149                      unsigned RegOp, unsigned MemOp, unsigned Flags);
    150 
    151 public:
    152   explicit X86InstrInfo(X86TargetMachine &tm);
    153 
    154   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
    155   /// such, whenever a client has an instance of instruction info, it should
    156   /// always be able to get register info as well (through this method).
    157   ///
    158   virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
    159 
    160   /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
    161   /// extension instruction. That is, it's like a copy where it's legal for the
    162   /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
    163   /// true, then it's expected the pre-extension value is available as a subreg
    164   /// of the result register. This also returns the sub-register index in
    165   /// SubIdx.
    166   virtual bool isCoalescableExtInstr(const MachineInstr &MI,
    167                                      unsigned &SrcReg, unsigned &DstReg,
    168                                      unsigned &SubIdx) const;
    169 
    170   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
    171   /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
    172   /// stack locations as well.  This uses a heuristic so it isn't
    173   /// reliable for correctness.
    174   unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
    175                                      int &FrameIndex) const;
    176 
    177   unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
    178   /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
    179   /// stack locations as well.  This uses a heuristic so it isn't
    180   /// reliable for correctness.
    181   unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
    182                                     int &FrameIndex) const;
    183 
    184   bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
    185                                          AliasAnalysis *AA) const;
    186   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
    187                      unsigned DestReg, unsigned SubIdx,
    188                      const MachineInstr *Orig,
    189                      const TargetRegisterInfo &TRI) const;
    190 
    191   /// convertToThreeAddress - This method must be implemented by targets that
    192   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
    193   /// may be able to convert a two-address instruction into a true
    194   /// three-address instruction on demand.  This allows the X86 target (for
    195   /// example) to convert ADD and SHL instructions into LEA instructions if they
    196   /// would require register copies due to two-addressness.
    197   ///
    198   /// This method returns a null pointer if the transformation cannot be
    199   /// performed, otherwise it returns the new instruction.
    200   ///
    201   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
    202                                               MachineBasicBlock::iterator &MBBI,
    203                                               LiveVariables *LV) const;
    204 
    205   /// commuteInstruction - We have a few instructions that must be hacked on to
    206   /// commute them.
    207   ///
    208   virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
    209 
    210   // Branch analysis.
    211   virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
    212   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
    213                              MachineBasicBlock *&FBB,
    214                              SmallVectorImpl<MachineOperand> &Cond,
    215                              bool AllowModify) const;
    216   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
    217   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
    218                                 MachineBasicBlock *FBB,
    219                                 const SmallVectorImpl<MachineOperand> &Cond,
    220                                 DebugLoc DL) const;
    221   virtual void copyPhysReg(MachineBasicBlock &MBB,
    222                            MachineBasicBlock::iterator MI, DebugLoc DL,
    223                            unsigned DestReg, unsigned SrcReg,
    224                            bool KillSrc) const;
    225   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
    226                                    MachineBasicBlock::iterator MI,
    227                                    unsigned SrcReg, bool isKill, int FrameIndex,
    228                                    const TargetRegisterClass *RC,
    229                                    const TargetRegisterInfo *TRI) const;
    230 
    231   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
    232                               SmallVectorImpl<MachineOperand> &Addr,
    233                               const TargetRegisterClass *RC,
    234                               MachineInstr::mmo_iterator MMOBegin,
    235                               MachineInstr::mmo_iterator MMOEnd,
    236                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
    237 
    238   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
    239                                     MachineBasicBlock::iterator MI,
    240                                     unsigned DestReg, int FrameIndex,
    241                                     const TargetRegisterClass *RC,
    242                                     const TargetRegisterInfo *TRI) const;
    243 
    244   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
    245                                SmallVectorImpl<MachineOperand> &Addr,
    246                                const TargetRegisterClass *RC,
    247                                MachineInstr::mmo_iterator MMOBegin,
    248                                MachineInstr::mmo_iterator MMOEnd,
    249                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
    250 
    251   virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
    252 
    253   virtual
    254   MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
    255                                          int FrameIx, uint64_t Offset,
    256                                          const MDNode *MDPtr,
    257                                          DebugLoc DL) const;
    258 
    259   /// foldMemoryOperand - If this target supports it, fold a load or store of
    260   /// the specified stack slot into the specified machine instruction for the
    261   /// specified operand(s).  If this is possible, the target should perform the
    262   /// folding and return true, otherwise it should return false.  If it folds
    263   /// the instruction, it is likely that the MachineInstruction the iterator
    264   /// references has been changed.
    265   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
    266                                               MachineInstr* MI,
    267                                            const SmallVectorImpl<unsigned> &Ops,
    268                                               int FrameIndex) const;
    269 
    270   /// foldMemoryOperand - Same as the previous version except it allows folding
    271   /// of any load and store from / to any address, not just from a specific
    272   /// stack slot.
    273   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
    274                                               MachineInstr* MI,
    275                                            const SmallVectorImpl<unsigned> &Ops,
    276                                               MachineInstr* LoadMI) const;
    277 
    278   /// canFoldMemoryOperand - Returns true if the specified load / store is
    279   /// folding is possible.
    280   virtual bool canFoldMemoryOperand(const MachineInstr*,
    281                                     const SmallVectorImpl<unsigned> &) const;
    282 
    283   /// unfoldMemoryOperand - Separate a single instruction which folded a load or
    284   /// a store or a load and a store into two or more instruction. If this is
    285   /// possible, returns true as well as the new instructions by reference.
    286   virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
    287                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
    288                            SmallVectorImpl<MachineInstr*> &NewMIs) const;
    289 
    290   virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
    291                            SmallVectorImpl<SDNode*> &NewNodes) const;
    292 
    293   /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
    294   /// instruction after load / store are unfolded from an instruction of the
    295   /// specified opcode. It returns zero if the specified unfolding is not
    296   /// possible. If LoadRegIndex is non-null, it is filled in with the operand
    297   /// index of the operand which will hold the register holding the loaded
    298   /// value.
    299   virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
    300                                       bool UnfoldLoad, bool UnfoldStore,
    301                                       unsigned *LoadRegIndex = 0) const;
    302 
    303   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
    304   /// to determine if two loads are loading from the same base address. It
    305   /// should only return true if the base pointers are the same and the
    306   /// only differences between the two addresses are the offset. It also returns
    307   /// the offsets by reference.
    308   virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
    309                                        int64_t &Offset1, int64_t &Offset2) const;
    310 
    311   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
    312   /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
    313   /// be scheduled togther. On some targets if two loads are loading from
    314   /// addresses in the same cache line, it's better if they are scheduled
    315   /// together. This function takes two integers that represent the load offsets
    316   /// from the common base address. It returns true if it decides it's desirable
    317   /// to schedule the two loads together. "NumLoads" is the number of loads that
    318   /// have already been scheduled after Load1.
    319   virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
    320                                        int64_t Offset1, int64_t Offset2,
    321                                        unsigned NumLoads) const;
    322 
    323   virtual void getNoopForMachoTarget(MCInst &NopInst) const;
    324 
    325   virtual
    326   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
    327 
    328   /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
    329   /// instruction that defines the specified register class.
    330   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
    331 
    332   static bool isX86_64ExtendedReg(const MachineOperand &MO) {
    333     if (!MO.isReg()) return false;
    334     return X86II::isX86_64ExtendedReg(MO.getReg());
    335   }
    336 
    337   /// getGlobalBaseReg - Return a virtual register initialized with the
    338   /// the global base register value. Output instructions required to
    339   /// initialize the register in the function entry block, if necessary.
    340   ///
    341   unsigned getGlobalBaseReg(MachineFunction *MF) const;
    342 
    343   std::pair<uint16_t, uint16_t>
    344   getExecutionDomain(const MachineInstr *MI) const;
    345 
    346   void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
    347 
    348   unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
    349                                         const TargetRegisterInfo *TRI) const;
    350   void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
    351                                  const TargetRegisterInfo *TRI) const;
    352 
    353   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
    354                                       MachineInstr* MI,
    355                                       unsigned OpNum,
    356                                       const SmallVectorImpl<MachineOperand> &MOs,
    357                                       unsigned Size, unsigned Alignment) const;
    358 
    359   bool isHighLatencyDef(int opc) const;
    360 
    361   bool hasHighOperandLatency(const InstrItineraryData *ItinData,
    362                              const MachineRegisterInfo *MRI,
    363                              const MachineInstr *DefMI, unsigned DefIdx,
    364                              const MachineInstr *UseMI, unsigned UseIdx) const;
    365 
    366 private:
    367   MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
    368                                               MachineFunction::iterator &MFI,
    369                                               MachineBasicBlock::iterator &MBBI,
    370                                               LiveVariables *LV) const;
    371 
    372   /// isFrameOperand - Return true and the FrameIndex if the specified
    373   /// operand and follow operands form a reference to the stack frame.
    374   bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
    375                       int &FrameIndex) const;
    376 };
    377 
    378 } // End llvm namespace
    379 
    380 #endif
    381