1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the pass that transforms the ARM machine instructions into 11 // relocatable machine code. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "jit" 16 #include "ARM.h" 17 #include "ARMConstantPoolValue.h" 18 #include "ARMBaseInstrInfo.h" 19 #include "ARMRelocations.h" 20 #include "ARMSubtarget.h" 21 #include "ARMTargetMachine.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/Constants.h" 24 #include "llvm/DerivedTypes.h" 25 #include "llvm/Function.h" 26 #include "llvm/PassManager.h" 27 #include "llvm/CodeGen/JITCodeEmitter.h" 28 #include "llvm/CodeGen/MachineConstantPool.h" 29 #include "llvm/CodeGen/MachineFunctionPass.h" 30 #include "llvm/CodeGen/MachineInstr.h" 31 #include "llvm/CodeGen/MachineJumpTableInfo.h" 32 #include "llvm/CodeGen/MachineModuleInfo.h" 33 #include "llvm/CodeGen/Passes.h" 34 #include "llvm/ADT/Statistic.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #ifndef NDEBUG 39 #include <iomanip> 40 #endif 41 using namespace llvm; 42 43 STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45 namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMBaseInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMBaseInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstantToMemory(unsigned CPI, const Constant *CV); 92 void emitConstPoolInstruction(const MachineInstr &MI); 93 void emitMOVi32immInstruction(const MachineInstr &MI); 94 void emitMOVi2piecesInstruction(const MachineInstr &MI); 95 void emitLEApcrelInstruction(const MachineInstr &MI); 96 void emitLEApcrelJTInstruction(const MachineInstr &MI); 97 void emitPseudoMoveInstruction(const MachineInstr &MI); 98 void addPCLabel(unsigned LabelID); 99 void emitPseudoInstruction(const MachineInstr &MI); 100 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 101 const MCInstrDesc &MCID, 102 const MachineOperand &MO, 103 unsigned OpIdx); 104 105 unsigned getMachineSoImmOpValue(unsigned SoImm); 106 unsigned getAddrModeSBit(const MachineInstr &MI, 107 const MCInstrDesc &MCID) const; 108 109 void emitDataProcessingInstruction(const MachineInstr &MI, 110 unsigned ImplicitRd = 0, 111 unsigned ImplicitRn = 0); 112 113 void emitLoadStoreInstruction(const MachineInstr &MI, 114 unsigned ImplicitRd = 0, 115 unsigned ImplicitRn = 0); 116 117 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 118 unsigned ImplicitRn = 0); 119 120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 121 122 void emitMulFrmInstruction(const MachineInstr &MI); 123 124 void emitExtendInstruction(const MachineInstr &MI); 125 126 void emitMiscArithInstruction(const MachineInstr &MI); 127 128 void emitSaturateInstruction(const MachineInstr &MI); 129 130 void emitBranchInstruction(const MachineInstr &MI); 131 132 void emitInlineJumpTable(unsigned JTIndex); 133 134 void emitMiscBranchInstruction(const MachineInstr &MI); 135 136 void emitVFPArithInstruction(const MachineInstr &MI); 137 138 void emitVFPConversionInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 141 142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 143 144 void emitMiscInstruction(const MachineInstr &MI); 145 146 void emitNEONLaneInstruction(const MachineInstr &MI); 147 void emitNEONDupInstruction(const MachineInstr &MI); 148 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 149 void emitNEON2RegInstruction(const MachineInstr &MI); 150 void emitNEON3RegInstruction(const MachineInstr &MI); 151 152 /// getMachineOpValue - Return binary encoding of operand. If the machine 153 /// operand requires relocation, record the relocation and return zero. 154 unsigned getMachineOpValue(const MachineInstr &MI, 155 const MachineOperand &MO) const; 156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 158 } 159 160 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 161 // TableGen'erated getBinaryCodeForInstr() function to encode any 162 // operand values, instead querying getMachineOpValue() directly for 163 // each operand it needs to encode. Thus, any of the new encoder 164 // helper functions can simply return 0 as the values the return 165 // are already handled elsewhere. They are placeholders to allow this 166 // encoder to continue to function until the MC encoder is sufficiently 167 // far along that this one can be eliminated entirely. 168 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 169 const { return 0; } 170 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 171 const { return 0; } 172 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 173 const { return 0; } 174 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 175 const { 176 if (IsThumb) { 177 Val &= 0x0FFFFFFF; 178 Val |= 0xE0000000; 179 } 180 return Val; 181 } 182 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 189 const { return 0; } 190 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 199 unsigned Op) const { return 0; } 200 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 205 const { return 0; } 206 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 207 const { return 0; } 208 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 209 const { return 0; } 210 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 211 const { return 0; } 212 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op) 213 const { return 0; } 214 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op) 215 const { return 0; } 216 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 217 const { return 0; } 218 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 219 const { return 0; } 220 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 221 const { return 0; } 222 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) 223 const { return 0; } 224 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 225 const { return 0; } 226 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) 227 const { return 0; } 228 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 229 const { return 0; } 230 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 231 const { return 0; } 232 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 233 const { return 0; } 234 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 235 const { return 0; } 236 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 237 const { return 0; } 238 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 239 const { return 0; } 240 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, 241 unsigned Op) 242 const { return 0; } 243 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 244 const { return 0; } 245 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 246 const { return 0; } 247 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 248 unsigned Op) const { return 0; } 249 unsigned getSsatBitPosValue(const MachineInstr &MI, 250 unsigned Op) const { return 0; } 251 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 252 const {return 0; } 253 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 254 const { return 0; } 255 256 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 257 const { 258 // {17-13} = reg 259 // {12} = (U)nsigned (add == '1', sub == '0') 260 // {11-0} = imm12 261 const MachineOperand &MO = MI.getOperand(Op); 262 const MachineOperand &MO1 = MI.getOperand(Op + 1); 263 if (!MO.isReg()) { 264 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 265 return 0; 266 } 267 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); 268 int32_t Imm12 = MO1.getImm(); 269 uint32_t Binary; 270 Binary = Imm12 & 0xfff; 271 if (Imm12 >= 0) 272 Binary |= (1 << 12); 273 Binary |= (Reg << 13); 274 return Binary; 275 } 276 277 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) 278 const { 279 const MCInstrDesc &MCID = MI.getDesc(); 280 const MachineOperand &MO = MI.getOperand(Op); 281 282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? 283 ARM::reloc_arm_movw : ARM::reloc_arm_movt); 284 285 if (!MO.isImm()) { 286 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 287 return 0; 288 } 289 unsigned Imm16 = static_cast<unsigned>(MO.getImm()); 290 return Imm16; 291 } 292 293 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 294 const { return 0;} 295 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 296 const { return 0;} 297 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 298 const { return 0;} 299 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 300 const { return 0;} 301 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 302 const { return 0; } 303 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 304 const { return 0; } 305 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op) 306 const { return 0; } 307 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 308 const { return 0; } 309 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 310 const { return 0; } 311 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 312 // {12-9} = reg 313 // {8} = (U)nsigned (add == '1', sub == '0') 314 // {7-0} = imm8 315 uint32_t Binary = 0; 316 const MachineOperand &MO = MI.getOperand(Op); 317 const MachineOperand &MO1 = MI.getOperand(Op + 1); 318 if (!MO.isReg()) { 319 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 320 return 0; 321 } 322 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); 323 int32_t Imm12 = MO1.getImm(); 324 325 // Special value for #-0 326 if (Imm12 == INT32_MIN) 327 Imm12 = 0; 328 329 // Immediate is always encoded as positive. The 'U' bit controls add vs 330 // sub. 331 bool isAdd = true; 332 if (Imm12 < 0) { 333 Imm12 = -Imm12; 334 isAdd = false; 335 } 336 337 // If immediate offset is omitted, default to +0. 338 Binary |= 1 << 8; 339 return Binary; 340 } 341 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 342 const { return 0; } 343 344 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 345 const { return 0; } 346 347 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 348 const { return 0; } 349 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 350 const { return 0; } 351 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 352 const { return 0; } 353 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 354 const { return 0; } 355 356 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 357 /// machine operand requires relocation, record the relocation and return 358 /// zero. 359 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 360 unsigned Reloc); 361 362 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 363 /// 364 unsigned getShiftOp(unsigned Imm) const ; 365 366 /// Routines that handle operands which add machine relocations which are 367 /// fixed up by the relocation stage. 368 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 369 bool MayNeedFarStub, bool Indirect, 370 intptr_t ACPV = 0) const; 371 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 372 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 373 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 374 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 375 intptr_t JTBase = 0) const; 376 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const; 377 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const; 378 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const; 379 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const; 380 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const; 381 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const; 382 }; 383 } 384 385 char ARMCodeEmitter::ID = 0; 386 387 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 388 /// code to the specified MCE object. 389 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 390 JITCodeEmitter &JCE) { 391 return new ARMCodeEmitter(TM, JCE); 392 } 393 394 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 395 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 396 MF.getTarget().getRelocationModel() != Reloc::Static) && 397 "JIT relocation model must be set to static or default!"); 398 JTI = ((ARMBaseTargetMachine &)MF.getTarget()).getJITInfo(); 399 II = (const ARMBaseInstrInfo *)MF.getTarget().getInstrInfo(); 400 TD = MF.getTarget().getTargetData(); 401 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 402 MCPEs = &MF.getConstantPool()->getConstants(); 403 MJTEs = 0; 404 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 405 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 406 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 407 JTI->Initialize(MF, IsPIC); 408 MMI = &getAnalysis<MachineModuleInfo>(); 409 MCE.setModuleInfo(MMI); 410 411 do { 412 DEBUG(errs() << "JITTing function '" 413 << MF.getName() << "'\n"); 414 MCE.startFunction(MF); 415 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 416 MBB != E; ++MBB) { 417 MCE.StartMachineBasicBlock(MBB); 418 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 419 I != E; ++I) 420 emitInstruction(*I); 421 } 422 } while (MCE.finishFunction(MF)); 423 424 return false; 425 } 426 427 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 428 /// 429 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 430 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 431 default: llvm_unreachable("Unknown shift opc!"); 432 case ARM_AM::asr: return 2; 433 case ARM_AM::lsl: return 0; 434 case ARM_AM::lsr: return 1; 435 case ARM_AM::ror: 436 case ARM_AM::rrx: return 3; 437 } 438 } 439 440 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 441 /// machine operand requires relocation, record the relocation and return zero. 442 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 443 const MachineOperand &MO, 444 unsigned Reloc) { 445 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 446 && "Relocation to this function should be for movt or movw"); 447 448 if (MO.isImm()) 449 return static_cast<unsigned>(MO.getImm()); 450 else if (MO.isGlobal()) 451 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 452 else if (MO.isSymbol()) 453 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 454 else if (MO.isMBB()) 455 emitMachineBasicBlock(MO.getMBB(), Reloc); 456 else { 457 #ifndef NDEBUG 458 errs() << MO; 459 #endif 460 llvm_unreachable("Unsupported operand type for movw/movt"); 461 } 462 return 0; 463 } 464 465 /// getMachineOpValue - Return binary encoding of operand. If the machine 466 /// operand requires relocation, record the relocation and return zero. 467 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 468 const MachineOperand &MO) const { 469 if (MO.isReg()) 470 return II->getRegisterInfo().getEncodingValue(MO.getReg()); 471 else if (MO.isImm()) 472 return static_cast<unsigned>(MO.getImm()); 473 else if (MO.isFPImm()) 474 return static_cast<unsigned>(MO.getFPImm()->getValueAPF() 475 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 476 else if (MO.isGlobal()) 477 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 478 else if (MO.isSymbol()) 479 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 480 else if (MO.isCPI()) { 481 const MCInstrDesc &MCID = MI.getDesc(); 482 // For VFP load, the immediate offset is multiplied by 4. 483 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 484 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 485 emitConstPoolAddress(MO.getIndex(), Reloc); 486 } else if (MO.isJTI()) 487 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 488 else if (MO.isMBB()) 489 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 490 else 491 llvm_unreachable("Unable to encode MachineOperand!"); 492 return 0; 493 } 494 495 /// emitGlobalAddress - Emit the specified address to the code stream. 496 /// 497 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 498 bool MayNeedFarStub, bool Indirect, 499 intptr_t ACPV) const { 500 MachineRelocation MR = Indirect 501 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 502 const_cast<GlobalValue *>(GV), 503 ACPV, MayNeedFarStub) 504 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 505 const_cast<GlobalValue *>(GV), ACPV, 506 MayNeedFarStub); 507 MCE.addRelocation(MR); 508 } 509 510 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to 511 /// be emitted to the current location in the function, and allow it to be PC 512 /// relative. 513 void ARMCodeEmitter:: 514 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 515 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 516 Reloc, ES)); 517 } 518 519 /// emitConstPoolAddress - Arrange for the address of an constant pool 520 /// to be emitted to the current location in the function, and allow it to be PC 521 /// relative. 522 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 523 // Tell JIT emitter we'll resolve the address. 524 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 525 Reloc, CPI, 0, true)); 526 } 527 528 /// emitJumpTableAddress - Arrange for the address of a jump table to 529 /// be emitted to the current location in the function, and allow it to be PC 530 /// relative. 531 void ARMCodeEmitter:: 532 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 533 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 534 Reloc, JTIndex, 0, true)); 535 } 536 537 /// emitMachineBasicBlock - Emit the specified address basic block. 538 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 539 unsigned Reloc, 540 intptr_t JTBase) const { 541 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 542 Reloc, BB, JTBase)); 543 } 544 545 void ARMCodeEmitter::emitWordLE(unsigned Binary) { 546 DEBUG(errs() << " 0x"; 547 errs().write_hex(Binary) << "\n"); 548 MCE.emitWordLE(Binary); 549 } 550 551 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 552 DEBUG(errs() << " 0x"; 553 errs().write_hex(Binary) << "\n"); 554 MCE.emitDWordLE(Binary); 555 } 556 557 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 558 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 559 560 MCE.processDebugLoc(MI.getDebugLoc(), true); 561 562 ++NumEmitted; // Keep track of the # of mi's emitted 563 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 564 default: { 565 llvm_unreachable("Unhandled instruction encoding format!"); 566 } 567 case ARMII::MiscFrm: 568 if (MI.getOpcode() == ARM::LEApcrelJT) { 569 // Materialize jumptable address. 570 emitLEApcrelJTInstruction(MI); 571 break; 572 } 573 llvm_unreachable("Unhandled instruction encoding!"); 574 case ARMII::Pseudo: 575 emitPseudoInstruction(MI); 576 break; 577 case ARMII::DPFrm: 578 case ARMII::DPSoRegFrm: 579 emitDataProcessingInstruction(MI); 580 break; 581 case ARMII::LdFrm: 582 case ARMII::StFrm: 583 emitLoadStoreInstruction(MI); 584 break; 585 case ARMII::LdMiscFrm: 586 case ARMII::StMiscFrm: 587 emitMiscLoadStoreInstruction(MI); 588 break; 589 case ARMII::LdStMulFrm: 590 emitLoadStoreMultipleInstruction(MI); 591 break; 592 case ARMII::MulFrm: 593 emitMulFrmInstruction(MI); 594 break; 595 case ARMII::ExtFrm: 596 emitExtendInstruction(MI); 597 break; 598 case ARMII::ArithMiscFrm: 599 emitMiscArithInstruction(MI); 600 break; 601 case ARMII::SatFrm: 602 emitSaturateInstruction(MI); 603 break; 604 case ARMII::BrFrm: 605 emitBranchInstruction(MI); 606 break; 607 case ARMII::BrMiscFrm: 608 emitMiscBranchInstruction(MI); 609 break; 610 // VFP instructions. 611 case ARMII::VFPUnaryFrm: 612 case ARMII::VFPBinaryFrm: 613 emitVFPArithInstruction(MI); 614 break; 615 case ARMII::VFPConv1Frm: 616 case ARMII::VFPConv2Frm: 617 case ARMII::VFPConv3Frm: 618 case ARMII::VFPConv4Frm: 619 case ARMII::VFPConv5Frm: 620 emitVFPConversionInstruction(MI); 621 break; 622 case ARMII::VFPLdStFrm: 623 emitVFPLoadStoreInstruction(MI); 624 break; 625 case ARMII::VFPLdStMulFrm: 626 emitVFPLoadStoreMultipleInstruction(MI); 627 break; 628 case ARMII::VFPMiscFrm: 629 emitMiscInstruction(MI); 630 break; 631 // NEON instructions. 632 case ARMII::NGetLnFrm: 633 case ARMII::NSetLnFrm: 634 emitNEONLaneInstruction(MI); 635 break; 636 case ARMII::NDupFrm: 637 emitNEONDupInstruction(MI); 638 break; 639 case ARMII::N1RegModImmFrm: 640 emitNEON1RegModImmInstruction(MI); 641 break; 642 case ARMII::N2RegFrm: 643 emitNEON2RegInstruction(MI); 644 break; 645 case ARMII::N3RegFrm: 646 emitNEON3RegInstruction(MI); 647 break; 648 } 649 MCE.processDebugLoc(MI.getDebugLoc(), false); 650 } 651 652 void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) { 653 DEBUG({ 654 errs() << " ** Constant pool #" << CPI << " @ " 655 << (void*)MCE.getCurrentPCValue() << " "; 656 if (const Function *F = dyn_cast<Function>(C)) 657 errs() << F->getName(); 658 else 659 errs() << *C; 660 errs() << '\n'; 661 }); 662 663 switch (C->getValueID()) { 664 default: { 665 llvm_unreachable("Unable to handle this constantpool entry!"); 666 break; 667 } 668 case Value::GlobalVariableVal: { 669 emitGlobalAddress(static_cast<const GlobalValue*>(C), 670 ARM::reloc_arm_absolute, isa<Function>(C), false); 671 emitWordLE(0); 672 break; 673 } 674 case Value::ConstantIntVal: { 675 const ConstantInt *CI = static_cast<const ConstantInt*>(C); 676 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 677 emitWordLE(Val); 678 break; 679 } 680 case Value::ConstantFPVal: { 681 const ConstantFP *CFP = static_cast<const ConstantFP*>(C); 682 if (CFP->getType()->isFloatTy()) 683 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 684 else if (CFP->getType()->isDoubleTy()) 685 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 686 else { 687 llvm_unreachable("Unable to handle this constantpool entry!"); 688 } 689 break; 690 } 691 case Value::ConstantArrayVal: { 692 const ConstantArray *CA = static_cast<const ConstantArray*>(C); 693 for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) 694 emitConstantToMemory(CPI, CA->getOperand(i)); 695 break; 696 } 697 } 698 699 return; 700 } 701 702 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 703 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 704 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 705 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 706 707 // Remember the CONSTPOOL_ENTRY address for later relocation. 708 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 709 710 // Emit constpool island entry. In most cases, the actual values will be 711 // resolved and relocated after code emission. 712 if (MCPE.isMachineConstantPoolEntry()) { 713 ARMConstantPoolValue *ACPV = 714 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 715 716 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 717 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 718 719 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 720 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 721 if (GV) { 722 Reloc::Model RelocM = TM.getRelocationModel(); 723 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 724 isa<Function>(GV), 725 Subtarget->GVIsIndirectSymbol(GV, RelocM), 726 (intptr_t)ACPV); 727 } else { 728 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 729 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute); 730 } 731 emitWordLE(0); 732 } else { 733 emitConstantToMemory(CPI, MCPE.Val.ConstVal); 734 } 735 } 736 737 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 738 const MachineOperand &MO0 = MI.getOperand(0); 739 const MachineOperand &MO1 = MI.getOperand(1); 740 741 // Emit the 'movw' instruction. 742 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 743 744 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 745 746 // Set the conditional execution predicate. 747 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 748 749 // Encode Rd. 750 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 751 752 // Encode imm16 as imm4:imm12 753 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 754 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 755 emitWordLE(Binary); 756 757 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 758 // Emit the 'movt' instruction. 759 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 760 761 // Set the conditional execution predicate. 762 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 763 764 // Encode Rd. 765 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 766 767 // Encode imm16 as imm4:imm1, same as movw above. 768 Binary |= Hi16 & 0xFFF; 769 Binary |= ((Hi16 >> 12) & 0xF) << 16; 770 emitWordLE(Binary); 771 } 772 773 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 774 const MachineOperand &MO0 = MI.getOperand(0); 775 const MachineOperand &MO1 = MI.getOperand(1); 776 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 777 "Not a valid so_imm value!"); 778 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 779 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 780 781 // Emit the 'mov' instruction. 782 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 783 784 // Set the conditional execution predicate. 785 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 786 787 // Encode Rd. 788 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 789 790 // Encode so_imm. 791 // Set bit I(25) to identify this is the immediate form of <shifter_op> 792 Binary |= 1 << ARMII::I_BitShift; 793 Binary |= getMachineSoImmOpValue(V1); 794 emitWordLE(Binary); 795 796 // Now the 'orr' instruction. 797 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 798 799 // Set the conditional execution predicate. 800 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 801 802 // Encode Rd. 803 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 804 805 // Encode Rn. 806 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 807 808 // Encode so_imm. 809 // Set bit I(25) to identify this is the immediate form of <shifter_op> 810 Binary |= 1 << ARMII::I_BitShift; 811 Binary |= getMachineSoImmOpValue(V2); 812 emitWordLE(Binary); 813 } 814 815 void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) { 816 // It's basically add r, pc, (LCPI - $+8) 817 const MCInstrDesc &MCID = MI.getDesc(); 818 819 unsigned Binary = 0; 820 821 // Set the conditional execution predicate 822 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 823 824 // Encode S bit if MI modifies CPSR. 825 Binary |= getAddrModeSBit(MI, MCID); 826 827 // Encode Rd. 828 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 829 830 // Encode Rn which is PC. 831 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift; 832 833 // Encode the displacement which is a so_imm. 834 // Set bit I(25) to identify this is the immediate form of <shifter_op> 835 Binary |= 1 << ARMII::I_BitShift; 836 emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry); 837 838 emitWordLE(Binary); 839 } 840 841 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 842 // It's basically add r, pc, (LJTI - $+8) 843 844 const MCInstrDesc &MCID = MI.getDesc(); 845 846 // Emit the 'add' instruction. 847 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 848 849 // Set the conditional execution predicate 850 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 851 852 // Encode S bit if MI modifies CPSR. 853 Binary |= getAddrModeSBit(MI, MCID); 854 855 // Encode Rd. 856 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 857 858 // Encode Rn which is PC. 859 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift; 860 861 // Encode the displacement. 862 Binary |= 1 << ARMII::I_BitShift; 863 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 864 865 emitWordLE(Binary); 866 } 867 868 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 869 unsigned Opcode = MI.getDesc().Opcode; 870 871 // Part of binary is determined by TableGn. 872 unsigned Binary = getBinaryCodeForInstr(MI); 873 874 // Set the conditional execution predicate 875 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 876 877 // Encode S bit if MI modifies CPSR. 878 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 879 Binary |= 1 << ARMII::S_BitShift; 880 881 // Encode register def if there is one. 882 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 883 884 // Encode the shift operation. 885 switch (Opcode) { 886 default: break; 887 case ARM::RRX: 888 // rrx 889 Binary |= 0x6 << 4; 890 break; 891 case ARM::MOVsrl_flag: 892 // lsr #1 893 Binary |= (0x2 << 4) | (1 << 7); 894 break; 895 case ARM::MOVsra_flag: 896 // asr #1 897 Binary |= (0x4 << 4) | (1 << 7); 898 break; 899 } 900 901 // Encode register Rm. 902 Binary |= getMachineOpValue(MI, 1); 903 904 emitWordLE(Binary); 905 } 906 907 void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 908 DEBUG(errs() << " ** LPC" << LabelID << " @ " 909 << (void*)MCE.getCurrentPCValue() << '\n'); 910 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 911 } 912 913 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 914 unsigned Opcode = MI.getDesc().Opcode; 915 switch (Opcode) { 916 default: 917 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 918 case ARM::B: 919 emitBranchInstruction(MI); 920 break; 921 case ARM::BR_JTr: 922 case ARM::BR_JTm: 923 case ARM::BR_JTadd: 924 emitMiscBranchInstruction(MI); 925 break; 926 case ARM::BX_CALL: 927 case ARM::BMOVPCRX_CALL: { 928 // First emit mov lr, pc 929 unsigned Binary = 0x01a0e00f; 930 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 931 emitWordLE(Binary); 932 933 // and then emit the branch. 934 emitMiscBranchInstruction(MI); 935 break; 936 } 937 case TargetOpcode::INLINEASM: { 938 // We allow inline assembler nodes with empty bodies - they can 939 // implicitly define registers, which is ok for JIT. 940 if (MI.getOperand(0).getSymbolName()[0]) { 941 report_fatal_error("JIT does not support inline asm!"); 942 } 943 break; 944 } 945 case TargetOpcode::PROLOG_LABEL: 946 case TargetOpcode::EH_LABEL: 947 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 948 break; 949 case TargetOpcode::IMPLICIT_DEF: 950 case TargetOpcode::KILL: 951 // Do nothing. 952 break; 953 case ARM::CONSTPOOL_ENTRY: 954 emitConstPoolInstruction(MI); 955 break; 956 case ARM::LDMIA_RET: 957 emitLoadStoreMultipleInstruction(MI); 958 break; 959 case ARM::PICADD: { 960 // Remember of the address of the PC label for relocation later. 961 addPCLabel(MI.getOperand(2).getImm()); 962 // PICADD is just an add instruction that implicitly read pc. 963 emitDataProcessingInstruction(MI, 0, ARM::PC); 964 break; 965 } 966 case ARM::PICLDR: 967 case ARM::PICLDRB: 968 case ARM::PICSTR: 969 case ARM::PICSTRB: { 970 // Remember of the address of the PC label for relocation later. 971 addPCLabel(MI.getOperand(2).getImm()); 972 // These are just load / store instructions that implicitly read pc. 973 emitLoadStoreInstruction(MI, 0, ARM::PC); 974 break; 975 } 976 case ARM::PICLDRH: 977 case ARM::PICLDRSH: 978 case ARM::PICLDRSB: 979 case ARM::PICSTRH: { 980 // Remember of the address of the PC label for relocation later. 981 addPCLabel(MI.getOperand(2).getImm()); 982 // These are just load / store instructions that implicitly read pc. 983 emitMiscLoadStoreInstruction(MI, ARM::PC); 984 break; 985 } 986 987 case ARM::MOVi32imm: 988 // Two instructions to materialize a constant. 989 if (Subtarget->hasV6T2Ops()) 990 emitMOVi32immInstruction(MI); 991 else 992 emitMOVi2piecesInstruction(MI); 993 break; 994 case ARM::LEApcrel: 995 // Materialize constantpool index address. 996 emitLEApcrelInstruction(MI); 997 break; 998 case ARM::LEApcrelJT: 999 // Materialize jumptable address. 1000 emitLEApcrelJTInstruction(MI); 1001 break; 1002 case ARM::RRX: 1003 case ARM::MOVsrl_flag: 1004 case ARM::MOVsra_flag: 1005 emitPseudoMoveInstruction(MI); 1006 break; 1007 } 1008 } 1009 1010 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 1011 const MCInstrDesc &MCID, 1012 const MachineOperand &MO, 1013 unsigned OpIdx) { 1014 unsigned Binary = getMachineOpValue(MI, MO); 1015 1016 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 1017 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 1018 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1019 1020 // Encode the shift opcode. 1021 unsigned SBits = 0; 1022 unsigned Rs = MO1.getReg(); 1023 if (Rs) { 1024 // Set shift operand (bit[7:4]). 1025 // LSL - 0001 1026 // LSR - 0011 1027 // ASR - 0101 1028 // ROR - 0111 1029 // RRX - 0110 and bit[11:8] clear. 1030 switch (SOpc) { 1031 default: llvm_unreachable("Unknown shift opc!"); 1032 case ARM_AM::lsl: SBits = 0x1; break; 1033 case ARM_AM::lsr: SBits = 0x3; break; 1034 case ARM_AM::asr: SBits = 0x5; break; 1035 case ARM_AM::ror: SBits = 0x7; break; 1036 case ARM_AM::rrx: SBits = 0x6; break; 1037 } 1038 } else { 1039 // Set shift operand (bit[6:4]). 1040 // LSL - 000 1041 // LSR - 010 1042 // ASR - 100 1043 // ROR - 110 1044 switch (SOpc) { 1045 default: llvm_unreachable("Unknown shift opc!"); 1046 case ARM_AM::lsl: SBits = 0x0; break; 1047 case ARM_AM::lsr: SBits = 0x2; break; 1048 case ARM_AM::asr: SBits = 0x4; break; 1049 case ARM_AM::ror: SBits = 0x6; break; 1050 } 1051 } 1052 Binary |= SBits << 4; 1053 if (SOpc == ARM_AM::rrx) 1054 return Binary; 1055 1056 // Encode the shift operation Rs or shift_imm (except rrx). 1057 if (Rs) { 1058 // Encode Rs bit[11:8]. 1059 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1060 return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift); 1061 } 1062 1063 // Encode shift_imm bit[11:7]. 1064 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 1065 } 1066 1067 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 1068 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 1069 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 1070 1071 // Encode rotate_imm. 1072 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 1073 << ARMII::SoRotImmShift; 1074 1075 // Encode immed_8. 1076 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 1077 return Binary; 1078 } 1079 1080 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 1081 const MCInstrDesc &MCID) const { 1082 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ 1083 const MachineOperand &MO = MI.getOperand(i-1); 1084 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 1085 return 1 << ARMII::S_BitShift; 1086 } 1087 return 0; 1088 } 1089 1090 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 1091 unsigned ImplicitRd, 1092 unsigned ImplicitRn) { 1093 const MCInstrDesc &MCID = MI.getDesc(); 1094 1095 // Part of binary is determined by TableGn. 1096 unsigned Binary = getBinaryCodeForInstr(MI); 1097 1098 if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) { 1099 emitWordLE(Binary); 1100 return; 1101 } 1102 1103 // Set the conditional execution predicate 1104 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1105 1106 // Encode S bit if MI modifies CPSR. 1107 Binary |= getAddrModeSBit(MI, MCID); 1108 1109 // Encode register def if there is one. 1110 unsigned NumDefs = MCID.getNumDefs(); 1111 unsigned OpIdx = 0; 1112 if (NumDefs) 1113 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1114 else if (ImplicitRd) 1115 // Special handling for implicit use (e.g. PC). 1116 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift); 1117 1118 if (MCID.Opcode == ARM::MOVi16) { 1119 // Get immediate from MI. 1120 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1121 ARM::reloc_arm_movw); 1122 // Encode imm which is the same as in emitMOVi32immInstruction(). 1123 Binary |= Lo16 & 0xFFF; 1124 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1125 emitWordLE(Binary); 1126 return; 1127 } else if(MCID.Opcode == ARM::MOVTi16) { 1128 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1129 ARM::reloc_arm_movt) >> 16); 1130 Binary |= Hi16 & 0xFFF; 1131 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1132 emitWordLE(Binary); 1133 return; 1134 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { 1135 uint32_t v = ~MI.getOperand(2).getImm(); 1136 int32_t lsb = CountTrailingZeros_32(v); 1137 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 1138 // Instr{20-16} = msb, Instr{11-7} = lsb 1139 Binary |= (msb & 0x1F) << 16; 1140 Binary |= (lsb & 0x1F) << 7; 1141 emitWordLE(Binary); 1142 return; 1143 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { 1144 // Encode Rn in Instr{0-3} 1145 Binary |= getMachineOpValue(MI, OpIdx++); 1146 1147 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1148 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1149 1150 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1151 Binary |= (widthm1 & 0x1F) << 16; 1152 Binary |= (lsb & 0x1F) << 7; 1153 emitWordLE(Binary); 1154 return; 1155 } 1156 1157 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1158 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1159 ++OpIdx; 1160 1161 // Encode first non-shifter register operand if there is one. 1162 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; 1163 if (!isUnary) { 1164 if (ImplicitRn) 1165 // Special handling for implicit use (e.g. PC). 1166 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1167 else { 1168 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1169 ++OpIdx; 1170 } 1171 } 1172 1173 // Encode shifter operand. 1174 const MachineOperand &MO = MI.getOperand(OpIdx); 1175 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1176 // Encode SoReg. 1177 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); 1178 return; 1179 } 1180 1181 if (MO.isReg()) { 1182 // Encode register Rm. 1183 emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg())); 1184 return; 1185 } 1186 1187 // Encode so_imm. 1188 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1189 1190 emitWordLE(Binary); 1191 } 1192 1193 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1194 unsigned ImplicitRd, 1195 unsigned ImplicitRn) { 1196 const MCInstrDesc &MCID = MI.getDesc(); 1197 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1198 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1199 1200 // Part of binary is determined by TableGn. 1201 unsigned Binary = getBinaryCodeForInstr(MI); 1202 1203 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1204 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1205 MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 || 1206 MI.getOpcode() == ARM::STRBi12) { 1207 emitWordLE(Binary); 1208 return; 1209 } 1210 1211 if (MI.getOpcode() == ARM::BR_JTm) 1212 Binary = 0x710F000; 1213 else if (MI.getOpcode() == ARM::BR_JTr) 1214 Binary = 0x1A0F000; 1215 1216 // Set the conditional execution predicate 1217 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1218 1219 unsigned OpIdx = 0; 1220 1221 // Operand 0 of a pre- and post-indexed store is the address base 1222 // writeback. Skip it. 1223 bool Skipped = false; 1224 if (IsPrePost && Form == ARMII::StFrm) { 1225 ++OpIdx; 1226 Skipped = true; 1227 } 1228 1229 // Set first operand 1230 if (ImplicitRd) 1231 // Special handling for implicit use (e.g. PC). 1232 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift); 1233 else 1234 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1235 1236 // Set second operand 1237 if (ImplicitRn) 1238 // Special handling for implicit use (e.g. PC). 1239 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1240 else 1241 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1242 1243 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1244 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1245 ++OpIdx; 1246 1247 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1248 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1249 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1250 1251 // Set bit U(23) according to sign of immed value (positive or negative). 1252 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1253 ARMII::U_BitShift); 1254 if (!MO2.getReg()) { // is immediate 1255 if (ARM_AM::getAM2Offset(AM2Opc)) 1256 // Set the value of offset_12 field 1257 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1258 emitWordLE(Binary); 1259 return; 1260 } 1261 1262 // Set bit I(25), because this is not in immediate encoding. 1263 Binary |= 1 << ARMII::I_BitShift; 1264 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1265 // Set bit[3:0] to the corresponding Rm register 1266 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); 1267 1268 // If this instr is in scaled register offset/index instruction, set 1269 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1270 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1271 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1272 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1273 } 1274 1275 emitWordLE(Binary); 1276 } 1277 1278 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1279 unsigned ImplicitRn) { 1280 const MCInstrDesc &MCID = MI.getDesc(); 1281 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1282 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1283 1284 // Part of binary is determined by TableGn. 1285 unsigned Binary = getBinaryCodeForInstr(MI); 1286 1287 // Set the conditional execution predicate 1288 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1289 1290 unsigned OpIdx = 0; 1291 1292 // Operand 0 of a pre- and post-indexed store is the address base 1293 // writeback. Skip it. 1294 bool Skipped = false; 1295 if (IsPrePost && Form == ARMII::StMiscFrm) { 1296 ++OpIdx; 1297 Skipped = true; 1298 } 1299 1300 // Set first operand 1301 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1302 1303 // Skip LDRD and STRD's second operand. 1304 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) 1305 ++OpIdx; 1306 1307 // Set second operand 1308 if (ImplicitRn) 1309 // Special handling for implicit use (e.g. PC). 1310 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1311 else 1312 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1313 1314 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1315 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1316 ++OpIdx; 1317 1318 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1319 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1320 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1321 1322 // Set bit U(23) according to sign of immed value (positive or negative) 1323 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1324 ARMII::U_BitShift); 1325 1326 // If this instr is in register offset/index encoding, set bit[3:0] 1327 // to the corresponding Rm register. 1328 if (MO2.getReg()) { 1329 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); 1330 emitWordLE(Binary); 1331 return; 1332 } 1333 1334 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1335 Binary |= 1 << ARMII::AM3_I_BitShift; 1336 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1337 // Set operands 1338 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1339 Binary |= (ImmOffs & 0xF); // immedL 1340 } 1341 1342 emitWordLE(Binary); 1343 } 1344 1345 static unsigned getAddrModeUPBits(unsigned Mode) { 1346 unsigned Binary = 0; 1347 1348 // Set addressing mode by modifying bits U(23) and P(24) 1349 // IA - Increment after - bit U = 1 and bit P = 0 1350 // IB - Increment before - bit U = 1 and bit P = 1 1351 // DA - Decrement after - bit U = 0 and bit P = 0 1352 // DB - Decrement before - bit U = 0 and bit P = 1 1353 switch (Mode) { 1354 default: llvm_unreachable("Unknown addressing sub-mode!"); 1355 case ARM_AM::da: break; 1356 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1357 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1358 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1359 } 1360 1361 return Binary; 1362 } 1363 1364 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1365 const MCInstrDesc &MCID = MI.getDesc(); 1366 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1367 1368 // Part of binary is determined by TableGn. 1369 unsigned Binary = getBinaryCodeForInstr(MI); 1370 1371 if (MCID.getOpcode() == ARM::LDMIA_RET) { 1372 IsUpdating = true; 1373 Binary |= 0x8B00000; 1374 } 1375 1376 // Set the conditional execution predicate 1377 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1378 1379 // Skip operand 0 of an instruction with base register update. 1380 unsigned OpIdx = 0; 1381 if (IsUpdating) 1382 ++OpIdx; 1383 1384 // Set base address operand 1385 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1386 1387 // Set addressing mode by modifying bits U(23) and P(24) 1388 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1389 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1390 1391 // Set bit W(21) 1392 if (IsUpdating) 1393 Binary |= 0x1 << ARMII::W_BitShift; 1394 1395 // Set registers 1396 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1397 const MachineOperand &MO = MI.getOperand(i); 1398 if (!MO.isReg() || MO.isImplicit()) 1399 break; 1400 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); 1401 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1402 RegNum < 16); 1403 Binary |= 0x1 << RegNum; 1404 } 1405 1406 emitWordLE(Binary); 1407 } 1408 1409 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1410 const MCInstrDesc &MCID = MI.getDesc(); 1411 1412 // Part of binary is determined by TableGn. 1413 unsigned Binary = getBinaryCodeForInstr(MI); 1414 1415 // Set the conditional execution predicate 1416 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1417 1418 // Encode S bit if MI modifies CPSR. 1419 Binary |= getAddrModeSBit(MI, MCID); 1420 1421 // 32x32->64bit operations have two destination registers. The number 1422 // of register definitions will tell us if that's what we're dealing with. 1423 unsigned OpIdx = 0; 1424 if (MCID.getNumDefs() == 2) 1425 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1426 1427 // Encode Rd 1428 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1429 1430 // Encode Rm 1431 Binary |= getMachineOpValue(MI, OpIdx++); 1432 1433 // Encode Rs 1434 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1435 1436 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1437 // it as Rn (for multiply, that's in the same offset as RdLo. 1438 if (MCID.getNumOperands() > OpIdx && 1439 !MCID.OpInfo[OpIdx].isPredicate() && 1440 !MCID.OpInfo[OpIdx].isOptionalDef()) 1441 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1442 1443 emitWordLE(Binary); 1444 } 1445 1446 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1447 const MCInstrDesc &MCID = MI.getDesc(); 1448 1449 // Part of binary is determined by TableGn. 1450 unsigned Binary = getBinaryCodeForInstr(MI); 1451 1452 // Set the conditional execution predicate 1453 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1454 1455 unsigned OpIdx = 0; 1456 1457 // Encode Rd 1458 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1459 1460 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1461 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1462 if (MO2.isReg()) { 1463 // Two register operand form. 1464 // Encode Rn. 1465 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1466 1467 // Encode Rm. 1468 Binary |= getMachineOpValue(MI, MO2); 1469 ++OpIdx; 1470 } else { 1471 Binary |= getMachineOpValue(MI, MO1); 1472 } 1473 1474 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1475 if (MI.getOperand(OpIdx).isImm() && 1476 !MCID.OpInfo[OpIdx].isPredicate() && 1477 !MCID.OpInfo[OpIdx].isOptionalDef()) 1478 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1479 1480 emitWordLE(Binary); 1481 } 1482 1483 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1484 const MCInstrDesc &MCID = MI.getDesc(); 1485 1486 // Part of binary is determined by TableGn. 1487 unsigned Binary = getBinaryCodeForInstr(MI); 1488 1489 // Set the conditional execution predicate 1490 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1491 1492 // PKH instructions are finished at this point 1493 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { 1494 emitWordLE(Binary); 1495 return; 1496 } 1497 1498 unsigned OpIdx = 0; 1499 1500 // Encode Rd 1501 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1502 1503 const MachineOperand &MO = MI.getOperand(OpIdx++); 1504 if (OpIdx == MCID.getNumOperands() || 1505 MCID.OpInfo[OpIdx].isPredicate() || 1506 MCID.OpInfo[OpIdx].isOptionalDef()) { 1507 // Encode Rm and it's done. 1508 Binary |= getMachineOpValue(MI, MO); 1509 emitWordLE(Binary); 1510 return; 1511 } 1512 1513 // Encode Rn. 1514 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1515 1516 // Encode Rm. 1517 Binary |= getMachineOpValue(MI, OpIdx++); 1518 1519 // Encode shift_imm. 1520 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1521 if (MCID.Opcode == ARM::PKHTB) { 1522 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1523 if (ShiftAmt == 32) 1524 ShiftAmt = 0; 1525 } 1526 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1527 Binary |= ShiftAmt << ARMII::ShiftShift; 1528 1529 emitWordLE(Binary); 1530 } 1531 1532 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1533 const MCInstrDesc &MCID = MI.getDesc(); 1534 1535 // Part of binary is determined by TableGen. 1536 unsigned Binary = getBinaryCodeForInstr(MI); 1537 1538 // Set the conditional execution predicate 1539 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1540 1541 // Encode Rd 1542 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1543 1544 // Encode saturate bit position. 1545 unsigned Pos = MI.getOperand(1).getImm(); 1546 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) 1547 Pos -= 1; 1548 assert((Pos < 16 || (Pos < 32 && 1549 MCID.Opcode != ARM::SSAT16 && 1550 MCID.Opcode != ARM::USAT16)) && 1551 "saturate bit position out of range"); 1552 Binary |= Pos << 16; 1553 1554 // Encode Rm 1555 Binary |= getMachineOpValue(MI, 2); 1556 1557 // Encode shift_imm. 1558 if (MCID.getNumOperands() == 4) { 1559 unsigned ShiftOp = MI.getOperand(3).getImm(); 1560 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1561 if (Opc == ARM_AM::asr) 1562 Binary |= (1 << 6); 1563 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1564 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1565 ShiftAmt = 0; 1566 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1567 Binary |= ShiftAmt << ARMII::ShiftShift; 1568 } 1569 1570 emitWordLE(Binary); 1571 } 1572 1573 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1574 const MCInstrDesc &MCID = MI.getDesc(); 1575 1576 if (MCID.Opcode == ARM::TPsoft) { 1577 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1578 } 1579 1580 // Part of binary is determined by TableGn. 1581 unsigned Binary = getBinaryCodeForInstr(MI); 1582 1583 if (MCID.Opcode == ARM::B) { 1584 Binary = 0xEA000000; 1585 } 1586 1587 // Set the conditional execution predicate 1588 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1589 1590 // Set signed_immed_24 field 1591 Binary |= getMachineOpValue(MI, 0); 1592 1593 emitWordLE(Binary); 1594 } 1595 1596 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1597 // Remember the base address of the inline jump table. 1598 uintptr_t JTBase = MCE.getCurrentPCValue(); 1599 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1600 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1601 << '\n'); 1602 1603 // Now emit the jump table entries. 1604 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1605 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1606 if (IsPIC) 1607 // DestBB address - JT base. 1608 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1609 else 1610 // Absolute DestBB address. 1611 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1612 emitWordLE(0); 1613 } 1614 } 1615 1616 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1617 const MCInstrDesc &MCID = MI.getDesc(); 1618 1619 // Handle jump tables. 1620 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { 1621 // First emit a ldr pc, [] instruction. 1622 emitDataProcessingInstruction(MI, ARM::PC); 1623 1624 // Then emit the inline jump table. 1625 unsigned JTIndex = 1626 (MCID.Opcode == ARM::BR_JTr) 1627 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1628 emitInlineJumpTable(JTIndex); 1629 return; 1630 } else if (MCID.Opcode == ARM::BR_JTm) { 1631 // First emit a ldr pc, [] instruction. 1632 emitLoadStoreInstruction(MI, ARM::PC); 1633 1634 // Then emit the inline jump table. 1635 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1636 return; 1637 } 1638 1639 // Part of binary is determined by TableGn. 1640 unsigned Binary = getBinaryCodeForInstr(MI); 1641 1642 // Set the conditional execution predicate 1643 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1644 1645 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) 1646 // The return register is LR. 1647 Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR); 1648 else 1649 // otherwise, set the return register 1650 Binary |= getMachineOpValue(MI, 0); 1651 1652 emitWordLE(Binary); 1653 } 1654 1655 unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI, 1656 unsigned OpIdx) const { 1657 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1658 unsigned Binary = 0; 1659 bool isSPVFP = ARM::SPRRegClass.contains(RegD); 1660 RegD = II->getRegisterInfo().getEncodingValue(RegD); 1661 if (!isSPVFP) { 1662 Binary |= (RegD & 0x0F) << ARMII::RegRdShift; 1663 Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift; 1664 } else { 1665 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1666 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1667 } 1668 return Binary; 1669 } 1670 1671 unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI, 1672 unsigned OpIdx) const { 1673 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1674 unsigned Binary = 0; 1675 bool isSPVFP = ARM::SPRRegClass.contains(RegN); 1676 RegN = II->getRegisterInfo().getEncodingValue(RegN); 1677 if (!isSPVFP) { 1678 Binary |= (RegN & 0x0F) << ARMII::RegRnShift; 1679 Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift; 1680 } else { 1681 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1682 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1683 } 1684 return Binary; 1685 } 1686 1687 unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI, 1688 unsigned OpIdx) const { 1689 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1690 unsigned Binary = 0; 1691 bool isSPVFP = ARM::SPRRegClass.contains(RegM); 1692 RegM = II->getRegisterInfo().getEncodingValue(RegM); 1693 if (!isSPVFP) { 1694 Binary |= (RegM & 0x0F); 1695 Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift; 1696 } else { 1697 Binary |= ((RegM & 0x1E) >> 1); 1698 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1699 } 1700 return Binary; 1701 } 1702 1703 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1704 const MCInstrDesc &MCID = MI.getDesc(); 1705 1706 // Part of binary is determined by TableGn. 1707 unsigned Binary = getBinaryCodeForInstr(MI); 1708 1709 // Set the conditional execution predicate 1710 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1711 1712 unsigned OpIdx = 0; 1713 1714 // Encode Dd / Sd. 1715 Binary |= encodeVFPRd(MI, OpIdx++); 1716 1717 // If this is a two-address operand, skip it, e.g. FMACD. 1718 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1719 ++OpIdx; 1720 1721 // Encode Dn / Sn. 1722 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1723 Binary |= encodeVFPRn(MI, OpIdx++); 1724 1725 if (OpIdx == MCID.getNumOperands() || 1726 MCID.OpInfo[OpIdx].isPredicate() || 1727 MCID.OpInfo[OpIdx].isOptionalDef()) { 1728 // FCMPEZD etc. has only one operand. 1729 emitWordLE(Binary); 1730 return; 1731 } 1732 1733 // Encode Dm / Sm. 1734 Binary |= encodeVFPRm(MI, OpIdx); 1735 1736 emitWordLE(Binary); 1737 } 1738 1739 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1740 const MCInstrDesc &MCID = MI.getDesc(); 1741 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1742 1743 // Part of binary is determined by TableGn. 1744 unsigned Binary = getBinaryCodeForInstr(MI); 1745 1746 // Set the conditional execution predicate 1747 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1748 1749 switch (Form) { 1750 default: break; 1751 case ARMII::VFPConv1Frm: 1752 case ARMII::VFPConv2Frm: 1753 case ARMII::VFPConv3Frm: 1754 // Encode Dd / Sd. 1755 Binary |= encodeVFPRd(MI, 0); 1756 break; 1757 case ARMII::VFPConv4Frm: 1758 // Encode Dn / Sn. 1759 Binary |= encodeVFPRn(MI, 0); 1760 break; 1761 case ARMII::VFPConv5Frm: 1762 // Encode Dm / Sm. 1763 Binary |= encodeVFPRm(MI, 0); 1764 break; 1765 } 1766 1767 switch (Form) { 1768 default: break; 1769 case ARMII::VFPConv1Frm: 1770 // Encode Dm / Sm. 1771 Binary |= encodeVFPRm(MI, 1); 1772 break; 1773 case ARMII::VFPConv2Frm: 1774 case ARMII::VFPConv3Frm: 1775 // Encode Dn / Sn. 1776 Binary |= encodeVFPRn(MI, 1); 1777 break; 1778 case ARMII::VFPConv4Frm: 1779 case ARMII::VFPConv5Frm: 1780 // Encode Dd / Sd. 1781 Binary |= encodeVFPRd(MI, 1); 1782 break; 1783 } 1784 1785 if (Form == ARMII::VFPConv5Frm) 1786 // Encode Dn / Sn. 1787 Binary |= encodeVFPRn(MI, 2); 1788 else if (Form == ARMII::VFPConv3Frm) 1789 // Encode Dm / Sm. 1790 Binary |= encodeVFPRm(MI, 2); 1791 1792 emitWordLE(Binary); 1793 } 1794 1795 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1796 // Part of binary is determined by TableGn. 1797 unsigned Binary = getBinaryCodeForInstr(MI); 1798 1799 // Set the conditional execution predicate 1800 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1801 1802 if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD || 1803 MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){ 1804 emitWordLE(Binary); 1805 return; 1806 } 1807 1808 unsigned OpIdx = 0; 1809 1810 // Encode Dd / Sd. 1811 Binary |= encodeVFPRd(MI, OpIdx++); 1812 1813 // Encode address base. 1814 const MachineOperand &Base = MI.getOperand(OpIdx++); 1815 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1816 1817 // If there is a non-zero immediate offset, encode it. 1818 if (Base.isReg()) { 1819 const MachineOperand &Offset = MI.getOperand(OpIdx); 1820 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1821 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1822 Binary |= 1 << ARMII::U_BitShift; 1823 Binary |= ImmOffs; 1824 emitWordLE(Binary); 1825 return; 1826 } 1827 } 1828 1829 // If immediate offset is omitted, default to +0. 1830 Binary |= 1 << ARMII::U_BitShift; 1831 1832 emitWordLE(Binary); 1833 } 1834 1835 void 1836 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1837 const MCInstrDesc &MCID = MI.getDesc(); 1838 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1839 1840 // Part of binary is determined by TableGn. 1841 unsigned Binary = getBinaryCodeForInstr(MI); 1842 1843 // Set the conditional execution predicate 1844 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1845 1846 // Skip operand 0 of an instruction with base register update. 1847 unsigned OpIdx = 0; 1848 if (IsUpdating) 1849 ++OpIdx; 1850 1851 // Set base address operand 1852 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1853 1854 // Set addressing mode by modifying bits U(23) and P(24) 1855 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1856 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1857 1858 // Set bit W(21) 1859 if (IsUpdating) 1860 Binary |= 0x1 << ARMII::W_BitShift; 1861 1862 // First register is encoded in Dd. 1863 Binary |= encodeVFPRd(MI, OpIdx+2); 1864 1865 // Count the number of registers. 1866 unsigned NumRegs = 1; 1867 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1868 const MachineOperand &MO = MI.getOperand(i); 1869 if (!MO.isReg() || MO.isImplicit()) 1870 break; 1871 ++NumRegs; 1872 } 1873 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1874 // Otherwise, it will be 0, in the case of 32-bit registers. 1875 if(Binary & 0x100) 1876 Binary |= NumRegs * 2; 1877 else 1878 Binary |= NumRegs; 1879 1880 emitWordLE(Binary); 1881 } 1882 1883 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { 1884 unsigned Opcode = MI.getDesc().Opcode; 1885 // Part of binary is determined by TableGn. 1886 unsigned Binary = getBinaryCodeForInstr(MI); 1887 1888 if (Opcode == ARM::FCONSTS) { 1889 unsigned Imm = getMachineOpValue(MI, 1); 1890 Binary &= ~(0x780000 >> 19); 1891 Binary |= (Imm & 0x780000) >> 19; 1892 Binary &= ~(0x3800000 >> 7); 1893 Binary |= (Imm & 0x3800000) >> 7; 1894 Binary = VFPThumb2PostEncoder(MI, Binary); 1895 } 1896 1897 // Set the conditional execution predicate 1898 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1899 1900 emitWordLE(Binary); 1901 } 1902 1903 unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI, 1904 unsigned OpIdx) const { 1905 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1906 unsigned Binary = 0; 1907 RegD = II->getRegisterInfo().getEncodingValue(RegD); 1908 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1909 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1910 return Binary; 1911 } 1912 1913 unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI, 1914 unsigned OpIdx) const { 1915 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1916 unsigned Binary = 0; 1917 RegN = II->getRegisterInfo().getEncodingValue(RegN); 1918 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1919 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1920 return Binary; 1921 } 1922 1923 unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI, 1924 unsigned OpIdx) const { 1925 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1926 unsigned Binary = 0; 1927 RegM = II->getRegisterInfo().getEncodingValue(RegM); 1928 Binary |= (RegM & 0xf); 1929 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1930 return Binary; 1931 } 1932 1933 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1934 /// data-processing instruction to the corresponding Thumb encoding. 1935 static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1936 assert((Binary & 0xfe000000) == 0xf2000000 && 1937 "not an ARM NEON data-processing instruction"); 1938 unsigned UBit = (Binary >> 24) & 1; 1939 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1940 } 1941 1942 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1943 unsigned Binary = getBinaryCodeForInstr(MI); 1944 1945 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1946 const MCInstrDesc &MCID = MI.getDesc(); 1947 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1948 RegTOpIdx = 0; 1949 RegNOpIdx = 1; 1950 LnOpIdx = 2; 1951 } else { // ARMII::NSetLnFrm 1952 RegTOpIdx = 2; 1953 RegNOpIdx = 0; 1954 LnOpIdx = 3; 1955 } 1956 1957 // Set the conditional execution predicate 1958 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1959 1960 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1961 RegT = II->getRegisterInfo().getEncodingValue(RegT); 1962 Binary |= (RegT << ARMII::RegRdShift); 1963 Binary |= encodeNEONRn(MI, RegNOpIdx); 1964 1965 unsigned LaneShift; 1966 if ((Binary & (1 << 22)) != 0) 1967 LaneShift = 0; // 8-bit elements 1968 else if ((Binary & (1 << 5)) != 0) 1969 LaneShift = 1; // 16-bit elements 1970 else 1971 LaneShift = 2; // 32-bit elements 1972 1973 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1974 unsigned Opc1 = Lane >> 2; 1975 unsigned Opc2 = Lane & 3; 1976 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1977 Binary |= (Opc1 << 21); 1978 Binary |= (Opc2 << 5); 1979 1980 emitWordLE(Binary); 1981 } 1982 1983 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1984 unsigned Binary = getBinaryCodeForInstr(MI); 1985 1986 // Set the conditional execution predicate 1987 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1988 1989 unsigned RegT = MI.getOperand(1).getReg(); 1990 RegT = II->getRegisterInfo().getEncodingValue(RegT); 1991 Binary |= (RegT << ARMII::RegRdShift); 1992 Binary |= encodeNEONRn(MI, 0); 1993 emitWordLE(Binary); 1994 } 1995 1996 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1997 unsigned Binary = getBinaryCodeForInstr(MI); 1998 // Destination register is encoded in Dd. 1999 Binary |= encodeNEONRd(MI, 0); 2000 // Immediate fields: Op, Cmode, I, Imm3, Imm4 2001 unsigned Imm = MI.getOperand(1).getImm(); 2002 unsigned Op = (Imm >> 12) & 1; 2003 unsigned Cmode = (Imm >> 8) & 0xf; 2004 unsigned I = (Imm >> 7) & 1; 2005 unsigned Imm3 = (Imm >> 4) & 0x7; 2006 unsigned Imm4 = Imm & 0xf; 2007 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 2008 if (IsThumb) 2009 Binary = convertNEONDataProcToThumb(Binary); 2010 emitWordLE(Binary); 2011 } 2012 2013 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 2014 const MCInstrDesc &MCID = MI.getDesc(); 2015 unsigned Binary = getBinaryCodeForInstr(MI); 2016 // Destination register is encoded in Dd; source register in Dm. 2017 unsigned OpIdx = 0; 2018 Binary |= encodeNEONRd(MI, OpIdx++); 2019 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2020 ++OpIdx; 2021 Binary |= encodeNEONRm(MI, OpIdx); 2022 if (IsThumb) 2023 Binary = convertNEONDataProcToThumb(Binary); 2024 // FIXME: This does not handle VDUPfdf or VDUPfqf. 2025 emitWordLE(Binary); 2026 } 2027 2028 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 2029 const MCInstrDesc &MCID = MI.getDesc(); 2030 unsigned Binary = getBinaryCodeForInstr(MI); 2031 // Destination register is encoded in Dd; source registers in Dn and Dm. 2032 unsigned OpIdx = 0; 2033 Binary |= encodeNEONRd(MI, OpIdx++); 2034 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2035 ++OpIdx; 2036 Binary |= encodeNEONRn(MI, OpIdx++); 2037 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2038 ++OpIdx; 2039 Binary |= encodeNEONRm(MI, OpIdx); 2040 if (IsThumb) 2041 Binary = convertNEONDataProcToThumb(Binary); 2042 // FIXME: This does not handle VMOVDneon or VMOVQ. 2043 emitWordLE(Binary); 2044 } 2045 2046 #include "ARMGenCodeEmitter.inc" 2047
