1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PPC implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCFrameLowering.h" 15 #include "PPCInstrInfo.h" 16 #include "PPCMachineFunctionInfo.h" 17 #include "llvm/Function.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineModuleInfo.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/RegisterScavenging.h" 24 #include "llvm/Target/TargetOptions.h" 25 26 using namespace llvm; 27 28 // FIXME This disables some code that aligns the stack to a boundary bigger than 29 // the default (16 bytes on Darwin) when there is a stack local of greater 30 // alignment. This does not currently work, because the delta between old and 31 // new stack pointers is added to offsets that reference incoming parameters 32 // after the prolog is generated, and the code that does that doesn't handle a 33 // variable delta. You don't want to do that anyway; a better approach is to 34 // reserve another register that retains to the incoming stack pointer, and 35 // reference parameters relative to that. 36 #define ALIGN_STACK 0 37 38 39 /// VRRegNo - Map from a numbered VR register to its enum value. 40 /// 41 static const uint16_t VRRegNo[] = { 42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 44 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 45 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 46 }; 47 48 /// RemoveVRSaveCode - We have found that this function does not need any code 49 /// to manipulate the VRSAVE register, even though it uses vector registers. 50 /// This can happen when the only registers used are known to be live in or out 51 /// of the function. Remove all of the VRSAVE related code from the function. 52 static void RemoveVRSaveCode(MachineInstr *MI) { 53 MachineBasicBlock *Entry = MI->getParent(); 54 MachineFunction *MF = Entry->getParent(); 55 56 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 57 MachineBasicBlock::iterator MBBI = MI; 58 ++MBBI; 59 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 60 MBBI->eraseFromParent(); 61 62 bool RemovedAllMTVRSAVEs = true; 63 // See if we can find and remove the MTVRSAVE instruction from all of the 64 // epilog blocks. 65 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 66 // If last instruction is a return instruction, add an epilogue 67 if (!I->empty() && I->back().isReturn()) { 68 bool FoundIt = false; 69 for (MBBI = I->end(); MBBI != I->begin(); ) { 70 --MBBI; 71 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 72 MBBI->eraseFromParent(); // remove it. 73 FoundIt = true; 74 break; 75 } 76 } 77 RemovedAllMTVRSAVEs &= FoundIt; 78 } 79 } 80 81 // If we found and removed all MTVRSAVE instructions, remove the read of 82 // VRSAVE as well. 83 if (RemovedAllMTVRSAVEs) { 84 MBBI = MI; 85 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 86 --MBBI; 87 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 88 MBBI->eraseFromParent(); 89 } 90 91 // Finally, nuke the UPDATE_VRSAVE. 92 MI->eraseFromParent(); 93 } 94 95 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 96 // instruction selector. Based on the vector registers that have been used, 97 // transform this into the appropriate ORI instruction. 98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 99 MachineFunction *MF = MI->getParent()->getParent(); 100 DebugLoc dl = MI->getDebugLoc(); 101 102 unsigned UsedRegMask = 0; 103 for (unsigned i = 0; i != 32; ++i) 104 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 105 UsedRegMask |= 1 << (31-i); 106 107 // Live in and live out values already must be in the mask, so don't bother 108 // marking them. 109 for (MachineRegisterInfo::livein_iterator 110 I = MF->getRegInfo().livein_begin(), 111 E = MF->getRegInfo().livein_end(); I != E; ++I) { 112 unsigned RegNo = getPPCRegisterNumbering(I->first); 113 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 114 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 115 } 116 for (MachineRegisterInfo::liveout_iterator 117 I = MF->getRegInfo().liveout_begin(), 118 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 119 unsigned RegNo = getPPCRegisterNumbering(*I); 120 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122 } 123 124 // If no registers are used, turn this into a copy. 125 if (UsedRegMask == 0) { 126 // Remove all VRSAVE code. 127 RemoveVRSaveCode(MI); 128 return; 129 } 130 131 unsigned SrcReg = MI->getOperand(1).getReg(); 132 unsigned DstReg = MI->getOperand(0).getReg(); 133 134 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 135 if (DstReg != SrcReg) 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 137 .addReg(SrcReg) 138 .addImm(UsedRegMask); 139 else 140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 141 .addReg(SrcReg, RegState::Kill) 142 .addImm(UsedRegMask); 143 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 144 if (DstReg != SrcReg) 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 146 .addReg(SrcReg) 147 .addImm(UsedRegMask >> 16); 148 else 149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 150 .addReg(SrcReg, RegState::Kill) 151 .addImm(UsedRegMask >> 16); 152 } else { 153 if (DstReg != SrcReg) 154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 155 .addReg(SrcReg) 156 .addImm(UsedRegMask >> 16); 157 else 158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 159 .addReg(SrcReg, RegState::Kill) 160 .addImm(UsedRegMask >> 16); 161 162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 163 .addReg(DstReg, RegState::Kill) 164 .addImm(UsedRegMask & 0xFFFF); 165 } 166 167 // Remove the old UPDATE_VRSAVE instruction. 168 MI->eraseFromParent(); 169 } 170 171 /// determineFrameLayout - Determine the size of the frame and maximum call 172 /// frame size. 173 void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 174 MachineFrameInfo *MFI = MF.getFrameInfo(); 175 176 // Get the number of bytes to allocate from the FrameInfo 177 unsigned FrameSize = MFI->getStackSize(); 178 179 // Get the alignments provided by the target, and the maximum alignment 180 // (if any) of the fixed frame objects. 181 unsigned MaxAlign = MFI->getMaxAlignment(); 182 unsigned TargetAlign = getStackAlignment(); 183 unsigned AlignMask = TargetAlign - 1; // 184 185 // If we are a leaf function, and use up to 224 bytes of stack space, 186 // don't have a frame pointer, calls, or dynamic alloca then we do not need 187 // to adjust the stack pointer (we fit in the Red Zone). 188 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 189 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 190 if (!DisableRedZone && 191 FrameSize <= 224 && // Fits in red zone. 192 !MFI->hasVarSizedObjects() && // No dynamic alloca. 193 !MFI->adjustsStack() && // No calls. 194 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 195 // No need for frame 196 MFI->setStackSize(0); 197 return; 198 } 199 200 // Get the maximum call frame size of all the calls. 201 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 202 203 // Maximum call frame needs to be at least big enough for linkage and 8 args. 204 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 205 Subtarget.isDarwinABI()); 206 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 207 208 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 209 // that allocations will be aligned. 210 if (MFI->hasVarSizedObjects()) 211 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 212 213 // Update maximum call frame size. 214 MFI->setMaxCallFrameSize(maxCallFrameSize); 215 216 // Include call frame size in total. 217 FrameSize += maxCallFrameSize; 218 219 // Make sure the frame is aligned. 220 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 221 222 // Update frame info. 223 MFI->setStackSize(FrameSize); 224 } 225 226 // hasFP - Return true if the specified function actually has a dedicated frame 227 // pointer register. 228 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 229 const MachineFrameInfo *MFI = MF.getFrameInfo(); 230 // FIXME: This is pretty much broken by design: hasFP() might be called really 231 // early, before the stack layout was calculated and thus hasFP() might return 232 // true or false here depending on the time of call. 233 return (MFI->getStackSize()) && needsFP(MF); 234 } 235 236 // needsFP - Return true if the specified function should have a dedicated frame 237 // pointer register. This is true if the function has variable sized allocas or 238 // if frame pointer elimination is disabled. 239 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 240 const MachineFrameInfo *MFI = MF.getFrameInfo(); 241 242 // Naked functions have no stack frame pushed, so we don't have a frame 243 // pointer. 244 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 245 return false; 246 247 return MF.getTarget().Options.DisableFramePointerElim(MF) || 248 MFI->hasVarSizedObjects() || 249 (MF.getTarget().Options.GuaranteedTailCallOpt && 250 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 251 } 252 253 254 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 255 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 256 MachineBasicBlock::iterator MBBI = MBB.begin(); 257 MachineFrameInfo *MFI = MF.getFrameInfo(); 258 const PPCInstrInfo &TII = 259 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 260 261 MachineModuleInfo &MMI = MF.getMMI(); 262 DebugLoc dl; 263 bool needsFrameMoves = MMI.hasDebugInfo() || 264 MF.getFunction()->needsUnwindTableEntry(); 265 266 // Prepare for frame info. 267 MCSymbol *FrameLabel = 0; 268 269 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 270 // process it. 271 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 272 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 273 HandleVRSaveUpdate(MBBI, TII); 274 break; 275 } 276 } 277 278 // Move MBBI back to the beginning of the function. 279 MBBI = MBB.begin(); 280 281 // Work out frame sizes. 282 // FIXME: determineFrameLayout() may change the frame size. This should be 283 // moved upper, to some hook. 284 determineFrameLayout(MF); 285 unsigned FrameSize = MFI->getStackSize(); 286 287 int NegFrameSize = -FrameSize; 288 289 // Get processor type. 290 bool isPPC64 = Subtarget.isPPC64(); 291 // Get operating system 292 bool isDarwinABI = Subtarget.isDarwinABI(); 293 // Check if the link register (LR) must be saved. 294 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 295 bool MustSaveLR = FI->mustSaveLR(); 296 // Do we have a frame pointer for this function? 297 bool HasFP = hasFP(MF); 298 299 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 300 301 int FPOffset = 0; 302 if (HasFP) { 303 if (Subtarget.isSVR4ABI()) { 304 MachineFrameInfo *FFI = MF.getFrameInfo(); 305 int FPIndex = FI->getFramePointerSaveIndex(); 306 assert(FPIndex && "No Frame Pointer Save Slot!"); 307 FPOffset = FFI->getObjectOffset(FPIndex); 308 } else { 309 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 310 } 311 } 312 313 if (isPPC64) { 314 if (MustSaveLR) 315 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 316 317 if (HasFP) 318 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 319 .addReg(PPC::X31) 320 .addImm(FPOffset/4) 321 .addReg(PPC::X1); 322 323 if (MustSaveLR) 324 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 325 .addReg(PPC::X0) 326 .addImm(LROffset / 4) 327 .addReg(PPC::X1); 328 } else { 329 if (MustSaveLR) 330 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 331 332 if (HasFP) 333 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 334 // offsets of R1 is not allowed. 335 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 336 .addReg(PPC::R31) 337 .addImm(FPOffset) 338 .addReg(PPC::R1); 339 340 if (MustSaveLR) 341 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 342 .addReg(PPC::R0) 343 .addImm(LROffset) 344 .addReg(PPC::R1); 345 } 346 347 // Skip if a leaf routine. 348 if (!FrameSize) return; 349 350 // Get stack alignments. 351 unsigned TargetAlign = getStackAlignment(); 352 unsigned MaxAlign = MFI->getMaxAlignment(); 353 354 // Adjust stack pointer: r1 += NegFrameSize. 355 // If there is a preferred stack alignment, align R1 now 356 if (!isPPC64) { 357 // PPC32. 358 if (ALIGN_STACK && MaxAlign > TargetAlign) { 359 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 360 "Invalid alignment!"); 361 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 362 363 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 364 .addReg(PPC::R1) 365 .addImm(0) 366 .addImm(32 - Log2_32(MaxAlign)) 367 .addImm(31); 368 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 369 .addReg(PPC::R0, RegState::Kill) 370 .addImm(NegFrameSize); 371 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 372 .addReg(PPC::R1, RegState::Kill) 373 .addReg(PPC::R1) 374 .addReg(PPC::R0); 375 } else if (isInt<16>(NegFrameSize)) { 376 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 377 .addReg(PPC::R1) 378 .addImm(NegFrameSize) 379 .addReg(PPC::R1); 380 } else { 381 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 382 .addImm(NegFrameSize >> 16); 383 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 384 .addReg(PPC::R0, RegState::Kill) 385 .addImm(NegFrameSize & 0xFFFF); 386 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 387 .addReg(PPC::R1, RegState::Kill) 388 .addReg(PPC::R1) 389 .addReg(PPC::R0); 390 } 391 } else { // PPC64. 392 if (ALIGN_STACK && MaxAlign > TargetAlign) { 393 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 394 "Invalid alignment!"); 395 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 396 397 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 398 .addReg(PPC::X1) 399 .addImm(0) 400 .addImm(64 - Log2_32(MaxAlign)); 401 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 402 .addReg(PPC::X0) 403 .addImm(NegFrameSize); 404 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 405 .addReg(PPC::X1, RegState::Kill) 406 .addReg(PPC::X1) 407 .addReg(PPC::X0); 408 } else if (isInt<16>(NegFrameSize)) { 409 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 410 .addReg(PPC::X1) 411 .addImm(NegFrameSize / 4) 412 .addReg(PPC::X1); 413 } else { 414 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 415 .addImm(NegFrameSize >> 16); 416 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 417 .addReg(PPC::X0, RegState::Kill) 418 .addImm(NegFrameSize & 0xFFFF); 419 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 420 .addReg(PPC::X1, RegState::Kill) 421 .addReg(PPC::X1) 422 .addReg(PPC::X0); 423 } 424 } 425 426 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 427 428 // Add the "machine moves" for the instructions we generated above, but in 429 // reverse order. 430 if (needsFrameMoves) { 431 // Mark effective beginning of when frame pointer becomes valid. 432 FrameLabel = MMI.getContext().CreateTempSymbol(); 433 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 434 435 // Show update of SP. 436 if (NegFrameSize) { 437 MachineLocation SPDst(MachineLocation::VirtualFP); 438 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 439 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 440 } else { 441 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 442 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 443 } 444 445 if (HasFP) { 446 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 447 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 448 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 449 } 450 451 if (MustSaveLR) { 452 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 453 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 454 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 455 } 456 } 457 458 MCSymbol *ReadyLabel = 0; 459 460 // If there is a frame pointer, copy R1 into R31 461 if (HasFP) { 462 if (!isPPC64) { 463 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 464 .addReg(PPC::R1) 465 .addReg(PPC::R1); 466 } else { 467 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 468 .addReg(PPC::X1) 469 .addReg(PPC::X1); 470 } 471 472 if (needsFrameMoves) { 473 ReadyLabel = MMI.getContext().CreateTempSymbol(); 474 475 // Mark effective beginning of when frame pointer is ready. 476 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 477 478 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 479 (isPPC64 ? PPC::X1 : PPC::R1)); 480 MachineLocation FPSrc(MachineLocation::VirtualFP); 481 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 482 } 483 } 484 485 if (needsFrameMoves) { 486 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 487 488 // Add callee saved registers to move list. 489 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 490 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 491 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 492 unsigned Reg = CSI[I].getReg(); 493 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 494 495 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 496 // subregisters of CR2. We just need to emit a move of CR2. 497 if (PPC::CRBITRCRegClass.contains(Reg)) 498 continue; 499 500 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 501 MachineLocation CSSrc(Reg); 502 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 503 } 504 } 505 } 506 507 void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 508 MachineBasicBlock &MBB) const { 509 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 510 assert(MBBI != MBB.end() && "Returning block has no terminator"); 511 const PPCInstrInfo &TII = 512 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 513 514 unsigned RetOpcode = MBBI->getOpcode(); 515 DebugLoc dl; 516 517 assert((RetOpcode == PPC::BLR || 518 RetOpcode == PPC::TCRETURNri || 519 RetOpcode == PPC::TCRETURNdi || 520 RetOpcode == PPC::TCRETURNai || 521 RetOpcode == PPC::TCRETURNri8 || 522 RetOpcode == PPC::TCRETURNdi8 || 523 RetOpcode == PPC::TCRETURNai8) && 524 "Can only insert epilog into returning blocks"); 525 526 // Get alignment info so we know how to restore r1 527 const MachineFrameInfo *MFI = MF.getFrameInfo(); 528 unsigned TargetAlign = getStackAlignment(); 529 unsigned MaxAlign = MFI->getMaxAlignment(); 530 531 // Get the number of bytes allocated from the FrameInfo. 532 int FrameSize = MFI->getStackSize(); 533 534 // Get processor type. 535 bool isPPC64 = Subtarget.isPPC64(); 536 // Get operating system 537 bool isDarwinABI = Subtarget.isDarwinABI(); 538 // Check if the link register (LR) has been saved. 539 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 540 bool MustSaveLR = FI->mustSaveLR(); 541 // Do we have a frame pointer for this function? 542 bool HasFP = hasFP(MF); 543 544 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 545 546 int FPOffset = 0; 547 if (HasFP) { 548 if (Subtarget.isSVR4ABI()) { 549 MachineFrameInfo *FFI = MF.getFrameInfo(); 550 int FPIndex = FI->getFramePointerSaveIndex(); 551 assert(FPIndex && "No Frame Pointer Save Slot!"); 552 FPOffset = FFI->getObjectOffset(FPIndex); 553 } else { 554 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 555 } 556 } 557 558 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 559 RetOpcode == PPC::TCRETURNdi || 560 RetOpcode == PPC::TCRETURNai || 561 RetOpcode == PPC::TCRETURNri8 || 562 RetOpcode == PPC::TCRETURNdi8 || 563 RetOpcode == PPC::TCRETURNai8; 564 565 if (UsesTCRet) { 566 int MaxTCRetDelta = FI->getTailCallSPDelta(); 567 MachineOperand &StackAdjust = MBBI->getOperand(1); 568 assert(StackAdjust.isImm() && "Expecting immediate value."); 569 // Adjust stack pointer. 570 int StackAdj = StackAdjust.getImm(); 571 int Delta = StackAdj - MaxTCRetDelta; 572 assert((Delta >= 0) && "Delta must be positive"); 573 if (MaxTCRetDelta>0) 574 FrameSize += (StackAdj +Delta); 575 else 576 FrameSize += StackAdj; 577 } 578 579 if (FrameSize) { 580 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 581 // on entry to the function. Add this offset back now. 582 if (!isPPC64) { 583 // If this function contained a fastcc call and GuaranteedTailCallOpt is 584 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 585 // call which invalidates the stack pointer value in SP(0). So we use the 586 // value of R31 in this case. 587 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 588 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 589 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 590 .addReg(PPC::R31).addImm(FrameSize); 591 } else if(FI->hasFastCall()) { 592 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 593 .addImm(FrameSize >> 16); 594 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 595 .addReg(PPC::R0, RegState::Kill) 596 .addImm(FrameSize & 0xFFFF); 597 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 598 .addReg(PPC::R1) 599 .addReg(PPC::R31) 600 .addReg(PPC::R0); 601 } else if (isInt<16>(FrameSize) && 602 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 603 !MFI->hasVarSizedObjects()) { 604 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 605 .addReg(PPC::R1).addImm(FrameSize); 606 } else { 607 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 608 .addImm(0).addReg(PPC::R1); 609 } 610 } else { 611 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 612 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 613 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 614 .addReg(PPC::X31).addImm(FrameSize); 615 } else if(FI->hasFastCall()) { 616 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 617 .addImm(FrameSize >> 16); 618 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 619 .addReg(PPC::X0, RegState::Kill) 620 .addImm(FrameSize & 0xFFFF); 621 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 622 .addReg(PPC::X1) 623 .addReg(PPC::X31) 624 .addReg(PPC::X0); 625 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 626 !MFI->hasVarSizedObjects()) { 627 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 628 .addReg(PPC::X1).addImm(FrameSize); 629 } else { 630 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 631 .addImm(0).addReg(PPC::X1); 632 } 633 } 634 } 635 636 if (isPPC64) { 637 if (MustSaveLR) 638 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 639 .addImm(LROffset/4).addReg(PPC::X1); 640 641 if (HasFP) 642 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 643 .addImm(FPOffset/4).addReg(PPC::X1); 644 645 if (MustSaveLR) 646 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 647 } else { 648 if (MustSaveLR) 649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 650 .addImm(LROffset).addReg(PPC::R1); 651 652 if (HasFP) 653 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 654 .addImm(FPOffset).addReg(PPC::R1); 655 656 if (MustSaveLR) 657 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 658 } 659 660 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 661 // call optimization 662 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 663 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 664 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 665 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 666 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 667 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 668 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 669 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 670 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 671 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 672 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 673 674 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 675 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 676 .addReg(StackReg).addImm(CallerAllocatedAmt); 677 } else { 678 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 679 .addImm(CallerAllocatedAmt >> 16); 680 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 681 .addReg(TmpReg, RegState::Kill) 682 .addImm(CallerAllocatedAmt & 0xFFFF); 683 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 684 .addReg(StackReg) 685 .addReg(FPReg) 686 .addReg(TmpReg); 687 } 688 } else if (RetOpcode == PPC::TCRETURNdi) { 689 MBBI = MBB.getLastNonDebugInstr(); 690 MachineOperand &JumpTarget = MBBI->getOperand(0); 691 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 692 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 693 } else if (RetOpcode == PPC::TCRETURNri) { 694 MBBI = MBB.getLastNonDebugInstr(); 695 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 696 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 697 } else if (RetOpcode == PPC::TCRETURNai) { 698 MBBI = MBB.getLastNonDebugInstr(); 699 MachineOperand &JumpTarget = MBBI->getOperand(0); 700 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 701 } else if (RetOpcode == PPC::TCRETURNdi8) { 702 MBBI = MBB.getLastNonDebugInstr(); 703 MachineOperand &JumpTarget = MBBI->getOperand(0); 704 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 705 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 706 } else if (RetOpcode == PPC::TCRETURNri8) { 707 MBBI = MBB.getLastNonDebugInstr(); 708 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 709 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 710 } else if (RetOpcode == PPC::TCRETURNai8) { 711 MBBI = MBB.getLastNonDebugInstr(); 712 MachineOperand &JumpTarget = MBBI->getOperand(0); 713 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 714 } 715 } 716 717 static bool spillsCR(const MachineFunction &MF) { 718 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 719 return FuncInfo->isCRSpilled(); 720 } 721 722 /// MustSaveLR - Return true if this function requires that we save the LR 723 /// register onto the stack in the prolog and restore it in the epilog of the 724 /// function. 725 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 726 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 727 728 // We need a save/restore of LR if there is any def of LR (which is 729 // defined by calls, including the PIC setup sequence), or if there is 730 // some use of the LR stack slot (e.g. for builtin_return_address). 731 // (LR comes in 32 and 64 bit versions.) 732 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 733 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 734 } 735 736 void 737 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 738 RegScavenger *RS) const { 739 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 740 741 // Save and clear the LR state. 742 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 743 unsigned LR = RegInfo->getRARegister(); 744 FI->setMustSaveLR(MustSaveLR(MF, LR)); 745 MF.getRegInfo().setPhysRegUnused(LR); 746 747 // Save R31 if necessary 748 int FPSI = FI->getFramePointerSaveIndex(); 749 bool isPPC64 = Subtarget.isPPC64(); 750 bool isDarwinABI = Subtarget.isDarwinABI(); 751 MachineFrameInfo *MFI = MF.getFrameInfo(); 752 753 // If the frame pointer save index hasn't been defined yet. 754 if (!FPSI && needsFP(MF)) { 755 // Find out what the fix offset of the frame pointer save area. 756 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 757 // Allocate the frame index for frame pointer save area. 758 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 759 // Save the result. 760 FI->setFramePointerSaveIndex(FPSI); 761 } 762 763 // Reserve stack space to move the linkage area to in case of a tail call. 764 int TCSPDelta = 0; 765 if (MF.getTarget().Options.GuaranteedTailCallOpt && 766 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 767 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 768 } 769 770 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 771 // a large stack, which will require scavenging a register to materialize a 772 // large offset. 773 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 774 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 775 // r0 for now. 776 777 if (RegInfo->requiresRegisterScavenging(MF)) 778 if (needsFP(MF) || spillsCR(MF)) { 779 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 780 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 781 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 782 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 783 RC->getAlignment(), 784 false)); 785 } 786 } 787 788 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 789 const { 790 // Early exit if not using the SVR4 ABI. 791 if (!Subtarget.isSVR4ABI()) 792 return; 793 794 // Get callee saved register information. 795 MachineFrameInfo *FFI = MF.getFrameInfo(); 796 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 797 798 // Early exit if no callee saved registers are modified! 799 if (CSI.empty() && !needsFP(MF)) { 800 return; 801 } 802 803 unsigned MinGPR = PPC::R31; 804 unsigned MinG8R = PPC::X31; 805 unsigned MinFPR = PPC::F31; 806 unsigned MinVR = PPC::V31; 807 808 bool HasGPSaveArea = false; 809 bool HasG8SaveArea = false; 810 bool HasFPSaveArea = false; 811 bool HasCRSaveArea = false; 812 bool HasVRSAVESaveArea = false; 813 bool HasVRSaveArea = false; 814 815 SmallVector<CalleeSavedInfo, 18> GPRegs; 816 SmallVector<CalleeSavedInfo, 18> G8Regs; 817 SmallVector<CalleeSavedInfo, 18> FPRegs; 818 SmallVector<CalleeSavedInfo, 18> VRegs; 819 820 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 821 unsigned Reg = CSI[i].getReg(); 822 if (PPC::GPRCRegClass.contains(Reg)) { 823 HasGPSaveArea = true; 824 825 GPRegs.push_back(CSI[i]); 826 827 if (Reg < MinGPR) { 828 MinGPR = Reg; 829 } 830 } else if (PPC::G8RCRegClass.contains(Reg)) { 831 HasG8SaveArea = true; 832 833 G8Regs.push_back(CSI[i]); 834 835 if (Reg < MinG8R) { 836 MinG8R = Reg; 837 } 838 } else if (PPC::F8RCRegClass.contains(Reg)) { 839 HasFPSaveArea = true; 840 841 FPRegs.push_back(CSI[i]); 842 843 if (Reg < MinFPR) { 844 MinFPR = Reg; 845 } 846 // FIXME SVR4: Disable CR save area for now. 847 } else if (PPC::CRBITRCRegClass.contains(Reg) || 848 PPC::CRRCRegClass.contains(Reg)) { 849 // HasCRSaveArea = true; 850 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 851 HasVRSAVESaveArea = true; 852 } else if (PPC::VRRCRegClass.contains(Reg)) { 853 HasVRSaveArea = true; 854 855 VRegs.push_back(CSI[i]); 856 857 if (Reg < MinVR) { 858 MinVR = Reg; 859 } 860 } else { 861 llvm_unreachable("Unknown RegisterClass!"); 862 } 863 } 864 865 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 866 867 int64_t LowerBound = 0; 868 869 // Take into account stack space reserved for tail calls. 870 int TCSPDelta = 0; 871 if (MF.getTarget().Options.GuaranteedTailCallOpt && 872 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 873 LowerBound = TCSPDelta; 874 } 875 876 // The Floating-point register save area is right below the back chain word 877 // of the previous stack frame. 878 if (HasFPSaveArea) { 879 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 880 int FI = FPRegs[i].getFrameIdx(); 881 882 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 883 } 884 885 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 886 } 887 888 // Check whether the frame pointer register is allocated. If so, make sure it 889 // is spilled to the correct offset. 890 if (needsFP(MF)) { 891 HasGPSaveArea = true; 892 893 int FI = PFI->getFramePointerSaveIndex(); 894 assert(FI && "No Frame Pointer Save Slot!"); 895 896 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 897 } 898 899 // General register save area starts right below the Floating-point 900 // register save area. 901 if (HasGPSaveArea || HasG8SaveArea) { 902 // Move general register save area spill slots down, taking into account 903 // the size of the Floating-point register save area. 904 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 905 int FI = GPRegs[i].getFrameIdx(); 906 907 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 908 } 909 910 // Move general register save area spill slots down, taking into account 911 // the size of the Floating-point register save area. 912 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 913 int FI = G8Regs[i].getFrameIdx(); 914 915 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 916 } 917 918 unsigned MinReg = 919 std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 920 getPPCRegisterNumbering(MinG8R)); 921 922 if (Subtarget.isPPC64()) { 923 LowerBound -= (31 - MinReg + 1) * 8; 924 } else { 925 LowerBound -= (31 - MinReg + 1) * 4; 926 } 927 } 928 929 // The CR save area is below the general register save area. 930 if (HasCRSaveArea) { 931 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 932 // which have the CR/CRBIT register class? 933 // Adjust the frame index of the CR spill slot. 934 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 935 unsigned Reg = CSI[i].getReg(); 936 937 if (PPC::CRBITRCRegClass.contains(Reg) || 938 PPC::CRRCRegClass.contains(Reg)) { 939 int FI = CSI[i].getFrameIdx(); 940 941 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 942 } 943 } 944 945 LowerBound -= 4; // The CR save area is always 4 bytes long. 946 } 947 948 if (HasVRSAVESaveArea) { 949 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 950 // which have the VRSAVE register class? 951 // Adjust the frame index of the VRSAVE spill slot. 952 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 953 unsigned Reg = CSI[i].getReg(); 954 955 if (PPC::VRSAVERCRegClass.contains(Reg)) { 956 int FI = CSI[i].getFrameIdx(); 957 958 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 959 } 960 } 961 962 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 963 } 964 965 if (HasVRSaveArea) { 966 // Insert alignment padding, we need 16-byte alignment. 967 LowerBound = (LowerBound - 15) & ~(15); 968 969 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 970 int FI = VRegs[i].getFrameIdx(); 971 972 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 973 } 974 } 975 } 976