1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines a pattern matching instruction selector for PowerPC, 11 // converting from a legalized dag to a PPC dag. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "ppc-codegen" 16 #include "PPC.h" 17 #include "PPCTargetMachine.h" 18 #include "MCTargetDesc/PPCPredicates.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/CodeGen/SelectionDAGISel.h" 24 #include "llvm/Target/TargetOptions.h" 25 #include "llvm/Constants.h" 26 #include "llvm/Function.h" 27 #include "llvm/GlobalValue.h" 28 #include "llvm/Intrinsics.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/raw_ostream.h" 33 using namespace llvm; 34 35 namespace { 36 //===--------------------------------------------------------------------===// 37 /// PPCDAGToDAGISel - PPC specific code to select PPC machine 38 /// instructions for SelectionDAG operations. 39 /// 40 class PPCDAGToDAGISel : public SelectionDAGISel { 41 const PPCTargetMachine &TM; 42 const PPCTargetLowering &PPCLowering; 43 const PPCSubtarget &PPCSubTarget; 44 unsigned GlobalBaseReg; 45 public: 46 explicit PPCDAGToDAGISel(PPCTargetMachine &tm) 47 : SelectionDAGISel(tm), TM(tm), 48 PPCLowering(*TM.getTargetLowering()), 49 PPCSubTarget(*TM.getSubtargetImpl()) {} 50 51 virtual bool runOnMachineFunction(MachineFunction &MF) { 52 // Make sure we re-emit a set of the global base reg if necessary 53 GlobalBaseReg = 0; 54 SelectionDAGISel::runOnMachineFunction(MF); 55 56 InsertVRSaveCode(MF); 57 return true; 58 } 59 60 /// getI32Imm - Return a target constant with the specified value, of type 61 /// i32. 62 inline SDValue getI32Imm(unsigned Imm) { 63 return CurDAG->getTargetConstant(Imm, MVT::i32); 64 } 65 66 /// getI64Imm - Return a target constant with the specified value, of type 67 /// i64. 68 inline SDValue getI64Imm(uint64_t Imm) { 69 return CurDAG->getTargetConstant(Imm, MVT::i64); 70 } 71 72 /// getSmallIPtrImm - Return a target constant of pointer type. 73 inline SDValue getSmallIPtrImm(unsigned Imm) { 74 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 75 } 76 77 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 78 /// with any number of 0s on either side. The 1s are allowed to wrap from 79 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 80 /// 0x0F0F0000 is not, since all 1s are not contiguous. 81 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 82 83 84 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 85 /// rotate and mask opcode and mask operation. 86 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask, 87 unsigned &SH, unsigned &MB, unsigned &ME); 88 89 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 90 /// base register. Return the virtual register that holds this value. 91 SDNode *getGlobalBaseReg(); 92 93 // Select - Convert the specified operand from a target-independent to a 94 // target-specific node if it hasn't already been changed. 95 SDNode *Select(SDNode *N); 96 97 SDNode *SelectBitfieldInsert(SDNode *N); 98 99 /// SelectCC - Select a comparison of the specified values with the 100 /// specified condition code, returning the CR# of the expression. 101 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); 102 103 /// SelectAddrImm - Returns true if the address N can be represented by 104 /// a base register plus a signed 16-bit displacement [r+imm]. 105 bool SelectAddrImm(SDValue N, SDValue &Disp, 106 SDValue &Base) { 107 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); 108 } 109 110 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 111 /// immediate field. Because preinc imms have already been validated, just 112 /// accept it. 113 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { 114 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo || 115 N.getOpcode() == ISD::TargetGlobalAddress) { 116 Out = N; 117 return true; 118 } 119 120 return false; 121 } 122 123 /// SelectAddrIdxOffs - Return true if the operand is valid for a preinc 124 /// index field. Because preinc imms have already been validated, just 125 /// accept it. 126 bool SelectAddrIdxOffs(SDValue N, SDValue &Out) const { 127 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo || 128 N.getOpcode() == ISD::TargetGlobalAddress) 129 return false; 130 131 Out = N; 132 return true; 133 } 134 135 /// SelectAddrIdx - Given the specified addressed, check to see if it can be 136 /// represented as an indexed [r+r] operation. Returns false if it can 137 /// be represented by [r+imm], which are preferred. 138 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { 139 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); 140 } 141 142 /// SelectAddrIdxOnly - Given the specified addressed, force it to be 143 /// represented as an indexed [r+r] operation. 144 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { 145 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); 146 } 147 148 /// SelectAddrImmShift - Returns true if the address N can be represented by 149 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable 150 /// for use by STD and friends. 151 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) { 152 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); 153 } 154 155 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 156 /// inline asm expressions. It is always correct to compute the value into 157 /// a register. The case of adding a (possibly relocatable) constant to a 158 /// register can be improved, but it is wrong to substitute Reg+Reg for 159 /// Reg in an asm, because the load or store opcode would have to change. 160 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 161 char ConstraintCode, 162 std::vector<SDValue> &OutOps) { 163 OutOps.push_back(Op); 164 return false; 165 } 166 167 void InsertVRSaveCode(MachineFunction &MF); 168 169 virtual const char *getPassName() const { 170 return "PowerPC DAG->DAG Pattern Instruction Selection"; 171 } 172 173 // Include the pieces autogenerated from the target description. 174 #include "PPCGenDAGISel.inc" 175 176 private: 177 SDNode *SelectSETCC(SDNode *N); 178 }; 179 } 180 181 /// InsertVRSaveCode - Once the entire function has been instruction selected, 182 /// all virtual registers are created and all machine instructions are built, 183 /// check to see if we need to save/restore VRSAVE. If so, do it. 184 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { 185 // Check to see if this function uses vector registers, which means we have to 186 // save and restore the VRSAVE register and update it with the regs we use. 187 // 188 // In this case, there will be virtual registers of vector type created 189 // by the scheduler. Detect them now. 190 bool HasVectorVReg = false; 191 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { 192 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 193 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 194 HasVectorVReg = true; 195 break; 196 } 197 } 198 if (!HasVectorVReg) return; // nothing to do. 199 200 // If we have a vector register, we want to emit code into the entry and exit 201 // blocks to save and restore the VRSAVE register. We do this here (instead 202 // of marking all vector instructions as clobbering VRSAVE) for two reasons: 203 // 204 // 1. This (trivially) reduces the load on the register allocator, by not 205 // having to represent the live range of the VRSAVE register. 206 // 2. This (more significantly) allows us to create a temporary virtual 207 // register to hold the saved VRSAVE value, allowing this temporary to be 208 // register allocated, instead of forcing it to be spilled to the stack. 209 210 // Create two vregs - one to hold the VRSAVE register that is live-in to the 211 // function and one for the value after having bits or'd into it. 212 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 213 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 214 215 const TargetInstrInfo &TII = *TM.getInstrInfo(); 216 MachineBasicBlock &EntryBB = *Fn.begin(); 217 DebugLoc dl; 218 // Emit the following code into the entry block: 219 // InVRSAVE = MFVRSAVE 220 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 221 // MTVRSAVE UpdatedVRSAVE 222 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 223 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 224 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 225 UpdatedVRSAVE).addReg(InVRSAVE); 226 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 227 228 // Find all return blocks, outputting a restore in each epilog. 229 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 230 if (!BB->empty() && BB->back().isReturn()) { 231 IP = BB->end(); --IP; 232 233 // Skip over all terminator instructions, which are part of the return 234 // sequence. 235 MachineBasicBlock::iterator I2 = IP; 236 while (I2 != BB->begin() && (--I2)->isTerminator()) 237 IP = I2; 238 239 // Emit: MTVRSAVE InVRSave 240 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 241 } 242 } 243 } 244 245 246 /// getGlobalBaseReg - Output the instructions required to put the 247 /// base address to use for accessing globals into a register. 248 /// 249 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { 250 if (!GlobalBaseReg) { 251 const TargetInstrInfo &TII = *TM.getInstrInfo(); 252 // Insert the set of GlobalBaseReg into the first MBB of the function 253 MachineBasicBlock &FirstMBB = MF->front(); 254 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 255 DebugLoc dl; 256 257 if (PPCLowering.getPointerTy() == MVT::i32) { 258 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 259 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 260 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 261 } else { 262 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass); 263 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 264 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); 265 } 266 } 267 return CurDAG->getRegister(GlobalBaseReg, 268 PPCLowering.getPointerTy()).getNode(); 269 } 270 271 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit 272 /// or 64-bit immediate, and if the value can be accurately represented as a 273 /// sign extension from a 16-bit value. If so, this returns true and the 274 /// immediate. 275 static bool isIntS16Immediate(SDNode *N, short &Imm) { 276 if (N->getOpcode() != ISD::Constant) 277 return false; 278 279 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 280 if (N->getValueType(0) == MVT::i32) 281 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 282 else 283 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 284 } 285 286 static bool isIntS16Immediate(SDValue Op, short &Imm) { 287 return isIntS16Immediate(Op.getNode(), Imm); 288 } 289 290 291 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant 292 /// operand. If so Imm will receive the 32-bit value. 293 static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 294 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 295 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 296 return true; 297 } 298 return false; 299 } 300 301 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant 302 /// operand. If so Imm will receive the 64-bit value. 303 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { 304 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 305 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 306 return true; 307 } 308 return false; 309 } 310 311 // isInt32Immediate - This method tests to see if a constant operand. 312 // If so Imm will receive the 32 bit value. 313 static bool isInt32Immediate(SDValue N, unsigned &Imm) { 314 return isInt32Immediate(N.getNode(), Imm); 315 } 316 317 318 // isOpcWithIntImmediate - This method tests to see if the node is a specific 319 // opcode and that it has a immediate integer right operand. 320 // If so Imm will receive the 32 bit value. 321 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 322 return N->getOpcode() == Opc 323 && isInt32Immediate(N->getOperand(1).getNode(), Imm); 324 } 325 326 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 327 if (isShiftedMask_32(Val)) { 328 // look for the first non-zero bit 329 MB = CountLeadingZeros_32(Val); 330 // look for the first zero bit after the run of ones 331 ME = CountLeadingZeros_32((Val - 1) ^ Val); 332 return true; 333 } else { 334 Val = ~Val; // invert mask 335 if (isShiftedMask_32(Val)) { 336 // effectively look for the first zero bit 337 ME = CountLeadingZeros_32(Val) - 1; 338 // effectively look for the first one bit after the run of zeros 339 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; 340 return true; 341 } 342 } 343 // no run present 344 return false; 345 } 346 347 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, 348 bool isShiftMask, unsigned &SH, 349 unsigned &MB, unsigned &ME) { 350 // Don't even go down this path for i64, since different logic will be 351 // necessary for rldicl/rldicr/rldimi. 352 if (N->getValueType(0) != MVT::i32) 353 return false; 354 355 unsigned Shift = 32; 356 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 357 unsigned Opcode = N->getOpcode(); 358 if (N->getNumOperands() != 2 || 359 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 360 return false; 361 362 if (Opcode == ISD::SHL) { 363 // apply shift left to mask if it comes first 364 if (isShiftMask) Mask = Mask << Shift; 365 // determine which bits are made indeterminant by shift 366 Indeterminant = ~(0xFFFFFFFFu << Shift); 367 } else if (Opcode == ISD::SRL) { 368 // apply shift right to mask if it comes first 369 if (isShiftMask) Mask = Mask >> Shift; 370 // determine which bits are made indeterminant by shift 371 Indeterminant = ~(0xFFFFFFFFu >> Shift); 372 // adjust for the left rotate 373 Shift = 32 - Shift; 374 } else if (Opcode == ISD::ROTL) { 375 Indeterminant = 0; 376 } else { 377 return false; 378 } 379 380 // if the mask doesn't intersect any Indeterminant bits 381 if (Mask && !(Mask & Indeterminant)) { 382 SH = Shift & 31; 383 // make sure the mask is still a mask (wrap arounds may not be) 384 return isRunOfOnes(Mask, MB, ME); 385 } 386 return false; 387 } 388 389 /// SelectBitfieldInsert - turn an or of two masked values into 390 /// the rotate left word immediate then mask insert (rlwimi) instruction. 391 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 392 SDValue Op0 = N->getOperand(0); 393 SDValue Op1 = N->getOperand(1); 394 DebugLoc dl = N->getDebugLoc(); 395 396 APInt LKZ, LKO, RKZ, RKO; 397 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); 398 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); 399 400 unsigned TargetMask = LKZ.getZExtValue(); 401 unsigned InsertMask = RKZ.getZExtValue(); 402 403 if ((TargetMask | InsertMask) == 0xFFFFFFFF) { 404 unsigned Op0Opc = Op0.getOpcode(); 405 unsigned Op1Opc = Op1.getOpcode(); 406 unsigned Value, SH = 0; 407 TargetMask = ~TargetMask; 408 InsertMask = ~InsertMask; 409 410 // If the LHS has a foldable shift and the RHS does not, then swap it to the 411 // RHS so that we can fold the shift into the insert. 412 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 413 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 414 Op0.getOperand(0).getOpcode() == ISD::SRL) { 415 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 416 Op1.getOperand(0).getOpcode() != ISD::SRL) { 417 std::swap(Op0, Op1); 418 std::swap(Op0Opc, Op1Opc); 419 std::swap(TargetMask, InsertMask); 420 } 421 } 422 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 423 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 424 Op1.getOperand(0).getOpcode() != ISD::SRL) { 425 std::swap(Op0, Op1); 426 std::swap(Op0Opc, Op1Opc); 427 std::swap(TargetMask, InsertMask); 428 } 429 } 430 431 unsigned MB, ME; 432 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { 433 SDValue Tmp1, Tmp2; 434 435 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 436 isInt32Immediate(Op1.getOperand(1), Value)) { 437 Op1 = Op1.getOperand(0); 438 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 439 } 440 if (Op1Opc == ISD::AND) { 441 unsigned SHOpc = Op1.getOperand(0).getOpcode(); 442 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 443 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 444 Op1 = Op1.getOperand(0).getOperand(0); 445 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 446 } else { 447 Op1 = Op1.getOperand(0); 448 } 449 } 450 451 SH &= 31; 452 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), 453 getI32Imm(ME) }; 454 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); 455 } 456 } 457 return 0; 458 } 459 460 /// SelectCC - Select a comparison of the specified values with the specified 461 /// condition code, returning the CR# of the expression. 462 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, 463 ISD::CondCode CC, DebugLoc dl) { 464 // Always select the LHS. 465 unsigned Opc; 466 467 if (LHS.getValueType() == MVT::i32) { 468 unsigned Imm; 469 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 470 if (isInt32Immediate(RHS, Imm)) { 471 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 472 if (isUInt<16>(Imm)) 473 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 474 getI32Imm(Imm & 0xFFFF)), 0); 475 // If this is a 16-bit signed immediate, fold it. 476 if (isInt<16>((int)Imm)) 477 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 478 getI32Imm(Imm & 0xFFFF)), 0); 479 480 // For non-equality comparisons, the default code would materialize the 481 // constant, then compare against it, like this: 482 // lis r2, 4660 483 // ori r2, r2, 22136 484 // cmpw cr0, r3, r2 485 // Since we are just comparing for equality, we can emit this instead: 486 // xoris r0,r3,0x1234 487 // cmplwi cr0,r0,0x5678 488 // beq cr0,L6 489 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, 490 getI32Imm(Imm >> 16)), 0); 491 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, 492 getI32Imm(Imm & 0xFFFF)), 0); 493 } 494 Opc = PPC::CMPLW; 495 } else if (ISD::isUnsignedIntSetCC(CC)) { 496 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) 497 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 498 getI32Imm(Imm & 0xFFFF)), 0); 499 Opc = PPC::CMPLW; 500 } else { 501 short SImm; 502 if (isIntS16Immediate(RHS, SImm)) 503 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, 504 getI32Imm((int)SImm & 0xFFFF)), 505 0); 506 Opc = PPC::CMPW; 507 } 508 } else if (LHS.getValueType() == MVT::i64) { 509 uint64_t Imm; 510 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 511 if (isInt64Immediate(RHS.getNode(), Imm)) { 512 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 513 if (isUInt<16>(Imm)) 514 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 515 getI32Imm(Imm & 0xFFFF)), 0); 516 // If this is a 16-bit signed immediate, fold it. 517 if (isInt<16>(Imm)) 518 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 519 getI32Imm(Imm & 0xFFFF)), 0); 520 521 // For non-equality comparisons, the default code would materialize the 522 // constant, then compare against it, like this: 523 // lis r2, 4660 524 // ori r2, r2, 22136 525 // cmpd cr0, r3, r2 526 // Since we are just comparing for equality, we can emit this instead: 527 // xoris r0,r3,0x1234 528 // cmpldi cr0,r0,0x5678 529 // beq cr0,L6 530 if (isUInt<32>(Imm)) { 531 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 532 getI64Imm(Imm >> 16)), 0); 533 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 534 getI64Imm(Imm & 0xFFFF)), 0); 535 } 536 } 537 Opc = PPC::CMPLD; 538 } else if (ISD::isUnsignedIntSetCC(CC)) { 539 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) 540 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 541 getI64Imm(Imm & 0xFFFF)), 0); 542 Opc = PPC::CMPLD; 543 } else { 544 short SImm; 545 if (isIntS16Immediate(RHS, SImm)) 546 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 547 getI64Imm(SImm & 0xFFFF)), 548 0); 549 Opc = PPC::CMPD; 550 } 551 } else if (LHS.getValueType() == MVT::f32) { 552 Opc = PPC::FCMPUS; 553 } else { 554 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 555 Opc = PPC::FCMPUD; 556 } 557 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); 558 } 559 560 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 561 switch (CC) { 562 case ISD::SETUEQ: 563 case ISD::SETONE: 564 case ISD::SETOLE: 565 case ISD::SETOGE: 566 llvm_unreachable("Should be lowered by legalize!"); 567 default: llvm_unreachable("Unknown condition!"); 568 case ISD::SETOEQ: 569 case ISD::SETEQ: return PPC::PRED_EQ; 570 case ISD::SETUNE: 571 case ISD::SETNE: return PPC::PRED_NE; 572 case ISD::SETOLT: 573 case ISD::SETLT: return PPC::PRED_LT; 574 case ISD::SETULE: 575 case ISD::SETLE: return PPC::PRED_LE; 576 case ISD::SETOGT: 577 case ISD::SETGT: return PPC::PRED_GT; 578 case ISD::SETUGE: 579 case ISD::SETGE: return PPC::PRED_GE; 580 case ISD::SETO: return PPC::PRED_NU; 581 case ISD::SETUO: return PPC::PRED_UN; 582 // These two are invalid for floating point. Assume we have int. 583 case ISD::SETULT: return PPC::PRED_LT; 584 case ISD::SETUGT: return PPC::PRED_GT; 585 } 586 } 587 588 /// getCRIdxForSetCC - Return the index of the condition register field 589 /// associated with the SetCC condition, and whether or not the field is 590 /// treated as inverted. That is, lt = 0; ge = 0 inverted. 591 /// 592 /// If this returns with Other != -1, then the returned comparison is an or of 593 /// two simpler comparisons. In this case, Invert is guaranteed to be false. 594 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { 595 Invert = false; 596 Other = -1; 597 switch (CC) { 598 default: llvm_unreachable("Unknown condition!"); 599 case ISD::SETOLT: 600 case ISD::SETLT: return 0; // Bit #0 = SETOLT 601 case ISD::SETOGT: 602 case ISD::SETGT: return 1; // Bit #1 = SETOGT 603 case ISD::SETOEQ: 604 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 605 case ISD::SETUO: return 3; // Bit #3 = SETUO 606 case ISD::SETUGE: 607 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 608 case ISD::SETULE: 609 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 610 case ISD::SETUNE: 611 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 612 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 613 case ISD::SETUEQ: 614 case ISD::SETOGE: 615 case ISD::SETOLE: 616 case ISD::SETONE: 617 llvm_unreachable("Invalid branch code: should be expanded by legalize"); 618 // These are invalid for floating point. Assume integer. 619 case ISD::SETULT: return 0; 620 case ISD::SETUGT: return 1; 621 } 622 } 623 624 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) { 625 DebugLoc dl = N->getDebugLoc(); 626 unsigned Imm; 627 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 628 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 629 bool isPPC64 = (PtrVT == MVT::i64); 630 631 if (isInt32Immediate(N->getOperand(1), Imm)) { 632 // We can codegen setcc op, imm very efficiently compared to a brcond. 633 // Check for those cases here. 634 // setcc op, 0 635 if (Imm == 0) { 636 SDValue Op = N->getOperand(0); 637 switch (CC) { 638 default: break; 639 case ISD::SETEQ: { 640 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 641 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 642 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 643 } 644 case ISD::SETNE: { 645 if (isPPC64) break; 646 SDValue AD = 647 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 648 Op, getI32Imm(~0U)), 0); 649 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 650 AD.getValue(1)); 651 } 652 case ISD::SETLT: { 653 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 654 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 655 } 656 case ISD::SETGT: { 657 SDValue T = 658 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); 659 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); 660 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 661 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 662 } 663 } 664 } else if (Imm == ~0U) { // setcc op, -1 665 SDValue Op = N->getOperand(0); 666 switch (CC) { 667 default: break; 668 case ISD::SETEQ: 669 if (isPPC64) break; 670 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 671 Op, getI32Imm(1)), 0); 672 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 673 SDValue(CurDAG->getMachineNode(PPC::LI, dl, 674 MVT::i32, 675 getI32Imm(0)), 0), 676 Op.getValue(1)); 677 case ISD::SETNE: { 678 if (isPPC64) break; 679 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); 680 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 681 Op, getI32Imm(~0U)); 682 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), 683 Op, SDValue(AD, 1)); 684 } 685 case ISD::SETLT: { 686 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 687 getI32Imm(1)), 0); 688 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, 689 Op), 0); 690 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 691 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 692 } 693 case ISD::SETGT: { 694 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 695 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 696 0); 697 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 698 getI32Imm(1)); 699 } 700 } 701 } 702 } 703 704 bool Inv; 705 int OtherCondIdx; 706 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); 707 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 708 SDValue IntCR; 709 710 // Force the ccreg into CR7. 711 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 712 713 SDValue InFlag(0, 0); // Null incoming flag value. 714 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, 715 InFlag).getValue(1); 716 717 if (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1) 718 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, 719 CCReg), 0); 720 else 721 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32, 722 CR7Reg, CCReg), 0); 723 724 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 725 getI32Imm(31), getI32Imm(31) }; 726 if (OtherCondIdx == -1 && !Inv) 727 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 728 729 // Get the specified bit. 730 SDValue Tmp = 731 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); 732 if (Inv) { 733 assert(OtherCondIdx == -1 && "Can't have split plus negation"); 734 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 735 } 736 737 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT. 738 // We already got the bit for the first part of the comparison (e.g. SETULE). 739 740 // Get the other bit of the comparison. 741 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); 742 SDValue OtherCond = 743 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); 744 745 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); 746 } 747 748 749 // Select - Convert the specified operand from a target-independent to a 750 // target-specific node if it hasn't already been changed. 751 SDNode *PPCDAGToDAGISel::Select(SDNode *N) { 752 DebugLoc dl = N->getDebugLoc(); 753 if (N->isMachineOpcode()) 754 return NULL; // Already selected. 755 756 switch (N->getOpcode()) { 757 default: break; 758 759 case ISD::Constant: { 760 if (N->getValueType(0) == MVT::i64) { 761 // Get 64 bit value. 762 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); 763 // Assume no remaining bits. 764 unsigned Remainder = 0; 765 // Assume no shift required. 766 unsigned Shift = 0; 767 768 // If it can't be represented as a 32 bit value. 769 if (!isInt<32>(Imm)) { 770 Shift = CountTrailingZeros_64(Imm); 771 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 772 773 // If the shifted value fits 32 bits. 774 if (isInt<32>(ImmSh)) { 775 // Go with the shifted value. 776 Imm = ImmSh; 777 } else { 778 // Still stuck with a 64 bit value. 779 Remainder = Imm; 780 Shift = 32; 781 Imm >>= 32; 782 } 783 } 784 785 // Intermediate operand. 786 SDNode *Result; 787 788 // Handle first 32 bits. 789 unsigned Lo = Imm & 0xFFFF; 790 unsigned Hi = (Imm >> 16) & 0xFFFF; 791 792 // Simple value. 793 if (isInt<16>(Imm)) { 794 // Just the Lo bits. 795 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 796 } else if (Lo) { 797 // Handle the Hi bits. 798 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 799 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); 800 // And Lo bits. 801 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 802 SDValue(Result, 0), getI32Imm(Lo)); 803 } else { 804 // Just the Hi bits. 805 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); 806 } 807 808 // If no shift, we're done. 809 if (!Shift) return Result; 810 811 // Shift for next step if the upper 32-bits were not zero. 812 if (Imm) { 813 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, 814 SDValue(Result, 0), 815 getI32Imm(Shift), 816 getI32Imm(63 - Shift)); 817 } 818 819 // Add in the last bits as required. 820 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 821 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, 822 SDValue(Result, 0), getI32Imm(Hi)); 823 } 824 if ((Lo = Remainder & 0xFFFF)) { 825 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, 826 SDValue(Result, 0), getI32Imm(Lo)); 827 } 828 829 return Result; 830 } 831 break; 832 } 833 834 case ISD::SETCC: 835 return SelectSETCC(N); 836 case PPCISD::GlobalBaseReg: 837 return getGlobalBaseReg(); 838 839 case ISD::FrameIndex: { 840 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 841 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); 842 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 843 if (N->hasOneUse()) 844 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, 845 getSmallIPtrImm(0)); 846 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, 847 getSmallIPtrImm(0)); 848 } 849 850 case PPCISD::MFCR: { 851 SDValue InFlag = N->getOperand(1); 852 // Use MFOCRF if supported. 853 if (PPCSubTarget.hasMFOCRF()) 854 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, 855 N->getOperand(0), InFlag); 856 else 857 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32, 858 N->getOperand(0), InFlag); 859 } 860 861 case ISD::SDIV: { 862 // FIXME: since this depends on the setting of the carry flag from the srawi 863 // we should really be making notes about that for the scheduler. 864 // FIXME: It sure would be nice if we could cheaply recognize the 865 // srl/add/sra pattern the dag combiner will generate for this as 866 // sra/addze rather than having to handle sdiv ourselves. oh well. 867 unsigned Imm; 868 if (isInt32Immediate(N->getOperand(1), Imm)) { 869 SDValue N0 = N->getOperand(0); 870 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 871 SDNode *Op = 872 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 873 N0, getI32Imm(Log2_32(Imm))); 874 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 875 SDValue(Op, 0), SDValue(Op, 1)); 876 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 877 SDNode *Op = 878 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, 879 N0, getI32Imm(Log2_32(-Imm))); 880 SDValue PT = 881 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, 882 SDValue(Op, 0), SDValue(Op, 1)), 883 0); 884 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 885 } 886 } 887 888 // Other cases are autogenerated. 889 break; 890 } 891 892 case ISD::LOAD: { 893 // Handle preincrement loads. 894 LoadSDNode *LD = cast<LoadSDNode>(N); 895 EVT LoadedVT = LD->getMemoryVT(); 896 897 // Normal loads are handled by code generated from the .td file. 898 if (LD->getAddressingMode() != ISD::PRE_INC) 899 break; 900 901 SDValue Offset = LD->getOffset(); 902 if (isa<ConstantSDNode>(Offset) || 903 Offset.getOpcode() == ISD::TargetGlobalAddress) { 904 905 unsigned Opcode; 906 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 907 if (LD->getValueType(0) != MVT::i64) { 908 // Handle PPC32 integer and normal FP loads. 909 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 910 switch (LoadedVT.getSimpleVT().SimpleTy) { 911 default: llvm_unreachable("Invalid PPC load type!"); 912 case MVT::f64: Opcode = PPC::LFDU; break; 913 case MVT::f32: Opcode = PPC::LFSU; break; 914 case MVT::i32: Opcode = PPC::LWZU; break; 915 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 916 case MVT::i1: 917 case MVT::i8: Opcode = PPC::LBZU; break; 918 } 919 } else { 920 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 921 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 922 switch (LoadedVT.getSimpleVT().SimpleTy) { 923 default: llvm_unreachable("Invalid PPC load type!"); 924 case MVT::i64: Opcode = PPC::LDU; break; 925 case MVT::i32: Opcode = PPC::LWZU8; break; 926 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 927 case MVT::i1: 928 case MVT::i8: Opcode = PPC::LBZU8; break; 929 } 930 } 931 932 SDValue Chain = LD->getChain(); 933 SDValue Base = LD->getBasePtr(); 934 SDValue Ops[] = { Offset, Base, Chain }; 935 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 936 PPCLowering.getPointerTy(), 937 MVT::Other, Ops, 3); 938 } else { 939 unsigned Opcode; 940 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 941 if (LD->getValueType(0) != MVT::i64) { 942 // Handle PPC32 integer and normal FP loads. 943 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 944 switch (LoadedVT.getSimpleVT().SimpleTy) { 945 default: llvm_unreachable("Invalid PPC load type!"); 946 case MVT::f64: Opcode = PPC::LFDUX; break; 947 case MVT::f32: Opcode = PPC::LFSUX; break; 948 case MVT::i32: Opcode = PPC::LWZUX; break; 949 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; 950 case MVT::i1: 951 case MVT::i8: Opcode = PPC::LBZUX; break; 952 } 953 } else { 954 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 955 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && 956 "Invalid sext update load"); 957 switch (LoadedVT.getSimpleVT().SimpleTy) { 958 default: llvm_unreachable("Invalid PPC load type!"); 959 case MVT::i64: Opcode = PPC::LDUX; break; 960 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; 961 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; 962 case MVT::i1: 963 case MVT::i8: Opcode = PPC::LBZUX8; break; 964 } 965 } 966 967 SDValue Chain = LD->getChain(); 968 SDValue Base = LD->getBasePtr(); 969 SDValue Ops[] = { Offset, Base, Chain }; 970 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), 971 PPCLowering.getPointerTy(), 972 MVT::Other, Ops, 3); 973 } 974 } 975 976 case ISD::AND: { 977 unsigned Imm, Imm2, SH, MB, ME; 978 uint64_t Imm64; 979 980 // If this is an and of a value rotated between 0 and 31 bits and then and'd 981 // with a mask, emit rlwinm 982 if (isInt32Immediate(N->getOperand(1), Imm) && 983 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { 984 SDValue Val = N->getOperand(0).getOperand(0); 985 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 986 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 987 } 988 // If this is just a masked value where the input is not handled above, and 989 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 990 if (isInt32Immediate(N->getOperand(1), Imm) && 991 isRunOfOnes(Imm, MB, ME) && 992 N->getOperand(0).getOpcode() != ISD::ROTL) { 993 SDValue Val = N->getOperand(0); 994 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 995 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 996 } 997 // If this is a 64-bit zero-extension mask, emit rldicl. 998 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) && 999 isMask_64(Imm64)) { 1000 SDValue Val = N->getOperand(0); 1001 MB = 64 - CountTrailingOnes_64(Imm64); 1002 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) }; 1003 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3); 1004 } 1005 // AND X, 0 -> 0, not "rlwinm 32". 1006 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 1007 ReplaceUses(SDValue(N, 0), N->getOperand(1)); 1008 return NULL; 1009 } 1010 // ISD::OR doesn't get all the bitfield insertion fun. 1011 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1012 if (isInt32Immediate(N->getOperand(1), Imm) && 1013 N->getOperand(0).getOpcode() == ISD::OR && 1014 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1015 unsigned MB, ME; 1016 Imm = ~(Imm^Imm2); 1017 if (isRunOfOnes(Imm, MB, ME)) { 1018 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1019 N->getOperand(0).getOperand(1), 1020 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1021 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); 1022 } 1023 } 1024 1025 // Other cases are autogenerated. 1026 break; 1027 } 1028 case ISD::OR: 1029 if (N->getValueType(0) == MVT::i32) 1030 if (SDNode *I = SelectBitfieldInsert(N)) 1031 return I; 1032 1033 // Other cases are autogenerated. 1034 break; 1035 case ISD::SHL: { 1036 unsigned Imm, SH, MB, ME; 1037 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1038 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1039 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1040 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1041 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1042 } 1043 1044 // Other cases are autogenerated. 1045 break; 1046 } 1047 case ISD::SRL: { 1048 unsigned Imm, SH, MB, ME; 1049 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1050 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1051 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1052 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1053 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1054 } 1055 1056 // Other cases are autogenerated. 1057 break; 1058 } 1059 case ISD::SELECT_CC: { 1060 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1061 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); 1062 bool isPPC64 = (PtrVT == MVT::i64); 1063 1064 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1065 if (!isPPC64) 1066 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1067 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1068 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1069 if (N1C->isNullValue() && N3C->isNullValue() && 1070 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && 1071 // FIXME: Implement this optzn for PPC64. 1072 N->getValueType(0) == MVT::i32) { 1073 SDNode *Tmp = 1074 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, 1075 N->getOperand(0), getI32Imm(~0U)); 1076 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1077 SDValue(Tmp, 0), N->getOperand(0), 1078 SDValue(Tmp, 1)); 1079 } 1080 1081 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 1082 unsigned BROpc = getPredicateForSetCC(CC); 1083 1084 unsigned SelectCCOp; 1085 if (N->getValueType(0) == MVT::i32) 1086 SelectCCOp = PPC::SELECT_CC_I4; 1087 else if (N->getValueType(0) == MVT::i64) 1088 SelectCCOp = PPC::SELECT_CC_I8; 1089 else if (N->getValueType(0) == MVT::f32) 1090 SelectCCOp = PPC::SELECT_CC_F4; 1091 else if (N->getValueType(0) == MVT::f64) 1092 SelectCCOp = PPC::SELECT_CC_F8; 1093 else 1094 SelectCCOp = PPC::SELECT_CC_VRRC; 1095 1096 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1097 getI32Imm(BROpc) }; 1098 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1099 } 1100 case PPCISD::COND_BRANCH: { 1101 // Op #0 is the Chain. 1102 // Op #1 is the PPC::PRED_* number. 1103 // Op #2 is the CR# 1104 // Op #3 is the Dest MBB 1105 // Op #4 is the Flag. 1106 // Prevent PPC::PRED_* from being selected into LI. 1107 SDValue Pred = 1108 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); 1109 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1110 N->getOperand(0), N->getOperand(4) }; 1111 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1112 } 1113 case ISD::BR_CC: { 1114 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1115 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); 1116 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1117 N->getOperand(4), N->getOperand(0) }; 1118 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1119 } 1120 case ISD::BRIND: { 1121 // FIXME: Should custom lower this. 1122 SDValue Chain = N->getOperand(0); 1123 SDValue Target = N->getOperand(1); 1124 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1125 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; 1126 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, 1127 Chain), 0); 1128 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); 1129 } 1130 } 1131 1132 return SelectCode(N); 1133 } 1134 1135 1136 1137 /// createPPCISelDag - This pass converts a legalized DAG into a 1138 /// PowerPC-specific DAG, ready for instruction scheduling. 1139 /// 1140 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { 1141 return new PPCDAGToDAGISel(TM); 1142 } 1143 1144