1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the target machine instruction set to the code generator. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H 15 #define LLVM_TARGET_TARGETINSTRINFO_H 16 17 #include "llvm/ADT/SmallSet.h" 18 #include "llvm/CodeGen/DFAPacketizer.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 22 namespace llvm { 23 24 class InstrItineraryData; 25 class LiveVariables; 26 class MCAsmInfo; 27 class MachineMemOperand; 28 class MachineRegisterInfo; 29 class MDNode; 30 class MCInst; 31 class MCSchedModel; 32 class SDNode; 33 class ScheduleHazardRecognizer; 34 class SelectionDAG; 35 class ScheduleDAG; 36 class TargetRegisterClass; 37 class TargetRegisterInfo; 38 class BranchProbability; 39 40 template<class T> class SmallVectorImpl; 41 42 43 //--------------------------------------------------------------------------- 44 /// 45 /// TargetInstrInfo - Interface to description of machine instruction set 46 /// 47 class TargetInstrInfo : public MCInstrInfo { 48 TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 49 void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 50 public: 51 TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 52 : CallFrameSetupOpcode(CFSetupOpcode), 53 CallFrameDestroyOpcode(CFDestroyOpcode) { 54 } 55 56 virtual ~TargetInstrInfo(); 57 58 /// getRegClass - Givem a machine instruction descriptor, returns the register 59 /// class constraint for OpNum, or NULL. 60 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 61 unsigned OpNum, 62 const TargetRegisterInfo *TRI, 63 const MachineFunction &MF) const; 64 65 /// isTriviallyReMaterializable - Return true if the instruction is trivially 66 /// rematerializable, meaning it has no side effects and requires no operands 67 /// that aren't always available. 68 bool isTriviallyReMaterializable(const MachineInstr *MI, 69 AliasAnalysis *AA = 0) const { 70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 71 (MI->getDesc().isRematerializable() && 72 (isReallyTriviallyReMaterializable(MI, AA) || 73 isReallyTriviallyReMaterializableGeneric(MI, AA))); 74 } 75 76 protected: 77 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 78 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 79 /// specify whether the instruction is actually trivially rematerializable, 80 /// taking into consideration its operands. This predicate must return false 81 /// if the instruction has any side effects other than producing a value, or 82 /// if it requres any address registers that are not always available. 83 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 84 AliasAnalysis *AA) const { 85 return false; 86 } 87 88 private: 89 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 90 /// for which the M_REMATERIALIZABLE flag is set and the target hook 91 /// isReallyTriviallyReMaterializable returns false, this function does 92 /// target-independent tests to determine if the instruction is really 93 /// trivially rematerializable. 94 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 95 AliasAnalysis *AA) const; 96 97 public: 98 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 99 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 100 /// targets use pseudo instructions in order to abstract away the difference 101 /// between operating with a frame pointer and operating without, through the 102 /// use of these two instructions. 103 /// 104 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 105 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 106 107 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 108 /// extension instruction. That is, it's like a copy where it's legal for the 109 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 110 /// true, then it's expected the pre-extension value is available as a subreg 111 /// of the result register. This also returns the sub-register index in 112 /// SubIdx. 113 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 114 unsigned &SrcReg, unsigned &DstReg, 115 unsigned &SubIdx) const { 116 return false; 117 } 118 119 /// isLoadFromStackSlot - If the specified machine instruction is a direct 120 /// load from a stack slot, return the virtual or physical register number of 121 /// the destination along with the FrameIndex of the loaded stack slot. If 122 /// not, return 0. This predicate must return 0 if the instruction has 123 /// any side effects other than loading from the stack slot. 124 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 125 int &FrameIndex) const { 126 return 0; 127 } 128 129 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 130 /// stack locations as well. This uses a heuristic so it isn't 131 /// reliable for correctness. 132 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 133 int &FrameIndex) const { 134 return 0; 135 } 136 137 /// hasLoadFromStackSlot - If the specified machine instruction has 138 /// a load from a stack slot, return true along with the FrameIndex 139 /// of the loaded stack slot and the machine mem operand containing 140 /// the reference. If not, return false. Unlike 141 /// isLoadFromStackSlot, this returns true for any instructions that 142 /// loads from the stack. This is just a hint, as some cases may be 143 /// missed. 144 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 145 const MachineMemOperand *&MMO, 146 int &FrameIndex) const; 147 148 /// isStoreToStackSlot - If the specified machine instruction is a direct 149 /// store to a stack slot, return the virtual or physical register number of 150 /// the source reg along with the FrameIndex of the loaded stack slot. If 151 /// not, return 0. This predicate must return 0 if the instruction has 152 /// any side effects other than storing to the stack slot. 153 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 154 int &FrameIndex) const { 155 return 0; 156 } 157 158 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 159 /// stack locations as well. This uses a heuristic so it isn't 160 /// reliable for correctness. 161 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 162 int &FrameIndex) const { 163 return 0; 164 } 165 166 /// hasStoreToStackSlot - If the specified machine instruction has a 167 /// store to a stack slot, return true along with the FrameIndex of 168 /// the loaded stack slot and the machine mem operand containing the 169 /// reference. If not, return false. Unlike isStoreToStackSlot, 170 /// this returns true for any instructions that stores to the 171 /// stack. This is just a hint, as some cases may be missed. 172 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 173 const MachineMemOperand *&MMO, 174 int &FrameIndex) const; 175 176 /// reMaterialize - Re-issue the specified 'original' instruction at the 177 /// specific location targeting a new destination register. 178 /// The register in Orig->getOperand(0).getReg() will be substituted by 179 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 180 /// SubIdx. 181 virtual void reMaterialize(MachineBasicBlock &MBB, 182 MachineBasicBlock::iterator MI, 183 unsigned DestReg, unsigned SubIdx, 184 const MachineInstr *Orig, 185 const TargetRegisterInfo &TRI) const; 186 187 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 188 /// MachineFunction::CloneMachineInstr(), but the target may update operands 189 /// that are required to be unique. 190 /// 191 /// The instruction must be duplicable as indicated by isNotDuplicable(). 192 virtual MachineInstr *duplicate(MachineInstr *Orig, 193 MachineFunction &MF) const; 194 195 /// convertToThreeAddress - This method must be implemented by targets that 196 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 197 /// may be able to convert a two-address instruction into one or more true 198 /// three-address instructions on demand. This allows the X86 target (for 199 /// example) to convert ADD and SHL instructions into LEA instructions if they 200 /// would require register copies due to two-addressness. 201 /// 202 /// This method returns a null pointer if the transformation cannot be 203 /// performed, otherwise it returns the last new instruction. 204 /// 205 virtual MachineInstr * 206 convertToThreeAddress(MachineFunction::iterator &MFI, 207 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 208 return 0; 209 } 210 211 /// commuteInstruction - If a target has any instructions that are 212 /// commutable but require converting to different instructions or making 213 /// non-trivial changes to commute them, this method can overloaded to do 214 /// that. The default implementation simply swaps the commutable operands. 215 /// If NewMI is false, MI is modified in place and returned; otherwise, a 216 /// new machine instruction is created and returned. Do not call this 217 /// method for a non-commutable instruction, but there may be some cases 218 /// where this method fails and returns null. 219 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 220 bool NewMI = false) const; 221 222 /// findCommutedOpIndices - If specified MI is commutable, return the two 223 /// operand indices that would swap value. Return false if the instruction 224 /// is not in a form which this routine understands. 225 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 226 unsigned &SrcOpIdx2) const; 227 228 /// produceSameValue - Return true if two machine instructions would produce 229 /// identical values. By default, this is only true when the two instructions 230 /// are deemed identical except for defs. If this function is called when the 231 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 232 /// aggressive checks. 233 virtual bool produceSameValue(const MachineInstr *MI0, 234 const MachineInstr *MI1, 235 const MachineRegisterInfo *MRI = 0) const; 236 237 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 238 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 239 /// implemented for a target). Upon success, this returns false and returns 240 /// with the following information in various cases: 241 /// 242 /// 1. If this block ends with no branches (it just falls through to its succ) 243 /// just return false, leaving TBB/FBB null. 244 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 245 /// the destination block. 246 /// 3. If this block ends with a conditional branch and it falls through to a 247 /// successor block, it sets TBB to be the branch destination block and a 248 /// list of operands that evaluate the condition. These operands can be 249 /// passed to other TargetInstrInfo methods to create new branches. 250 /// 4. If this block ends with a conditional branch followed by an 251 /// unconditional branch, it returns the 'true' destination in TBB, the 252 /// 'false' destination in FBB, and a list of operands that evaluate the 253 /// condition. These operands can be passed to other TargetInstrInfo 254 /// methods to create new branches. 255 /// 256 /// Note that RemoveBranch and InsertBranch must be implemented to support 257 /// cases where this method returns success. 258 /// 259 /// If AllowModify is true, then this routine is allowed to modify the basic 260 /// block (e.g. delete instructions after the unconditional branch). 261 /// 262 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 263 MachineBasicBlock *&FBB, 264 SmallVectorImpl<MachineOperand> &Cond, 265 bool AllowModify = false) const { 266 return true; 267 } 268 269 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 270 /// This is only invoked in cases where AnalyzeBranch returns success. It 271 /// returns the number of instructions that were removed. 272 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 273 llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 274 } 275 276 /// InsertBranch - Insert branch code into the end of the specified 277 /// MachineBasicBlock. The operands to this method are the same as those 278 /// returned by AnalyzeBranch. This is only invoked in cases where 279 /// AnalyzeBranch returns success. It returns the number of instructions 280 /// inserted. 281 /// 282 /// It is also invoked by tail merging to add unconditional branches in 283 /// cases where AnalyzeBranch doesn't apply because there was no original 284 /// branch to analyze. At least this much must be implemented, else tail 285 /// merging needs to be disabled. 286 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 287 MachineBasicBlock *FBB, 288 const SmallVectorImpl<MachineOperand> &Cond, 289 DebugLoc DL) const { 290 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 291 } 292 293 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 294 /// after it, replacing it with an unconditional branch to NewDest. This is 295 /// used by the tail merging pass. 296 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 297 MachineBasicBlock *NewDest) const; 298 299 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 300 /// block at the specified instruction (i.e. instruction would be the start 301 /// of a new basic block). 302 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 303 MachineBasicBlock::iterator MBBI) const { 304 return true; 305 } 306 307 /// isProfitableToIfCvt - Return true if it's profitable to predicate 308 /// instructions with accumulated instruction latency of "NumCycles" 309 /// of the specified basic block, where the probability of the instructions 310 /// being executed is given by Probability, and Confidence is a measure 311 /// of our confidence that it will be properly predicted. 312 virtual 313 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 314 unsigned ExtraPredCycles, 315 const BranchProbability &Probability) const { 316 return false; 317 } 318 319 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 320 /// checks for the case where two basic blocks from true and false path 321 /// of a if-then-else (diamond) are predicated on mutally exclusive 322 /// predicates, where the probability of the true path being taken is given 323 /// by Probability, and Confidence is a measure of our confidence that it 324 /// will be properly predicted. 325 virtual bool 326 isProfitableToIfCvt(MachineBasicBlock &TMBB, 327 unsigned NumTCycles, unsigned ExtraTCycles, 328 MachineBasicBlock &FMBB, 329 unsigned NumFCycles, unsigned ExtraFCycles, 330 const BranchProbability &Probability) const { 331 return false; 332 } 333 334 /// isProfitableToDupForIfCvt - Return true if it's profitable for 335 /// if-converter to duplicate instructions of specified accumulated 336 /// instruction latencies in the specified MBB to enable if-conversion. 337 /// The probability of the instructions being executed is given by 338 /// Probability, and Confidence is a measure of our confidence that it 339 /// will be properly predicted. 340 virtual bool 341 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 342 const BranchProbability &Probability) const { 343 return false; 344 } 345 346 /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 347 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 348 /// exclusive predicates. 349 /// e.g. 350 /// subeq r0, r1, #1 351 /// addne r0, r1, #1 352 /// => 353 /// sub r0, r1, #1 354 /// addne r0, r1, #1 355 /// 356 /// This may be profitable is conditional instructions are always executed. 357 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 358 MachineBasicBlock &FMBB) const { 359 return false; 360 } 361 362 /// canInsertSelect - Return true if it is possible to insert a select 363 /// instruction that chooses between TrueReg and FalseReg based on the 364 /// condition code in Cond. 365 /// 366 /// When successful, also return the latency in cycles from TrueReg, 367 /// FalseReg, and Cond to the destination register. The Cond latency should 368 /// compensate for a conditional branch being removed. For example, if a 369 /// conditional branch has a 3 cycle latency from the condition code read, 370 /// and a cmov instruction has a 2 cycle latency from the condition code 371 /// read, CondCycles should be returned as -1. 372 /// 373 /// @param MBB Block where select instruction would be inserted. 374 /// @param Cond Condition returned by AnalyzeBranch. 375 /// @param TrueReg Virtual register to select when Cond is true. 376 /// @param FalseReg Virtual register to select when Cond is false. 377 /// @param CondCycles Latency from Cond+Branch to select output. 378 /// @param TrueCycles Latency from TrueReg to select output. 379 /// @param FalseCycles Latency from FalseReg to select output. 380 virtual bool canInsertSelect(const MachineBasicBlock &MBB, 381 const SmallVectorImpl<MachineOperand> &Cond, 382 unsigned TrueReg, unsigned FalseReg, 383 int &CondCycles, 384 int &TrueCycles, int &FalseCycles) const { 385 return false; 386 } 387 388 /// insertSelect - Insert a select instruction into MBB before I that will 389 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 390 /// Cond is false. 391 /// 392 /// This function can only be called after canInsertSelect() returned true. 393 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed 394 /// that the same flags or registers required by Cond are available at the 395 /// insertion point. 396 /// 397 /// @param MBB Block where select instruction should be inserted. 398 /// @param I Insertion point. 399 /// @param DL Source location for debugging. 400 /// @param DstReg Virtual register to be defined by select instruction. 401 /// @param Cond Condition as computed by AnalyzeBranch. 402 /// @param TrueReg Virtual register to copy when Cond is true. 403 /// @param FalseReg Virtual register to copy when Cons is false. 404 virtual void insertSelect(MachineBasicBlock &MBB, 405 MachineBasicBlock::iterator I, DebugLoc DL, 406 unsigned DstReg, 407 const SmallVectorImpl<MachineOperand> &Cond, 408 unsigned TrueReg, unsigned FalseReg) const { 409 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 410 } 411 412 /// analyzeSelect - Analyze the given select instruction, returning true if 413 /// it cannot be understood. It is assumed that MI->isSelect() is true. 414 /// 415 /// When successful, return the controlling condition and the operands that 416 /// determine the true and false result values. 417 /// 418 /// Result = SELECT Cond, TrueOp, FalseOp 419 /// 420 /// Some targets can optimize select instructions, for example by predicating 421 /// the instruction defining one of the operands. Such targets should set 422 /// Optimizable. 423 /// 424 /// @param MI Select instruction to analyze. 425 /// @param Cond Condition controlling the select. 426 /// @param TrueOp Operand number of the value selected when Cond is true. 427 /// @param FalseOp Operand number of the value selected when Cond is false. 428 /// @param Optimizable Returned as true if MI is optimizable. 429 /// @returns False on success. 430 virtual bool analyzeSelect(const MachineInstr *MI, 431 SmallVectorImpl<MachineOperand> &Cond, 432 unsigned &TrueOp, unsigned &FalseOp, 433 bool &Optimizable) const { 434 assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction"); 435 return true; 436 } 437 438 /// optimizeSelect - Given a select instruction that was understood by 439 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 440 /// merging it with one of its operands. Returns NULL on failure. 441 /// 442 /// When successful, returns the new select instruction. The client is 443 /// responsible for deleting MI. 444 /// 445 /// If both sides of the select can be optimized, PreferFalse is used to pick 446 /// a side. 447 /// 448 /// @param MI Optimizable select instruction. 449 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 450 /// @returns Optimized instruction or NULL. 451 virtual MachineInstr *optimizeSelect(MachineInstr *MI, 452 bool PreferFalse = false) const { 453 // This function must be implemented if Optimizable is ever set. 454 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 455 } 456 457 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 458 /// 459 /// This function should support copies within any legal register class as 460 /// well as any cross-class copies created during instruction selection. 461 /// 462 /// The source and destination registers may overlap, which may require a 463 /// careful implementation when multiple copy instructions are required for 464 /// large registers. See for example the ARM target. 465 virtual void copyPhysReg(MachineBasicBlock &MBB, 466 MachineBasicBlock::iterator MI, DebugLoc DL, 467 unsigned DestReg, unsigned SrcReg, 468 bool KillSrc) const { 469 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 470 } 471 472 /// storeRegToStackSlot - Store the specified register of the given register 473 /// class to the specified stack frame index. The store instruction is to be 474 /// added to the given machine basic block before the specified machine 475 /// instruction. If isKill is true, the register operand is the last use and 476 /// must be marked kill. 477 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 478 MachineBasicBlock::iterator MI, 479 unsigned SrcReg, bool isKill, int FrameIndex, 480 const TargetRegisterClass *RC, 481 const TargetRegisterInfo *TRI) const { 482 llvm_unreachable("Target didn't implement " 483 "TargetInstrInfo::storeRegToStackSlot!"); 484 } 485 486 /// loadRegFromStackSlot - Load the specified register of the given register 487 /// class from the specified stack frame index. The load instruction is to be 488 /// added to the given machine basic block before the specified machine 489 /// instruction. 490 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 491 MachineBasicBlock::iterator MI, 492 unsigned DestReg, int FrameIndex, 493 const TargetRegisterClass *RC, 494 const TargetRegisterInfo *TRI) const { 495 llvm_unreachable("Target didn't implement " 496 "TargetInstrInfo::loadRegFromStackSlot!"); 497 } 498 499 /// expandPostRAPseudo - This function is called for all pseudo instructions 500 /// that remain after register allocation. Many pseudo instructions are 501 /// created to help register allocation. This is the place to convert them 502 /// into real instructions. The target can edit MI in place, or it can insert 503 /// new instructions and erase MI. The function should return true if 504 /// anything was changed. 505 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 506 return false; 507 } 508 509 /// emitFrameIndexDebugValue - Emit a target-dependent form of 510 /// DBG_VALUE encoding the address of a frame index. Addresses would 511 /// normally be lowered the same way as other addresses on the target, 512 /// e.g. in load instructions. For targets that do not support this 513 /// the debug info is simply lost. 514 /// If you add this for a target you should handle this DBG_VALUE in the 515 /// target-specific AsmPrinter code as well; you will probably get invalid 516 /// assembly output if you don't. 517 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 518 int FrameIx, 519 uint64_t Offset, 520 const MDNode *MDPtr, 521 DebugLoc dl) const { 522 return 0; 523 } 524 525 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 526 /// slot into the specified machine instruction for the specified operand(s). 527 /// If this is possible, a new instruction is returned with the specified 528 /// operand folded, otherwise NULL is returned. 529 /// The new instruction is inserted before MI, and the client is responsible 530 /// for removing the old instruction. 531 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 532 const SmallVectorImpl<unsigned> &Ops, 533 int FrameIndex) const; 534 535 /// foldMemoryOperand - Same as the previous version except it allows folding 536 /// of any load and store from / to any address, not just from a specific 537 /// stack slot. 538 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 539 const SmallVectorImpl<unsigned> &Ops, 540 MachineInstr* LoadMI) const; 541 542 protected: 543 /// foldMemoryOperandImpl - Target-dependent implementation for 544 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 545 /// take care of adding a MachineMemOperand to the newly created instruction. 546 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 547 MachineInstr* MI, 548 const SmallVectorImpl<unsigned> &Ops, 549 int FrameIndex) const { 550 return 0; 551 } 552 553 /// foldMemoryOperandImpl - Target-dependent implementation for 554 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 555 /// take care of adding a MachineMemOperand to the newly created instruction. 556 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 557 MachineInstr* MI, 558 const SmallVectorImpl<unsigned> &Ops, 559 MachineInstr* LoadMI) const { 560 return 0; 561 } 562 563 public: 564 /// canFoldMemoryOperand - Returns true for the specified load / store if 565 /// folding is possible. 566 virtual 567 bool canFoldMemoryOperand(const MachineInstr *MI, 568 const SmallVectorImpl<unsigned> &Ops) const; 569 570 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 571 /// a store or a load and a store into two or more instruction. If this is 572 /// possible, returns true as well as the new instructions by reference. 573 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 574 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 575 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 576 return false; 577 } 578 579 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 580 SmallVectorImpl<SDNode*> &NewNodes) const { 581 return false; 582 } 583 584 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 585 /// instruction after load / store are unfolded from an instruction of the 586 /// specified opcode. It returns zero if the specified unfolding is not 587 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 588 /// index of the operand which will hold the register holding the loaded 589 /// value. 590 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 591 bool UnfoldLoad, bool UnfoldStore, 592 unsigned *LoadRegIndex = 0) const { 593 return 0; 594 } 595 596 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 597 /// to determine if two loads are loading from the same base address. It 598 /// should only return true if the base pointers are the same and the 599 /// only differences between the two addresses are the offset. It also returns 600 /// the offsets by reference. 601 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 602 int64_t &Offset1, int64_t &Offset2) const { 603 return false; 604 } 605 606 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 607 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 608 /// be scheduled togther. On some targets if two loads are loading from 609 /// addresses in the same cache line, it's better if they are scheduled 610 /// together. This function takes two integers that represent the load offsets 611 /// from the common base address. It returns true if it decides it's desirable 612 /// to schedule the two loads together. "NumLoads" is the number of loads that 613 /// have already been scheduled after Load1. 614 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 615 int64_t Offset1, int64_t Offset2, 616 unsigned NumLoads) const { 617 return false; 618 } 619 620 /// \brief Get the base register and byte offset of a load/store instr. 621 virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt, 622 unsigned &BaseReg, unsigned &Offset, 623 const TargetRegisterInfo *TRI) const { 624 return false; 625 } 626 627 virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, 628 MachineInstr *SecondLdSt, 629 unsigned NumLoads) const { 630 return false; 631 } 632 633 /// \brief Can this target fuse the given instructions if they are scheduled 634 /// adjacent. 635 virtual bool shouldScheduleAdjacent(MachineInstr* First, 636 MachineInstr *Second) const { 637 return false; 638 } 639 640 /// ReverseBranchCondition - Reverses the branch condition of the specified 641 /// condition list, returning false on success and true if it cannot be 642 /// reversed. 643 virtual 644 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 645 return true; 646 } 647 648 /// insertNoop - Insert a noop into the instruction stream at the specified 649 /// point. 650 virtual void insertNoop(MachineBasicBlock &MBB, 651 MachineBasicBlock::iterator MI) const; 652 653 654 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 655 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 656 // Default to just using 'nop' string. 657 } 658 659 660 /// isPredicated - Returns true if the instruction is already predicated. 661 /// 662 virtual bool isPredicated(const MachineInstr *MI) const { 663 return false; 664 } 665 666 /// isUnpredicatedTerminator - Returns true if the instruction is a 667 /// terminator instruction that has not been predicated. 668 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 669 670 /// PredicateInstruction - Convert the instruction into a predicated 671 /// instruction. It returns true if the operation was successful. 672 virtual 673 bool PredicateInstruction(MachineInstr *MI, 674 const SmallVectorImpl<MachineOperand> &Pred) const; 675 676 /// SubsumesPredicate - Returns true if the first specified predicate 677 /// subsumes the second, e.g. GE subsumes GT. 678 virtual 679 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 680 const SmallVectorImpl<MachineOperand> &Pred2) const { 681 return false; 682 } 683 684 /// DefinesPredicate - If the specified instruction defines any predicate 685 /// or condition code register(s) used for predication, returns true as well 686 /// as the definition predicate(s) by reference. 687 virtual bool DefinesPredicate(MachineInstr *MI, 688 std::vector<MachineOperand> &Pred) const { 689 return false; 690 } 691 692 /// isPredicable - Return true if the specified instruction can be predicated. 693 /// By default, this returns true for every instruction with a 694 /// PredicateOperand. 695 virtual bool isPredicable(MachineInstr *MI) const { 696 return MI->getDesc().isPredicable(); 697 } 698 699 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 700 /// instruction that defines the specified register class. 701 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 702 return true; 703 } 704 705 /// isSchedulingBoundary - Test if the given instruction should be 706 /// considered a scheduling boundary. This primarily includes labels and 707 /// terminators. 708 virtual bool isSchedulingBoundary(const MachineInstr *MI, 709 const MachineBasicBlock *MBB, 710 const MachineFunction &MF) const; 711 712 /// Measure the specified inline asm to determine an approximation of its 713 /// length. 714 virtual unsigned getInlineAsmLength(const char *Str, 715 const MCAsmInfo &MAI) const; 716 717 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 718 /// use for this target when scheduling the machine instructions before 719 /// register allocation. 720 virtual ScheduleHazardRecognizer* 721 CreateTargetHazardRecognizer(const TargetMachine *TM, 722 const ScheduleDAG *DAG) const; 723 724 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 725 /// to use for this target when scheduling the machine instructions before 726 /// register allocation. 727 virtual ScheduleHazardRecognizer* 728 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 729 const ScheduleDAG *DAG) const; 730 731 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 732 /// recognizer to use for this target when scheduling the machine instructions 733 /// after register allocation. 734 virtual ScheduleHazardRecognizer* 735 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 736 const ScheduleDAG *DAG) const; 737 738 /// Provide a global flag for disabling the PreRA hazard recognizer that 739 /// targets may choose to honor. 740 bool usePreRAHazardRecognizer() const; 741 742 /// analyzeCompare - For a comparison instruction, return the source registers 743 /// in SrcReg and SrcReg2 if having two register operands, and the value it 744 /// compares against in CmpValue. Return true if the comparison instruction 745 /// can be analyzed. 746 virtual bool analyzeCompare(const MachineInstr *MI, 747 unsigned &SrcReg, unsigned &SrcReg2, 748 int &Mask, int &Value) const { 749 return false; 750 } 751 752 /// optimizeCompareInstr - See if the comparison instruction can be converted 753 /// into something more efficient. E.g., on ARM most instructions can set the 754 /// flags register, obviating the need for a separate CMP. 755 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 756 unsigned SrcReg, unsigned SrcReg2, 757 int Mask, int Value, 758 const MachineRegisterInfo *MRI) const { 759 return false; 760 } 761 762 /// optimizeLoadInstr - Try to remove the load by folding it to a register 763 /// operand at the use. We fold the load instructions if and only if the 764 /// def and use are in the same BB. We only look at one load and see 765 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 766 /// defined by the load we are trying to fold. DefMI returns the machine 767 /// instruction that defines FoldAsLoadDefReg, and the function returns 768 /// the machine instruction generated due to folding. 769 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 770 const MachineRegisterInfo *MRI, 771 unsigned &FoldAsLoadDefReg, 772 MachineInstr *&DefMI) const { 773 return 0; 774 } 775 776 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 777 /// instruction, try to fold the immediate into the use instruction. 778 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 779 unsigned Reg, MachineRegisterInfo *MRI) const { 780 return false; 781 } 782 783 /// getNumMicroOps - Return the number of u-operations the given machine 784 /// instruction will be decoded to on the target cpu. The itinerary's 785 /// IssueWidth is the number of microops that can be dispatched each 786 /// cycle. An instruction with zero microops takes no dispatch resources. 787 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 788 const MachineInstr *MI) const; 789 790 /// isZeroCost - Return true for pseudo instructions that don't consume any 791 /// machine resources in their current form. These are common cases that the 792 /// scheduler should consider free, rather than conservatively handling them 793 /// as instructions with no itinerary. 794 bool isZeroCost(unsigned Opcode) const { 795 return Opcode <= TargetOpcode::COPY; 796 } 797 798 virtual int getOperandLatency(const InstrItineraryData *ItinData, 799 SDNode *DefNode, unsigned DefIdx, 800 SDNode *UseNode, unsigned UseIdx) const; 801 802 /// getOperandLatency - Compute and return the use operand latency of a given 803 /// pair of def and use. 804 /// In most cases, the static scheduling itinerary was enough to determine the 805 /// operand latency. But it may not be possible for instructions with variable 806 /// number of defs / uses. 807 /// 808 /// This is a raw interface to the itinerary that may be directly overriden by 809 /// a target. Use computeOperandLatency to get the best estimate of latency. 810 virtual int getOperandLatency(const InstrItineraryData *ItinData, 811 const MachineInstr *DefMI, unsigned DefIdx, 812 const MachineInstr *UseMI, 813 unsigned UseIdx) const; 814 815 /// computeOperandLatency - Compute and return the latency of the given data 816 /// dependent def and use when the operand indices are already known. 817 /// 818 /// FindMin may be set to get the minimum vs. expected latency. 819 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 820 const MachineInstr *DefMI, unsigned DefIdx, 821 const MachineInstr *UseMI, unsigned UseIdx, 822 bool FindMin = false) const; 823 824 /// getInstrLatency - Compute the instruction latency of a given instruction. 825 /// If the instruction has higher cost when predicated, it's returned via 826 /// PredCost. 827 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 828 const MachineInstr *MI, 829 unsigned *PredCost = 0) const; 830 831 virtual int getInstrLatency(const InstrItineraryData *ItinData, 832 SDNode *Node) const; 833 834 /// Return the default expected latency for a def based on it's opcode. 835 unsigned defaultDefLatency(const MCSchedModel *SchedModel, 836 const MachineInstr *DefMI) const; 837 838 int computeDefOperandLatency(const InstrItineraryData *ItinData, 839 const MachineInstr *DefMI, bool FindMin) const; 840 841 /// isHighLatencyDef - Return true if this opcode has high latency to its 842 /// result. 843 virtual bool isHighLatencyDef(int opc) const { return false; } 844 845 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 846 /// and an use in the current loop, return true if the target considered 847 /// it 'high'. This is used by optimization passes such as machine LICM to 848 /// determine whether it makes sense to hoist an instruction out even in 849 /// high register pressure situation. 850 virtual 851 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 852 const MachineRegisterInfo *MRI, 853 const MachineInstr *DefMI, unsigned DefIdx, 854 const MachineInstr *UseMI, unsigned UseIdx) const { 855 return false; 856 } 857 858 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 859 /// if the target considered it 'low'. 860 virtual 861 bool hasLowDefLatency(const InstrItineraryData *ItinData, 862 const MachineInstr *DefMI, unsigned DefIdx) const; 863 864 /// verifyInstruction - Perform target specific instruction verification. 865 virtual 866 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 867 return true; 868 } 869 870 /// getExecutionDomain - Return the current execution domain and bit mask of 871 /// possible domains for instruction. 872 /// 873 /// Some micro-architectures have multiple execution domains, and multiple 874 /// opcodes that perform the same operation in different domains. For 875 /// example, the x86 architecture provides the por, orps, and orpd 876 /// instructions that all do the same thing. There is a latency penalty if a 877 /// register is written in one domain and read in another. 878 /// 879 /// This function returns a pair (domain, mask) containing the execution 880 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 881 /// function can be used to change the opcode to one of the domains in the 882 /// bit mask. Instructions whose execution domain can't be changed should 883 /// return a 0 mask. 884 /// 885 /// The execution domain numbers don't have any special meaning except domain 886 /// 0 is used for instructions that are not associated with any interesting 887 /// execution domain. 888 /// 889 virtual std::pair<uint16_t, uint16_t> 890 getExecutionDomain(const MachineInstr *MI) const { 891 return std::make_pair(0, 0); 892 } 893 894 /// setExecutionDomain - Change the opcode of MI to execute in Domain. 895 /// 896 /// The bit (1 << Domain) must be set in the mask returned from 897 /// getExecutionDomain(MI). 898 /// 899 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 900 901 902 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 903 /// before an instruction with an unwanted partial register update. 904 /// 905 /// Some instructions only write part of a register, and implicitly need to 906 /// read the other parts of the register. This may cause unwanted stalls 907 /// preventing otherwise unrelated instructions from executing in parallel in 908 /// an out-of-order CPU. 909 /// 910 /// For example, the x86 instruction cvtsi2ss writes its result to bits 911 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 912 /// the instruction needs to wait for the old value of the register to become 913 /// available: 914 /// 915 /// addps %xmm1, %xmm0 916 /// movaps %xmm0, (%rax) 917 /// cvtsi2ss %rbx, %xmm0 918 /// 919 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 920 /// instruction before it can issue, even though the high bits of %xmm0 921 /// probably aren't needed. 922 /// 923 /// This hook returns the preferred clearance before MI, measured in 924 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 925 /// instructions before MI. It should only return a positive value for 926 /// unwanted dependencies. If the old bits of the defined register have 927 /// useful values, or if MI is determined to otherwise read the dependency, 928 /// the hook should return 0. 929 /// 930 /// The unwanted dependency may be handled by: 931 /// 932 /// 1. Allocating the same register for an MI def and use. That makes the 933 /// unwanted dependency identical to a required dependency. 934 /// 935 /// 2. Allocating a register for the def that has no defs in the previous N 936 /// instructions. 937 /// 938 /// 3. Calling breakPartialRegDependency() with the same arguments. This 939 /// allows the target to insert a dependency breaking instruction. 940 /// 941 virtual unsigned 942 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 943 const TargetRegisterInfo *TRI) const { 944 // The default implementation returns 0 for no partial register dependency. 945 return 0; 946 } 947 948 /// breakPartialRegDependency - Insert a dependency-breaking instruction 949 /// before MI to eliminate an unwanted dependency on OpNum. 950 /// 951 /// If it wasn't possible to avoid a def in the last N instructions before MI 952 /// (see getPartialRegUpdateClearance), this hook will be called to break the 953 /// unwanted dependency. 954 /// 955 /// On x86, an xorps instruction can be used as a dependency breaker: 956 /// 957 /// addps %xmm1, %xmm0 958 /// movaps %xmm0, (%rax) 959 /// xorps %xmm0, %xmm0 960 /// cvtsi2ss %rbx, %xmm0 961 /// 962 /// An <imp-kill> operand should be added to MI if an instruction was 963 /// inserted. This ties the instructions together in the post-ra scheduler. 964 /// 965 virtual void 966 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 967 const TargetRegisterInfo *TRI) const {} 968 969 /// Create machine specific model for scheduling. 970 virtual DFAPacketizer* 971 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 972 return NULL; 973 } 974 975 private: 976 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 977 }; 978 979 } // End llvm namespace 980 981 #endif 982
