| /dalvik/dx/tests/060-dex-call-static/ |
| expected.txt | 2 regs: 0001; ins: 0000; outs: 0001
|
| /dalvik/dx/tests/068-dex-infinite-loop/ |
| expected.txt | 2 regs: 0000; ins: 0000; outs: 0000
5 regs: 0001; ins: 0000; outs: 0000
11 regs: 0001; ins: 0000; outs: 0000
19 regs: 0001; ins: 0000; outs: 0000
|
| /dalvik/dx/tests/095-dex-const-string-jumbo/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0001
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrFormatsV4.td | 31 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
33 : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV>;
35 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
37 : NVInst<outs, ins, asmstr, pattern, cstr>;
40 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
42 : NVInst<outs, ins, asmstr, pattern, cstr>;
46 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
48 : NVInst<outs, ins, asmstr, pattern, cstr>;
51 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
53 : NVInst<outs, ins, asmstr, pattern, cstr>
[all...] |
| HexagonInstrInfoV5.td | 7 def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
14 def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
20 def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
34 def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
41 def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
49 def TFRI_cNotPt_f : ALU32_ri<(outs IntRegs:$dst),
56 def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),
61 def CONVERT_df2sf : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src),
68 def LDrid_f : LDInst<(outs DoubleRegs:$dst),
76 def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst)
[all...] |
| HexagonIntrinsicsV5.td | 2 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
7 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
12 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
17 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
22 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
27 : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1),
32 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
37 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
42 : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
47 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1)
[all...] |
| HexagonIntrinsics.td | 21 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
26 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
31 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
46 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
53 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
60 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
67 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
72 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2)
[all...] |
| /external/llvm/tools/bugpoint/ |
| FindBugs.cpp | 36 outs() << "Starting bug finding procedure...\n\n";
41 outs() << "\n";
43 outs() << "Generating reference output from raw program: \n";
60 outs() << "Running selected passes on program to test for crash: ";
62 outs() << "-" << PassesToRun[i] << " ";
67 outs() << "\n";
68 outs() << "Optimizer passes caused failure!\n\n";
72 outs() << "Combination " << num << " optimized successfully!\n";
78 outs() << "Running the code generator to test for a crash: ";
82 outs() << "\n*** compileProgram threw an exception: "
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrTSX.td | 22 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
27 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
30 def XEND : I<0x01, MRM_D5, (outs), (ins),
34 def XTEST : I<0x01, MRM_D6, (outs), (ins),
37 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
43 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>;
45 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>;
|
| X86InstrInfo.td | [all...] |
| X86InstrXOP.td | 15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
61 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
64 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
76 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
79 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
92 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
96 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.td | [all...] |
| PPCInstrAltivec.td | 166 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
174 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
182 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
189 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
197 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
205 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
211 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
219 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
230 def DSS : DSS_Form<822, (outs),
233 def DSSALL : DSS_Form<822, (outs),
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrFormats.td | 14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern> {
26 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
27 InstSI <outs, ins, asm, pattern> {
33 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
34 InstSI <outs, ins, asm, pattern> {
44 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
45 Enc32<outs, ins, asm, pattern> {
60 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
61 Enc32 <outs, ins, asm, pattern>
[all...] |
| /external/llvm/tools/llvm-bcanalyzer/ |
| llvm-bcanalyzer.cpp | 336 if (Dump) outs() << Indent << "<BLOCKINFO_BLOCK/>\n";
350 outs() << Indent << "<";
352 outs() << BlockName;
354 outs() << "UnknownBlock" << BlockID;
357 outs() << " BlockID=" << BlockID;
359 outs() << " NumWords=" << NumWords
382 outs() << Indent << "</";
384 outs() << BlockName << ">\n";
386 outs() << "UnknownBlock" << BlockID << ">\n";
432 outs() << Indent << " <"
[all...] |
| /dalvik/dx/tests/065-dex-new-array/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0000
9 regs: 0003; ins: 0001; outs: 0000
16 regs: 0003; ins: 0001; outs: 0000
23 regs: 0003; ins: 0001; outs: 0000
30 regs: 0003; ins: 0001; outs: 0000
37 regs: 0003; ins: 0001; outs: 0000
44 regs: 0003; ins: 0001; outs: 0000
51 regs: 0003; ins: 0001; outs: 0000
58 regs: 0003; ins: 0001; outs: 0000
|
| /dalvik/dx/tests/073-dex-null-array-refs/ |
| expected.txt | 2 regs: 0002; ins: 0000; outs: 0000
9 regs: 0003; ins: 0000; outs: 0000
17 regs: 0001; ins: 0000; outs: 0000
23 regs: 0003; ins: 0000; outs: 0000
32 regs: 0004; ins: 0000; outs: 0000
41 regs: 0002; ins: 0000; outs: 0000
49 regs: 0004; ins: 0001; outs: 0000
62 regs: 0005; ins: 0001; outs: 0000
75 regs: 0003; ins: 0001; outs: 0000
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.td | 192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
196 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
205 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
208 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
217 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
218 : InstSP<outs, ins, asmstr, pattern>;
222 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
226 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
229 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
236 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | 17 def NOP : NVPTXInst<(outs), (ins), "", []>;
170 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
174 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
177 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
181 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
184 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
188 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
194 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
199 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
205 def f64rr : NVPTXInst<(outs Float64Regs:$dst)
[all...] |
| /external/llvm/utils/yaml-bench/ |
| YAMLBench.cpp | 72 outs() << indent(Indent);
75 outs() << "&" << Anchor << " ";
79 outs() << "!!str \"" << yaml::escape(Val) << "\"";
81 outs() << "!!seq [\n";
86 outs() << ",\n";
89 outs() << indent(Indent) << "]";
91 outs() << "!!map {\n";
95 outs() << indent(Indent) << "? ";
97 outs() << "\n";
98 outs() << indent(Indent) << ": "
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrFormats.td | 26 : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
29 : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
33 : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
36 : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
39 : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
42 : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
45 : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
50 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
73 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
95 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrFormats.td | 26 : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
29 : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
33 : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
36 : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
39 : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
42 : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
45 : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
50 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
73 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
95 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>
[all...] |
| /dalvik/dx/tests/059-dex-call-super/ |
| expected.txt | 2 regs: 0004; ins: 0001; outs: 0002
13 regs: 0003; ins: 0001; outs: 0001
|
| /dalvik/dx/tests/061-dex-try-catch/ |
| expected.txt | 2 regs: 0004; ins: 0001; outs: 0000
8 regs: 0004; ins: 0001; outs: 0000
23 regs: 0002; ins: 0000; outs: 0001
36 regs: 0004; ins: 0001; outs: 0001
|
| /external/llvm/test/TableGen/ |
| Slice.td | 24 def outs;
65 def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
68 def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
74 def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
77 def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
|
