1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the PowerPC-specific support for the FastISel class. Some 11 // of the target-specific code is generated by tablegen in the file 12 // PPCGenFastISel.inc, which is #included here. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "PPC.h" 17 #include "MCTargetDesc/PPCPredicates.h" 18 #include "PPCISelLowering.h" 19 #include "PPCSubtarget.h" 20 #include "PPCTargetMachine.h" 21 #include "llvm/ADT/Optional.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/FastISel.h" 24 #include "llvm/CodeGen/FunctionLoweringInfo.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineFrameInfo.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/GetElementPtrTypeIterator.h" 31 #include "llvm/IR/GlobalAlias.h" 32 #include "llvm/IR/GlobalVariable.h" 33 #include "llvm/IR/IntrinsicInst.h" 34 #include "llvm/IR/Operator.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Target/TargetLowering.h" 37 #include "llvm/Target/TargetMachine.h" 38 39 //===----------------------------------------------------------------------===// 40 // 41 // TBD: 42 // FastLowerArguments: Handle simple cases. 43 // PPCMaterializeGV: Handle TLS. 44 // SelectCall: Handle function pointers. 45 // SelectCall: Handle multi-register return values. 46 // SelectCall: Optimize away nops for local calls. 47 // processCallArgs: Handle bit-converted arguments. 48 // finishCall: Handle multi-register return values. 49 // PPCComputeAddress: Handle parameter references as FrameIndex's. 50 // PPCEmitCmp: Handle immediate as operand 1. 51 // SelectCall: Handle small byval arguments. 52 // SelectIntrinsicCall: Implement. 53 // SelectSelect: Implement. 54 // Consider factoring isTypeLegal into the base class. 55 // Implement switches and jump tables. 56 // 57 //===----------------------------------------------------------------------===// 58 using namespace llvm; 59 60 #define DEBUG_TYPE "ppcfastisel" 61 62 namespace { 63 64 typedef struct Address { 65 enum { 66 RegBase, 67 FrameIndexBase 68 } BaseType; 69 70 union { 71 unsigned Reg; 72 int FI; 73 } Base; 74 75 long Offset; 76 77 // Innocuous defaults for our address. 78 Address() 79 : BaseType(RegBase), Offset(0) { 80 Base.Reg = 0; 81 } 82 } Address; 83 84 class PPCFastISel final : public FastISel { 85 86 const TargetMachine &TM; 87 const TargetInstrInfo &TII; 88 const TargetLowering &TLI; 89 const PPCSubtarget *PPCSubTarget; 90 LLVMContext *Context; 91 92 public: 93 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo, 94 const TargetLibraryInfo *LibInfo) 95 : FastISel(FuncInfo, LibInfo), 96 TM(FuncInfo.MF->getTarget()), 97 TII(*TM.getInstrInfo()), 98 TLI(*TM.getTargetLowering()), 99 PPCSubTarget(&TM.getSubtarget<PPCSubtarget>()), 100 Context(&FuncInfo.Fn->getContext()) { } 101 102 // Backend specific FastISel code. 103 private: 104 bool TargetSelectInstruction(const Instruction *I) override; 105 unsigned TargetMaterializeConstant(const Constant *C) override; 106 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override; 107 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 108 const LoadInst *LI) override; 109 bool FastLowerArguments() override; 110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override; 111 unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 112 const TargetRegisterClass *RC, 113 unsigned Op0, bool Op0IsKill, 114 uint64_t Imm); 115 unsigned FastEmitInst_r(unsigned MachineInstOpcode, 116 const TargetRegisterClass *RC, 117 unsigned Op0, bool Op0IsKill); 118 unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 119 const TargetRegisterClass *RC, 120 unsigned Op0, bool Op0IsKill, 121 unsigned Op1, bool Op1IsKill); 122 123 // Instruction selection routines. 124 private: 125 bool SelectLoad(const Instruction *I); 126 bool SelectStore(const Instruction *I); 127 bool SelectBranch(const Instruction *I); 128 bool SelectIndirectBr(const Instruction *I); 129 bool SelectFPExt(const Instruction *I); 130 bool SelectFPTrunc(const Instruction *I); 131 bool SelectIToFP(const Instruction *I, bool IsSigned); 132 bool SelectFPToI(const Instruction *I, bool IsSigned); 133 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode); 134 bool SelectCall(const Instruction *I); 135 bool SelectRet(const Instruction *I); 136 bool SelectTrunc(const Instruction *I); 137 bool SelectIntExt(const Instruction *I); 138 139 // Utility routines. 140 private: 141 bool isTypeLegal(Type *Ty, MVT &VT); 142 bool isLoadTypeLegal(Type *Ty, MVT &VT); 143 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, 144 bool isZExt, unsigned DestReg); 145 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 146 const TargetRegisterClass *RC, bool IsZExt = true, 147 unsigned FP64LoadOpc = PPC::LFD); 148 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr); 149 bool PPCComputeAddress(const Value *Obj, Address &Addr); 150 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, 151 unsigned &IndexReg); 152 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 153 unsigned DestReg, bool IsZExt); 154 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT); 155 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT); 156 unsigned PPCMaterializeInt(const Constant *C, MVT VT); 157 unsigned PPCMaterialize32BitInt(int64_t Imm, 158 const TargetRegisterClass *RC); 159 unsigned PPCMaterialize64BitInt(int64_t Imm, 160 const TargetRegisterClass *RC); 161 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT, 162 unsigned SrcReg, bool IsSigned); 163 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned); 164 165 // Call handling routines. 166 private: 167 bool processCallArgs(SmallVectorImpl<Value*> &Args, 168 SmallVectorImpl<unsigned> &ArgRegs, 169 SmallVectorImpl<MVT> &ArgVTs, 170 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 171 SmallVectorImpl<unsigned> &RegArgs, 172 CallingConv::ID CC, 173 unsigned &NumBytes, 174 bool IsVarArg); 175 void finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 176 const Instruction *I, CallingConv::ID CC, 177 unsigned &NumBytes, bool IsVarArg); 178 CCAssignFn *usePPC32CCs(unsigned Flag); 179 180 private: 181 #include "PPCGenFastISel.inc" 182 183 }; 184 185 } // end anonymous namespace 186 187 #include "PPCGenCallingConv.inc" 188 189 // Function whose sole purpose is to kill compiler warnings 190 // stemming from unused functions included from PPCGenCallingConv.inc. 191 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) { 192 if (Flag == 1) 193 return CC_PPC32_SVR4; 194 else if (Flag == 2) 195 return CC_PPC32_SVR4_ByVal; 196 else if (Flag == 3) 197 return CC_PPC32_SVR4_VarArg; 198 else 199 return RetCC_PPC; 200 } 201 202 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { 203 switch (Pred) { 204 // These are not representable with any single compare. 205 case CmpInst::FCMP_FALSE: 206 case CmpInst::FCMP_UEQ: 207 case CmpInst::FCMP_UGT: 208 case CmpInst::FCMP_UGE: 209 case CmpInst::FCMP_ULT: 210 case CmpInst::FCMP_ULE: 211 case CmpInst::FCMP_UNE: 212 case CmpInst::FCMP_TRUE: 213 default: 214 return Optional<PPC::Predicate>(); 215 216 case CmpInst::FCMP_OEQ: 217 case CmpInst::ICMP_EQ: 218 return PPC::PRED_EQ; 219 220 case CmpInst::FCMP_OGT: 221 case CmpInst::ICMP_UGT: 222 case CmpInst::ICMP_SGT: 223 return PPC::PRED_GT; 224 225 case CmpInst::FCMP_OGE: 226 case CmpInst::ICMP_UGE: 227 case CmpInst::ICMP_SGE: 228 return PPC::PRED_GE; 229 230 case CmpInst::FCMP_OLT: 231 case CmpInst::ICMP_ULT: 232 case CmpInst::ICMP_SLT: 233 return PPC::PRED_LT; 234 235 case CmpInst::FCMP_OLE: 236 case CmpInst::ICMP_ULE: 237 case CmpInst::ICMP_SLE: 238 return PPC::PRED_LE; 239 240 case CmpInst::FCMP_ONE: 241 case CmpInst::ICMP_NE: 242 return PPC::PRED_NE; 243 244 case CmpInst::FCMP_ORD: 245 return PPC::PRED_NU; 246 247 case CmpInst::FCMP_UNO: 248 return PPC::PRED_UN; 249 } 250 } 251 252 // Determine whether the type Ty is simple enough to be handled by 253 // fast-isel, and return its equivalent machine type in VT. 254 // FIXME: Copied directly from ARM -- factor into base class? 255 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { 256 EVT Evt = TLI.getValueType(Ty, true); 257 258 // Only handle simple types. 259 if (Evt == MVT::Other || !Evt.isSimple()) return false; 260 VT = Evt.getSimpleVT(); 261 262 // Handle all legal types, i.e. a register that will directly hold this 263 // value. 264 return TLI.isTypeLegal(VT); 265 } 266 267 // Determine whether the type Ty is simple enough to be handled by 268 // fast-isel as a load target, and return its equivalent machine type in VT. 269 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { 270 if (isTypeLegal(Ty, VT)) return true; 271 272 // If this is a type than can be sign or zero-extended to a basic operation 273 // go ahead and accept it now. 274 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { 275 return true; 276 } 277 278 return false; 279 } 280 281 // Given a value Obj, create an Address object Addr that represents its 282 // address. Return false if we can't handle it. 283 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) { 284 const User *U = nullptr; 285 unsigned Opcode = Instruction::UserOp1; 286 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 287 // Don't walk into other basic blocks unless the object is an alloca from 288 // another block, otherwise it may not have a virtual register assigned. 289 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) || 290 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 291 Opcode = I->getOpcode(); 292 U = I; 293 } 294 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 295 Opcode = C->getOpcode(); 296 U = C; 297 } 298 299 switch (Opcode) { 300 default: 301 break; 302 case Instruction::BitCast: 303 // Look through bitcasts. 304 return PPCComputeAddress(U->getOperand(0), Addr); 305 case Instruction::IntToPtr: 306 // Look past no-op inttoptrs. 307 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 308 return PPCComputeAddress(U->getOperand(0), Addr); 309 break; 310 case Instruction::PtrToInt: 311 // Look past no-op ptrtoints. 312 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 313 return PPCComputeAddress(U->getOperand(0), Addr); 314 break; 315 case Instruction::GetElementPtr: { 316 Address SavedAddr = Addr; 317 long TmpOffset = Addr.Offset; 318 319 // Iterate through the GEP folding the constants into offsets where 320 // we can. 321 gep_type_iterator GTI = gep_type_begin(U); 322 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end(); 323 II != IE; ++II, ++GTI) { 324 const Value *Op = *II; 325 if (StructType *STy = dyn_cast<StructType>(*GTI)) { 326 const StructLayout *SL = DL.getStructLayout(STy); 327 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 328 TmpOffset += SL->getElementOffset(Idx); 329 } else { 330 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType()); 331 for (;;) { 332 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 333 // Constant-offset addressing. 334 TmpOffset += CI->getSExtValue() * S; 335 break; 336 } 337 if (canFoldAddIntoGEP(U, Op)) { 338 // A compatible add with a constant operand. Fold the constant. 339 ConstantInt *CI = 340 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 341 TmpOffset += CI->getSExtValue() * S; 342 // Iterate on the other operand. 343 Op = cast<AddOperator>(Op)->getOperand(0); 344 continue; 345 } 346 // Unsupported 347 goto unsupported_gep; 348 } 349 } 350 } 351 352 // Try to grab the base operand now. 353 Addr.Offset = TmpOffset; 354 if (PPCComputeAddress(U->getOperand(0), Addr)) return true; 355 356 // We failed, restore everything and try the other options. 357 Addr = SavedAddr; 358 359 unsupported_gep: 360 break; 361 } 362 case Instruction::Alloca: { 363 const AllocaInst *AI = cast<AllocaInst>(Obj); 364 DenseMap<const AllocaInst*, int>::iterator SI = 365 FuncInfo.StaticAllocaMap.find(AI); 366 if (SI != FuncInfo.StaticAllocaMap.end()) { 367 Addr.BaseType = Address::FrameIndexBase; 368 Addr.Base.FI = SI->second; 369 return true; 370 } 371 break; 372 } 373 } 374 375 // FIXME: References to parameters fall through to the behavior 376 // below. They should be able to reference a frame index since 377 // they are stored to the stack, so we can get "ld rx, offset(r1)" 378 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will 379 // just contain the parameter. Try to handle this with a FI. 380 381 // Try to get this in a register if nothing else has worked. 382 if (Addr.Base.Reg == 0) 383 Addr.Base.Reg = getRegForValue(Obj); 384 385 // Prevent assignment of base register to X0, which is inappropriate 386 // for loads and stores alike. 387 if (Addr.Base.Reg != 0) 388 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); 389 390 return Addr.Base.Reg != 0; 391 } 392 393 // Fix up some addresses that can't be used directly. For example, if 394 // an offset won't fit in an instruction field, we may need to move it 395 // into an index register. 396 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, 397 unsigned &IndexReg) { 398 399 // Check whether the offset fits in the instruction field. 400 if (!isInt<16>(Addr.Offset)) 401 UseOffset = false; 402 403 // If this is a stack pointer and the offset needs to be simplified then 404 // put the alloca address into a register, set the base type back to 405 // register and continue. This should almost never happen. 406 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) { 407 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8), 409 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); 410 Addr.Base.Reg = ResultReg; 411 Addr.BaseType = Address::RegBase; 412 } 413 414 if (!UseOffset) { 415 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context) 416 : Type::getInt64Ty(*Context)); 417 const ConstantInt *Offset = 418 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset)); 419 IndexReg = PPCMaterializeInt(Offset, MVT::i64); 420 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); 421 } 422 } 423 424 // Emit a load instruction if possible, returning true if we succeeded, 425 // otherwise false. See commentary below for how the register class of 426 // the load is determined. 427 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 428 const TargetRegisterClass *RC, 429 bool IsZExt, unsigned FP64LoadOpc) { 430 unsigned Opc; 431 bool UseOffset = true; 432 433 // If ResultReg is given, it determines the register class of the load. 434 // Otherwise, RC is the register class to use. If the result of the 435 // load isn't anticipated in this block, both may be zero, in which 436 // case we must make a conservative guess. In particular, don't assign 437 // R0 or X0 to the result register, as the result may be used in a load, 438 // store, add-immediate, or isel that won't permit this. (Though 439 // perhaps the spill and reload of live-exit values would handle this?) 440 const TargetRegisterClass *UseRC = 441 (ResultReg ? MRI.getRegClass(ResultReg) : 442 (RC ? RC : 443 (VT == MVT::f64 ? &PPC::F8RCRegClass : 444 (VT == MVT::f32 ? &PPC::F4RCRegClass : 445 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : 446 &PPC::GPRC_and_GPRC_NOR0RegClass))))); 447 448 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); 449 450 switch (VT.SimpleTy) { 451 default: // e.g., vector types not handled 452 return false; 453 case MVT::i8: 454 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; 455 break; 456 case MVT::i16: 457 Opc = (IsZExt ? 458 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) : 459 (Is32BitInt ? PPC::LHA : PPC::LHA8)); 460 break; 461 case MVT::i32: 462 Opc = (IsZExt ? 463 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) : 464 (Is32BitInt ? PPC::LWA_32 : PPC::LWA)); 465 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) 466 UseOffset = false; 467 break; 468 case MVT::i64: 469 Opc = PPC::LD; 470 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && 471 "64-bit load with 32-bit target??"); 472 UseOffset = ((Addr.Offset & 3) == 0); 473 break; 474 case MVT::f32: 475 Opc = PPC::LFS; 476 break; 477 case MVT::f64: 478 Opc = FP64LoadOpc; 479 break; 480 } 481 482 // If necessary, materialize the offset into a register and use 483 // the indexed form. Also handle stack pointers with special needs. 484 unsigned IndexReg = 0; 485 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); 486 if (ResultReg == 0) 487 ResultReg = createResultReg(UseRC); 488 489 // Note: If we still have a frame index here, we know the offset is 490 // in range, as otherwise PPCSimplifyAddress would have converted it 491 // into a RegBase. 492 if (Addr.BaseType == Address::FrameIndexBase) { 493 494 MachineMemOperand *MMO = 495 FuncInfo.MF->getMachineMemOperand( 496 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset), 497 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI), 498 MFI.getObjectAlignment(Addr.Base.FI)); 499 500 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 501 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO); 502 503 // Base reg with offset in range. 504 } else if (UseOffset) { 505 506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 507 .addImm(Addr.Offset).addReg(Addr.Base.Reg); 508 509 // Indexed form. 510 } else { 511 // Get the RR opcode corresponding to the RI one. FIXME: It would be 512 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it 513 // is hard to get at. 514 switch (Opc) { 515 default: llvm_unreachable("Unexpected opcode!"); 516 case PPC::LBZ: Opc = PPC::LBZX; break; 517 case PPC::LBZ8: Opc = PPC::LBZX8; break; 518 case PPC::LHZ: Opc = PPC::LHZX; break; 519 case PPC::LHZ8: Opc = PPC::LHZX8; break; 520 case PPC::LHA: Opc = PPC::LHAX; break; 521 case PPC::LHA8: Opc = PPC::LHAX8; break; 522 case PPC::LWZ: Opc = PPC::LWZX; break; 523 case PPC::LWZ8: Opc = PPC::LWZX8; break; 524 case PPC::LWA: Opc = PPC::LWAX; break; 525 case PPC::LWA_32: Opc = PPC::LWAX_32; break; 526 case PPC::LD: Opc = PPC::LDX; break; 527 case PPC::LFS: Opc = PPC::LFSX; break; 528 case PPC::LFD: Opc = PPC::LFDX; break; 529 } 530 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 531 .addReg(Addr.Base.Reg).addReg(IndexReg); 532 } 533 534 return true; 535 } 536 537 // Attempt to fast-select a load instruction. 538 bool PPCFastISel::SelectLoad(const Instruction *I) { 539 // FIXME: No atomic loads are supported. 540 if (cast<LoadInst>(I)->isAtomic()) 541 return false; 542 543 // Verify we have a legal type before going any further. 544 MVT VT; 545 if (!isLoadTypeLegal(I->getType(), VT)) 546 return false; 547 548 // See if we can handle this address. 549 Address Addr; 550 if (!PPCComputeAddress(I->getOperand(0), Addr)) 551 return false; 552 553 // Look at the currently assigned register for this instruction 554 // to determine the required register class. This is necessary 555 // to constrain RA from using R0/X0 when this is not legal. 556 unsigned AssignedReg = FuncInfo.ValueMap[I]; 557 const TargetRegisterClass *RC = 558 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; 559 560 unsigned ResultReg = 0; 561 if (!PPCEmitLoad(VT, ResultReg, Addr, RC)) 562 return false; 563 UpdateValueMap(I, ResultReg); 564 return true; 565 } 566 567 // Emit a store instruction to store SrcReg at Addr. 568 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { 569 assert(SrcReg && "Nothing to store!"); 570 unsigned Opc; 571 bool UseOffset = true; 572 573 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); 574 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); 575 576 switch (VT.SimpleTy) { 577 default: // e.g., vector types not handled 578 return false; 579 case MVT::i8: 580 Opc = Is32BitInt ? PPC::STB : PPC::STB8; 581 break; 582 case MVT::i16: 583 Opc = Is32BitInt ? PPC::STH : PPC::STH8; 584 break; 585 case MVT::i32: 586 assert(Is32BitInt && "Not GPRC for i32??"); 587 Opc = PPC::STW; 588 break; 589 case MVT::i64: 590 Opc = PPC::STD; 591 UseOffset = ((Addr.Offset & 3) == 0); 592 break; 593 case MVT::f32: 594 Opc = PPC::STFS; 595 break; 596 case MVT::f64: 597 Opc = PPC::STFD; 598 break; 599 } 600 601 // If necessary, materialize the offset into a register and use 602 // the indexed form. Also handle stack pointers with special needs. 603 unsigned IndexReg = 0; 604 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); 605 606 // Note: If we still have a frame index here, we know the offset is 607 // in range, as otherwise PPCSimplifyAddress would have converted it 608 // into a RegBase. 609 if (Addr.BaseType == Address::FrameIndexBase) { 610 MachineMemOperand *MMO = 611 FuncInfo.MF->getMachineMemOperand( 612 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset), 613 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI), 614 MFI.getObjectAlignment(Addr.Base.FI)); 615 616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) 617 .addReg(SrcReg) 618 .addImm(Addr.Offset) 619 .addFrameIndex(Addr.Base.FI) 620 .addMemOperand(MMO); 621 622 // Base reg with offset in range. 623 } else if (UseOffset) 624 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) 625 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg); 626 627 // Indexed form. 628 else { 629 // Get the RR opcode corresponding to the RI one. FIXME: It would be 630 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it 631 // is hard to get at. 632 switch (Opc) { 633 default: llvm_unreachable("Unexpected opcode!"); 634 case PPC::STB: Opc = PPC::STBX; break; 635 case PPC::STH : Opc = PPC::STHX; break; 636 case PPC::STW : Opc = PPC::STWX; break; 637 case PPC::STB8: Opc = PPC::STBX8; break; 638 case PPC::STH8: Opc = PPC::STHX8; break; 639 case PPC::STW8: Opc = PPC::STWX8; break; 640 case PPC::STD: Opc = PPC::STDX; break; 641 case PPC::STFS: Opc = PPC::STFSX; break; 642 case PPC::STFD: Opc = PPC::STFDX; break; 643 } 644 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) 645 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg); 646 } 647 648 return true; 649 } 650 651 // Attempt to fast-select a store instruction. 652 bool PPCFastISel::SelectStore(const Instruction *I) { 653 Value *Op0 = I->getOperand(0); 654 unsigned SrcReg = 0; 655 656 // FIXME: No atomics loads are supported. 657 if (cast<StoreInst>(I)->isAtomic()) 658 return false; 659 660 // Verify we have a legal type before going any further. 661 MVT VT; 662 if (!isLoadTypeLegal(Op0->getType(), VT)) 663 return false; 664 665 // Get the value to be stored into a register. 666 SrcReg = getRegForValue(Op0); 667 if (SrcReg == 0) 668 return false; 669 670 // See if we can handle this address. 671 Address Addr; 672 if (!PPCComputeAddress(I->getOperand(1), Addr)) 673 return false; 674 675 if (!PPCEmitStore(VT, SrcReg, Addr)) 676 return false; 677 678 return true; 679 } 680 681 // Attempt to fast-select a branch instruction. 682 bool PPCFastISel::SelectBranch(const Instruction *I) { 683 const BranchInst *BI = cast<BranchInst>(I); 684 MachineBasicBlock *BrBB = FuncInfo.MBB; 685 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 686 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 687 688 // For now, just try the simplest case where it's fed by a compare. 689 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 690 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate()); 691 if (!OptPPCPred) 692 return false; 693 694 PPC::Predicate PPCPred = OptPPCPred.getValue(); 695 696 // Take advantage of fall-through opportunities. 697 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 698 std::swap(TBB, FBB); 699 PPCPred = PPC::InvertPredicate(PPCPred); 700 } 701 702 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); 703 704 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), 705 CondReg)) 706 return false; 707 708 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC)) 709 .addImm(PPCPred).addReg(CondReg).addMBB(TBB); 710 FastEmitBranch(FBB, DbgLoc); 711 FuncInfo.MBB->addSuccessor(TBB); 712 return true; 713 714 } else if (const ConstantInt *CI = 715 dyn_cast<ConstantInt>(BI->getCondition())) { 716 uint64_t Imm = CI->getZExtValue(); 717 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; 718 FastEmitBranch(Target, DbgLoc); 719 return true; 720 } 721 722 // FIXME: ARM looks for a case where the block containing the compare 723 // has been split from the block containing the branch. If this happens, 724 // there is a vreg available containing the result of the compare. I'm 725 // not sure we can do much, as we've lost the predicate information with 726 // the compare instruction -- we have a 4-bit CR but don't know which bit 727 // to test here. 728 return false; 729 } 730 731 // Attempt to emit a compare of the two source values. Signed and unsigned 732 // comparisons are supported. Return false if we can't handle it. 733 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2, 734 bool IsZExt, unsigned DestReg) { 735 Type *Ty = SrcValue1->getType(); 736 EVT SrcEVT = TLI.getValueType(Ty, true); 737 if (!SrcEVT.isSimple()) 738 return false; 739 MVT SrcVT = SrcEVT.getSimpleVT(); 740 741 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) 742 return false; 743 744 // See if operand 2 is an immediate encodeable in the compare. 745 // FIXME: Operands are not in canonical order at -O0, so an immediate 746 // operand in position 1 is a lost opportunity for now. We are 747 // similar to ARM in this regard. 748 long Imm = 0; 749 bool UseImm = false; 750 751 // Only 16-bit integer constants can be represented in compares for 752 // PowerPC. Others will be materialized into a register. 753 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) { 754 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 755 SrcVT == MVT::i8 || SrcVT == MVT::i1) { 756 const APInt &CIVal = ConstInt->getValue(); 757 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); 758 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) 759 UseImm = true; 760 } 761 } 762 763 unsigned CmpOpc; 764 bool NeedsExt = false; 765 switch (SrcVT.SimpleTy) { 766 default: return false; 767 case MVT::f32: 768 CmpOpc = PPC::FCMPUS; 769 break; 770 case MVT::f64: 771 CmpOpc = PPC::FCMPUD; 772 break; 773 case MVT::i1: 774 case MVT::i8: 775 case MVT::i16: 776 NeedsExt = true; 777 // Intentional fall-through. 778 case MVT::i32: 779 if (!UseImm) 780 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; 781 else 782 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; 783 break; 784 case MVT::i64: 785 if (!UseImm) 786 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; 787 else 788 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; 789 break; 790 } 791 792 unsigned SrcReg1 = getRegForValue(SrcValue1); 793 if (SrcReg1 == 0) 794 return false; 795 796 unsigned SrcReg2 = 0; 797 if (!UseImm) { 798 SrcReg2 = getRegForValue(SrcValue2); 799 if (SrcReg2 == 0) 800 return false; 801 } 802 803 if (NeedsExt) { 804 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); 805 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) 806 return false; 807 SrcReg1 = ExtReg; 808 809 if (!UseImm) { 810 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); 811 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) 812 return false; 813 SrcReg2 = ExtReg; 814 } 815 } 816 817 if (!UseImm) 818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) 819 .addReg(SrcReg1).addReg(SrcReg2); 820 else 821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) 822 .addReg(SrcReg1).addImm(Imm); 823 824 return true; 825 } 826 827 // Attempt to fast-select a floating-point extend instruction. 828 bool PPCFastISel::SelectFPExt(const Instruction *I) { 829 Value *Src = I->getOperand(0); 830 EVT SrcVT = TLI.getValueType(Src->getType(), true); 831 EVT DestVT = TLI.getValueType(I->getType(), true); 832 833 if (SrcVT != MVT::f32 || DestVT != MVT::f64) 834 return false; 835 836 unsigned SrcReg = getRegForValue(Src); 837 if (!SrcReg) 838 return false; 839 840 // No code is generated for a FP extend. 841 UpdateValueMap(I, SrcReg); 842 return true; 843 } 844 845 // Attempt to fast-select a floating-point truncate instruction. 846 bool PPCFastISel::SelectFPTrunc(const Instruction *I) { 847 Value *Src = I->getOperand(0); 848 EVT SrcVT = TLI.getValueType(Src->getType(), true); 849 EVT DestVT = TLI.getValueType(I->getType(), true); 850 851 if (SrcVT != MVT::f64 || DestVT != MVT::f32) 852 return false; 853 854 unsigned SrcReg = getRegForValue(Src); 855 if (!SrcReg) 856 return false; 857 858 // Round the result to single precision. 859 unsigned DestReg = createResultReg(&PPC::F4RCRegClass); 860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg) 861 .addReg(SrcReg); 862 863 UpdateValueMap(I, DestReg); 864 return true; 865 } 866 867 // Move an i32 or i64 value in a GPR to an f64 value in an FPR. 868 // FIXME: When direct register moves are implemented (see PowerISA 2.08), 869 // those should be used instead of moving via a stack slot when the 870 // subtarget permits. 871 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte 872 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte 873 // case to 8 bytes which produces tighter code but wastes stack space. 874 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, 875 bool IsSigned) { 876 877 // If necessary, extend 32-bit int to 64-bit. 878 if (SrcVT == MVT::i32) { 879 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); 880 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) 881 return 0; 882 SrcReg = TmpReg; 883 } 884 885 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary. 886 Address Addr; 887 Addr.BaseType = Address::FrameIndexBase; 888 Addr.Base.FI = MFI.CreateStackObject(8, 8, false); 889 890 // Store the value from the GPR. 891 if (!PPCEmitStore(MVT::i64, SrcReg, Addr)) 892 return 0; 893 894 // Load the integer value into an FPR. The kind of load used depends 895 // on a number of conditions. 896 unsigned LoadOpc = PPC::LFD; 897 898 if (SrcVT == MVT::i32) { 899 if (!IsSigned) { 900 LoadOpc = PPC::LFIWZX; 901 Addr.Offset = 4; 902 } else if (PPCSubTarget->hasLFIWAX()) { 903 LoadOpc = PPC::LFIWAX; 904 Addr.Offset = 4; 905 } 906 } 907 908 const TargetRegisterClass *RC = &PPC::F8RCRegClass; 909 unsigned ResultReg = 0; 910 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc)) 911 return 0; 912 913 return ResultReg; 914 } 915 916 // Attempt to fast-select an integer-to-floating-point conversion. 917 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) { 918 MVT DstVT; 919 Type *DstTy = I->getType(); 920 if (!isTypeLegal(DstTy, DstVT)) 921 return false; 922 923 if (DstVT != MVT::f32 && DstVT != MVT::f64) 924 return false; 925 926 Value *Src = I->getOperand(0); 927 EVT SrcEVT = TLI.getValueType(Src->getType(), true); 928 if (!SrcEVT.isSimple()) 929 return false; 930 931 MVT SrcVT = SrcEVT.getSimpleVT(); 932 933 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && 934 SrcVT != MVT::i32 && SrcVT != MVT::i64) 935 return false; 936 937 unsigned SrcReg = getRegForValue(Src); 938 if (SrcReg == 0) 939 return false; 940 941 // We can only lower an unsigned convert if we have the newer 942 // floating-point conversion operations. 943 if (!IsSigned && !PPCSubTarget->hasFPCVT()) 944 return false; 945 946 // FIXME: For now we require the newer floating-point conversion operations 947 // (which are present only on P7 and A2 server models) when converting 948 // to single-precision float. Otherwise we have to generate a lot of 949 // fiddly code to avoid double rounding. If necessary, the fiddly code 950 // can be found in PPCTargetLowering::LowerINT_TO_FP(). 951 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) 952 return false; 953 954 // Extend the input if necessary. 955 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { 956 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); 957 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) 958 return false; 959 SrcVT = MVT::i64; 960 SrcReg = TmpReg; 961 } 962 963 // Move the integer value to an FPR. 964 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned); 965 if (FPReg == 0) 966 return false; 967 968 // Determine the opcode for the conversion. 969 const TargetRegisterClass *RC = &PPC::F8RCRegClass; 970 unsigned DestReg = createResultReg(RC); 971 unsigned Opc; 972 973 if (DstVT == MVT::f32) 974 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS; 975 else 976 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU; 977 978 // Generate the convert. 979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 980 .addReg(FPReg); 981 982 UpdateValueMap(I, DestReg); 983 return true; 984 } 985 986 // Move the floating-point value in SrcReg into an integer destination 987 // register, and return the register (or zero if we can't handle it). 988 // FIXME: When direct register moves are implemented (see PowerISA 2.08), 989 // those should be used instead of moving via a stack slot when the 990 // subtarget permits. 991 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, 992 unsigned SrcReg, bool IsSigned) { 993 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary. 994 // Note that if have STFIWX available, we could use a 4-byte stack 995 // slot for i32, but this being fast-isel we'll just go with the 996 // easiest code gen possible. 997 Address Addr; 998 Addr.BaseType = Address::FrameIndexBase; 999 Addr.Base.FI = MFI.CreateStackObject(8, 8, false); 1000 1001 // Store the value from the FPR. 1002 if (!PPCEmitStore(MVT::f64, SrcReg, Addr)) 1003 return 0; 1004 1005 // Reload it into a GPR. If we want an i32, modify the address 1006 // to have a 4-byte offset so we load from the right place. 1007 if (VT == MVT::i32) 1008 Addr.Offset = 4; 1009 1010 // Look at the currently assigned register for this instruction 1011 // to determine the required register class. 1012 unsigned AssignedReg = FuncInfo.ValueMap[I]; 1013 const TargetRegisterClass *RC = 1014 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; 1015 1016 unsigned ResultReg = 0; 1017 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned)) 1018 return 0; 1019 1020 return ResultReg; 1021 } 1022 1023 // Attempt to fast-select a floating-point-to-integer conversion. 1024 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) { 1025 MVT DstVT, SrcVT; 1026 Type *DstTy = I->getType(); 1027 if (!isTypeLegal(DstTy, DstVT)) 1028 return false; 1029 1030 if (DstVT != MVT::i32 && DstVT != MVT::i64) 1031 return false; 1032 1033 // If we don't have FCTIDUZ and we need it, punt to SelectionDAG. 1034 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT()) 1035 return false; 1036 1037 Value *Src = I->getOperand(0); 1038 Type *SrcTy = Src->getType(); 1039 if (!isTypeLegal(SrcTy, SrcVT)) 1040 return false; 1041 1042 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) 1043 return false; 1044 1045 unsigned SrcReg = getRegForValue(Src); 1046 if (SrcReg == 0) 1047 return false; 1048 1049 // Convert f32 to f64 if necessary. This is just a meaningless copy 1050 // to get the register class right. COPY_TO_REGCLASS is needed since 1051 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream. 1052 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg); 1053 if (InRC == &PPC::F4RCRegClass) { 1054 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); 1055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1056 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg) 1057 .addReg(SrcReg).addImm(PPC::F8RCRegClassID); 1058 SrcReg = TmpReg; 1059 } 1060 1061 // Determine the opcode for the conversion, which takes place 1062 // entirely within FPRs. 1063 unsigned DestReg = createResultReg(&PPC::F8RCRegClass); 1064 unsigned Opc; 1065 1066 if (DstVT == MVT::i32) 1067 if (IsSigned) 1068 Opc = PPC::FCTIWZ; 1069 else 1070 Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ; 1071 else 1072 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ; 1073 1074 // Generate the convert. 1075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 1076 .addReg(SrcReg); 1077 1078 // Now move the integer value from a float register to an integer register. 1079 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned); 1080 if (IntReg == 0) 1081 return false; 1082 1083 UpdateValueMap(I, IntReg); 1084 return true; 1085 } 1086 1087 // Attempt to fast-select a binary integer operation that isn't already 1088 // handled automatically. 1089 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { 1090 EVT DestVT = TLI.getValueType(I->getType(), true); 1091 1092 // We can get here in the case when we have a binary operation on a non-legal 1093 // type and the target independent selector doesn't know how to handle it. 1094 if (DestVT != MVT::i16 && DestVT != MVT::i8) 1095 return false; 1096 1097 // Look at the currently assigned register for this instruction 1098 // to determine the required register class. If there is no register, 1099 // make a conservative choice (don't assign R0). 1100 unsigned AssignedReg = FuncInfo.ValueMap[I]; 1101 const TargetRegisterClass *RC = 1102 (AssignedReg ? MRI.getRegClass(AssignedReg) : 1103 &PPC::GPRC_and_GPRC_NOR0RegClass); 1104 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); 1105 1106 unsigned Opc; 1107 switch (ISDOpcode) { 1108 default: return false; 1109 case ISD::ADD: 1110 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8; 1111 break; 1112 case ISD::OR: 1113 Opc = IsGPRC ? PPC::OR : PPC::OR8; 1114 break; 1115 case ISD::SUB: 1116 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8; 1117 break; 1118 } 1119 1120 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); 1121 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); 1122 if (SrcReg1 == 0) return false; 1123 1124 // Handle case of small immediate operand. 1125 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) { 1126 const APInt &CIVal = ConstInt->getValue(); 1127 int Imm = (int)CIVal.getSExtValue(); 1128 bool UseImm = true; 1129 if (isInt<16>(Imm)) { 1130 switch (Opc) { 1131 default: 1132 llvm_unreachable("Missing case!"); 1133 case PPC::ADD4: 1134 Opc = PPC::ADDI; 1135 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1136 break; 1137 case PPC::ADD8: 1138 Opc = PPC::ADDI8; 1139 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); 1140 break; 1141 case PPC::OR: 1142 Opc = PPC::ORI; 1143 break; 1144 case PPC::OR8: 1145 Opc = PPC::ORI8; 1146 break; 1147 case PPC::SUBF: 1148 if (Imm == -32768) 1149 UseImm = false; 1150 else { 1151 Opc = PPC::ADDI; 1152 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1153 Imm = -Imm; 1154 } 1155 break; 1156 case PPC::SUBF8: 1157 if (Imm == -32768) 1158 UseImm = false; 1159 else { 1160 Opc = PPC::ADDI8; 1161 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); 1162 Imm = -Imm; 1163 } 1164 break; 1165 } 1166 1167 if (UseImm) { 1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), 1169 ResultReg) 1170 .addReg(SrcReg1) 1171 .addImm(Imm); 1172 UpdateValueMap(I, ResultReg); 1173 return true; 1174 } 1175 } 1176 } 1177 1178 // Reg-reg case. 1179 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); 1180 if (SrcReg2 == 0) return false; 1181 1182 // Reverse operands for subtract-from. 1183 if (ISDOpcode == ISD::SUB) 1184 std::swap(SrcReg1, SrcReg2); 1185 1186 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) 1187 .addReg(SrcReg1).addReg(SrcReg2); 1188 UpdateValueMap(I, ResultReg); 1189 return true; 1190 } 1191 1192 // Handle arguments to a call that we're attempting to fast-select. 1193 // Return false if the arguments are too complex for us at the moment. 1194 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args, 1195 SmallVectorImpl<unsigned> &ArgRegs, 1196 SmallVectorImpl<MVT> &ArgVTs, 1197 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 1198 SmallVectorImpl<unsigned> &RegArgs, 1199 CallingConv::ID CC, 1200 unsigned &NumBytes, 1201 bool IsVarArg) { 1202 SmallVector<CCValAssign, 16> ArgLocs; 1203 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context); 1204 1205 // Reserve space for the linkage area on the stack. 1206 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false); 1207 CCInfo.AllocateStack(LinkageSize, 8); 1208 1209 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS); 1210 1211 // Bail out if we can't handle any of the arguments. 1212 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 1213 CCValAssign &VA = ArgLocs[I]; 1214 MVT ArgVT = ArgVTs[VA.getValNo()]; 1215 1216 // Skip vector arguments for now, as well as long double and 1217 // uint128_t, and anything that isn't passed in a register. 1218 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 || 1219 !VA.isRegLoc() || VA.needsCustom()) 1220 return false; 1221 1222 // Skip bit-converted arguments for now. 1223 if (VA.getLocInfo() == CCValAssign::BCvt) 1224 return false; 1225 } 1226 1227 // Get a count of how many bytes are to be pushed onto the stack. 1228 NumBytes = CCInfo.getNextStackOffset(); 1229 1230 // The prolog code of the callee may store up to 8 GPR argument registers to 1231 // the stack, allowing va_start to index over them in memory if its varargs. 1232 // Because we cannot tell if this is needed on the caller side, we have to 1233 // conservatively assume that it is needed. As such, make sure we have at 1234 // least enough stack space for the caller to store the 8 GPRs. 1235 NumBytes = std::max(NumBytes, LinkageSize + 64); 1236 1237 // Issue CALLSEQ_START. 1238 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1239 TII.get(TII.getCallFrameSetupOpcode())) 1240 .addImm(NumBytes); 1241 1242 // Prepare to assign register arguments. Every argument uses up a 1243 // GPR protocol register even if it's passed in a floating-point 1244 // register. 1245 unsigned NextGPR = PPC::X3; 1246 unsigned NextFPR = PPC::F1; 1247 1248 // Process arguments. 1249 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 1250 CCValAssign &VA = ArgLocs[I]; 1251 unsigned Arg = ArgRegs[VA.getValNo()]; 1252 MVT ArgVT = ArgVTs[VA.getValNo()]; 1253 1254 // Handle argument promotion and bitcasts. 1255 switch (VA.getLocInfo()) { 1256 default: 1257 llvm_unreachable("Unknown loc info!"); 1258 case CCValAssign::Full: 1259 break; 1260 case CCValAssign::SExt: { 1261 MVT DestVT = VA.getLocVT(); 1262 const TargetRegisterClass *RC = 1263 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1264 unsigned TmpReg = createResultReg(RC); 1265 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) 1266 llvm_unreachable("Failed to emit a sext!"); 1267 ArgVT = DestVT; 1268 Arg = TmpReg; 1269 break; 1270 } 1271 case CCValAssign::AExt: 1272 case CCValAssign::ZExt: { 1273 MVT DestVT = VA.getLocVT(); 1274 const TargetRegisterClass *RC = 1275 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1276 unsigned TmpReg = createResultReg(RC); 1277 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true)) 1278 llvm_unreachable("Failed to emit a zext!"); 1279 ArgVT = DestVT; 1280 Arg = TmpReg; 1281 break; 1282 } 1283 case CCValAssign::BCvt: { 1284 // FIXME: Not yet handled. 1285 llvm_unreachable("Should have bailed before getting here!"); 1286 break; 1287 } 1288 } 1289 1290 // Copy this argument to the appropriate register. 1291 unsigned ArgReg; 1292 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) { 1293 ArgReg = NextFPR++; 1294 ++NextGPR; 1295 } else 1296 ArgReg = NextGPR++; 1297 1298 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1299 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg); 1300 RegArgs.push_back(ArgReg); 1301 } 1302 1303 return true; 1304 } 1305 1306 // For a call that we've determined we can fast-select, finish the 1307 // call sequence and generate a copy to obtain the return value (if any). 1308 void PPCFastISel::finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 1309 const Instruction *I, CallingConv::ID CC, 1310 unsigned &NumBytes, bool IsVarArg) { 1311 // Issue CallSEQ_END. 1312 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1313 TII.get(TII.getCallFrameDestroyOpcode())) 1314 .addImm(NumBytes).addImm(0); 1315 1316 // Next, generate a copy to obtain the return value. 1317 // FIXME: No multi-register return values yet, though I don't foresee 1318 // any real difficulties there. 1319 if (RetVT != MVT::isVoid) { 1320 SmallVector<CCValAssign, 16> RVLocs; 1321 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 1322 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS); 1323 CCValAssign &VA = RVLocs[0]; 1324 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); 1325 assert(VA.isRegLoc() && "Can only return in registers!"); 1326 1327 MVT DestVT = VA.getValVT(); 1328 MVT CopyVT = DestVT; 1329 1330 // Ints smaller than a register still arrive in a full 64-bit 1331 // register, so make sure we recognize this. 1332 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) 1333 CopyVT = MVT::i64; 1334 1335 unsigned SourcePhysReg = VA.getLocReg(); 1336 unsigned ResultReg = 0; 1337 1338 if (RetVT == CopyVT) { 1339 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); 1340 ResultReg = createResultReg(CpyRC); 1341 1342 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1343 TII.get(TargetOpcode::COPY), ResultReg) 1344 .addReg(SourcePhysReg); 1345 1346 // If necessary, round the floating result to single precision. 1347 } else if (CopyVT == MVT::f64) { 1348 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1349 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), 1350 ResultReg).addReg(SourcePhysReg); 1351 1352 // If only the low half of a general register is needed, generate 1353 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be 1354 // used along the fast-isel path (not lowered), and downstream logic 1355 // also doesn't like a direct subreg copy on a physical reg.) 1356 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { 1357 ResultReg = createResultReg(&PPC::GPRCRegClass); 1358 // Convert physical register from G8RC to GPRC. 1359 SourcePhysReg -= PPC::X0 - PPC::R0; 1360 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1361 TII.get(TargetOpcode::COPY), ResultReg) 1362 .addReg(SourcePhysReg); 1363 } 1364 1365 assert(ResultReg && "ResultReg unset!"); 1366 UsedRegs.push_back(SourcePhysReg); 1367 UpdateValueMap(I, ResultReg); 1368 } 1369 } 1370 1371 // Attempt to fast-select a call instruction. 1372 bool PPCFastISel::SelectCall(const Instruction *I) { 1373 const CallInst *CI = cast<CallInst>(I); 1374 const Value *Callee = CI->getCalledValue(); 1375 1376 // Can't handle inline asm. 1377 if (isa<InlineAsm>(Callee)) 1378 return false; 1379 1380 // Allow SelectionDAG isel to handle tail calls. 1381 if (CI->isTailCall()) 1382 return false; 1383 1384 // Obtain calling convention. 1385 ImmutableCallSite CS(CI); 1386 CallingConv::ID CC = CS.getCallingConv(); 1387 1388 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1389 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1390 bool IsVarArg = FTy->isVarArg(); 1391 1392 // Not ready for varargs yet. 1393 if (IsVarArg) 1394 return false; 1395 1396 // Handle simple calls for now, with legal return types and 1397 // those that can be extended. 1398 Type *RetTy = I->getType(); 1399 MVT RetVT; 1400 if (RetTy->isVoidTy()) 1401 RetVT = MVT::isVoid; 1402 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && 1403 RetVT != MVT::i8) 1404 return false; 1405 1406 // FIXME: No multi-register return values yet. 1407 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 && 1408 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 && 1409 RetVT != MVT::f64) { 1410 SmallVector<CCValAssign, 16> RVLocs; 1411 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 1412 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS); 1413 if (RVLocs.size() > 1) 1414 return false; 1415 } 1416 1417 // Bail early if more than 8 arguments, as we only currently 1418 // handle arguments passed in registers. 1419 unsigned NumArgs = CS.arg_size(); 1420 if (NumArgs > 8) 1421 return false; 1422 1423 // Set up the argument vectors. 1424 SmallVector<Value*, 8> Args; 1425 SmallVector<unsigned, 8> ArgRegs; 1426 SmallVector<MVT, 8> ArgVTs; 1427 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1428 1429 Args.reserve(NumArgs); 1430 ArgRegs.reserve(NumArgs); 1431 ArgVTs.reserve(NumArgs); 1432 ArgFlags.reserve(NumArgs); 1433 1434 for (ImmutableCallSite::arg_iterator II = CS.arg_begin(), IE = CS.arg_end(); 1435 II != IE; ++II) { 1436 // FIXME: ARM does something for intrinsic calls here, check into that. 1437 1438 unsigned AttrIdx = II - CS.arg_begin() + 1; 1439 1440 // Only handle easy calls for now. It would be reasonably easy 1441 // to handle <= 8-byte structures passed ByVal in registers, but we 1442 // have to ensure they are right-justified in the register. 1443 if (CS.paramHasAttr(AttrIdx, Attribute::InReg) || 1444 CS.paramHasAttr(AttrIdx, Attribute::StructRet) || 1445 CS.paramHasAttr(AttrIdx, Attribute::Nest) || 1446 CS.paramHasAttr(AttrIdx, Attribute::ByVal)) 1447 return false; 1448 1449 ISD::ArgFlagsTy Flags; 1450 if (CS.paramHasAttr(AttrIdx, Attribute::SExt)) 1451 Flags.setSExt(); 1452 if (CS.paramHasAttr(AttrIdx, Attribute::ZExt)) 1453 Flags.setZExt(); 1454 1455 Type *ArgTy = (*II)->getType(); 1456 MVT ArgVT; 1457 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8) 1458 return false; 1459 1460 if (ArgVT.isVector()) 1461 return false; 1462 1463 unsigned Arg = getRegForValue(*II); 1464 if (Arg == 0) 1465 return false; 1466 1467 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy); 1468 Flags.setOrigAlign(OriginalAlignment); 1469 1470 Args.push_back(*II); 1471 ArgRegs.push_back(Arg); 1472 ArgVTs.push_back(ArgVT); 1473 ArgFlags.push_back(Flags); 1474 } 1475 1476 // Process the arguments. 1477 SmallVector<unsigned, 8> RegArgs; 1478 unsigned NumBytes; 1479 1480 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 1481 RegArgs, CC, NumBytes, IsVarArg)) 1482 return false; 1483 1484 // FIXME: No handling for function pointers yet. This requires 1485 // implementing the function descriptor (OPD) setup. 1486 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); 1487 if (!GV) 1488 return false; 1489 1490 // Build direct call with NOP for TOC restore. 1491 // FIXME: We can and should optimize away the NOP for local calls. 1492 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1493 TII.get(PPC::BL8_NOP)); 1494 // Add callee. 1495 MIB.addGlobalAddress(GV); 1496 1497 // Add implicit physical register uses to the call. 1498 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) 1499 MIB.addReg(RegArgs[II], RegState::Implicit); 1500 1501 // Add a register mask with the call-preserved registers. Proper 1502 // defs for return values will be added by setPhysRegsDeadExcept(). 1503 MIB.addRegMask(TRI.getCallPreservedMask(CC)); 1504 1505 // Finish off the call including any return values. 1506 SmallVector<unsigned, 4> UsedRegs; 1507 finishCall(RetVT, UsedRegs, I, CC, NumBytes, IsVarArg); 1508 1509 // Set all unused physregs defs as dead. 1510 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1511 1512 return true; 1513 } 1514 1515 // Attempt to fast-select a return instruction. 1516 bool PPCFastISel::SelectRet(const Instruction *I) { 1517 1518 if (!FuncInfo.CanLowerReturn) 1519 return false; 1520 1521 const ReturnInst *Ret = cast<ReturnInst>(I); 1522 const Function &F = *I->getParent()->getParent(); 1523 1524 // Build a list of return value registers. 1525 SmallVector<unsigned, 4> RetRegs; 1526 CallingConv::ID CC = F.getCallingConv(); 1527 1528 if (Ret->getNumOperands() > 0) { 1529 SmallVector<ISD::OutputArg, 4> Outs; 1530 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); 1531 1532 // Analyze operands of the call, assigning locations to each operand. 1533 SmallVector<CCValAssign, 16> ValLocs; 1534 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context); 1535 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS); 1536 const Value *RV = Ret->getOperand(0); 1537 1538 // FIXME: Only one output register for now. 1539 if (ValLocs.size() > 1) 1540 return false; 1541 1542 // Special case for returning a constant integer of any size. 1543 // Materialize the constant as an i64 and copy it to the return 1544 // register. This avoids an unnecessary extend or truncate. 1545 if (isa<ConstantInt>(*RV)) { 1546 const Constant *C = cast<Constant>(RV); 1547 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64); 1548 unsigned RetReg = ValLocs[0].getLocReg(); 1549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1550 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); 1551 RetRegs.push_back(RetReg); 1552 1553 } else { 1554 unsigned Reg = getRegForValue(RV); 1555 1556 if (Reg == 0) 1557 return false; 1558 1559 // Copy the result values into the output registers. 1560 for (unsigned i = 0; i < ValLocs.size(); ++i) { 1561 1562 CCValAssign &VA = ValLocs[i]; 1563 assert(VA.isRegLoc() && "Can only return in registers!"); 1564 RetRegs.push_back(VA.getLocReg()); 1565 unsigned SrcReg = Reg + VA.getValNo(); 1566 1567 EVT RVEVT = TLI.getValueType(RV->getType()); 1568 if (!RVEVT.isSimple()) 1569 return false; 1570 MVT RVVT = RVEVT.getSimpleVT(); 1571 MVT DestVT = VA.getLocVT(); 1572 1573 if (RVVT != DestVT && RVVT != MVT::i8 && 1574 RVVT != MVT::i16 && RVVT != MVT::i32) 1575 return false; 1576 1577 if (RVVT != DestVT) { 1578 switch (VA.getLocInfo()) { 1579 default: 1580 llvm_unreachable("Unknown loc info!"); 1581 case CCValAssign::Full: 1582 llvm_unreachable("Full value assign but types don't match?"); 1583 case CCValAssign::AExt: 1584 case CCValAssign::ZExt: { 1585 const TargetRegisterClass *RC = 1586 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1587 unsigned TmpReg = createResultReg(RC); 1588 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true)) 1589 return false; 1590 SrcReg = TmpReg; 1591 break; 1592 } 1593 case CCValAssign::SExt: { 1594 const TargetRegisterClass *RC = 1595 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1596 unsigned TmpReg = createResultReg(RC); 1597 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false)) 1598 return false; 1599 SrcReg = TmpReg; 1600 break; 1601 } 1602 } 1603 } 1604 1605 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1606 TII.get(TargetOpcode::COPY), RetRegs[i]) 1607 .addReg(SrcReg); 1608 } 1609 } 1610 } 1611 1612 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1613 TII.get(PPC::BLR)); 1614 1615 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i) 1616 MIB.addReg(RetRegs[i], RegState::Implicit); 1617 1618 return true; 1619 } 1620 1621 // Attempt to emit an integer extend of SrcReg into DestReg. Both 1622 // signed and zero extensions are supported. Return false if we 1623 // can't handle it. 1624 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 1625 unsigned DestReg, bool IsZExt) { 1626 if (DestVT != MVT::i32 && DestVT != MVT::i64) 1627 return false; 1628 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32) 1629 return false; 1630 1631 // Signed extensions use EXTSB, EXTSH, EXTSW. 1632 if (!IsZExt) { 1633 unsigned Opc; 1634 if (SrcVT == MVT::i8) 1635 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64; 1636 else if (SrcVT == MVT::i16) 1637 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64; 1638 else { 1639 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??"); 1640 Opc = PPC::EXTSW_32_64; 1641 } 1642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 1643 .addReg(SrcReg); 1644 1645 // Unsigned 32-bit extensions use RLWINM. 1646 } else if (DestVT == MVT::i32) { 1647 unsigned MB; 1648 if (SrcVT == MVT::i8) 1649 MB = 24; 1650 else { 1651 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??"); 1652 MB = 16; 1653 } 1654 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM), 1655 DestReg) 1656 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31); 1657 1658 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source). 1659 } else { 1660 unsigned MB; 1661 if (SrcVT == MVT::i8) 1662 MB = 56; 1663 else if (SrcVT == MVT::i16) 1664 MB = 48; 1665 else 1666 MB = 32; 1667 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1668 TII.get(PPC::RLDICL_32_64), DestReg) 1669 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB); 1670 } 1671 1672 return true; 1673 } 1674 1675 // Attempt to fast-select an indirect branch instruction. 1676 bool PPCFastISel::SelectIndirectBr(const Instruction *I) { 1677 unsigned AddrReg = getRegForValue(I->getOperand(0)); 1678 if (AddrReg == 0) 1679 return false; 1680 1681 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8)) 1682 .addReg(AddrReg); 1683 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8)); 1684 1685 const IndirectBrInst *IB = cast<IndirectBrInst>(I); 1686 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i) 1687 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]); 1688 1689 return true; 1690 } 1691 1692 // Attempt to fast-select an integer truncate instruction. 1693 bool PPCFastISel::SelectTrunc(const Instruction *I) { 1694 Value *Src = I->getOperand(0); 1695 EVT SrcVT = TLI.getValueType(Src->getType(), true); 1696 EVT DestVT = TLI.getValueType(I->getType(), true); 1697 1698 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16) 1699 return false; 1700 1701 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) 1702 return false; 1703 1704 unsigned SrcReg = getRegForValue(Src); 1705 if (!SrcReg) 1706 return false; 1707 1708 // The only interesting case is when we need to switch register classes. 1709 if (SrcVT == MVT::i64) { 1710 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass); 1711 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1712 TII.get(TargetOpcode::COPY), 1713 ResultReg).addReg(SrcReg, 0, PPC::sub_32); 1714 SrcReg = ResultReg; 1715 } 1716 1717 UpdateValueMap(I, SrcReg); 1718 return true; 1719 } 1720 1721 // Attempt to fast-select an integer extend instruction. 1722 bool PPCFastISel::SelectIntExt(const Instruction *I) { 1723 Type *DestTy = I->getType(); 1724 Value *Src = I->getOperand(0); 1725 Type *SrcTy = Src->getType(); 1726 1727 bool IsZExt = isa<ZExtInst>(I); 1728 unsigned SrcReg = getRegForValue(Src); 1729 if (!SrcReg) return false; 1730 1731 EVT SrcEVT, DestEVT; 1732 SrcEVT = TLI.getValueType(SrcTy, true); 1733 DestEVT = TLI.getValueType(DestTy, true); 1734 if (!SrcEVT.isSimple()) 1735 return false; 1736 if (!DestEVT.isSimple()) 1737 return false; 1738 1739 MVT SrcVT = SrcEVT.getSimpleVT(); 1740 MVT DestVT = DestEVT.getSimpleVT(); 1741 1742 // If we know the register class needed for the result of this 1743 // instruction, use it. Otherwise pick the register class of the 1744 // correct size that does not contain X0/R0, since we don't know 1745 // whether downstream uses permit that assignment. 1746 unsigned AssignedReg = FuncInfo.ValueMap[I]; 1747 const TargetRegisterClass *RC = 1748 (AssignedReg ? MRI.getRegClass(AssignedReg) : 1749 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : 1750 &PPC::GPRC_and_GPRC_NOR0RegClass)); 1751 unsigned ResultReg = createResultReg(RC); 1752 1753 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) 1754 return false; 1755 1756 UpdateValueMap(I, ResultReg); 1757 return true; 1758 } 1759 1760 // Attempt to fast-select an instruction that wasn't handled by 1761 // the table-generated machinery. 1762 bool PPCFastISel::TargetSelectInstruction(const Instruction *I) { 1763 1764 switch (I->getOpcode()) { 1765 case Instruction::Load: 1766 return SelectLoad(I); 1767 case Instruction::Store: 1768 return SelectStore(I); 1769 case Instruction::Br: 1770 return SelectBranch(I); 1771 case Instruction::IndirectBr: 1772 return SelectIndirectBr(I); 1773 case Instruction::FPExt: 1774 return SelectFPExt(I); 1775 case Instruction::FPTrunc: 1776 return SelectFPTrunc(I); 1777 case Instruction::SIToFP: 1778 return SelectIToFP(I, /*IsSigned*/ true); 1779 case Instruction::UIToFP: 1780 return SelectIToFP(I, /*IsSigned*/ false); 1781 case Instruction::FPToSI: 1782 return SelectFPToI(I, /*IsSigned*/ true); 1783 case Instruction::FPToUI: 1784 return SelectFPToI(I, /*IsSigned*/ false); 1785 case Instruction::Add: 1786 return SelectBinaryIntOp(I, ISD::ADD); 1787 case Instruction::Or: 1788 return SelectBinaryIntOp(I, ISD::OR); 1789 case Instruction::Sub: 1790 return SelectBinaryIntOp(I, ISD::SUB); 1791 case Instruction::Call: 1792 if (dyn_cast<IntrinsicInst>(I)) 1793 return false; 1794 return SelectCall(I); 1795 case Instruction::Ret: 1796 return SelectRet(I); 1797 case Instruction::Trunc: 1798 return SelectTrunc(I); 1799 case Instruction::ZExt: 1800 case Instruction::SExt: 1801 return SelectIntExt(I); 1802 // Here add other flavors of Instruction::XXX that automated 1803 // cases don't catch. For example, switches are terminators 1804 // that aren't yet handled. 1805 default: 1806 break; 1807 } 1808 return false; 1809 } 1810 1811 // Materialize a floating-point constant into a register, and return 1812 // the register number (or zero if we failed to handle it). 1813 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { 1814 // No plans to handle long double here. 1815 if (VT != MVT::f32 && VT != MVT::f64) 1816 return 0; 1817 1818 // All FP constants are loaded from the constant pool. 1819 unsigned Align = DL.getPrefTypeAlignment(CFP->getType()); 1820 assert(Align > 0 && "Unexpectedly missing alignment information!"); 1821 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); 1822 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 1823 CodeModel::Model CModel = TM.getCodeModel(); 1824 1825 MachineMemOperand *MMO = 1826 FuncInfo.MF->getMachineMemOperand( 1827 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 1828 (VT == MVT::f32) ? 4 : 8, Align); 1829 1830 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; 1831 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 1832 1833 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)). 1834 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) { 1835 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT), 1836 TmpReg) 1837 .addConstantPoolIndex(Idx).addReg(PPC::X2); 1838 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 1839 .addImm(0).addReg(TmpReg).addMemOperand(MMO); 1840 } else { 1841 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)). 1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA), 1843 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx); 1844 // But for large code model, we must generate a LDtocL followed 1845 // by the LF[SD]. 1846 if (CModel == CodeModel::Large) { 1847 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 1848 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL), 1849 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg); 1850 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 1851 .addImm(0).addReg(TmpReg2); 1852 } else 1853 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 1854 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO) 1855 .addReg(TmpReg) 1856 .addMemOperand(MMO); 1857 } 1858 1859 return DestReg; 1860 } 1861 1862 // Materialize the address of a global value into a register, and return 1863 // the register number (or zero if we failed to handle it). 1864 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { 1865 assert(VT == MVT::i64 && "Non-address!"); 1866 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; 1867 unsigned DestReg = createResultReg(RC); 1868 1869 // Global values may be plain old object addresses, TLS object 1870 // addresses, constant pool entries, or jump tables. How we generate 1871 // code for these may depend on small, medium, or large code model. 1872 CodeModel::Model CModel = TM.getCodeModel(); 1873 1874 // FIXME: Jump tables are not yet required because fast-isel doesn't 1875 // handle switches; if that changes, we need them as well. For now, 1876 // what follows assumes everything's a generic (or TLS) global address. 1877 1878 // FIXME: We don't yet handle the complexity of TLS. 1879 if (GV->isThreadLocal()) 1880 return 0; 1881 1882 // For small code model, generate a simple TOC load. 1883 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) 1884 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc), 1885 DestReg) 1886 .addGlobalAddress(GV) 1887 .addReg(PPC::X2); 1888 else { 1889 // If the address is an externally defined symbol, a symbol with common 1890 // or externally available linkage, a non-local function address, or a 1891 // jump table address (not yet needed), or if we are generating code 1892 // for large code model, we generate: 1893 // LDtocL(GV, ADDIStocHA(%X2, GV)) 1894 // Otherwise we generate: 1895 // ADDItocL(ADDIStocHA(%X2, GV), GV) 1896 // Either way, start with the ADDIStocHA: 1897 unsigned HighPartReg = createResultReg(RC); 1898 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA), 1899 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV); 1900 1901 // If/when switches are implemented, jump tables should be handled 1902 // on the "if" path here. 1903 if (CModel == CodeModel::Large || 1904 (GV->getType()->getElementType()->isFunctionTy() && 1905 (GV->isDeclaration() || GV->isWeakForLinker())) || 1906 GV->isDeclaration() || GV->hasCommonLinkage() || 1907 GV->hasAvailableExternallyLinkage()) 1908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL), 1909 DestReg).addGlobalAddress(GV).addReg(HighPartReg); 1910 else 1911 // Otherwise generate the ADDItocL. 1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL), 1913 DestReg).addReg(HighPartReg).addGlobalAddress(GV); 1914 } 1915 1916 return DestReg; 1917 } 1918 1919 // Materialize a 32-bit integer constant into a register, and return 1920 // the register number (or zero if we failed to handle it). 1921 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm, 1922 const TargetRegisterClass *RC) { 1923 unsigned Lo = Imm & 0xFFFF; 1924 unsigned Hi = (Imm >> 16) & 0xFFFF; 1925 1926 unsigned ResultReg = createResultReg(RC); 1927 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); 1928 1929 if (isInt<16>(Imm)) 1930 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1931 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg) 1932 .addImm(Imm); 1933 else if (Lo) { 1934 // Both Lo and Hi have nonzero bits. 1935 unsigned TmpReg = createResultReg(RC); 1936 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1937 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg) 1938 .addImm(Hi); 1939 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1940 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg) 1941 .addReg(TmpReg).addImm(Lo); 1942 } else 1943 // Just Hi bits. 1944 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1945 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg) 1946 .addImm(Hi); 1947 1948 return ResultReg; 1949 } 1950 1951 // Materialize a 64-bit integer constant into a register, and return 1952 // the register number (or zero if we failed to handle it). 1953 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm, 1954 const TargetRegisterClass *RC) { 1955 unsigned Remainder = 0; 1956 unsigned Shift = 0; 1957 1958 // If the value doesn't fit in 32 bits, see if we can shift it 1959 // so that it fits in 32 bits. 1960 if (!isInt<32>(Imm)) { 1961 Shift = countTrailingZeros<uint64_t>(Imm); 1962 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 1963 1964 if (isInt<32>(ImmSh)) 1965 Imm = ImmSh; 1966 else { 1967 Remainder = Imm; 1968 Shift = 32; 1969 Imm >>= 32; 1970 } 1971 } 1972 1973 // Handle the high-order 32 bits (if shifted) or the whole 32 bits 1974 // (if not shifted). 1975 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC); 1976 if (!Shift) 1977 return TmpReg1; 1978 1979 // If upper 32 bits were not zero, we've built them and need to shift 1980 // them into place. 1981 unsigned TmpReg2; 1982 if (Imm) { 1983 TmpReg2 = createResultReg(RC); 1984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR), 1985 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift); 1986 } else 1987 TmpReg2 = TmpReg1; 1988 1989 unsigned TmpReg3, Hi, Lo; 1990 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 1991 TmpReg3 = createResultReg(RC); 1992 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8), 1993 TmpReg3).addReg(TmpReg2).addImm(Hi); 1994 } else 1995 TmpReg3 = TmpReg2; 1996 1997 if ((Lo = Remainder & 0xFFFF)) { 1998 unsigned ResultReg = createResultReg(RC); 1999 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8), 2000 ResultReg).addReg(TmpReg3).addImm(Lo); 2001 return ResultReg; 2002 } 2003 2004 return TmpReg3; 2005 } 2006 2007 2008 // Materialize an integer constant into a register, and return 2009 // the register number (or zero if we failed to handle it). 2010 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) { 2011 // If we're using CR bit registers for i1 values, handle that as a special 2012 // case first. 2013 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) { 2014 const ConstantInt *CI = cast<ConstantInt>(C); 2015 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); 2016 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2017 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg); 2018 return ImmReg; 2019 } 2020 2021 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && 2022 VT != MVT::i8 && VT != MVT::i1) 2023 return 0; 2024 2025 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : 2026 &PPC::GPRCRegClass); 2027 2028 // If the constant is in range, use a load-immediate. 2029 const ConstantInt *CI = cast<ConstantInt>(C); 2030 if (isInt<16>(CI->getSExtValue())) { 2031 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; 2032 unsigned ImmReg = createResultReg(RC); 2033 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg) 2034 .addImm(CI->getSExtValue()); 2035 return ImmReg; 2036 } 2037 2038 // Construct the constant piecewise. 2039 int64_t Imm = CI->getZExtValue(); 2040 2041 if (VT == MVT::i64) 2042 return PPCMaterialize64BitInt(Imm, RC); 2043 else if (VT == MVT::i32) 2044 return PPCMaterialize32BitInt(Imm, RC); 2045 2046 return 0; 2047 } 2048 2049 // Materialize a constant into a register, and return the register 2050 // number (or zero if we failed to handle it). 2051 unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) { 2052 EVT CEVT = TLI.getValueType(C->getType(), true); 2053 2054 // Only handle simple types. 2055 if (!CEVT.isSimple()) return 0; 2056 MVT VT = CEVT.getSimpleVT(); 2057 2058 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 2059 return PPCMaterializeFP(CFP, VT); 2060 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 2061 return PPCMaterializeGV(GV, VT); 2062 else if (isa<ConstantInt>(C)) 2063 return PPCMaterializeInt(C, VT); 2064 2065 return 0; 2066 } 2067 2068 // Materialize the address created by an alloca into a register, and 2069 // return the register number (or zero if we failed to handle it). 2070 unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { 2071 // Don't handle dynamic allocas. 2072 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; 2073 2074 MVT VT; 2075 if (!isLoadTypeLegal(AI->getType(), VT)) return 0; 2076 2077 DenseMap<const AllocaInst*, int>::iterator SI = 2078 FuncInfo.StaticAllocaMap.find(AI); 2079 2080 if (SI != FuncInfo.StaticAllocaMap.end()) { 2081 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 2082 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8), 2083 ResultReg).addFrameIndex(SI->second).addImm(0); 2084 return ResultReg; 2085 } 2086 2087 return 0; 2088 } 2089 2090 // Fold loads into extends when possible. 2091 // FIXME: We can have multiple redundant extend/trunc instructions 2092 // following a load. The folding only picks up one. Extend this 2093 // to check subsequent instructions for the same pattern and remove 2094 // them. Thus ResultReg should be the def reg for the last redundant 2095 // instruction in a chain, and all intervening instructions can be 2096 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll 2097 // to add ELF64-NOT: rldicl to the appropriate tests when this works. 2098 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 2099 const LoadInst *LI) { 2100 // Verify we have a legal type before going any further. 2101 MVT VT; 2102 if (!isLoadTypeLegal(LI->getType(), VT)) 2103 return false; 2104 2105 // Combine load followed by zero- or sign-extend. 2106 bool IsZExt = false; 2107 switch(MI->getOpcode()) { 2108 default: 2109 return false; 2110 2111 case PPC::RLDICL: 2112 case PPC::RLDICL_32_64: { 2113 IsZExt = true; 2114 unsigned MB = MI->getOperand(3).getImm(); 2115 if ((VT == MVT::i8 && MB <= 56) || 2116 (VT == MVT::i16 && MB <= 48) || 2117 (VT == MVT::i32 && MB <= 32)) 2118 break; 2119 return false; 2120 } 2121 2122 case PPC::RLWINM: 2123 case PPC::RLWINM8: { 2124 IsZExt = true; 2125 unsigned MB = MI->getOperand(3).getImm(); 2126 if ((VT == MVT::i8 && MB <= 24) || 2127 (VT == MVT::i16 && MB <= 16)) 2128 break; 2129 return false; 2130 } 2131 2132 case PPC::EXTSB: 2133 case PPC::EXTSB8: 2134 case PPC::EXTSB8_32_64: 2135 /* There is no sign-extending load-byte instruction. */ 2136 return false; 2137 2138 case PPC::EXTSH: 2139 case PPC::EXTSH8: 2140 case PPC::EXTSH8_32_64: { 2141 if (VT != MVT::i16 && VT != MVT::i8) 2142 return false; 2143 break; 2144 } 2145 2146 case PPC::EXTSW: 2147 case PPC::EXTSW_32_64: { 2148 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8) 2149 return false; 2150 break; 2151 } 2152 } 2153 2154 // See if we can handle this address. 2155 Address Addr; 2156 if (!PPCComputeAddress(LI->getOperand(0), Addr)) 2157 return false; 2158 2159 unsigned ResultReg = MI->getOperand(0).getReg(); 2160 2161 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt)) 2162 return false; 2163 2164 MI->eraseFromParent(); 2165 return true; 2166 } 2167 2168 // Attempt to lower call arguments in a faster way than done by 2169 // the selection DAG code. 2170 bool PPCFastISel::FastLowerArguments() { 2171 // Defer to normal argument lowering for now. It's reasonably 2172 // efficient. Consider doing something like ARM to handle the 2173 // case where all args fit in registers, no varargs, no float 2174 // or vector args. 2175 return false; 2176 } 2177 2178 // Handle materializing integer constants into a register. This is not 2179 // automatically generated for PowerPC, so must be explicitly created here. 2180 unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) { 2181 2182 if (Opc != ISD::Constant) 2183 return 0; 2184 2185 // If we're using CR bit registers for i1 values, handle that as a special 2186 // case first. 2187 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) { 2188 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); 2189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2190 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg); 2191 return ImmReg; 2192 } 2193 2194 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && 2195 VT != MVT::i8 && VT != MVT::i1) 2196 return 0; 2197 2198 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : 2199 &PPC::GPRCRegClass); 2200 if (VT == MVT::i64) 2201 return PPCMaterialize64BitInt(Imm, RC); 2202 else 2203 return PPCMaterialize32BitInt(Imm, RC); 2204 } 2205 2206 // Override for ADDI and ADDI8 to set the correct register class 2207 // on RHS operand 0. The automatic infrastructure naively assumes 2208 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost 2209 // for these cases. At the moment, none of the other automatically 2210 // generated RI instructions require special treatment. However, once 2211 // SelectSelect is implemented, "isel" requires similar handling. 2212 // 2213 // Also be conservative about the output register class. Avoid 2214 // assigning R0 or X0 to the output register for GPRC and G8RC 2215 // register classes, as any such result could be used in ADDI, etc., 2216 // where those regs have another meaning. 2217 unsigned PPCFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 2218 const TargetRegisterClass *RC, 2219 unsigned Op0, bool Op0IsKill, 2220 uint64_t Imm) { 2221 if (MachineInstOpcode == PPC::ADDI) 2222 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); 2223 else if (MachineInstOpcode == PPC::ADDI8) 2224 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); 2225 2226 const TargetRegisterClass *UseRC = 2227 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : 2228 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); 2229 2230 return FastISel::FastEmitInst_ri(MachineInstOpcode, UseRC, 2231 Op0, Op0IsKill, Imm); 2232 } 2233 2234 // Override for instructions with one register operand to avoid use of 2235 // R0/X0. The automatic infrastructure isn't aware of the context so 2236 // we must be conservative. 2237 unsigned PPCFastISel::FastEmitInst_r(unsigned MachineInstOpcode, 2238 const TargetRegisterClass* RC, 2239 unsigned Op0, bool Op0IsKill) { 2240 const TargetRegisterClass *UseRC = 2241 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : 2242 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); 2243 2244 return FastISel::FastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); 2245 } 2246 2247 // Override for instructions with two register operands to avoid use 2248 // of R0/X0. The automatic infrastructure isn't aware of the context 2249 // so we must be conservative. 2250 unsigned PPCFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 2251 const TargetRegisterClass* RC, 2252 unsigned Op0, bool Op0IsKill, 2253 unsigned Op1, bool Op1IsKill) { 2254 const TargetRegisterClass *UseRC = 2255 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : 2256 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); 2257 2258 return FastISel::FastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill, 2259 Op1, Op1IsKill); 2260 } 2261 2262 namespace llvm { 2263 // Create the fast instruction selector for PowerPC64 ELF. 2264 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo, 2265 const TargetLibraryInfo *LibInfo) { 2266 const TargetMachine &TM = FuncInfo.MF->getTarget(); 2267 2268 // Only available on 64-bit ELF for now. 2269 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 2270 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI()) 2271 return new PPCFastISel(FuncInfo, LibInfo); 2272 2273 return nullptr; 2274 } 2275 } 2276