Home | History | Annotate | Download | only in Mips 
      1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsSEISelDAGToDAG.h"
     15 #include "MCTargetDesc/MipsBaseInfo.h"
     16 #include "Mips.h"
     17 #include "MipsAnalyzeImmediate.h"
     18 #include "MipsMachineFunction.h"
     19 #include "MipsRegisterInfo.h"
     20 #include "llvm/CodeGen/MachineConstantPool.h"
     21 #include "llvm/CodeGen/MachineFrameInfo.h"
     22 #include "llvm/CodeGen/MachineFunction.h"
     23 #include "llvm/CodeGen/MachineInstrBuilder.h"
     24 #include "llvm/CodeGen/MachineRegisterInfo.h"
     25 #include "llvm/CodeGen/SelectionDAGNodes.h"
     26 #include "llvm/IR/CFG.h"
     27 #include "llvm/IR/GlobalValue.h"
     28 #include "llvm/IR/Instructions.h"
     29 #include "llvm/IR/Intrinsics.h"
     30 #include "llvm/IR/Type.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/ErrorHandling.h"
     33 #include "llvm/Support/raw_ostream.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 using namespace llvm;
     36 
     37 #define DEBUG_TYPE "mips-isel"
     38 
     39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
     40   if (Subtarget->inMips16Mode())
     41     return false;
     42   return MipsDAGToDAGISel::runOnMachineFunction(MF);
     43 }
     44 
     45 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
     46                                                MachineFunction &MF) {
     47   MachineInstrBuilder MIB(MF, &MI);
     48   unsigned Mask = MI.getOperand(1).getImm();
     49   unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
     50 
     51   if (Mask & 1)
     52     MIB.addReg(Mips::DSPPos, Flag);
     53 
     54   if (Mask & 2)
     55     MIB.addReg(Mips::DSPSCount, Flag);
     56 
     57   if (Mask & 4)
     58     MIB.addReg(Mips::DSPCarry, Flag);
     59 
     60   if (Mask & 8)
     61     MIB.addReg(Mips::DSPOutFlag, Flag);
     62 
     63   if (Mask & 16)
     64     MIB.addReg(Mips::DSPCCond, Flag);
     65 
     66   if (Mask & 32)
     67     MIB.addReg(Mips::DSPEFI, Flag);
     68 }
     69 
     70 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
     71   switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
     72   default:
     73     llvm_unreachable("Could not map int to register");
     74   case 0: return Mips::MSAIR;
     75   case 1: return Mips::MSACSR;
     76   case 2: return Mips::MSAAccess;
     77   case 3: return Mips::MSASave;
     78   case 4: return Mips::MSAModify;
     79   case 5: return Mips::MSARequest;
     80   case 6: return Mips::MSAMap;
     81   case 7: return Mips::MSAUnmap;
     82   }
     83 }
     84 
     85 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
     86                                                 const MachineInstr& MI) {
     87   unsigned DstReg = 0, ZeroReg = 0;
     88 
     89   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
     90   if ((MI.getOpcode() == Mips::ADDiu) &&
     91       (MI.getOperand(1).getReg() == Mips::ZERO) &&
     92       (MI.getOperand(2).getImm() == 0)) {
     93     DstReg = MI.getOperand(0).getReg();
     94     ZeroReg = Mips::ZERO;
     95   } else if ((MI.getOpcode() == Mips::DADDiu) &&
     96              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
     97              (MI.getOperand(2).getImm() == 0)) {
     98     DstReg = MI.getOperand(0).getReg();
     99     ZeroReg = Mips::ZERO_64;
    100   }
    101 
    102   if (!DstReg)
    103     return false;
    104 
    105   // Replace uses with ZeroReg.
    106   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
    107        E = MRI->use_end(); U != E;) {
    108     MachineOperand &MO = *U;
    109     unsigned OpNo = U.getOperandNo();
    110     MachineInstr *MI = MO.getParent();
    111     ++U;
    112 
    113     // Do not replace if it is a phi's operand or is tied to def operand.
    114     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
    115       continue;
    116 
    117     MO.setReg(ZeroReg);
    118   }
    119 
    120   return true;
    121 }
    122 
    123 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
    124   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
    125 
    126   if (!MipsFI->globalBaseRegSet())
    127     return;
    128 
    129   MachineBasicBlock &MBB = MF.front();
    130   MachineBasicBlock::iterator I = MBB.begin();
    131   MachineRegisterInfo &RegInfo = MF.getRegInfo();
    132   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    133   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
    134   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
    135   const TargetRegisterClass *RC;
    136 
    137   if (Subtarget->isABI_N64())
    138     RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
    139   else
    140     RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
    141 
    142   V0 = RegInfo.createVirtualRegister(RC);
    143   V1 = RegInfo.createVirtualRegister(RC);
    144 
    145   if (Subtarget->isABI_N64()) {
    146     MF.getRegInfo().addLiveIn(Mips::T9_64);
    147     MBB.addLiveIn(Mips::T9_64);
    148 
    149     // lui $v0, %hi(%neg(%gp_rel(fname)))
    150     // daddu $v1, $v0, $t9
    151     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    152     const GlobalValue *FName = MF.getFunction();
    153     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
    154       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    155     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
    156       .addReg(Mips::T9_64);
    157     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
    158       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    159     return;
    160   }
    161 
    162   if (MF.getTarget().getRelocationModel() == Reloc::Static) {
    163     // Set global register to __gnu_local_gp.
    164     //
    165     // lui   $v0, %hi(__gnu_local_gp)
    166     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
    167     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    168       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
    169     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
    170       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
    171     return;
    172   }
    173 
    174   MF.getRegInfo().addLiveIn(Mips::T9);
    175   MBB.addLiveIn(Mips::T9);
    176 
    177   if (Subtarget->isABI_N32()) {
    178     // lui $v0, %hi(%neg(%gp_rel(fname)))
    179     // addu $v1, $v0, $t9
    180     // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    181     const GlobalValue *FName = MF.getFunction();
    182     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    183       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    184     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
    185     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
    186       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    187     return;
    188   }
    189 
    190   assert(Subtarget->isABI_O32());
    191 
    192   // For O32 ABI, the following instruction sequence is emitted to initialize
    193   // the global base register:
    194   //
    195   //  0. lui   $2, %hi(_gp_disp)
    196   //  1. addiu $2, $2, %lo(_gp_disp)
    197   //  2. addu  $globalbasereg, $2, $t9
    198   //
    199   // We emit only the last instruction here.
    200   //
    201   // GNU linker requires that the first two instructions appear at the beginning
    202   // of a function and no instructions be inserted before or between them.
    203   // The two instructions are emitted during lowering to MC layer in order to
    204   // avoid any reordering.
    205   //
    206   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
    207   // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
    208   // reads it.
    209   MF.getRegInfo().addLiveIn(Mips::V0);
    210   MBB.addLiveIn(Mips::V0);
    211   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
    212     .addReg(Mips::V0).addReg(Mips::T9);
    213 }
    214 
    215 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
    216   initGlobalBaseReg(MF);
    217 
    218   MachineRegisterInfo *MRI = &MF.getRegInfo();
    219 
    220   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
    221        ++MFI)
    222     for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
    223       if (I->getOpcode() == Mips::RDDSP)
    224         addDSPCtrlRegOperands(false, *I, MF);
    225       else if (I->getOpcode() == Mips::WRDSP)
    226         addDSPCtrlRegOperands(true, *I, MF);
    227       else
    228         replaceUsesWithZeroReg(MRI, *I);
    229     }
    230 }
    231 
    232 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
    233                                            SDValue CmpLHS, SDLoc DL,
    234                                            SDNode *Node) const {
    235   unsigned Opc = InFlag.getOpcode(); (void)Opc;
    236 
    237   assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
    238           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
    239          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
    240 
    241   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
    242   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
    243   EVT VT = LHS.getValueType();
    244 
    245   SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
    246   SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
    247                                             SDValue(Carry, 0), RHS);
    248   return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
    249                               SDValue(AddCarry, 0));
    250 }
    251 
    252 /// Match frameindex
    253 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
    254                                               SDValue &Offset) const {
    255   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
    256     EVT ValTy = Addr.getValueType();
    257 
    258     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    259     Offset = CurDAG->getTargetConstant(0, ValTy);
    260     return true;
    261   }
    262   return false;
    263 }
    264 
    265 /// Match frameindex+offset and frameindex|offset
    266 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
    267                                                     SDValue &Offset,
    268                                                     unsigned OffsetBits) const {
    269   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    270     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
    271     if (isIntN(OffsetBits, CN->getSExtValue())) {
    272       EVT ValTy = Addr.getValueType();
    273 
    274       // If the first operand is a FI, get the TargetFI Node
    275       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
    276                                   (Addr.getOperand(0)))
    277         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    278       else
    279         Base = Addr.getOperand(0);
    280 
    281       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
    282       return true;
    283     }
    284   }
    285   return false;
    286 }
    287 
    288 /// ComplexPattern used on MipsInstrInfo
    289 /// Used on Mips Load/Store instructions
    290 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
    291                                           SDValue &Offset) const {
    292   // if Address is FI, get the TargetFrameIndex.
    293   if (selectAddrFrameIndex(Addr, Base, Offset))
    294     return true;
    295 
    296   // on PIC code Load GA
    297   if (Addr.getOpcode() == MipsISD::Wrapper) {
    298     Base   = Addr.getOperand(0);
    299     Offset = Addr.getOperand(1);
    300     return true;
    301   }
    302 
    303   if (TM.getRelocationModel() != Reloc::PIC_) {
    304     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
    305         Addr.getOpcode() == ISD::TargetGlobalAddress))
    306       return false;
    307   }
    308 
    309   // Addresses of the form FI+const or FI|const
    310   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
    311     return true;
    312 
    313   // Operand is a result from an ADD.
    314   if (Addr.getOpcode() == ISD::ADD) {
    315     // When loading from constant pools, load the lower address part in
    316     // the instruction itself. Example, instead of:
    317     //  lui $2, %hi($CPI1_0)
    318     //  addiu $2, $2, %lo($CPI1_0)
    319     //  lwc1 $f0, 0($2)
    320     // Generate:
    321     //  lui $2, %hi($CPI1_0)
    322     //  lwc1 $f0, %lo($CPI1_0)($2)
    323     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
    324         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
    325       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
    326       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
    327           isa<JumpTableSDNode>(Opnd0)) {
    328         Base = Addr.getOperand(0);
    329         Offset = Opnd0;
    330         return true;
    331       }
    332     }
    333   }
    334 
    335   return false;
    336 }
    337 
    338 /// ComplexPattern used on MipsInstrInfo
    339 /// Used on Mips Load/Store instructions
    340 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
    341                                           SDValue &Offset) const {
    342   // Operand is a result from an ADD.
    343   if (Addr.getOpcode() == ISD::ADD) {
    344     Base = Addr.getOperand(0);
    345     Offset = Addr.getOperand(1);
    346     return true;
    347   }
    348 
    349   return false;
    350 }
    351 
    352 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
    353                                            SDValue &Offset) const {
    354   Base = Addr;
    355   Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
    356   return true;
    357 }
    358 
    359 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
    360                                        SDValue &Offset) const {
    361   return selectAddrRegImm(Addr, Base, Offset) ||
    362     selectAddrDefault(Addr, Base, Offset);
    363 }
    364 
    365 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
    366                                             SDValue &Offset) const {
    367   if (selectAddrFrameIndex(Addr, Base, Offset))
    368     return true;
    369 
    370   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
    371     return true;
    372 
    373   return false;
    374 }
    375 
    376 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
    377 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
    378                                             SDValue &Offset) const {
    379   if (selectAddrFrameIndex(Addr, Base, Offset))
    380     return true;
    381 
    382   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
    383     return true;
    384 
    385   return false;
    386 }
    387 
    388 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
    389                                          SDValue &Offset) const {
    390   return selectAddrRegImm12(Addr, Base, Offset) ||
    391     selectAddrDefault(Addr, Base, Offset);
    392 }
    393 
    394 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
    395                                           SDValue &Offset) const {
    396   if (selectAddrRegImm10(Addr, Base, Offset))
    397     return true;
    398 
    399   if (selectAddrDefault(Addr, Base, Offset))
    400     return true;
    401 
    402   return false;
    403 }
    404 
    405 // Select constant vector splats.
    406 //
    407 // Returns true and sets Imm if:
    408 // * MSA is enabled
    409 // * N is a ISD::BUILD_VECTOR representing a constant splat
    410 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
    411   if (!Subtarget->hasMSA())
    412     return false;
    413 
    414   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
    415 
    416   if (!Node)
    417     return false;
    418 
    419   APInt SplatValue, SplatUndef;
    420   unsigned SplatBitSize;
    421   bool HasAnyUndefs;
    422 
    423   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
    424                              HasAnyUndefs, 8,
    425                              !Subtarget->isLittle()))
    426     return false;
    427 
    428   Imm = SplatValue;
    429 
    430   return true;
    431 }
    432 
    433 // Select constant vector splats.
    434 //
    435 // In addition to the requirements of selectVSplat(), this function returns
    436 // true and sets Imm if:
    437 // * The splat value is the same width as the elements of the vector
    438 // * The splat value fits in an integer with the specified signed-ness and
    439 //   width.
    440 //
    441 // This function looks through ISD::BITCAST nodes.
    442 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    443 //       sometimes a shuffle in big-endian mode.
    444 //
    445 // It's worth noting that this function is not used as part of the selection
    446 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
    447 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
    448 // MipsSEDAGToDAGISel::selectNode.
    449 bool MipsSEDAGToDAGISel::
    450 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
    451                    unsigned ImmBitSize) const {
    452   APInt ImmValue;
    453   EVT EltTy = N->getValueType(0).getVectorElementType();
    454 
    455   if (N->getOpcode() == ISD::BITCAST)
    456     N = N->getOperand(0);
    457 
    458   if (selectVSplat (N.getNode(), ImmValue) &&
    459       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    460     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
    461         (!Signed && ImmValue.isIntN(ImmBitSize))) {
    462       Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
    463       return true;
    464     }
    465   }
    466 
    467   return false;
    468 }
    469 
    470 // Select constant vector splats.
    471 bool MipsSEDAGToDAGISel::
    472 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
    473   return selectVSplatCommon(N, Imm, false, 1);
    474 }
    475 
    476 bool MipsSEDAGToDAGISel::
    477 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
    478   return selectVSplatCommon(N, Imm, false, 2);
    479 }
    480 
    481 bool MipsSEDAGToDAGISel::
    482 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
    483   return selectVSplatCommon(N, Imm, false, 3);
    484 }
    485 
    486 // Select constant vector splats.
    487 bool MipsSEDAGToDAGISel::
    488 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
    489   return selectVSplatCommon(N, Imm, false, 4);
    490 }
    491 
    492 // Select constant vector splats.
    493 bool MipsSEDAGToDAGISel::
    494 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
    495   return selectVSplatCommon(N, Imm, false, 5);
    496 }
    497 
    498 // Select constant vector splats.
    499 bool MipsSEDAGToDAGISel::
    500 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
    501   return selectVSplatCommon(N, Imm, false, 6);
    502 }
    503 
    504 // Select constant vector splats.
    505 bool MipsSEDAGToDAGISel::
    506 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
    507   return selectVSplatCommon(N, Imm, false, 8);
    508 }
    509 
    510 // Select constant vector splats.
    511 bool MipsSEDAGToDAGISel::
    512 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
    513   return selectVSplatCommon(N, Imm, true, 5);
    514 }
    515 
    516 // Select constant vector splats whose value is a power of 2.
    517 //
    518 // In addition to the requirements of selectVSplat(), this function returns
    519 // true and sets Imm if:
    520 // * The splat value is the same width as the elements of the vector
    521 // * The splat value is a power of two.
    522 //
    523 // This function looks through ISD::BITCAST nodes.
    524 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    525 //       sometimes a shuffle in big-endian mode.
    526 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
    527   APInt ImmValue;
    528   EVT EltTy = N->getValueType(0).getVectorElementType();
    529 
    530   if (N->getOpcode() == ISD::BITCAST)
    531     N = N->getOperand(0);
    532 
    533   if (selectVSplat (N.getNode(), ImmValue) &&
    534       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    535     int32_t Log2 = ImmValue.exactLogBase2();
    536 
    537     if (Log2 != -1) {
    538       Imm = CurDAG->getTargetConstant(Log2, EltTy);
    539       return true;
    540     }
    541   }
    542 
    543   return false;
    544 }
    545 
    546 // Select constant vector splats whose value only has a consecutive sequence
    547 // of left-most bits set (e.g. 0b11...1100...00).
    548 //
    549 // In addition to the requirements of selectVSplat(), this function returns
    550 // true and sets Imm if:
    551 // * The splat value is the same width as the elements of the vector
    552 // * The splat value is a consecutive sequence of left-most bits.
    553 //
    554 // This function looks through ISD::BITCAST nodes.
    555 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    556 //       sometimes a shuffle in big-endian mode.
    557 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
    558   APInt ImmValue;
    559   EVT EltTy = N->getValueType(0).getVectorElementType();
    560 
    561   if (N->getOpcode() == ISD::BITCAST)
    562     N = N->getOperand(0);
    563 
    564   if (selectVSplat(N.getNode(), ImmValue) &&
    565       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    566     // Extract the run of set bits starting with bit zero from the bitwise
    567     // inverse of ImmValue, and test that the inverse of this is the same
    568     // as the original value.
    569     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
    570 
    571       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
    572       return true;
    573     }
    574   }
    575 
    576   return false;
    577 }
    578 
    579 // Select constant vector splats whose value only has a consecutive sequence
    580 // of right-most bits set (e.g. 0b00...0011...11).
    581 //
    582 // In addition to the requirements of selectVSplat(), this function returns
    583 // true and sets Imm if:
    584 // * The splat value is the same width as the elements of the vector
    585 // * The splat value is a consecutive sequence of right-most bits.
    586 //
    587 // This function looks through ISD::BITCAST nodes.
    588 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    589 //       sometimes a shuffle in big-endian mode.
    590 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
    591   APInt ImmValue;
    592   EVT EltTy = N->getValueType(0).getVectorElementType();
    593 
    594   if (N->getOpcode() == ISD::BITCAST)
    595     N = N->getOperand(0);
    596 
    597   if (selectVSplat(N.getNode(), ImmValue) &&
    598       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    599     // Extract the run of set bits starting with bit zero, and test that the
    600     // result is the same as the original value
    601     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
    602       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
    603       return true;
    604     }
    605   }
    606 
    607   return false;
    608 }
    609 
    610 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
    611                                                  SDValue &Imm) const {
    612   APInt ImmValue;
    613   EVT EltTy = N->getValueType(0).getVectorElementType();
    614 
    615   if (N->getOpcode() == ISD::BITCAST)
    616     N = N->getOperand(0);
    617 
    618   if (selectVSplat(N.getNode(), ImmValue) &&
    619       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    620     int32_t Log2 = (~ImmValue).exactLogBase2();
    621 
    622     if (Log2 != -1) {
    623       Imm = CurDAG->getTargetConstant(Log2, EltTy);
    624       return true;
    625     }
    626   }
    627 
    628   return false;
    629 }
    630 
    631 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
    632   unsigned Opcode = Node->getOpcode();
    633   SDLoc DL(Node);
    634 
    635   ///
    636   // Instruction Selection not handled by the auto-generated
    637   // tablegen selection should be handled here.
    638   ///
    639   SDNode *Result;
    640 
    641   switch(Opcode) {
    642   default: break;
    643 
    644   case ISD::SUBE: {
    645     SDValue InFlag = Node->getOperand(2);
    646     Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
    647     return std::make_pair(true, Result);
    648   }
    649 
    650   case ISD::ADDE: {
    651     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
    652       break;
    653     SDValue InFlag = Node->getOperand(2);
    654     Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
    655     return std::make_pair(true, Result);
    656   }
    657 
    658   case ISD::ConstantFP: {
    659     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
    660     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
    661       if (Subtarget->isGP64bit()) {
    662         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    663                                               Mips::ZERO_64, MVT::i64);
    664         Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
    665       } else if (Subtarget->isFP64bit()) {
    666         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    667                                               Mips::ZERO, MVT::i32);
    668         Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
    669                                         Zero, Zero);
    670       } else {
    671         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    672                                               Mips::ZERO, MVT::i32);
    673         Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
    674                                         Zero);
    675       }
    676 
    677       return std::make_pair(true, Result);
    678     }
    679     break;
    680   }
    681 
    682   case ISD::Constant: {
    683     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
    684     unsigned Size = CN->getValueSizeInBits(0);
    685 
    686     if (Size == 32)
    687       break;
    688 
    689     MipsAnalyzeImmediate AnalyzeImm;
    690     int64_t Imm = CN->getSExtValue();
    691 
    692     const MipsAnalyzeImmediate::InstSeq &Seq =
    693       AnalyzeImm.Analyze(Imm, Size, false);
    694 
    695     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
    696     SDLoc DL(CN);
    697     SDNode *RegOpnd;
    698     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
    699                                                 MVT::i64);
    700 
    701     // The first instruction can be a LUi which is different from other
    702     // instructions (ADDiu, ORI and SLL) in that it does not have a register
    703     // operand.
    704     if (Inst->Opc == Mips::LUi64)
    705       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
    706     else
    707       RegOpnd =
    708         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    709                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
    710                                ImmOpnd);
    711 
    712     // The remaining instructions in the sequence are handled here.
    713     for (++Inst; Inst != Seq.end(); ++Inst) {
    714       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
    715                                           MVT::i64);
    716       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    717                                        SDValue(RegOpnd, 0), ImmOpnd);
    718     }
    719 
    720     return std::make_pair(true, RegOpnd);
    721   }
    722 
    723   case ISD::INTRINSIC_W_CHAIN: {
    724     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
    725     default:
    726       break;
    727 
    728     case Intrinsic::mips_cfcmsa: {
    729       SDValue ChainIn = Node->getOperand(0);
    730       SDValue RegIdx = Node->getOperand(2);
    731       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
    732                                            getMSACtrlReg(RegIdx), MVT::i32);
    733       return std::make_pair(true, Reg.getNode());
    734     }
    735     }
    736     break;
    737   }
    738 
    739   case ISD::INTRINSIC_WO_CHAIN: {
    740     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
    741     default:
    742       break;
    743 
    744     case Intrinsic::mips_move_v:
    745       // Like an assignment but will always produce a move.v even if
    746       // unnecessary.
    747       return std::make_pair(true,
    748                             CurDAG->getMachineNode(Mips::MOVE_V, DL,
    749                                                    Node->getValueType(0),
    750                                                    Node->getOperand(1)));
    751     }
    752     break;
    753   }
    754 
    755   case ISD::INTRINSIC_VOID: {
    756     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
    757     default:
    758       break;
    759 
    760     case Intrinsic::mips_ctcmsa: {
    761       SDValue ChainIn = Node->getOperand(0);
    762       SDValue RegIdx  = Node->getOperand(2);
    763       SDValue Value   = Node->getOperand(3);
    764       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
    765                                               getMSACtrlReg(RegIdx), Value);
    766       return std::make_pair(true, ChainOut.getNode());
    767     }
    768     }
    769     break;
    770   }
    771 
    772   case MipsISD::ThreadPointer: {
    773     EVT PtrVT = getTargetLowering()->getPointerTy();
    774     unsigned RdhwrOpc, DestReg;
    775 
    776     if (PtrVT == MVT::i32) {
    777       RdhwrOpc = Mips::RDHWR;
    778       DestReg = Mips::V1;
    779     } else {
    780       RdhwrOpc = Mips::RDHWR64;
    781       DestReg = Mips::V1_64;
    782     }
    783 
    784     SDNode *Rdhwr =
    785       CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
    786                              Node->getValueType(0),
    787                              CurDAG->getRegister(Mips::HWR29, MVT::i32));
    788     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
    789                                          SDValue(Rdhwr, 0));
    790     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
    791     ReplaceUses(SDValue(Node, 0), ResNode);
    792     return std::make_pair(true, ResNode.getNode());
    793   }
    794 
    795   case ISD::BUILD_VECTOR: {
    796     // Select appropriate ldi.[bhwd] instructions for constant splats of
    797     // 128-bit when MSA is enabled. Fixup any register class mismatches that
    798     // occur as a result.
    799     //
    800     // This allows the compiler to use a wider range of immediates than would
    801     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
    802     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
    803     // 0x01010101 } without using a constant pool. This would be sub-optimal
    804     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
    805     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
    806     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
    807 
    808     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
    809     APInt SplatValue, SplatUndef;
    810     unsigned SplatBitSize;
    811     bool HasAnyUndefs;
    812     unsigned LdiOp;
    813     EVT ResVecTy = BVN->getValueType(0);
    814     EVT ViaVecTy;
    815 
    816     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
    817       return std::make_pair(false, nullptr);
    818 
    819     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
    820                               HasAnyUndefs, 8,
    821                               !Subtarget->isLittle()))
    822       return std::make_pair(false, nullptr);
    823 
    824     switch (SplatBitSize) {
    825     default:
    826       return std::make_pair(false, nullptr);
    827     case 8:
    828       LdiOp = Mips::LDI_B;
    829       ViaVecTy = MVT::v16i8;
    830       break;
    831     case 16:
    832       LdiOp = Mips::LDI_H;
    833       ViaVecTy = MVT::v8i16;
    834       break;
    835     case 32:
    836       LdiOp = Mips::LDI_W;
    837       ViaVecTy = MVT::v4i32;
    838       break;
    839     case 64:
    840       LdiOp = Mips::LDI_D;
    841       ViaVecTy = MVT::v2i64;
    842       break;
    843     }
    844 
    845     if (!SplatValue.isSignedIntN(10))
    846       return std::make_pair(false, nullptr);
    847 
    848     SDValue Imm = CurDAG->getTargetConstant(SplatValue,
    849                                             ViaVecTy.getVectorElementType());
    850 
    851     SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
    852 
    853     if (ResVecTy != ViaVecTy) {
    854       // If LdiOp is writing to a different register class to ResVecTy, then
    855       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
    856       // since the source and destination register sets contain the same
    857       // registers.
    858       const TargetLowering *TLI = getTargetLowering();
    859       MVT ResVecTySimple = ResVecTy.getSimpleVT();
    860       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
    861       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
    862                                    ResVecTy, SDValue(Res, 0),
    863                                    CurDAG->getTargetConstant(RC->getID(),
    864                                                              MVT::i32));
    865     }
    866 
    867     return std::make_pair(true, Res);
    868   }
    869 
    870   }
    871 
    872   return std::make_pair(false, nullptr);
    873 }
    874 
    875 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
    876   return new MipsSEDAGToDAGISel(TM);
    877 }
    878