1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the base ARM implementation of TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMBaseRegisterInfo.h" 15 #include "ARM.h" 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMFrameLowering.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "ARMSubtarget.h" 20 #include "MCTargetDesc/ARMAddressingModes.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/SmallVector.h" 23 #include "llvm/CodeGen/MachineConstantPool.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/CodeGen/VirtRegMap.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/DerivedTypes.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/LLVMContext.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/raw_ostream.h" 37 #include "llvm/Target/TargetFrameLowering.h" 38 #include "llvm/Target/TargetMachine.h" 39 #include "llvm/Target/TargetOptions.h" 40 41 #define GET_REGINFO_TARGET_DESC 42 #include "ARMGenRegisterInfo.inc" 43 44 using namespace llvm; 45 46 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) { 48 if (STI.isTargetMachO()) { 49 if (STI.isTargetDarwin() || STI.isThumb1Only()) 50 FramePtr = ARM::R7; 51 else 52 FramePtr = ARM::R11; 53 } else if (STI.isTargetWindows()) 54 FramePtr = ARM::R11; 55 else // ARM EABI 56 FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11; 57 } 58 59 const MCPhysReg* 60 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 61 const MCPhysReg *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 62 ? CSR_iOS_SaveList 63 : CSR_AAPCS_SaveList; 64 65 if (!MF) return RegList; 66 67 const Function *F = MF->getFunction(); 68 if (F->getCallingConv() == CallingConv::GHC) { 69 // GHC set of callee saved regs is empty as all those regs are 70 // used for passing STG regs around 71 return CSR_NoRegs_SaveList; 72 } else if (F->hasFnAttribute("interrupt")) { 73 if (STI.isMClass()) { 74 // M-class CPUs have hardware which saves the registers needed to allow a 75 // function conforming to the AAPCS to function as a handler. 76 return CSR_AAPCS_SaveList; 77 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 78 // Fast interrupt mode gives the handler a private copy of R8-R14, so less 79 // need to be saved to restore user-mode state. 80 return CSR_FIQ_SaveList; 81 } else { 82 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 83 // exception handling. 84 return CSR_GenericInt_SaveList; 85 } 86 } 87 88 return RegList; 89 } 90 91 const uint32_t* 92 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 93 if (CC == CallingConv::GHC) 94 // This is academic becase all GHC calls are (supposed to be) tail calls 95 return CSR_NoRegs_RegMask; 96 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 97 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 98 } 99 100 const uint32_t* 101 ARMBaseRegisterInfo::getNoPreservedMask() const { 102 return CSR_NoRegs_RegMask; 103 } 104 105 const uint32_t* 106 ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { 107 // This should return a register mask that is the same as that returned by 108 // getCallPreservedMask but that additionally preserves the register used for 109 // the first i32 argument (which must also be the register used to return a 110 // single i32 return value) 111 // 112 // In case that the calling convention does not use the same register for 113 // both or otherwise does not want to enable this optimization, the function 114 // should return NULL 115 if (CC == CallingConv::GHC) 116 // This is academic becase all GHC calls are (supposed to be) tail calls 117 return nullptr; 118 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 119 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask; 120 } 121 122 BitVector ARMBaseRegisterInfo:: 123 getReservedRegs(const MachineFunction &MF) const { 124 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 125 126 // FIXME: avoid re-calculating this every time. 127 BitVector Reserved(getNumRegs()); 128 Reserved.set(ARM::SP); 129 Reserved.set(ARM::PC); 130 Reserved.set(ARM::FPSCR); 131 Reserved.set(ARM::APSR_NZCV); 132 if (TFI->hasFP(MF)) 133 Reserved.set(FramePtr); 134 if (hasBasePointer(MF)) 135 Reserved.set(BasePtr); 136 // Some targets reserve R9. 137 if (STI.isR9Reserved()) 138 Reserved.set(ARM::R9); 139 // Reserve D16-D31 if the subtarget doesn't support them. 140 if (!STI.hasVFP3() || STI.hasD16()) { 141 assert(ARM::D31 == ARM::D16 + 15); 142 for (unsigned i = 0; i != 16; ++i) 143 Reserved.set(ARM::D16 + i); 144 } 145 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 146 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 147 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 148 if (Reserved.test(*SI)) Reserved.set(*I); 149 150 return Reserved; 151 } 152 153 const TargetRegisterClass* 154 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 155 const { 156 const TargetRegisterClass *Super = RC; 157 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 158 do { 159 switch (Super->getID()) { 160 case ARM::GPRRegClassID: 161 case ARM::SPRRegClassID: 162 case ARM::DPRRegClassID: 163 case ARM::QPRRegClassID: 164 case ARM::QQPRRegClassID: 165 case ARM::QQQQPRRegClassID: 166 case ARM::GPRPairRegClassID: 167 return Super; 168 } 169 Super = *I++; 170 } while (Super); 171 return RC; 172 } 173 174 const TargetRegisterClass * 175 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 176 const { 177 return &ARM::GPRRegClass; 178 } 179 180 const TargetRegisterClass * 181 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 182 if (RC == &ARM::CCRRegClass) 183 return nullptr; // Can't copy CCR registers. 184 return RC; 185 } 186 187 unsigned 188 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 189 MachineFunction &MF) const { 190 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 191 192 switch (RC->getID()) { 193 default: 194 return 0; 195 case ARM::tGPRRegClassID: 196 return TFI->hasFP(MF) ? 4 : 5; 197 case ARM::GPRRegClassID: { 198 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 199 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 200 } 201 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 202 case ARM::DPRRegClassID: 203 return 32 - 10; 204 } 205 } 206 207 // Get the other register in a GPRPair. 208 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 209 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 210 if (ARM::GPRPairRegClass.contains(*Supers)) 211 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 212 return 0; 213 } 214 215 // Resolve the RegPairEven / RegPairOdd register allocator hints. 216 void 217 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 218 ArrayRef<MCPhysReg> Order, 219 SmallVectorImpl<MCPhysReg> &Hints, 220 const MachineFunction &MF, 221 const VirtRegMap *VRM) const { 222 const MachineRegisterInfo &MRI = MF.getRegInfo(); 223 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 224 225 unsigned Odd; 226 switch (Hint.first) { 227 case ARMRI::RegPairEven: 228 Odd = 0; 229 break; 230 case ARMRI::RegPairOdd: 231 Odd = 1; 232 break; 233 default: 234 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 235 return; 236 } 237 238 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 239 // Check if the other part of the pair has already been assigned, and provide 240 // the paired register as the first hint. 241 unsigned PairedPhys = 0; 242 if (VRM && VRM->hasPhys(Hint.second)) { 243 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 244 if (PairedPhys && MRI.isReserved(PairedPhys)) 245 PairedPhys = 0; 246 } 247 248 // First prefer the paired physreg. 249 if (PairedPhys && 250 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 251 Hints.push_back(PairedPhys); 252 253 // Then prefer even or odd registers. 254 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 255 unsigned Reg = Order[I]; 256 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 257 continue; 258 // Don't provide hints that are paired to a reserved register. 259 unsigned Paired = getPairedGPR(Reg, !Odd, this); 260 if (!Paired || MRI.isReserved(Paired)) 261 continue; 262 Hints.push_back(Reg); 263 } 264 } 265 266 void 267 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 268 MachineFunction &MF) const { 269 MachineRegisterInfo *MRI = &MF.getRegInfo(); 270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 271 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 272 Hint.first == (unsigned)ARMRI::RegPairEven) && 273 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 274 // If 'Reg' is one of the even / odd register pair and it's now changed 275 // (e.g. coalesced) into a different register. The other register of the 276 // pair allocation hint must be updated to reflect the relationship 277 // change. 278 unsigned OtherReg = Hint.second; 279 Hint = MRI->getRegAllocationHint(OtherReg); 280 if (Hint.second == Reg) 281 // Make sure the pair has not already divorced. 282 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 283 } 284 } 285 286 bool 287 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 288 // CortexA9 has a Write-after-write hazard for NEON registers. 289 if (!STI.isLikeA9()) 290 return false; 291 292 switch (RC->getID()) { 293 case ARM::DPRRegClassID: 294 case ARM::DPR_8RegClassID: 295 case ARM::DPR_VFP2RegClassID: 296 case ARM::QPRRegClassID: 297 case ARM::QPR_8RegClassID: 298 case ARM::QPR_VFP2RegClassID: 299 case ARM::SPRRegClassID: 300 case ARM::SPR_8RegClassID: 301 // Avoid reusing S, D, and Q registers. 302 // Don't increase register pressure for QQ and QQQQ. 303 return true; 304 default: 305 return false; 306 } 307 } 308 309 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 310 const MachineFrameInfo *MFI = MF.getFrameInfo(); 311 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 312 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 313 314 // When outgoing call frames are so large that we adjust the stack pointer 315 // around the call, we can no longer use the stack pointer to reach the 316 // emergency spill slot. 317 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 318 return true; 319 320 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 321 // negative range for ldr/str (255), and thumb1 is positive offsets only. 322 // It's going to be better to use the SP or Base Pointer instead. When there 323 // are variable sized objects, we can't reference off of the SP, so we 324 // reserve a Base Pointer. 325 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 326 // Conservatively estimate whether the negative offset from the frame 327 // pointer will be sufficient to reach. If a function has a smallish 328 // frame, it's less likely to have lots of spills and callee saved 329 // space, so it's all more likely to be within range of the frame pointer. 330 // If it's wrong, the scavenger will still enable access to work, it just 331 // won't be optimal. 332 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 333 return false; 334 return true; 335 } 336 337 return false; 338 } 339 340 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 341 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 342 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 343 // We can't realign the stack if: 344 // 1. Dynamic stack realignment is explicitly disabled, 345 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 346 // 3. There are VLAs in the function and the base pointer is disabled. 347 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 348 return false; 349 if (AFI->isThumb1OnlyFunction()) 350 return false; 351 // Stack realignment requires a frame pointer. If we already started 352 // register allocation with frame pointer elimination, it is too late now. 353 if (!MRI->canReserveReg(FramePtr)) 354 return false; 355 // We may also need a base pointer if there are dynamic allocas or stack 356 // pointer adjustments around calls. 357 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 358 return true; 359 // A base pointer is required and allowed. Check that it isn't too late to 360 // reserve it. 361 return MRI->canReserveReg(BasePtr); 362 } 363 364 bool ARMBaseRegisterInfo:: 365 needsStackRealignment(const MachineFunction &MF) const { 366 const MachineFrameInfo *MFI = MF.getFrameInfo(); 367 const Function *F = MF.getFunction(); 368 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 369 bool requiresRealignment = 370 ((MFI->getMaxAlignment() > StackAlign) || 371 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 372 Attribute::StackAlignment)); 373 374 return requiresRealignment && canRealignStack(MF); 375 } 376 377 bool ARMBaseRegisterInfo:: 378 cannotEliminateFrame(const MachineFunction &MF) const { 379 const MachineFrameInfo *MFI = MF.getFrameInfo(); 380 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 381 return true; 382 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 383 || needsStackRealignment(MF); 384 } 385 386 unsigned 387 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 388 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 389 390 if (TFI->hasFP(MF)) 391 return FramePtr; 392 return ARM::SP; 393 } 394 395 /// emitLoadConstPool - Emits a load from constpool to materialize the 396 /// specified immediate. 397 void ARMBaseRegisterInfo:: 398 emitLoadConstPool(MachineBasicBlock &MBB, 399 MachineBasicBlock::iterator &MBBI, 400 DebugLoc dl, 401 unsigned DestReg, unsigned SubIdx, int Val, 402 ARMCC::CondCodes Pred, 403 unsigned PredReg, unsigned MIFlags) const { 404 MachineFunction &MF = *MBB.getParent(); 405 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 406 MachineConstantPool *ConstantPool = MF.getConstantPool(); 407 const Constant *C = 408 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 409 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 410 411 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 412 .addReg(DestReg, getDefRegState(true), SubIdx) 413 .addConstantPoolIndex(Idx) 414 .addImm(0).addImm(Pred).addReg(PredReg) 415 .setMIFlags(MIFlags); 416 } 417 418 bool ARMBaseRegisterInfo::mayOverrideLocalAssignment() const { 419 // The native linux build hits a downstream codegen bug when this is enabled. 420 return STI.isTargetDarwin(); 421 } 422 423 bool ARMBaseRegisterInfo:: 424 requiresRegisterScavenging(const MachineFunction &MF) const { 425 return true; 426 } 427 428 bool ARMBaseRegisterInfo:: 429 trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 430 return true; 431 } 432 433 bool ARMBaseRegisterInfo:: 434 requiresFrameIndexScavenging(const MachineFunction &MF) const { 435 return true; 436 } 437 438 bool ARMBaseRegisterInfo:: 439 requiresVirtualBaseRegisters(const MachineFunction &MF) const { 440 return true; 441 } 442 443 int64_t ARMBaseRegisterInfo:: 444 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 445 const MCInstrDesc &Desc = MI->getDesc(); 446 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 447 int64_t InstrOffs = 0; 448 int Scale = 1; 449 unsigned ImmIdx = 0; 450 switch (AddrMode) { 451 case ARMII::AddrModeT2_i8: 452 case ARMII::AddrModeT2_i12: 453 case ARMII::AddrMode_i12: 454 InstrOffs = MI->getOperand(Idx+1).getImm(); 455 Scale = 1; 456 break; 457 case ARMII::AddrMode5: { 458 // VFP address mode. 459 const MachineOperand &OffOp = MI->getOperand(Idx+1); 460 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 461 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 462 InstrOffs = -InstrOffs; 463 Scale = 4; 464 break; 465 } 466 case ARMII::AddrMode2: { 467 ImmIdx = Idx+2; 468 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 469 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 470 InstrOffs = -InstrOffs; 471 break; 472 } 473 case ARMII::AddrMode3: { 474 ImmIdx = Idx+2; 475 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 476 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 477 InstrOffs = -InstrOffs; 478 break; 479 } 480 case ARMII::AddrModeT1_s: { 481 ImmIdx = Idx+1; 482 InstrOffs = MI->getOperand(ImmIdx).getImm(); 483 Scale = 4; 484 break; 485 } 486 default: 487 llvm_unreachable("Unsupported addressing mode!"); 488 } 489 490 return InstrOffs * Scale; 491 } 492 493 /// needsFrameBaseReg - Returns true if the instruction's frame index 494 /// reference would be better served by a base register other than FP 495 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 496 /// references it should create new base registers for. 497 bool ARMBaseRegisterInfo:: 498 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 499 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 500 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 501 } 502 503 // It's the load/store FI references that cause issues, as it can be difficult 504 // to materialize the offset if it won't fit in the literal field. Estimate 505 // based on the size of the local frame and some conservative assumptions 506 // about the rest of the stack frame (note, this is pre-regalloc, so 507 // we don't know everything for certain yet) whether this offset is likely 508 // to be out of range of the immediate. Return true if so. 509 510 // We only generate virtual base registers for loads and stores, so 511 // return false for everything else. 512 unsigned Opc = MI->getOpcode(); 513 switch (Opc) { 514 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 515 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 516 case ARM::t2LDRi12: case ARM::t2LDRi8: 517 case ARM::t2STRi12: case ARM::t2STRi8: 518 case ARM::VLDRS: case ARM::VLDRD: 519 case ARM::VSTRS: case ARM::VSTRD: 520 case ARM::tSTRspi: case ARM::tLDRspi: 521 break; 522 default: 523 return false; 524 } 525 526 // Without a virtual base register, if the function has variable sized 527 // objects, all fixed-size local references will be via the frame pointer, 528 // Approximate the offset and see if it's legal for the instruction. 529 // Note that the incoming offset is based on the SP value at function entry, 530 // so it'll be negative. 531 MachineFunction &MF = *MI->getParent()->getParent(); 532 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 533 MachineFrameInfo *MFI = MF.getFrameInfo(); 534 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 535 536 // Estimate an offset from the frame pointer. 537 // Conservatively assume all callee-saved registers get pushed. R4-R6 538 // will be earlier than the FP, so we ignore those. 539 // R7, LR 540 int64_t FPOffset = Offset - 8; 541 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 542 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 543 FPOffset -= 80; 544 // Estimate an offset from the stack pointer. 545 // The incoming offset is relating to the SP at the start of the function, 546 // but when we access the local it'll be relative to the SP after local 547 // allocation, so adjust our SP-relative offset by that allocation size. 548 Offset = -Offset; 549 Offset += MFI->getLocalFrameSize(); 550 // Assume that we'll have at least some spill slots allocated. 551 // FIXME: This is a total SWAG number. We should run some statistics 552 // and pick a real one. 553 Offset += 128; // 128 bytes of spill slots 554 555 // If there is a frame pointer, try using it. 556 // The FP is only available if there is no dynamic realignment. We 557 // don't know for sure yet whether we'll need that, so we guess based 558 // on whether there are any local variables that would trigger it. 559 unsigned StackAlign = TFI->getStackAlignment(); 560 if (TFI->hasFP(MF) && 561 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 562 if (isFrameOffsetLegal(MI, FPOffset)) 563 return false; 564 } 565 // If we can reference via the stack pointer, try that. 566 // FIXME: This (and the code that resolves the references) can be improved 567 // to only disallow SP relative references in the live range of 568 // the VLA(s). In practice, it's unclear how much difference that 569 // would make, but it may be worth doing. 570 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 571 return false; 572 573 // The offset likely isn't legal, we want to allocate a virtual base register. 574 return true; 575 } 576 577 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 578 /// be a pointer to FrameIdx at the beginning of the basic block. 579 void ARMBaseRegisterInfo:: 580 materializeFrameBaseRegister(MachineBasicBlock *MBB, 581 unsigned BaseReg, int FrameIdx, 582 int64_t Offset) const { 583 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 584 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 585 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 586 587 MachineBasicBlock::iterator Ins = MBB->begin(); 588 DebugLoc DL; // Defaults to "unknown" 589 if (Ins != MBB->end()) 590 DL = Ins->getDebugLoc(); 591 592 const MachineFunction &MF = *MBB->getParent(); 593 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 594 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 595 const MCInstrDesc &MCID = TII.get(ADDriOpc); 596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 597 598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 599 .addFrameIndex(FrameIdx).addImm(Offset)); 600 601 if (!AFI->isThumb1OnlyFunction()) 602 AddDefaultCC(MIB); 603 } 604 605 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 606 int64_t Offset) const { 607 MachineBasicBlock &MBB = *MI.getParent(); 608 MachineFunction &MF = *MBB.getParent(); 609 const ARMBaseInstrInfo &TII = 610 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 611 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 612 int Off = Offset; // ARM doesn't need the general 64-bit offsets 613 unsigned i = 0; 614 615 assert(!AFI->isThumb1OnlyFunction() && 616 "This resolveFrameIndex does not support Thumb1!"); 617 618 while (!MI.getOperand(i).isFI()) { 619 ++i; 620 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 621 } 622 bool Done = false; 623 if (!AFI->isThumbFunction()) 624 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 625 else { 626 assert(AFI->isThumb2Function()); 627 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 628 } 629 assert (Done && "Unable to resolve frame index!"); 630 (void)Done; 631 } 632 633 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 634 int64_t Offset) const { 635 const MCInstrDesc &Desc = MI->getDesc(); 636 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 637 unsigned i = 0; 638 639 while (!MI->getOperand(i).isFI()) { 640 ++i; 641 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 642 } 643 644 // AddrMode4 and AddrMode6 cannot handle any offset. 645 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 646 return Offset == 0; 647 648 unsigned NumBits = 0; 649 unsigned Scale = 1; 650 bool isSigned = true; 651 switch (AddrMode) { 652 case ARMII::AddrModeT2_i8: 653 case ARMII::AddrModeT2_i12: 654 // i8 supports only negative, and i12 supports only positive, so 655 // based on Offset sign, consider the appropriate instruction 656 Scale = 1; 657 if (Offset < 0) { 658 NumBits = 8; 659 Offset = -Offset; 660 } else { 661 NumBits = 12; 662 } 663 break; 664 case ARMII::AddrMode5: 665 // VFP address mode. 666 NumBits = 8; 667 Scale = 4; 668 break; 669 case ARMII::AddrMode_i12: 670 case ARMII::AddrMode2: 671 NumBits = 12; 672 break; 673 case ARMII::AddrMode3: 674 NumBits = 8; 675 break; 676 case ARMII::AddrModeT1_s: 677 NumBits = 5; 678 Scale = 4; 679 isSigned = false; 680 break; 681 default: 682 llvm_unreachable("Unsupported addressing mode!"); 683 } 684 685 Offset += getFrameIndexInstrOffset(MI, i); 686 // Make sure the offset is encodable for instructions that scale the 687 // immediate. 688 if ((Offset & (Scale-1)) != 0) 689 return false; 690 691 if (isSigned && Offset < 0) 692 Offset = -Offset; 693 694 unsigned Mask = (1 << NumBits) - 1; 695 if ((unsigned)Offset <= Mask * Scale) 696 return true; 697 698 return false; 699 } 700 701 void 702 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 703 int SPAdj, unsigned FIOperandNum, 704 RegScavenger *RS) const { 705 MachineInstr &MI = *II; 706 MachineBasicBlock &MBB = *MI.getParent(); 707 MachineFunction &MF = *MBB.getParent(); 708 const ARMBaseInstrInfo &TII = 709 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 710 const ARMFrameLowering *TFI = 711 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 712 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 713 assert(!AFI->isThumb1OnlyFunction() && 714 "This eliminateFrameIndex does not support Thumb1!"); 715 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 716 unsigned FrameReg; 717 718 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 719 720 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 721 // call frame setup/destroy instructions have already been eliminated. That 722 // means the stack pointer cannot be used to access the emergency spill slot 723 // when !hasReservedCallFrame(). 724 #ifndef NDEBUG 725 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 726 assert(TFI->hasReservedCallFrame(MF) && 727 "Cannot use SP to access the emergency spill slot in " 728 "functions without a reserved call frame"); 729 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 730 "Cannot use SP to access the emergency spill slot in " 731 "functions with variable sized frame objects"); 732 } 733 #endif // NDEBUG 734 735 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 736 737 // Modify MI as necessary to handle as much of 'Offset' as possible 738 bool Done = false; 739 if (!AFI->isThumbFunction()) 740 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 741 else { 742 assert(AFI->isThumb2Function()); 743 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 744 } 745 if (Done) 746 return; 747 748 // If we get here, the immediate doesn't fit into the instruction. We folded 749 // as much as possible above, handle the rest, providing a register that is 750 // SP+LargeImm. 751 assert((Offset || 752 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 753 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 754 "This code isn't needed if offset already handled!"); 755 756 unsigned ScratchReg = 0; 757 int PIdx = MI.findFirstPredOperandIdx(); 758 ARMCC::CondCodes Pred = (PIdx == -1) 759 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 760 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 761 if (Offset == 0) 762 // Must be addrmode4/6. 763 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 764 else { 765 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 766 if (!AFI->isThumbFunction()) 767 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 768 Offset, Pred, PredReg, TII); 769 else { 770 assert(AFI->isThumb2Function()); 771 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 772 Offset, Pred, PredReg, TII); 773 } 774 // Update the original instruction to use the scratch register. 775 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 776 } 777 } 778