| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 35 if (getOpcode() < ISD::BUILTIN_OP_END)
53 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
55 case ISD::PREFETCH: return "Prefetch";
56 case ISD::ATOMIC_FENCE: return "AtomicFence";
57 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
58 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
59 case ISD::ATOMIC_SWAP: return "AtomicSwap";
60 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
61 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
62 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"
[all...] |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
199 if (Op.getOpcode() == ISD::LOAD) {
201 ISD::LoadExtType ExtType = LD->getExtensionType();
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
208 } else if (Op.getOpcode() == ISD::STORE) {
238 case ISD::ADD:
239 case ISD::SUB
[all...] |
| LegalizeVectorTypes.cpp | 51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break
[all...] |
| LegalizeIntegerTypes.cpp | 52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break
[all...] |
| LegalizeDAG.cpp | 278 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
291 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
308 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
325 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
366 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
378 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
390 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
406 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
414 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr
[all...] |
| TargetLowering.cpp | 119 ISD::CondCode &CCCode,
127 case ISD::SETEQ:
128 case ISD::SETOEQ:
132 case ISD::SETNE:
133 case ISD::SETUNE:
137 case ISD::SETGE:
138 case ISD::SETOGE:
142 case ISD::SETLT:
143 case ISD::SETOLT:
147 case ISD::SETLE
[all...] |
| DAGCombiner.cpp | 172 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
175 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
193 ISD::NodeType ExtType);
293 SDValue N3, ISD::CondCode CC,
295 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
453 if (Op.getOpcode() == ISD::FNEG) return 2;
463 case ISD::ConstantFP:
467 case ISD::FADD:
473 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
483 case ISD::FSUB
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 187 int ISD = TLI->InstructionOpcodeToISD(Opcode);
188 assert(ISD && "Invalid opcode");
192 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
193 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
194 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
195 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
200 int Idx = CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second);
208 { ISD::SHL, MVT::v4i32, 1 },
209 { ISD::SRL, MVT::v4i32, 1 },
210 { ISD::SRA, MVT::v4i32, 1 }
[all...] |
| X86CallingConv.h | 24 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
|
| X86ISelLowering.cpp | 88 if (Vec.getOpcode() == ISD::UNDEF)
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
138 if (Vec.getOpcode() == ISD::UNDEF)
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand)
[all...] |
| /external/llvm/include/llvm/Target/ |
| CostTable.h | 23 int ISD;
30 int CostTableLookup(const CostTblEntry<TypeTy> *Tbl, unsigned len, int ISD,
33 if (ISD == Tbl[i].ISD && Ty == Tbl[i].Type)
42 int CostTableLookup(const CostTblEntry<TypeTy>(&Tbl)[N], int ISD,
44 return CostTableLookup(Tbl, N, ISD, Ty);
50 int ISD;
60 unsigned len, int ISD, CompareTy Dst,
63 if (ISD == Tbl[i].ISD && Src == Tbl[i].Src && Dst == Tbl[i].Dst
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 185 int ISD = TLI->InstructionOpcodeToISD(Opcode);
186 assert(ISD && "Invalid opcode");
191 { ISD::FP_ROUND, MVT::v2f64, 2 },
192 { ISD::FP_EXTEND, MVT::v2f32, 2 },
193 { ISD::FP_EXTEND, MVT::v4f32, 4 }
196 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
197 ISD == ISD::FP_EXTEND)) {
199 int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second)
[all...] |
| ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Expand);
112 setOperationAction(ISD::SUBC, VT, Expand);
113 setOperationAction(ISD::ADDE, VT, Expand);
114 setOperationAction(ISD::ADDC, VT, Expand);
115 setOperationAction(ISD::BRCOND, VT, Custom);
116 setOperationAction(ISD::BR_JT, VT, Expand);
117 setOperationAction(ISD::BRIND, VT, Expand);
119 setOperationAction(ISD::SREM, VT, Expand);
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand)
[all...] |
| AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
39 setOperationAction(ISD::UDIV, MVT::i32, Expand);
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
41 setOperationAction(ISD::UREM, MVT::i32, Expand);
52 const SmallVectorImpl<ISD::InputArg> &Ins,
68 const SmallVectorImpl<ISD::OutputArg> &Outs,
89 case ISD::SDIV: return LowerSDIV(Op, DAG)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Expand);
112 setOperationAction(ISD::SUBC, VT, Expand);
113 setOperationAction(ISD::ADDE, VT, Expand);
114 setOperationAction(ISD::ADDC, VT, Expand);
115 setOperationAction(ISD::BRCOND, VT, Custom);
116 setOperationAction(ISD::BR_JT, VT, Expand);
117 setOperationAction(ISD::BRIND, VT, Expand);
119 setOperationAction(ISD::SREM, VT, Expand);
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand)
[all...] |
| AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
39 setOperationAction(ISD::UDIV, MVT::i32, Expand);
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
41 setOperationAction(ISD::UREM, MVT::i32, Expand);
52 const SmallVectorImpl<ISD::InputArg> &Ins,
68 const SmallVectorImpl<ISD::OutputArg> &Outs,
89 case ISD::SDIV: return LowerSDIV(Op, DAG)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 297 int ISD = TLI->InstructionOpcodeToISD(Opcode);
298 assert(ISD && "Invalid opcode");
308 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
309 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
311 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
313 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
316 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
317 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 67 ISD::ArgFlagsTy ArgFlags, CCState &State);
72 ISD::ArgFlagsTy ArgFlags, CCState &State);
77 ISD::ArgFlagsTy ArgFlags, CCState &State);
82 ISD::ArgFlagsTy ArgFlags, CCState &State);
87 ISD::ArgFlagsTy ArgFlags, CCState &State);
92 ISD::ArgFlagsTy ArgFlags, CCState &State);
97 ISD::ArgFlagsTy ArgFlags, CCState &State) {
147 ISD::ArgFlagsTy ArgFlags, CCState &State) {
185 ISD::ArgFlagsTy ArgFlags, CCState &State) {
203 ISD::ArgFlagsTy ArgFlags, CCState &State)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
111 setOperationAction(ISD::Constant, MVT::i32, Legal);
112 setOperationAction(ISD::Constant, MVT::i64, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
114 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
116 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
117 setOperationAction(ISD::BRIND, MVT::Other, Expand);
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal)
[all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 190 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
191 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
197 return TLI->isTypeLegal(VT) && TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
294 int ISD = TLI->InstructionOpcodeToISD(Opcode);
295 assert(ISD && "Invalid opcode");
304 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
314 if (!TLI->isOperationExpand(ISD, LT.second)) {
361 int ISD = TLI->InstructionOpcodeToISD(Opcode);
362 assert(ISD && "Invalid opcode");
386 TLI->isOperationLegalOrPromote(ISD, DstLT.second)
[all...] |
| TargetLoweringBase.cpp | 640 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
641 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
642 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
643 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
644 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
645 CCs[RTLIB::UNE_F32] = ISD::SETNE;
646 CCs[RTLIB::UNE_F64] = ISD::SETNE;
647 CCs[RTLIB::UNE_F128] = ISD::SETNE;
648 CCs[RTLIB::OGE_F32] = ISD::SETGE
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 80 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
81 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
83 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
92 setOperationAction(ISD::SRA, MVT::i8, Custom);
93 setOperationAction(ISD::SHL, MVT::i8, Custom);
94 setOperationAction(ISD::SRL, MVT::i8, Custom)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 57 case ISD::SDIV:
58 case ISD::UDIV:
59 case ISD::SRA:
60 case ISD::SRL:
61 case ISD::MUL:
62 case ISD::ADD:
63 case ISD::SUB:
64 case ISD::SHL:
83 namespace ISD {
99 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the lo
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 55 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
71 setOperationAction(ISD::ADD, VecTys[i], Legal);
72 setOperationAction(ISD::SUB, VecTys[i], Legal);
73 setOperationAction(ISD::LOAD, VecTys[i], Legal);
74 setOperationAction(ISD::STORE, VecTys[i], Legal);
75 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
78 setTargetDAGCombine(ISD::SHL)
[all...] |
