| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 693 { ISD::SETCC, MVT::v2f64, 1 },
694 { ISD::SETCC, MVT::v4f32, 1 },
695 { ISD::SETCC, MVT::v2i64, 1 },
696 { ISD::SETCC, MVT::v4i32, 1 },
697 { ISD::SETCC, MVT::v8i16, 1 },
698 { ISD::SETCC, MVT::v16i8, 1 },
702 { ISD::SETCC, MVT::v4f64, 1 },
703 { ISD::SETCC, MVT::v8f32, 1 },
705 { ISD::SETCC, MVT::v4i64, 4 },
706 { ISD::SETCC, MVT::v8i32, 4 }
[all...] |
| X86ISelLowering.cpp | 243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
550 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
| X86ISelLowering.h | 98 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
100 SETCC,
105 // Same as SETCC except it's materialized with a sbb and the value is all
109 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
608 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 325 /// Much like the scalar select and setcc, each bit in the condition selects
338 /// SetCC operator - This evaluates to a true value iff the condition is
344 SETCC,
530 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 32 SETCC,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 109 setOperationAction(ISD::SETCC, MVT::i8, Custom);
110 setOperationAction(ISD::SETCC, MVT::i16, Custom);
193 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
274 if (Cond->getOpcode() == ISD::SETCC) {
335 // Turn it into a scalar SETCC.
336 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
374 // Turn it into a scalar SETCC.
375 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
577 case ISD::SETCC:
[all...] |
| LegalizeVectorOps.cpp | 267 case ISD::SETCC:
656 case ISD::SETCC:
[all...] |
| DAGCombiner.cpp | 590 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
592 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
597 if (N.getOpcode() == ISD::SETCC) {
615 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| TargetLowering.cpp | 116 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
122 && "Unsupported setcc type!");
194 default: llvm_unreachable("Do not know how to soften this setcc!");
206 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
211 NewLHS = DAG.getNode(ISD::SETCC, dl,
[all...] |
| SelectionDAGDumper.cpp | 193 case ISD::SETCC: return "setcc";
297 default: llvm_unreachable("Unknown setcc condition!");
|
| LegalizeDAG.cpp | 47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| LegalizeFloatTypes.cpp | 633 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 114 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
115 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
222 setTargetDAGCombine(ISD::SETCC);
774 if (Intr->getOpcode() == ISD::SETCC) {
776 SDNode *SetCC = Intr;
777 assert(SetCC->getConstantOperandVal(1) == 1);
778 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
780 Intr = SetCC->getOperand(0).getNode();
[all...] |
| R600ISelLowering.cpp | 66 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
67 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
82 setOperationAction(ISD::SETCC, MVT::i32, Expand);
83 setOperationAction(ISD::SETCC, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 81 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
220 setOperationAction(ISD::SETCC, MVT::i64, Legal);
282 setOperationAction(ISD::SETCC, Ty, Legal);
319 setOperationAction(ISD::SETCC, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 215 // setcc operations results (slt, sgt, ...).
233 // Used by legalize types to correctly generate the setcc result.
234 // Without this, every float setcc comes with a AND/OR with the result,
237 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
251 setOperationAction(ISD::SETCC, MVT::f32, Custom);
252 setOperationAction(ISD::SETCC, MVT::f64, Custom);
504 // Creates and returns an FPCmp node from a setcc node.
505 // Returns Op if setcc is not a floating point comparison.
507 // must be a SETCC node
508 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
519 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
