| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 75 auto &MBB = *Root.getParent();
76 auto &MF = *MBB.getParent();
90 if (!GenericAddrDef || GenericAddrDef->getParent() != &MBB ||
106 auto &MBB = *Root.getParent();
107 auto &MF = *MBB.getParent();
118 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
130 for (auto &MBB : MF) {
132 auto BlockIter = MBB.begin();
134 while (BlockIter != MBB.end()) {
|
| NVPTXInstrInfo.cpp | 34 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
36 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
63 BuildMI(MBB, I, DL, get(Op), DestReg)
125 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
149 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
152 MachineBasicBlock::iterator I = MBB.end();
153 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
160 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
178 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
205 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineBranchProbabilityInfo.cpp | 54 MachineBranchProbabilityInfo::getHotSucc(MachineBasicBlock *MBB) const {
57 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
58 E = MBB->succ_end(); I != E; ++I) {
59 auto Prob = getEdgeProbability(MBB, I);
67 if (getEdgeProbability(MBB, MaxSucc) >= HotProb)
78 OS << "edge MBB#" << Src->getNumber() << " -> MBB#" << Dst->getNumber()
|
| MachineTraceMetrics.cpp | 83 /// Compute the resource usage in basic block MBB.
85 MachineTraceMetrics::getResources(const MachineBasicBlock *MBB) {
86 assert(MBB && "No basic block");
87 FixedBlockInfo *FBI = &BlockInfo[MBB->getNumber()];
99 for (const auto &MI : *MBB) {
123 unsigned PROffset = MBB->getNumber() * PRKinds;
157 MachineTraceMetrics::Ensemble::getLoopFor(const MachineBasicBlock *MBB) const {
158 return MTM.Loops->getLoopFor(MBB);
161 // Update resource-related information in the TraceBlockInfo for MBB.
162 // Only update resources related to the trace above MBB
[all...] |
| PHIElimination.cpp | 73 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
74 void LowerPHINode(MachineBasicBlock &MBB,
86 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
91 bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
92 bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
146 for (auto &MBB : MF)
147 Changed |= SplitPHIEdges(MF, MBB, MLI);
154 for (auto &MBB : MF)
155 Changed |= EliminatePHINodes(MF, MBB);
186 MachineBasicBlock &MBB) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 51 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
54 BuildMI(MBB, MI, DL, get(Mips::NOP));
57 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
59 MachineFunction &MF = *MBB.getParent();
78 // MBB.
86 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
92 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
98 MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
116 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB
[all...] |
| MipsSEInstrInfo.cpp | 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
128 BuildMI(MBB, I, DL, get(Mips::WRDSP))
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
180 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
185 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
226 const Function *Func = MBB.getParent()->getFunction();
229 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
232 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
235 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0)
[all...] |
| Mips16InstrInfo.cpp | 61 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
93 void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
100 if (I != MBB.end()) DL = I->getDebugLoc();
101 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
106 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
111 void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB,
118 if (I != MBB.end()) DL = I->getDebugLoc();
119 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
125 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.h | 32 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
36 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
43 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
44 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
50 MachineBasicBlock &MBB,
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 69 MachineBasicBlock& MBB,
76 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), SPReg)
84 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::LOAD_I32), SPReg)
90 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
92 BuildMI(MBB, InsertPt, DL,
98 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
102 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32)
110 MachineFunction &MF, MachineBasicBlock &MBB,
119 adjustStackPointer(Amount, IsDestroy, MF, MBB,
121 MBB.erase(I)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 127 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator I = MBB.end();
135 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
136 while (I != MBB.begin()) {
159 while (std::next(I) != MBB.end())
165 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
168 I = MBB.end();
169 UnCondBrIter = MBB.end();
185 if (AllowModify && UnCondBrIter != MBB.end() &&
186 MBB.isLayoutSuccessor(TargetBB))
[all...] |
| SparcFrameLowering.cpp | 41 MachineBasicBlock &MBB,
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
86 MachineBasicBlock &MBB) const {
89 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported")
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 37 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
43 if (MI != MBB.end()) DL = MI->getDebugLoc();
44 MachineFunction &MF = *MBB.getParent();
53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
64 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
70 if (MI != MBB.end()) DL = MI->getDebugLoc();
71 MachineFunction &MF = *MBB.getParent();
80 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
83 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 77 MachineBasicBlock *MBB = &*MBBb;
79 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
110 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
120 MII = MBB->erase(MI);
150 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr),
153 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(),
163 MII = MBB->erase(MI);
191 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr)
[all...] |
| HexagonFixupHwLoops.cpp | 110 for (const MachineBasicBlock &MBB : MF) {
111 if (MBB.getAlignment()) {
115 int ByteAlign = (1u << MBB.getAlignment()) - 1;
119 BlockToInstOffset[&MBB] = InstOffset;
120 for (const MachineInstr &MI : MBB)
128 for (MachineBasicBlock &MBB : MF) {
129 InstOffset = BlockToInstOffset[&MBB];
132 MachineBasicBlock::iterator MII = MBB.begin();
133 MachineBasicBlock::iterator MIE = MBB.end();
146 MII = MBB.erase(MII)
[all...] |
| HexagonSplitConst32AndConst64.cpp | 84 MachineBasicBlock *MBB = &*MBBb;
86 MachineBasicBlock::iterator MII = MBB->begin();
87 MachineBasicBlock::iterator MIE = MBB->end ();
96 BuildMI (*MBB, MII, MI->getDebugLoc(),
98 BuildMI (*MBB, MII, MI->getDebugLoc(),
100 // MBB->erase returns the iterator to the next instruction, which is the
102 MII = MBB->erase (MI);
120 BuildMI(*MBB, MII, MI->getDebugLoc(),
122 MII = MBB->erase (MI);
145 BuildMI(*MBB, MII, MI->getDebugLoc()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 170 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
194 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
199 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
200 if (I == MBB.end())
210 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
233 if (SecondLastInst && I != MBB.begin() &&
277 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
289 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
293 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.h | 41 void copyPhysReg(MachineBasicBlock &MBB,
45 void storeRegToStackSlot(MachineBasicBlock &MBB,
51 void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
| Thumb1FrameLowering.cpp | 42 emitSPUpdate(MachineBasicBlock &MBB,
47 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
53 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
83 MBB.erase(I);
87 MachineBasicBlock &MBB) const {
88 MachineBasicBlock::iterator MBBI = MBB.begin();
122 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
127 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| ThumbRegisterInfo.cpp | 62 static void emitThumb1LoadConstPool(MachineBasicBlock &MBB,
68 MachineFunction &MF = *MBB.getParent();
73 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
82 static void emitThumb2LoadConstPool(MachineBasicBlock &MBB,
88 MachineFunction &MF = *MBB.getParent();
92 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
95 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
104 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl,
107 MachineFunction &MF = *MBB.getParent()
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineBlockFrequencyInfo.h | 1 //===- MachineBlockFrequencyInfo.h - MBB Frequency Analysis -*- C++ -*-----===//
51 BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const;
63 const MachineBasicBlock *MBB) const;
|
| /external/llvm/lib/Target/BPF/ |
| BPFFrameLowering.cpp | 27 MachineBasicBlock &MBB) const {}
30 MachineBasicBlock &MBB) const {}
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 86 MachineBasicBlock &MBB) const {
87 while (iter != MBB.end()) {
100 MachineBasicBlock::iterator skipFlowControl(MachineBasicBlock *MBB) {
101 MachineBasicBlock::iterator tmp = MBB->end();
102 if (!MBB->size()) {
103 return MBB->end();
109 if (tmp == MBB->begin()) {
118 return MBB->end();
122 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
132 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 147 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
151 const MachineFunction *MF = MBB.getParent();
212 flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB) {
213 for (const MachineInstr &MI : MBB.terminators()) {
239 for (const MachineBasicBlock *Succ : MBB.successors())
248 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
255 DebugLoc DL = MBB.findDebugLoc(MBBI);
263 if (isSub && !isEAXLiveIn(*MBB.getParent()))
266 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
270 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.h | 25 MachineBasicBlock &MBB) const override;
|
