| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 77 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
79 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
82 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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| AArch64StorePairSuppress.cpp | 143 unsigned BaseReg;
145 if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
146 if (PrevBaseReg == BaseReg) {
155 PrevBaseReg = BaseReg;
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| AArch64RegisterInfo.cpp | 306 unsigned BaseReg,
314 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
317 unsigned BaseReg,
329 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
332 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
338 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
350 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
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| AArch64LoadStoreOptimizer.cpp | 121 unsigned BaseReg, int Offset);
880 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
890 if (FirstMI->modifiesRegister(BaseReg, TRI))
946 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
[all...] |
| AArch64InstrInfo.h | 93 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
97 bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
|
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg,
264 return TRI->isFrameOffsetLegal(MI, BaseReg, Offset);
330 unsigned BaseReg = 0;
366 if (UsedBaseReg && lookupCandidateBaseReg(BaseReg, BaseOffset,
369 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
387 BaseReg, BaseOffset, FrameSizeAdjust,
396 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
398 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
404 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
415 assert(BaseReg != 0 && "Unable to allocate virtual base register!")
[all...] |
| ImplicitNullChecks.cpp | 327 unsigned BaseReg, Offset;
328 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
329 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
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| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.cpp | 120 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
127 unsigned DestReg, unsigned BaseReg,
134 (BaseReg != 0 && !isARMLowRegister(BaseReg));
146 assert(BaseReg == ARM::SP && "Unexpected!");
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
177 /// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
183 unsigned DestReg, unsigned BaseReg,
203 // DestReg and BaseReg are low, high or the stack pointer
[all...] |
| ThumbRegisterInfo.h | 52 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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| ARMBaseRegisterInfo.h | 142 unsigned BaseReg, int FrameIdx,
144 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
146 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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| Thumb2InstrInfo.cpp | 218 unsigned DestReg, unsigned BaseReg, int NumBytes,
221 if (NumBytes == 0 && DestReg != BaseReg) {
223 .addReg(BaseReg, RegState::Kill)
233 if (DestReg != ARM::SP && DestReg != BaseReg &&
255 .addReg(BaseReg)
261 // know anything about BaseReg. t2ADDrr is an invalid
264 // do not generate invalid encoding, put BaseReg first.
266 .addReg(BaseReg)
278 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
281 .addReg(BaseReg).setMIFlags(MIFlags))
[all...] |
| ARMBaseInstrInfo.h | 74 /// \p [out] BaseReg and \p [out] InsertedReg contain
77 /// - BaseReg: vreg0:sub0
86 RegSubRegPair &BaseReg,
466 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
470 unsigned DestReg, unsigned BaseReg, int NumBytes,
476 unsigned DestReg, unsigned BaseReg, int NumBytes,
481 unsigned DestReg, unsigned BaseReg,
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| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMBaseRegisterInfo.cpp | 554 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
558 unsigned BaseReg, int FrameIdx,
573 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
575 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
582 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
601 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
604 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
610 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
654 NumBits = (BaseReg == ARM::SP ? 8 : 5);
|
| Thumb2SizeReduction.cpp | 128 // ARM::t2STMIA (with no basereg writeback) has no Thumb1 equivalent.
421 unsigned BaseReg = MI->getOperand(0).getReg();
422 assert(isARMLowRegister(BaseReg));
428 if (MI->getOperand(i).getReg() == BaseReg) {
450 unsigned BaseReg = MI->getOperand(1).getReg();
451 if (BaseReg != ARM::SP)
463 unsigned BaseReg = MI->getOperand(1).getReg();
464 if (BaseReg == ARM::SP &&
469 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 127 unsigned BaseReg, int FrameIdx,
129 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
131 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 189 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
204 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
211 if (IndexReg.getReg() || BaseReg.getReg()) {
213 if (BaseReg.getReg())
|
| X86IntelInstPrinter.cpp | 159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
174 if (BaseReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale;
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
280 unsigned getBaseReg() { return BaseReg; }
384 // If we already have a BaseReg, then assume this is the IndexReg with
386 if (!BaseReg) {
387 BaseReg = TmpReg;
389 assert (!IndexReg && "BaseReg/IndexReg already set!");
421 // If we already have a BaseReg, then assume this is the IndexReg with
423 if (!BaseReg) {
424 BaseReg = TmpReg
1012 unsigned basereg = local
1021 unsigned basereg = local
[all...] |
| X86Operand.h | 55 unsigned BaseReg;
117 return Mem.BaseReg;
502 Res->Mem.BaseReg = 0;
516 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
521 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
529 Res->Mem.BaseReg = BaseReg;
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
229 if ((BaseReg.getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
244 if ((BaseReg.getReg() != 0 &&
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) |
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 245 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
250 bool HasBaseReg = BaseReg.getReg() != 0;
252 BaseReg.getReg() == X86::RIP)
310 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
325 if (BaseReg.getReg()) {
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | [all...] |
