1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the ARM implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMFrameLowering.h" 15 #include "ARMBaseInstrInfo.h" 16 #include "ARMBaseRegisterInfo.h" 17 #include "ARMConstantPoolValue.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "MCTargetDesc/ARMAddressingModes.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/RegisterScavenging.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Target/TargetOptions.h" 32 33 using namespace llvm; 34 35 static cl::opt<bool> 36 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), 37 cl::desc("Align ARM NEON spills in prolog and epilog")); 38 39 static MachineBasicBlock::iterator 40 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 41 unsigned NumAlignedDPRCS2Regs); 42 43 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti) 44 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4), 45 STI(sti) {} 46 47 bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const { 48 // iOS always has a FP for backtracking, force other targets to keep their FP 49 // when doing FastISel. The emitted code is currently superior, and in cases 50 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated. 51 return TargetFrameLowering::noFramePointerElim(MF) || 52 MF.getSubtarget<ARMSubtarget>().useFastISel(); 53 } 54 55 /// hasFP - Return true if the specified function should have a dedicated frame 56 /// pointer register. This is true if the function has variable sized allocas 57 /// or if frame pointer elimination is disabled. 58 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 59 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 60 61 // iOS requires FP not to be clobbered for backtracing purpose. 62 if (STI.isTargetIOS() || STI.isTargetWatchOS()) 63 return true; 64 65 const MachineFrameInfo *MFI = MF.getFrameInfo(); 66 // Always eliminate non-leaf frame pointers. 67 return ((MF.getTarget().Options.DisableFramePointerElim(MF) && 68 MFI->hasCalls()) || 69 RegInfo->needsStackRealignment(MF) || 70 MFI->hasVarSizedObjects() || 71 MFI->isFrameAddressTaken()); 72 } 73 74 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 75 /// not required, we reserve argument space for call sites in the function 76 /// immediately on entry to the current function. This eliminates the need for 77 /// add/sub sp brackets around call sites. Returns true if the call frame is 78 /// included as part of the stack frame. 79 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 80 const MachineFrameInfo *FFI = MF.getFrameInfo(); 81 unsigned CFSize = FFI->getMaxCallFrameSize(); 82 // It's not always a good idea to include the call frame as part of the 83 // stack frame. ARM (especially Thumb) has small immediate offset to 84 // address the stack frame. So a large call frame can cause poor codegen 85 // and may even makes it impossible to scavenge a register. 86 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 87 return false; 88 89 return !MF.getFrameInfo()->hasVarSizedObjects(); 90 } 91 92 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the 93 /// call frame pseudos can be simplified. Unlike most targets, having a FP 94 /// is not sufficient here since we still may reference some objects via SP 95 /// even when FP is available in Thumb2 mode. 96 bool 97 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 98 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 99 } 100 101 static bool isCSRestore(MachineInstr *MI, 102 const ARMBaseInstrInfo &TII, 103 const MCPhysReg *CSRegs) { 104 // Integer spill area is handled with "pop". 105 if (isPopOpcode(MI->getOpcode())) { 106 // The first two operands are predicates. The last two are 107 // imp-def and imp-use of SP. Check everything in between. 108 for (int i = 5, e = MI->getNumOperands(); i != e; ++i) 109 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 110 return false; 111 return true; 112 } 113 if ((MI->getOpcode() == ARM::LDR_POST_IMM || 114 MI->getOpcode() == ARM::LDR_POST_REG || 115 MI->getOpcode() == ARM::t2LDR_POST) && 116 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && 117 MI->getOperand(1).getReg() == ARM::SP) 118 return true; 119 120 return false; 121 } 122 123 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, 124 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 125 const ARMBaseInstrInfo &TII, unsigned DestReg, 126 unsigned SrcReg, int NumBytes, 127 unsigned MIFlags = MachineInstr::NoFlags, 128 ARMCC::CondCodes Pred = ARMCC::AL, 129 unsigned PredReg = 0) { 130 if (isARM) 131 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 132 Pred, PredReg, TII, MIFlags); 133 else 134 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 135 Pred, PredReg, TII, MIFlags); 136 } 137 138 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB, 139 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 140 const ARMBaseInstrInfo &TII, int NumBytes, 141 unsigned MIFlags = MachineInstr::NoFlags, 142 ARMCC::CondCodes Pred = ARMCC::AL, 143 unsigned PredReg = 0) { 144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, 145 MIFlags, Pred, PredReg); 146 } 147 148 static int sizeOfSPAdjustment(const MachineInstr *MI) { 149 int RegSize; 150 switch (MI->getOpcode()) { 151 case ARM::VSTMDDB_UPD: 152 RegSize = 8; 153 break; 154 case ARM::STMDB_UPD: 155 case ARM::t2STMDB_UPD: 156 RegSize = 4; 157 break; 158 case ARM::t2STR_PRE: 159 case ARM::STR_PRE_IMM: 160 return 4; 161 default: 162 llvm_unreachable("Unknown push or pop like instruction"); 163 } 164 165 int count = 0; 166 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 167 // pred) so the list starts at 4. 168 for (int i = MI->getNumOperands() - 1; i >= 4; --i) 169 count += RegSize; 170 return count; 171 } 172 173 static bool WindowsRequiresStackProbe(const MachineFunction &MF, 174 size_t StackSizeInBytes) { 175 const MachineFrameInfo *MFI = MF.getFrameInfo(); 176 const Function *F = MF.getFunction(); 177 unsigned StackProbeSize = (MFI->getStackProtectorIndex() > 0) ? 4080 : 4096; 178 if (F->hasFnAttribute("stack-probe-size")) 179 F->getFnAttribute("stack-probe-size") 180 .getValueAsString() 181 .getAsInteger(0, StackProbeSize); 182 return StackSizeInBytes >= StackProbeSize; 183 } 184 185 namespace { 186 struct StackAdjustingInsts { 187 struct InstInfo { 188 MachineBasicBlock::iterator I; 189 unsigned SPAdjust; 190 bool BeforeFPSet; 191 }; 192 193 SmallVector<InstInfo, 4> Insts; 194 195 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust, 196 bool BeforeFPSet = false) { 197 InstInfo Info = {I, SPAdjust, BeforeFPSet}; 198 Insts.push_back(Info); 199 } 200 201 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) { 202 auto Info = std::find_if(Insts.begin(), Insts.end(), 203 [&](InstInfo &Info) { return Info.I == I; }); 204 assert(Info != Insts.end() && "invalid sp adjusting instruction"); 205 Info->SPAdjust += ExtraBytes; 206 } 207 208 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB, 209 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) { 210 unsigned CFAOffset = 0; 211 for (auto &Info : Insts) { 212 if (HasFP && !Info.BeforeFPSet) 213 return; 214 215 CFAOffset -= Info.SPAdjust; 216 unsigned CFIIndex = MMI.addFrameInst( 217 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset)); 218 BuildMI(MBB, std::next(Info.I), dl, 219 TII.get(TargetOpcode::CFI_INSTRUCTION)) 220 .addCFIIndex(CFIIndex) 221 .setMIFlags(MachineInstr::FrameSetup); 222 } 223 } 224 }; 225 } 226 227 /// Emit an instruction sequence that will align the address in 228 /// register Reg by zero-ing out the lower bits. For versions of the 229 /// architecture that support Neon, this must be done in a single 230 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a 231 /// single instruction. That function only gets called when optimizing 232 /// spilling of D registers on a core with the Neon instruction set 233 /// present. 234 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, 235 const TargetInstrInfo &TII, 236 MachineBasicBlock &MBB, 237 MachineBasicBlock::iterator MBBI, 238 DebugLoc DL, const unsigned Reg, 239 const unsigned Alignment, 240 const bool MustBeSingleInstruction) { 241 const ARMSubtarget &AST = 242 static_cast<const ARMSubtarget &>(MF.getSubtarget()); 243 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops(); 244 const unsigned AlignMask = Alignment - 1; 245 const unsigned NrBitsToZero = countTrailingZeros(Alignment); 246 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported"); 247 if (!AFI->isThumbFunction()) { 248 // if the BFC instruction is available, use that to zero the lower 249 // bits: 250 // bfc Reg, #0, log2(Alignment) 251 // otherwise use BIC, if the mask to zero the required number of bits 252 // can be encoded in the bic immediate field 253 // bic Reg, Reg, Alignment-1 254 // otherwise, emit 255 // lsr Reg, Reg, log2(Alignment) 256 // lsl Reg, Reg, log2(Alignment) 257 if (CanUseBFC) { 258 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) 259 .addReg(Reg, RegState::Kill) 260 .addImm(~AlignMask)); 261 } else if (AlignMask <= 255) { 262 AddDefaultCC( 263 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) 264 .addReg(Reg, RegState::Kill) 265 .addImm(AlignMask))); 266 } else { 267 assert(!MustBeSingleInstruction && 268 "Shouldn't call emitAligningInstructions demanding a single " 269 "instruction to be emitted for large stack alignment for a target " 270 "without BFC."); 271 AddDefaultCC(AddDefaultPred( 272 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) 273 .addReg(Reg, RegState::Kill) 274 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero)))); 275 AddDefaultCC(AddDefaultPred( 276 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) 277 .addReg(Reg, RegState::Kill) 278 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero)))); 279 } 280 } else { 281 // Since this is only reached for Thumb-2 targets, the BFC instruction 282 // should always be available. 283 assert(CanUseBFC); 284 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) 285 .addReg(Reg, RegState::Kill) 286 .addImm(~AlignMask)); 287 } 288 } 289 290 void ARMFrameLowering::emitPrologue(MachineFunction &MF, 291 MachineBasicBlock &MBB) const { 292 MachineBasicBlock::iterator MBBI = MBB.begin(); 293 MachineFrameInfo *MFI = MF.getFrameInfo(); 294 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 295 MachineModuleInfo &MMI = MF.getMMI(); 296 MCContext &Context = MMI.getContext(); 297 const TargetMachine &TM = MF.getTarget(); 298 const MCRegisterInfo *MRI = Context.getRegisterInfo(); 299 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); 300 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); 301 assert(!AFI->isThumb1OnlyFunction() && 302 "This emitPrologue does not support Thumb1!"); 303 bool isARM = !AFI->isThumbFunction(); 304 unsigned Align = STI.getFrameLowering()->getStackAlignment(); 305 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 306 unsigned NumBytes = MFI->getStackSize(); 307 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 308 309 // Debug location must be unknown since the first debug location is used 310 // to determine the end of the prologue. 311 DebugLoc dl; 312 313 unsigned FramePtr = RegInfo->getFrameRegister(MF); 314 315 // Determine the sizes of each callee-save spill areas and record which frame 316 // belongs to which callee-save spill areas. 317 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 318 int FramePtrSpillFI = 0; 319 int D8SpillFI = 0; 320 321 // All calls are tail calls in GHC calling conv, and functions have no 322 // prologue/epilogue. 323 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 324 return; 325 326 StackAdjustingInsts DefCFAOffsetCandidates; 327 bool HasFP = hasFP(MF); 328 329 // Allocate the vararg register save area. 330 if (ArgRegsSaveSize) { 331 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, 332 MachineInstr::FrameSetup); 333 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true); 334 } 335 336 if (!AFI->hasStackFrame() && 337 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) { 338 if (NumBytes - ArgRegsSaveSize != 0) { 339 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize), 340 MachineInstr::FrameSetup); 341 DefCFAOffsetCandidates.addInst(std::prev(MBBI), 342 NumBytes - ArgRegsSaveSize, true); 343 } 344 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP); 345 return; 346 } 347 348 // Determine spill area sizes. 349 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 350 unsigned Reg = CSI[i].getReg(); 351 int FI = CSI[i].getFrameIdx(); 352 switch (Reg) { 353 case ARM::R8: 354 case ARM::R9: 355 case ARM::R10: 356 case ARM::R11: 357 case ARM::R12: 358 if (STI.isTargetDarwin()) { 359 GPRCS2Size += 4; 360 break; 361 } 362 // fallthrough 363 case ARM::R0: 364 case ARM::R1: 365 case ARM::R2: 366 case ARM::R3: 367 case ARM::R4: 368 case ARM::R5: 369 case ARM::R6: 370 case ARM::R7: 371 case ARM::LR: 372 if (Reg == FramePtr) 373 FramePtrSpillFI = FI; 374 GPRCS1Size += 4; 375 break; 376 default: 377 // This is a DPR. Exclude the aligned DPRCS2 spills. 378 if (Reg == ARM::D8) 379 D8SpillFI = FI; 380 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) 381 DPRCSSize += 8; 382 } 383 } 384 385 // Move past area 1. 386 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push; 387 if (GPRCS1Size > 0) { 388 GPRCS1Push = LastPush = MBBI++; 389 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true); 390 } 391 392 // Determine starting offsets of spill areas. 393 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size; 394 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size; 395 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U; 396 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign; 397 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize; 398 int FramePtrOffsetInPush = 0; 399 if (HasFP) { 400 FramePtrOffsetInPush = 401 MFI->getObjectOffset(FramePtrSpillFI) + ArgRegsSaveSize; 402 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 403 NumBytes); 404 } 405 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 406 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 407 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 408 409 // Move past area 2. 410 if (GPRCS2Size > 0) { 411 GPRCS2Push = LastPush = MBBI++; 412 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size); 413 } 414 415 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our 416 // .cfi_offset operations will reflect that. 417 if (DPRGapSize) { 418 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs"); 419 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize)) 420 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize); 421 else { 422 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, 423 MachineInstr::FrameSetup); 424 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize); 425 } 426 } 427 428 // Move past area 3. 429 if (DPRCSSize > 0) { 430 // Since vpush register list cannot have gaps, there may be multiple vpush 431 // instructions in the prologue. 432 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) { 433 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(MBBI)); 434 LastPush = MBBI++; 435 } 436 } 437 438 // Move past the aligned DPRCS2 area. 439 if (AFI->getNumAlignedDPRCS2Regs() > 0) { 440 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs()); 441 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and 442 // leaves the stack pointer pointing to the DPRCS2 area. 443 // 444 // Adjust NumBytes to represent the stack slots below the DPRCS2 area. 445 NumBytes += MFI->getObjectOffset(D8SpillFI); 446 } else 447 NumBytes = DPRCSOffset; 448 449 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) { 450 uint32_t NumWords = NumBytes >> 2; 451 452 if (NumWords < 65536) 453 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) 454 .addImm(NumWords) 455 .setMIFlags(MachineInstr::FrameSetup)); 456 else 457 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) 458 .addImm(NumWords) 459 .setMIFlags(MachineInstr::FrameSetup); 460 461 switch (TM.getCodeModel()) { 462 case CodeModel::Small: 463 case CodeModel::Medium: 464 case CodeModel::Default: 465 case CodeModel::Kernel: 466 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) 467 .addImm((unsigned)ARMCC::AL).addReg(0) 468 .addExternalSymbol("__chkstk") 469 .addReg(ARM::R4, RegState::Implicit) 470 .setMIFlags(MachineInstr::FrameSetup); 471 break; 472 case CodeModel::Large: 473 case CodeModel::JITDefault: 474 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) 475 .addExternalSymbol("__chkstk") 476 .setMIFlags(MachineInstr::FrameSetup); 477 478 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) 479 .addImm((unsigned)ARMCC::AL).addReg(0) 480 .addReg(ARM::R12, RegState::Kill) 481 .addReg(ARM::R4, RegState::Implicit) 482 .setMIFlags(MachineInstr::FrameSetup); 483 break; 484 } 485 486 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), 487 ARM::SP) 488 .addReg(ARM::SP, RegState::Define) 489 .addReg(ARM::R4, RegState::Kill) 490 .setMIFlags(MachineInstr::FrameSetup))); 491 NumBytes = 0; 492 } 493 494 if (NumBytes) { 495 // Adjust SP after all the callee-save spills. 496 if (AFI->getNumAlignedDPRCS2Regs() == 0 && 497 tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes)) 498 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes); 499 else { 500 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 501 MachineInstr::FrameSetup); 502 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes); 503 } 504 505 if (HasFP && isARM) 506 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 507 // Note it's not safe to do this in Thumb2 mode because it would have 508 // taken two instructions: 509 // mov sp, r7 510 // sub sp, #24 511 // If an interrupt is taken between the two instructions, then sp is in 512 // an inconsistent state (pointing to the middle of callee-saved area). 513 // The interrupt handler can end up clobbering the registers. 514 AFI->setShouldRestoreSPFromFP(true); 515 } 516 517 // Set FP to point to the stack slot that contains the previous FP. 518 // For iOS, FP is R7, which has now been stored in spill area 1. 519 // Otherwise, if this is not iOS, all the callee-saved registers go 520 // into spill area 1, including the FP in R11. In either case, it 521 // is in area one and the adjustment needs to take place just after 522 // that push. 523 if (HasFP) { 524 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push); 525 unsigned PushSize = sizeOfSPAdjustment(GPRCS1Push); 526 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, 527 dl, TII, FramePtr, ARM::SP, 528 PushSize + FramePtrOffsetInPush, 529 MachineInstr::FrameSetup); 530 if (FramePtrOffsetInPush + PushSize != 0) { 531 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa( 532 nullptr, MRI->getDwarfRegNum(FramePtr, true), 533 -(ArgRegsSaveSize - FramePtrOffsetInPush))); 534 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 535 .addCFIIndex(CFIIndex) 536 .setMIFlags(MachineInstr::FrameSetup); 537 } else { 538 unsigned CFIIndex = 539 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( 540 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 541 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 542 .addCFIIndex(CFIIndex) 543 .setMIFlags(MachineInstr::FrameSetup); 544 } 545 } 546 547 // Now that the prologue's actual instructions are finalised, we can insert 548 // the necessary DWARF cf instructions to describe the situation. Start by 549 // recording where each register ended up: 550 if (GPRCS1Size > 0) { 551 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push); 552 int CFIIndex; 553 for (const auto &Entry : CSI) { 554 unsigned Reg = Entry.getReg(); 555 int FI = Entry.getFrameIdx(); 556 switch (Reg) { 557 case ARM::R8: 558 case ARM::R9: 559 case ARM::R10: 560 case ARM::R11: 561 case ARM::R12: 562 if (STI.isTargetDarwin()) 563 break; 564 // fallthrough 565 case ARM::R0: 566 case ARM::R1: 567 case ARM::R2: 568 case ARM::R3: 569 case ARM::R4: 570 case ARM::R5: 571 case ARM::R6: 572 case ARM::R7: 573 case ARM::LR: 574 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 575 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI))); 576 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 577 .addCFIIndex(CFIIndex) 578 .setMIFlags(MachineInstr::FrameSetup); 579 break; 580 } 581 } 582 } 583 584 if (GPRCS2Size > 0) { 585 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push); 586 for (const auto &Entry : CSI) { 587 unsigned Reg = Entry.getReg(); 588 int FI = Entry.getFrameIdx(); 589 switch (Reg) { 590 case ARM::R8: 591 case ARM::R9: 592 case ARM::R10: 593 case ARM::R11: 594 case ARM::R12: 595 if (STI.isTargetDarwin()) { 596 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 597 unsigned Offset = MFI->getObjectOffset(FI); 598 unsigned CFIIndex = MMI.addFrameInst( 599 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); 600 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 601 .addCFIIndex(CFIIndex) 602 .setMIFlags(MachineInstr::FrameSetup); 603 } 604 break; 605 } 606 } 607 } 608 609 if (DPRCSSize > 0) { 610 // Since vpush register list cannot have gaps, there may be multiple vpush 611 // instructions in the prologue. 612 MachineBasicBlock::iterator Pos = std::next(LastPush); 613 for (const auto &Entry : CSI) { 614 unsigned Reg = Entry.getReg(); 615 int FI = Entry.getFrameIdx(); 616 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && 617 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { 618 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 619 unsigned Offset = MFI->getObjectOffset(FI); 620 unsigned CFIIndex = MMI.addFrameInst( 621 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); 622 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 623 .addCFIIndex(CFIIndex) 624 .setMIFlags(MachineInstr::FrameSetup); 625 } 626 } 627 } 628 629 // Now we can emit descriptions of where the canonical frame address was 630 // throughout the process. If we have a frame pointer, it takes over the job 631 // half-way through, so only the first few .cfi_def_cfa_offset instructions 632 // actually get emitted. 633 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP); 634 635 if (STI.isTargetELF() && hasFP(MF)) 636 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 637 AFI->getFramePtrSpillOffset()); 638 639 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 640 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 641 AFI->setDPRCalleeSavedGapSize(DPRGapSize); 642 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 643 644 // If we need dynamic stack realignment, do it here. Be paranoid and make 645 // sure if we also have VLAs, we have a base pointer for frame access. 646 // If aligned NEON registers were spilled, the stack has already been 647 // realigned. 648 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 649 unsigned MaxAlign = MFI->getMaxAlignment(); 650 assert(!AFI->isThumb1OnlyFunction()); 651 if (!AFI->isThumbFunction()) { 652 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, 653 false); 654 } else { 655 // We cannot use sp as source/dest register here, thus we're using r4 to 656 // perform the calculations. We're emitting the following sequence: 657 // mov r4, sp 658 // -- use emitAligningInstructions to produce best sequence to zero 659 // -- out lower bits in r4 660 // mov sp, r4 661 // FIXME: It will be better just to find spare register here. 662 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 663 .addReg(ARM::SP, RegState::Kill)); 664 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, 665 false); 666 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 667 .addReg(ARM::R4, RegState::Kill)); 668 } 669 670 AFI->setShouldRestoreSPFromFP(true); 671 } 672 673 // If we need a base pointer, set it up here. It's whatever the value 674 // of the stack pointer is at this point. Any variable size objects 675 // will be allocated after this, so we can still use the base pointer 676 // to reference locals. 677 // FIXME: Clarify FrameSetup flags here. 678 if (RegInfo->hasBasePointer(MF)) { 679 if (isARM) 680 BuildMI(MBB, MBBI, dl, 681 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 682 .addReg(ARM::SP) 683 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 684 else 685 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 686 RegInfo->getBaseRegister()) 687 .addReg(ARM::SP)); 688 } 689 690 // If the frame has variable sized objects then the epilogue must restore 691 // the sp from fp. We can assume there's an FP here since hasFP already 692 // checks for hasVarSizedObjects. 693 if (MFI->hasVarSizedObjects()) 694 AFI->setShouldRestoreSPFromFP(true); 695 } 696 697 void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 698 MachineBasicBlock &MBB) const { 699 MachineFrameInfo *MFI = MF.getFrameInfo(); 700 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 701 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 702 const ARMBaseInstrInfo &TII = 703 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 704 assert(!AFI->isThumb1OnlyFunction() && 705 "This emitEpilogue does not support Thumb1!"); 706 bool isARM = !AFI->isThumbFunction(); 707 708 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 709 int NumBytes = (int)MFI->getStackSize(); 710 unsigned FramePtr = RegInfo->getFrameRegister(MF); 711 712 // All calls are tail calls in GHC calling conv, and functions have no 713 // prologue/epilogue. 714 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 715 return; 716 717 // First put ourselves on the first (from top) terminator instructions. 718 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 719 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 720 721 if (!AFI->hasStackFrame()) { 722 if (NumBytes - ArgRegsSaveSize != 0) 723 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize); 724 } else { 725 // Unwind MBBI to point to first LDR / VLDRD. 726 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 727 if (MBBI != MBB.begin()) { 728 do { 729 --MBBI; 730 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 731 if (!isCSRestore(MBBI, TII, CSRegs)) 732 ++MBBI; 733 } 734 735 // Move SP to start of FP callee save spill area. 736 NumBytes -= (ArgRegsSaveSize + 737 AFI->getGPRCalleeSavedArea1Size() + 738 AFI->getGPRCalleeSavedArea2Size() + 739 AFI->getDPRCalleeSavedGapSize() + 740 AFI->getDPRCalleeSavedAreaSize()); 741 742 // Reset SP based on frame pointer only if the stack frame extends beyond 743 // frame pointer stack slot or target is ELF and the function has FP. 744 if (AFI->shouldRestoreSPFromFP()) { 745 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 746 if (NumBytes) { 747 if (isARM) 748 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 749 ARMCC::AL, 0, TII); 750 else { 751 // It's not possible to restore SP from FP in a single instruction. 752 // For iOS, this looks like: 753 // mov sp, r7 754 // sub sp, #24 755 // This is bad, if an interrupt is taken after the mov, sp is in an 756 // inconsistent state. 757 // Use the first callee-saved register as a scratch register. 758 assert(!MFI->getPristineRegs(MF).test(ARM::R4) && 759 "No scratch register to restore SP from FP!"); 760 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 761 ARMCC::AL, 0, TII); 762 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 763 ARM::SP) 764 .addReg(ARM::R4)); 765 } 766 } else { 767 // Thumb2 or ARM. 768 if (isARM) 769 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 770 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 771 else 772 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 773 ARM::SP) 774 .addReg(FramePtr)); 775 } 776 } else if (NumBytes && 777 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes)) 778 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 779 780 // Increment past our save areas. 781 if (AFI->getDPRCalleeSavedAreaSize()) { 782 MBBI++; 783 // Since vpop register list cannot have gaps, there may be multiple vpop 784 // instructions in the epilogue. 785 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) 786 MBBI++; 787 } 788 if (AFI->getDPRCalleeSavedGapSize()) { 789 assert(AFI->getDPRCalleeSavedGapSize() == 4 && 790 "unexpected DPR alignment gap"); 791 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize()); 792 } 793 794 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 795 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 796 } 797 798 if (ArgRegsSaveSize) 799 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize); 800 } 801 802 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for 803 /// debug info. It's the same as what we use for resolving the code-gen 804 /// references for now. FIXME: This can go wrong when references are 805 /// SP-relative and simple call frames aren't used. 806 int 807 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 808 unsigned &FrameReg) const { 809 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 810 } 811 812 int 813 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 814 int FI, unsigned &FrameReg, 815 int SPAdj) const { 816 const MachineFrameInfo *MFI = MF.getFrameInfo(); 817 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( 818 MF.getSubtarget().getRegisterInfo()); 819 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 820 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 821 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 822 bool isFixed = MFI->isFixedObjectIndex(FI); 823 824 FrameReg = ARM::SP; 825 Offset += SPAdj; 826 827 // SP can move around if there are allocas. We may also lose track of SP 828 // when emergency spilling inside a non-reserved call frame setup. 829 bool hasMovingSP = !hasReservedCallFrame(MF); 830 831 // When dynamically realigning the stack, use the frame pointer for 832 // parameters, and the stack/base pointer for locals. 833 if (RegInfo->needsStackRealignment(MF)) { 834 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 835 if (isFixed) { 836 FrameReg = RegInfo->getFrameRegister(MF); 837 Offset = FPOffset; 838 } else if (hasMovingSP) { 839 assert(RegInfo->hasBasePointer(MF) && 840 "VLAs and dynamic stack alignment, but missing base pointer!"); 841 FrameReg = RegInfo->getBaseRegister(); 842 } 843 return Offset; 844 } 845 846 // If there is a frame pointer, use it when we can. 847 if (hasFP(MF) && AFI->hasStackFrame()) { 848 // Use frame pointer to reference fixed objects. Use it for locals if 849 // there are VLAs (and thus the SP isn't reliable as a base). 850 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) { 851 FrameReg = RegInfo->getFrameRegister(MF); 852 return FPOffset; 853 } else if (hasMovingSP) { 854 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 855 if (AFI->isThumb2Function()) { 856 // Try to use the frame pointer if we can, else use the base pointer 857 // since it's available. This is handy for the emergency spill slot, in 858 // particular. 859 if (FPOffset >= -255 && FPOffset < 0) { 860 FrameReg = RegInfo->getFrameRegister(MF); 861 return FPOffset; 862 } 863 } 864 } else if (AFI->isThumb2Function()) { 865 // Use add <rd>, sp, #<imm8> 866 // ldr <rd>, [sp, #<imm8>] 867 // if at all possible to save space. 868 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 869 return Offset; 870 // In Thumb2 mode, the negative offset is very limited. Try to avoid 871 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 872 if (FPOffset >= -255 && FPOffset < 0) { 873 FrameReg = RegInfo->getFrameRegister(MF); 874 return FPOffset; 875 } 876 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 877 // Otherwise, use SP or FP, whichever is closer to the stack slot. 878 FrameReg = RegInfo->getFrameRegister(MF); 879 return FPOffset; 880 } 881 } 882 // Use the base pointer if we have one. 883 if (RegInfo->hasBasePointer(MF)) 884 FrameReg = RegInfo->getBaseRegister(); 885 return Offset; 886 } 887 888 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 889 MachineBasicBlock::iterator MI, 890 const std::vector<CalleeSavedInfo> &CSI, 891 unsigned StmOpc, unsigned StrOpc, 892 bool NoGap, 893 bool(*Func)(unsigned, bool), 894 unsigned NumAlignedDPRCS2Regs, 895 unsigned MIFlags) const { 896 MachineFunction &MF = *MBB.getParent(); 897 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 898 899 DebugLoc DL; 900 901 SmallVector<std::pair<unsigned,bool>, 4> Regs; 902 unsigned i = CSI.size(); 903 while (i != 0) { 904 unsigned LastReg = 0; 905 for (; i != 0; --i) { 906 unsigned Reg = CSI[i-1].getReg(); 907 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 908 909 // D-registers in the aligned area DPRCS2 are NOT spilled here. 910 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 911 continue; 912 913 // Add the callee-saved register as live-in unless it's LR and 914 // @llvm.returnaddress is called. If LR is returned for 915 // @llvm.returnaddress then it's already added to the function and 916 // entry block live-in sets. 917 bool isKill = true; 918 if (Reg == ARM::LR) { 919 if (MF.getFrameInfo()->isReturnAddressTaken() && 920 MF.getRegInfo().isLiveIn(Reg)) 921 isKill = false; 922 } 923 924 if (isKill) 925 MBB.addLiveIn(Reg); 926 927 // If NoGap is true, push consecutive registers and then leave the rest 928 // for other instructions. e.g. 929 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 930 if (NoGap && LastReg && LastReg != Reg-1) 931 break; 932 LastReg = Reg; 933 Regs.push_back(std::make_pair(Reg, isKill)); 934 } 935 936 if (Regs.empty()) 937 continue; 938 if (Regs.size() > 1 || StrOpc== 0) { 939 MachineInstrBuilder MIB = 940 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 941 .addReg(ARM::SP).setMIFlags(MIFlags)); 942 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 943 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 944 } else if (Regs.size() == 1) { 945 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 946 ARM::SP) 947 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 948 .addReg(ARM::SP).setMIFlags(MIFlags) 949 .addImm(-4); 950 AddDefaultPred(MIB); 951 } 952 Regs.clear(); 953 954 // Put any subsequent vpush instructions before this one: they will refer to 955 // higher register numbers so need to be pushed first in order to preserve 956 // monotonicity. 957 if (MI != MBB.begin()) 958 --MI; 959 } 960 } 961 962 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 963 MachineBasicBlock::iterator MI, 964 const std::vector<CalleeSavedInfo> &CSI, 965 unsigned LdmOpc, unsigned LdrOpc, 966 bool isVarArg, bool NoGap, 967 bool(*Func)(unsigned, bool), 968 unsigned NumAlignedDPRCS2Regs) const { 969 MachineFunction &MF = *MBB.getParent(); 970 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 971 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 972 DebugLoc DL; 973 bool isTailCall = false; 974 bool isInterrupt = false; 975 bool isTrap = false; 976 if (MBB.end() != MI) { 977 DL = MI->getDebugLoc(); 978 unsigned RetOpcode = MI->getOpcode(); 979 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri); 980 isInterrupt = 981 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; 982 isTrap = 983 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || 984 RetOpcode == ARM::tTRAP; 985 } 986 987 SmallVector<unsigned, 4> Regs; 988 unsigned i = CSI.size(); 989 while (i != 0) { 990 unsigned LastReg = 0; 991 bool DeleteRet = false; 992 for (; i != 0; --i) { 993 unsigned Reg = CSI[i-1].getReg(); 994 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 995 996 // The aligned reloads from area DPRCS2 are not inserted here. 997 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 998 continue; 999 1000 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && 1001 !isTrap && STI.hasV5TOps()) { 1002 if (MBB.succ_empty()) { 1003 Reg = ARM::PC; 1004 DeleteRet = true; 1005 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 1006 } else 1007 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1008 // Fold the return instruction into the LDM. 1009 } 1010 1011 // If NoGap is true, pop consecutive registers and then leave the rest 1012 // for other instructions. e.g. 1013 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 1014 if (NoGap && LastReg && LastReg != Reg-1) 1015 break; 1016 1017 LastReg = Reg; 1018 Regs.push_back(Reg); 1019 } 1020 1021 if (Regs.empty()) 1022 continue; 1023 if (Regs.size() > 1 || LdrOpc == 0) { 1024 MachineInstrBuilder MIB = 1025 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 1026 .addReg(ARM::SP)); 1027 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 1028 MIB.addReg(Regs[i], getDefRegState(true)); 1029 if (DeleteRet && MI != MBB.end()) { 1030 MIB.copyImplicitOps(&*MI); 1031 MI->eraseFromParent(); 1032 } 1033 MI = MIB; 1034 } else if (Regs.size() == 1) { 1035 // If we adjusted the reg to PC from LR above, switch it back here. We 1036 // only do that for LDM. 1037 if (Regs[0] == ARM::PC) 1038 Regs[0] = ARM::LR; 1039 MachineInstrBuilder MIB = 1040 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 1041 .addReg(ARM::SP, RegState::Define) 1042 .addReg(ARM::SP); 1043 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 1044 // that refactoring is complete (eventually). 1045 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { 1046 MIB.addReg(0); 1047 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 1048 } else 1049 MIB.addImm(4); 1050 AddDefaultPred(MIB); 1051 } 1052 Regs.clear(); 1053 1054 // Put any subsequent vpop instructions after this one: they will refer to 1055 // higher register numbers so need to be popped afterwards. 1056 if (MI != MBB.end()) 1057 ++MI; 1058 } 1059 } 1060 1061 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers 1062 /// starting from d8. Also insert stack realignment code and leave the stack 1063 /// pointer pointing to the d8 spill slot. 1064 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, 1065 MachineBasicBlock::iterator MI, 1066 unsigned NumAlignedDPRCS2Regs, 1067 const std::vector<CalleeSavedInfo> &CSI, 1068 const TargetRegisterInfo *TRI) { 1069 MachineFunction &MF = *MBB.getParent(); 1070 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1071 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 1072 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1073 MachineFrameInfo &MFI = *MF.getFrameInfo(); 1074 1075 // Mark the D-register spill slots as properly aligned. Since MFI computes 1076 // stack slot layout backwards, this can actually mean that the d-reg stack 1077 // slot offsets can be wrong. The offset for d8 will always be correct. 1078 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1079 unsigned DNum = CSI[i].getReg() - ARM::D8; 1080 if (DNum > NumAlignedDPRCS2Regs - 1) 1081 continue; 1082 int FI = CSI[i].getFrameIdx(); 1083 // The even-numbered registers will be 16-byte aligned, the odd-numbered 1084 // registers will be 8-byte aligned. 1085 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16); 1086 1087 // The stack slot for D8 needs to be maximally aligned because this is 1088 // actually the point where we align the stack pointer. MachineFrameInfo 1089 // computes all offsets relative to the incoming stack pointer which is a 1090 // bit weird when realigning the stack. Any extra padding for this 1091 // over-alignment is not realized because the code inserted below adjusts 1092 // the stack pointer by numregs * 8 before aligning the stack pointer. 1093 if (DNum == 0) 1094 MFI.setObjectAlignment(FI, MFI.getMaxAlignment()); 1095 } 1096 1097 // Move the stack pointer to the d8 spill slot, and align it at the same 1098 // time. Leave the stack slot address in the scratch register r4. 1099 // 1100 // sub r4, sp, #numregs * 8 1101 // bic r4, r4, #align - 1 1102 // mov sp, r4 1103 // 1104 bool isThumb = AFI->isThumbFunction(); 1105 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 1106 AFI->setShouldRestoreSPFromFP(true); 1107 1108 // sub r4, sp, #numregs * 8 1109 // The immediate is <= 64, so it doesn't need any special encoding. 1110 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; 1111 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 1112 .addReg(ARM::SP) 1113 .addImm(8 * NumAlignedDPRCS2Regs))); 1114 1115 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment(); 1116 // We must set parameter MustBeSingleInstruction to true, since 1117 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform 1118 // stack alignment. Luckily, this can always be done since all ARM 1119 // architecture versions that support Neon also support the BFC 1120 // instruction. 1121 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); 1122 1123 // mov sp, r4 1124 // The stack pointer must be adjusted before spilling anything, otherwise 1125 // the stack slots could be clobbered by an interrupt handler. 1126 // Leave r4 live, it is used below. 1127 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; 1128 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) 1129 .addReg(ARM::R4); 1130 MIB = AddDefaultPred(MIB); 1131 if (!isThumb) 1132 AddDefaultCC(MIB); 1133 1134 // Now spill NumAlignedDPRCS2Regs registers starting from d8. 1135 // r4 holds the stack slot address. 1136 unsigned NextReg = ARM::D8; 1137 1138 // 16-byte aligned vst1.64 with 4 d-regs and address writeback. 1139 // The writeback is only needed when emitting two vst1.64 instructions. 1140 if (NumAlignedDPRCS2Regs >= 6) { 1141 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1142 &ARM::QQPRRegClass); 1143 MBB.addLiveIn(SupReg); 1144 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), 1145 ARM::R4) 1146 .addReg(ARM::R4, RegState::Kill).addImm(16) 1147 .addReg(NextReg) 1148 .addReg(SupReg, RegState::ImplicitKill)); 1149 NextReg += 4; 1150 NumAlignedDPRCS2Regs -= 4; 1151 } 1152 1153 // We won't modify r4 beyond this point. It currently points to the next 1154 // register to be spilled. 1155 unsigned R4BaseReg = NextReg; 1156 1157 // 16-byte aligned vst1.64 with 4 d-regs, no writeback. 1158 if (NumAlignedDPRCS2Regs >= 4) { 1159 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1160 &ARM::QQPRRegClass); 1161 MBB.addLiveIn(SupReg); 1162 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) 1163 .addReg(ARM::R4).addImm(16).addReg(NextReg) 1164 .addReg(SupReg, RegState::ImplicitKill)); 1165 NextReg += 4; 1166 NumAlignedDPRCS2Regs -= 4; 1167 } 1168 1169 // 16-byte aligned vst1.64 with 2 d-regs. 1170 if (NumAlignedDPRCS2Regs >= 2) { 1171 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1172 &ARM::QPRRegClass); 1173 MBB.addLiveIn(SupReg); 1174 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) 1175 .addReg(ARM::R4).addImm(16).addReg(SupReg)); 1176 NextReg += 2; 1177 NumAlignedDPRCS2Regs -= 2; 1178 } 1179 1180 // Finally, use a vanilla vstr.64 for the odd last register. 1181 if (NumAlignedDPRCS2Regs) { 1182 MBB.addLiveIn(NextReg); 1183 // vstr.64 uses addrmode5 which has an offset scale of 4. 1184 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) 1185 .addReg(NextReg) 1186 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2)); 1187 } 1188 1189 // The last spill instruction inserted should kill the scratch register r4. 1190 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); 1191 } 1192 1193 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an 1194 /// iterator to the following instruction. 1195 static MachineBasicBlock::iterator 1196 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 1197 unsigned NumAlignedDPRCS2Regs) { 1198 // sub r4, sp, #numregs * 8 1199 // bic r4, r4, #align - 1 1200 // mov sp, r4 1201 ++MI; ++MI; ++MI; 1202 assert(MI->mayStore() && "Expecting spill instruction"); 1203 1204 // These switches all fall through. 1205 switch(NumAlignedDPRCS2Regs) { 1206 case 7: 1207 ++MI; 1208 assert(MI->mayStore() && "Expecting spill instruction"); 1209 default: 1210 ++MI; 1211 assert(MI->mayStore() && "Expecting spill instruction"); 1212 case 1: 1213 case 2: 1214 case 4: 1215 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); 1216 ++MI; 1217 } 1218 return MI; 1219 } 1220 1221 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers 1222 /// starting from d8. These instructions are assumed to execute while the 1223 /// stack is still aligned, unlike the code inserted by emitPopInst. 1224 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, 1225 MachineBasicBlock::iterator MI, 1226 unsigned NumAlignedDPRCS2Regs, 1227 const std::vector<CalleeSavedInfo> &CSI, 1228 const TargetRegisterInfo *TRI) { 1229 MachineFunction &MF = *MBB.getParent(); 1230 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1231 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 1232 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1233 1234 // Find the frame index assigned to d8. 1235 int D8SpillFI = 0; 1236 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 1237 if (CSI[i].getReg() == ARM::D8) { 1238 D8SpillFI = CSI[i].getFrameIdx(); 1239 break; 1240 } 1241 1242 // Materialize the address of the d8 spill slot into the scratch register r4. 1243 // This can be fairly complicated if the stack frame is large, so just use 1244 // the normal frame index elimination mechanism to do it. This code runs as 1245 // the initial part of the epilog where the stack and base pointers haven't 1246 // been changed yet. 1247 bool isThumb = AFI->isThumbFunction(); 1248 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 1249 1250 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 1251 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 1252 .addFrameIndex(D8SpillFI).addImm(0))); 1253 1254 // Now restore NumAlignedDPRCS2Regs registers starting from d8. 1255 unsigned NextReg = ARM::D8; 1256 1257 // 16-byte aligned vld1.64 with 4 d-regs and writeback. 1258 if (NumAlignedDPRCS2Regs >= 6) { 1259 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1260 &ARM::QQPRRegClass); 1261 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) 1262 .addReg(ARM::R4, RegState::Define) 1263 .addReg(ARM::R4, RegState::Kill).addImm(16) 1264 .addReg(SupReg, RegState::ImplicitDefine)); 1265 NextReg += 4; 1266 NumAlignedDPRCS2Regs -= 4; 1267 } 1268 1269 // We won't modify r4 beyond this point. It currently points to the next 1270 // register to be spilled. 1271 unsigned R4BaseReg = NextReg; 1272 1273 // 16-byte aligned vld1.64 with 4 d-regs, no writeback. 1274 if (NumAlignedDPRCS2Regs >= 4) { 1275 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1276 &ARM::QQPRRegClass); 1277 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) 1278 .addReg(ARM::R4).addImm(16) 1279 .addReg(SupReg, RegState::ImplicitDefine)); 1280 NextReg += 4; 1281 NumAlignedDPRCS2Regs -= 4; 1282 } 1283 1284 // 16-byte aligned vld1.64 with 2 d-regs. 1285 if (NumAlignedDPRCS2Regs >= 2) { 1286 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1287 &ARM::QPRRegClass); 1288 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) 1289 .addReg(ARM::R4).addImm(16)); 1290 NextReg += 2; 1291 NumAlignedDPRCS2Regs -= 2; 1292 } 1293 1294 // Finally, use a vanilla vldr.64 for the remaining odd register. 1295 if (NumAlignedDPRCS2Regs) 1296 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) 1297 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg))); 1298 1299 // Last store kills r4. 1300 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); 1301 } 1302 1303 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1304 MachineBasicBlock::iterator MI, 1305 const std::vector<CalleeSavedInfo> &CSI, 1306 const TargetRegisterInfo *TRI) const { 1307 if (CSI.empty()) 1308 return false; 1309 1310 MachineFunction &MF = *MBB.getParent(); 1311 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1312 1313 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 1314 unsigned PushOneOpc = AFI->isThumbFunction() ? 1315 ARM::t2STR_PRE : ARM::STR_PRE_IMM; 1316 unsigned FltOpc = ARM::VSTMDDB_UPD; 1317 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 1318 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0, 1319 MachineInstr::FrameSetup); 1320 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0, 1321 MachineInstr::FrameSetup); 1322 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 1323 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup); 1324 1325 // The code above does not insert spill code for the aligned DPRCS2 registers. 1326 // The stack realignment code will be inserted between the push instructions 1327 // and these spills. 1328 if (NumAlignedDPRCS2Regs) 1329 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1330 1331 return true; 1332 } 1333 1334 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1335 MachineBasicBlock::iterator MI, 1336 const std::vector<CalleeSavedInfo> &CSI, 1337 const TargetRegisterInfo *TRI) const { 1338 if (CSI.empty()) 1339 return false; 1340 1341 MachineFunction &MF = *MBB.getParent(); 1342 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1343 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 1344 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 1345 1346 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2 1347 // registers. Do that here instead. 1348 if (NumAlignedDPRCS2Regs) 1349 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1350 1351 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1352 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; 1353 unsigned FltOpc = ARM::VLDMDIA_UPD; 1354 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register, 1355 NumAlignedDPRCS2Regs); 1356 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1357 &isARMArea2Register, 0); 1358 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1359 &isARMArea1Register, 0); 1360 1361 return true; 1362 } 1363 1364 // FIXME: Make generic? 1365 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 1366 const ARMBaseInstrInfo &TII) { 1367 unsigned FnSize = 0; 1368 for (auto &MBB : MF) { 1369 for (auto &MI : MBB) 1370 FnSize += TII.GetInstSizeInBytes(&MI); 1371 } 1372 return FnSize; 1373 } 1374 1375 /// estimateRSStackSizeLimit - Look at each instruction that references stack 1376 /// frames and return the stack size limit beyond which some of these 1377 /// instructions will require a scratch register during their expansion later. 1378 // FIXME: Move to TII? 1379 static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 1380 const TargetFrameLowering *TFI) { 1381 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1382 unsigned Limit = (1 << 12) - 1; 1383 for (auto &MBB : MF) { 1384 for (auto &MI : MBB) { 1385 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1386 if (!MI.getOperand(i).isFI()) 1387 continue; 1388 1389 // When using ADDri to get the address of a stack object, 255 is the 1390 // largest offset guaranteed to fit in the immediate offset. 1391 if (MI.getOpcode() == ARM::ADDri) { 1392 Limit = std::min(Limit, (1U << 8) - 1); 1393 break; 1394 } 1395 1396 // Otherwise check the addressing mode. 1397 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) { 1398 case ARMII::AddrMode3: 1399 case ARMII::AddrModeT2_i8: 1400 Limit = std::min(Limit, (1U << 8) - 1); 1401 break; 1402 case ARMII::AddrMode5: 1403 case ARMII::AddrModeT2_i8s4: 1404 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 1405 break; 1406 case ARMII::AddrModeT2_i12: 1407 // i12 supports only positive offset so these will be converted to 1408 // i8 opcodes. See llvm::rewriteT2FrameIndex. 1409 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 1410 Limit = std::min(Limit, (1U << 8) - 1); 1411 break; 1412 case ARMII::AddrMode4: 1413 case ARMII::AddrMode6: 1414 // Addressing modes 4 & 6 (load/store) instructions can't encode an 1415 // immediate offset for stack references. 1416 return 0; 1417 default: 1418 break; 1419 } 1420 break; // At most one FI per instruction 1421 } 1422 } 1423 } 1424 1425 return Limit; 1426 } 1427 1428 // In functions that realign the stack, it can be an advantage to spill the 1429 // callee-saved vector registers after realigning the stack. The vst1 and vld1 1430 // instructions take alignment hints that can improve performance. 1431 // 1432 static void 1433 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) { 1434 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0); 1435 if (!SpillAlignedNEONRegs) 1436 return; 1437 1438 // Naked functions don't spill callee-saved registers. 1439 if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 1440 return; 1441 1442 // We are planning to use NEON instructions vst1 / vld1. 1443 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON()) 1444 return; 1445 1446 // Don't bother if the default stack alignment is sufficiently high. 1447 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8) 1448 return; 1449 1450 // Aligned spills require stack realignment. 1451 if (!static_cast<const ARMBaseRegisterInfo *>( 1452 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF)) 1453 return; 1454 1455 // We always spill contiguous d-registers starting from d8. Count how many 1456 // needs spilling. The register allocator will almost always use the 1457 // callee-saved registers in order, but it can happen that there are holes in 1458 // the range. Registers above the hole will be spilled to the standard DPRCS 1459 // area. 1460 unsigned NumSpills = 0; 1461 for (; NumSpills < 8; ++NumSpills) 1462 if (!SavedRegs.test(ARM::D8 + NumSpills)) 1463 break; 1464 1465 // Don't do this for just one d-register. It's not worth it. 1466 if (NumSpills < 2) 1467 return; 1468 1469 // Spill the first NumSpills D-registers after realigning the stack. 1470 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills); 1471 1472 // A scratch register is required for the vst1 / vld1 instructions. 1473 SavedRegs.set(ARM::R4); 1474 } 1475 1476 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, 1477 BitVector &SavedRegs, 1478 RegScavenger *RS) const { 1479 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1480 // This tells PEI to spill the FP as if it is any other callee-save register 1481 // to take advantage the eliminateFrameIndex machinery. This also ensures it 1482 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1483 // to combine multiple loads / stores. 1484 bool CanEliminateFrame = true; 1485 bool CS1Spilled = false; 1486 bool LRSpilled = false; 1487 unsigned NumGPRSpills = 0; 1488 SmallVector<unsigned, 4> UnspilledCS1GPRs; 1489 SmallVector<unsigned, 4> UnspilledCS2GPRs; 1490 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( 1491 MF.getSubtarget().getRegisterInfo()); 1492 const ARMBaseInstrInfo &TII = 1493 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1494 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1495 MachineFrameInfo *MFI = MF.getFrameInfo(); 1496 MachineRegisterInfo &MRI = MF.getRegInfo(); 1497 unsigned FramePtr = RegInfo->getFrameRegister(MF); 1498 1499 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 1500 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 1501 // since it's not always possible to restore sp from fp in a single 1502 // instruction. 1503 // FIXME: It will be better just to find spare register here. 1504 if (AFI->isThumb2Function() && 1505 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 1506 SavedRegs.set(ARM::R4); 1507 1508 if (AFI->isThumb1OnlyFunction()) { 1509 // Spill LR if Thumb1 function uses variable length argument lists. 1510 if (AFI->getArgRegsSaveSize() > 0) 1511 SavedRegs.set(ARM::LR); 1512 1513 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know 1514 // for sure what the stack size will be, but for this, an estimate is good 1515 // enough. If there anything changes it, it'll be a spill, which implies 1516 // we've used all the registers and so R4 is already used, so not marking 1517 // it here will be OK. 1518 // FIXME: It will be better just to find spare register here. 1519 unsigned StackSize = MFI->estimateStackSize(MF); 1520 if (MFI->hasVarSizedObjects() || StackSize > 508) 1521 SavedRegs.set(ARM::R4); 1522 } 1523 1524 // See if we can spill vector registers to aligned stack. 1525 checkNumAlignedDPRCS2Regs(MF, SavedRegs); 1526 1527 // Spill the BasePtr if it's used. 1528 if (RegInfo->hasBasePointer(MF)) 1529 SavedRegs.set(RegInfo->getBaseRegister()); 1530 1531 // Don't spill FP if the frame can be eliminated. This is determined 1532 // by scanning the callee-save registers to see if any is modified. 1533 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 1534 for (unsigned i = 0; CSRegs[i]; ++i) { 1535 unsigned Reg = CSRegs[i]; 1536 bool Spilled = false; 1537 if (SavedRegs.test(Reg)) { 1538 Spilled = true; 1539 CanEliminateFrame = false; 1540 } 1541 1542 if (!ARM::GPRRegClass.contains(Reg)) 1543 continue; 1544 1545 if (Spilled) { 1546 NumGPRSpills++; 1547 1548 if (!STI.isTargetDarwin()) { 1549 if (Reg == ARM::LR) 1550 LRSpilled = true; 1551 CS1Spilled = true; 1552 continue; 1553 } 1554 1555 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 1556 switch (Reg) { 1557 case ARM::LR: 1558 LRSpilled = true; 1559 // Fallthrough 1560 case ARM::R0: case ARM::R1: 1561 case ARM::R2: case ARM::R3: 1562 case ARM::R4: case ARM::R5: 1563 case ARM::R6: case ARM::R7: 1564 CS1Spilled = true; 1565 break; 1566 default: 1567 break; 1568 } 1569 } else { 1570 if (!STI.isTargetDarwin()) { 1571 UnspilledCS1GPRs.push_back(Reg); 1572 continue; 1573 } 1574 1575 switch (Reg) { 1576 case ARM::R0: case ARM::R1: 1577 case ARM::R2: case ARM::R3: 1578 case ARM::R4: case ARM::R5: 1579 case ARM::R6: case ARM::R7: 1580 case ARM::LR: 1581 UnspilledCS1GPRs.push_back(Reg); 1582 break; 1583 default: 1584 UnspilledCS2GPRs.push_back(Reg); 1585 break; 1586 } 1587 } 1588 } 1589 1590 bool ForceLRSpill = false; 1591 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 1592 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 1593 // Force LR to be spilled if the Thumb function size is > 2048. This enables 1594 // use of BL to implement far jump. If it turns out that it's not needed 1595 // then the branch fix up path will undo it. 1596 if (FnSize >= (1 << 11)) { 1597 CanEliminateFrame = false; 1598 ForceLRSpill = true; 1599 } 1600 } 1601 1602 // If any of the stack slot references may be out of range of an immediate 1603 // offset, make sure a register (or a spill slot) is available for the 1604 // register scavenger. Note that if we're indexing off the frame pointer, the 1605 // effective stack size is 4 bytes larger since the FP points to the stack 1606 // slot of the previous FP. Also, if we have variable sized objects in the 1607 // function, stack slot references will often be negative, and some of 1608 // our instructions are positive-offset only, so conservatively consider 1609 // that case to want a spill slot (or register) as well. Similarly, if 1610 // the function adjusts the stack pointer during execution and the 1611 // adjustments aren't already part of our stack size estimate, our offset 1612 // calculations may be off, so be conservative. 1613 // FIXME: We could add logic to be more precise about negative offsets 1614 // and which instructions will need a scratch register for them. Is it 1615 // worth the effort and added fragility? 1616 bool BigStack = (RS && (MFI->estimateStackSize(MF) + 1617 ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >= 1618 estimateRSStackSizeLimit(MF, this))) || 1619 MFI->hasVarSizedObjects() || 1620 (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 1621 1622 bool ExtraCSSpill = false; 1623 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 1624 AFI->setHasStackFrame(true); 1625 1626 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1627 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1628 if (!LRSpilled && CS1Spilled) { 1629 SavedRegs.set(ARM::LR); 1630 NumGPRSpills++; 1631 SmallVectorImpl<unsigned>::iterator LRPos; 1632 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(), 1633 (unsigned)ARM::LR); 1634 if (LRPos != UnspilledCS1GPRs.end()) 1635 UnspilledCS1GPRs.erase(LRPos); 1636 1637 ForceLRSpill = false; 1638 ExtraCSSpill = true; 1639 } 1640 1641 if (hasFP(MF)) { 1642 SavedRegs.set(FramePtr); 1643 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(), 1644 FramePtr); 1645 if (FPPos != UnspilledCS1GPRs.end()) 1646 UnspilledCS1GPRs.erase(FPPos); 1647 NumGPRSpills++; 1648 } 1649 1650 // If stack and double are 8-byte aligned and we are spilling an odd number 1651 // of GPRs, spill one extra callee save GPR so we won't have to pad between 1652 // the integer and double callee save areas. 1653 unsigned TargetAlign = getStackAlignment(); 1654 if (TargetAlign >= 8 && (NumGPRSpills & 1)) { 1655 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1656 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1657 unsigned Reg = UnspilledCS1GPRs[i]; 1658 // Don't spill high register if the function is thumb. In the case of 1659 // Windows on ARM, accept R11 (frame pointer) 1660 if (!AFI->isThumbFunction() || 1661 (STI.isTargetWindows() && Reg == ARM::R11) || 1662 isARMLowRegister(Reg) || Reg == ARM::LR) { 1663 SavedRegs.set(Reg); 1664 if (!MRI.isReserved(Reg)) 1665 ExtraCSSpill = true; 1666 break; 1667 } 1668 } 1669 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 1670 unsigned Reg = UnspilledCS2GPRs.front(); 1671 SavedRegs.set(Reg); 1672 if (!MRI.isReserved(Reg)) 1673 ExtraCSSpill = true; 1674 } 1675 } 1676 1677 // Estimate if we might need to scavenge a register at some point in order 1678 // to materialize a stack offset. If so, either spill one additional 1679 // callee-saved register or reserve a special spill slot to facilitate 1680 // register scavenging. Thumb1 needs a spill slot for stack pointer 1681 // adjustments also, even when the frame itself is small. 1682 if (BigStack && !ExtraCSSpill) { 1683 // If any non-reserved CS register isn't spilled, just spill one or two 1684 // extra. That should take care of it! 1685 unsigned NumExtras = TargetAlign / 4; 1686 SmallVector<unsigned, 2> Extras; 1687 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1688 unsigned Reg = UnspilledCS1GPRs.back(); 1689 UnspilledCS1GPRs.pop_back(); 1690 if (!MRI.isReserved(Reg) && 1691 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 1692 Reg == ARM::LR)) { 1693 Extras.push_back(Reg); 1694 NumExtras--; 1695 } 1696 } 1697 // For non-Thumb1 functions, also check for hi-reg CS registers 1698 if (!AFI->isThumb1OnlyFunction()) { 1699 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1700 unsigned Reg = UnspilledCS2GPRs.back(); 1701 UnspilledCS2GPRs.pop_back(); 1702 if (!MRI.isReserved(Reg)) { 1703 Extras.push_back(Reg); 1704 NumExtras--; 1705 } 1706 } 1707 } 1708 if (Extras.size() && NumExtras == 0) { 1709 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1710 SavedRegs.set(Extras[i]); 1711 } 1712 } else if (!AFI->isThumb1OnlyFunction()) { 1713 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 1714 // closest to SP or frame pointer. 1715 const TargetRegisterClass *RC = &ARM::GPRRegClass; 1716 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1717 RC->getAlignment(), 1718 false)); 1719 } 1720 } 1721 } 1722 1723 if (ForceLRSpill) { 1724 SavedRegs.set(ARM::LR); 1725 AFI->setLRIsSpilledForFarJump(true); 1726 } 1727 } 1728 1729 1730 void ARMFrameLowering:: 1731 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1732 MachineBasicBlock::iterator I) const { 1733 const ARMBaseInstrInfo &TII = 1734 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1735 if (!hasReservedCallFrame(MF)) { 1736 // If we have alloca, convert as follows: 1737 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1738 // ADJCALLSTACKUP -> add, sp, sp, amount 1739 MachineInstr *Old = I; 1740 DebugLoc dl = Old->getDebugLoc(); 1741 unsigned Amount = Old->getOperand(0).getImm(); 1742 if (Amount != 0) { 1743 // We need to keep the stack aligned properly. To do this, we round the 1744 // amount of space needed for the outgoing arguments up to the next 1745 // alignment boundary. 1746 Amount = alignSPAdjust(Amount); 1747 1748 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1749 assert(!AFI->isThumb1OnlyFunction() && 1750 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 1751 bool isARM = !AFI->isThumbFunction(); 1752 1753 // Replace the pseudo instruction with a new instruction... 1754 unsigned Opc = Old->getOpcode(); 1755 int PIdx = Old->findFirstPredOperandIdx(); 1756 ARMCC::CondCodes Pred = (PIdx == -1) 1757 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1758 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1759 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1760 unsigned PredReg = Old->getOperand(2).getReg(); 1761 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, 1762 Pred, PredReg); 1763 } else { 1764 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1765 unsigned PredReg = Old->getOperand(3).getReg(); 1766 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1767 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, 1768 Pred, PredReg); 1769 } 1770 } 1771 } 1772 MBB.erase(I); 1773 } 1774 1775 /// Get the minimum constant for ARM that is greater than or equal to the 1776 /// argument. In ARM, constants can have any value that can be produced by 1777 /// rotating an 8-bit value to the right by an even number of bits within a 1778 /// 32-bit word. 1779 static uint32_t alignToARMConstant(uint32_t Value) { 1780 unsigned Shifted = 0; 1781 1782 if (Value == 0) 1783 return 0; 1784 1785 while (!(Value & 0xC0000000)) { 1786 Value = Value << 2; 1787 Shifted += 2; 1788 } 1789 1790 bool Carry = (Value & 0x00FFFFFF); 1791 Value = ((Value & 0xFF000000) >> 24) + Carry; 1792 1793 if (Value & 0x0000100) 1794 Value = Value & 0x000001FC; 1795 1796 if (Shifted > 24) 1797 Value = Value >> (Shifted - 24); 1798 else 1799 Value = Value << (24 - Shifted); 1800 1801 return Value; 1802 } 1803 1804 // The stack limit in the TCB is set to this many bytes above the actual 1805 // stack limit. 1806 static const uint64_t kSplitStackAvailable = 256; 1807 1808 // Adjust the function prologue to enable split stacks. This currently only 1809 // supports android and linux. 1810 // 1811 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but 1812 // must be well defined in order to allow for consistent implementations of the 1813 // __morestack helper function. The ABI is also not a normal ABI in that it 1814 // doesn't follow the normal calling conventions because this allows the 1815 // prologue of each function to be optimized further. 1816 // 1817 // Currently, the ABI looks like (when calling __morestack) 1818 // 1819 // * r4 holds the minimum stack size requested for this function call 1820 // * r5 holds the stack size of the arguments to the function 1821 // * the beginning of the function is 3 instructions after the call to 1822 // __morestack 1823 // 1824 // Implementations of __morestack should use r4 to allocate a new stack, r5 to 1825 // place the arguments on to the new stack, and the 3-instruction knowledge to 1826 // jump directly to the body of the function when working on the new stack. 1827 // 1828 // An old (and possibly no longer compatible) implementation of __morestack for 1829 // ARM can be found at [1]. 1830 // 1831 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S 1832 void ARMFrameLowering::adjustForSegmentedStacks( 1833 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const { 1834 unsigned Opcode; 1835 unsigned CFIIndex; 1836 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>(); 1837 bool Thumb = ST->isThumb(); 1838 1839 // Sadly, this currently doesn't support varargs, platforms other than 1840 // android/linux. Note that thumb1/thumb2 are support for android/linux. 1841 if (MF.getFunction()->isVarArg()) 1842 report_fatal_error("Segmented stacks do not support vararg functions."); 1843 if (!ST->isTargetAndroid() && !ST->isTargetLinux()) 1844 report_fatal_error("Segmented stacks not supported on this platform."); 1845 1846 MachineFrameInfo *MFI = MF.getFrameInfo(); 1847 MachineModuleInfo &MMI = MF.getMMI(); 1848 MCContext &Context = MMI.getContext(); 1849 const MCRegisterInfo *MRI = Context.getRegisterInfo(); 1850 const ARMBaseInstrInfo &TII = 1851 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1852 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>(); 1853 DebugLoc DL; 1854 1855 uint64_t StackSize = MFI->getStackSize(); 1856 1857 // Do not generate a prologue for functions with a stack of size zero 1858 if (StackSize == 0) 1859 return; 1860 1861 // Use R4 and R5 as scratch registers. 1862 // We save R4 and R5 before use and restore them before leaving the function. 1863 unsigned ScratchReg0 = ARM::R4; 1864 unsigned ScratchReg1 = ARM::R5; 1865 uint64_t AlignedStackSize; 1866 1867 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock(); 1868 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock(); 1869 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock(); 1870 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock(); 1871 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock(); 1872 1873 // Grab everything that reaches PrologueMBB to update there liveness as well. 1874 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion; 1875 SmallVector<MachineBasicBlock *, 2> WalkList; 1876 WalkList.push_back(&PrologueMBB); 1877 1878 do { 1879 MachineBasicBlock *CurMBB = WalkList.pop_back_val(); 1880 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) { 1881 if (BeforePrologueRegion.insert(PredBB).second) 1882 WalkList.push_back(PredBB); 1883 } 1884 } while (!WalkList.empty()); 1885 1886 // The order in that list is important. 1887 // The blocks will all be inserted before PrologueMBB using that order. 1888 // Therefore the block that should appear first in the CFG should appear 1889 // first in the list. 1890 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB, 1891 PostStackMBB}; 1892 1893 for (MachineBasicBlock *B : AddedBlocks) 1894 BeforePrologueRegion.insert(B); 1895 1896 for (const auto &LI : PrologueMBB.liveins()) { 1897 for (MachineBasicBlock *PredBB : BeforePrologueRegion) 1898 PredBB->addLiveIn(LI); 1899 } 1900 1901 // Remove the newly added blocks from the list, since we know 1902 // we do not have to do the following updates for them. 1903 for (MachineBasicBlock *B : AddedBlocks) { 1904 BeforePrologueRegion.erase(B); 1905 MF.insert(PrologueMBB.getIterator(), B); 1906 } 1907 1908 for (MachineBasicBlock *MBB : BeforePrologueRegion) { 1909 // Make sure the LiveIns are still sorted and unique. 1910 MBB->sortUniqueLiveIns(); 1911 // Replace the edges to PrologueMBB by edges to the sequences 1912 // we are about to add. 1913 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]); 1914 } 1915 1916 // The required stack size that is aligned to ARM constant criterion. 1917 AlignedStackSize = alignToARMConstant(StackSize); 1918 1919 // When the frame size is less than 256 we just compare the stack 1920 // boundary directly to the value of the stack pointer, per gcc. 1921 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable; 1922 1923 // We will use two of the callee save registers as scratch registers so we 1924 // need to save those registers onto the stack. 1925 // We will use SR0 to hold stack limit and SR1 to hold the stack size 1926 // requested and arguments for __morestack(). 1927 // SR0: Scratch Register #0 1928 // SR1: Scratch Register #1 1929 // push {SR0, SR1} 1930 if (Thumb) { 1931 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))) 1932 .addReg(ScratchReg0).addReg(ScratchReg1); 1933 } else { 1934 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) 1935 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP)) 1936 .addReg(ScratchReg0).addReg(ScratchReg1); 1937 } 1938 1939 // Emit the relevant DWARF information about the change in stack pointer as 1940 // well as where to find both r4 and r5 (the callee-save registers) 1941 CFIIndex = 1942 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8)); 1943 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1944 .addCFIIndex(CFIIndex); 1945 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1946 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4)); 1947 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1948 .addCFIIndex(CFIIndex); 1949 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 1950 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8)); 1951 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1952 .addCFIIndex(CFIIndex); 1953 1954 // mov SR1, sp 1955 if (Thumb) { 1956 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) 1957 .addReg(ARM::SP)); 1958 } else if (CompareStackPointer) { 1959 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) 1960 .addReg(ARM::SP)).addReg(0); 1961 } 1962 1963 // sub SR1, sp, #StackSize 1964 if (!CompareStackPointer && Thumb) { 1965 AddDefaultPred( 1966 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)) 1967 .addReg(ScratchReg1).addImm(AlignedStackSize)); 1968 } else if (!CompareStackPointer) { 1969 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) 1970 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0); 1971 } 1972 1973 if (Thumb && ST->isThumb1Only()) { 1974 unsigned PCLabelId = ARMFI->createPICLabelUId(); 1975 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create( 1976 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0); 1977 MachineConstantPool *MCP = MF.getConstantPool(); 1978 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4); 1979 1980 // ldr SR0, [pc, offset(STACK_LIMIT)] 1981 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) 1982 .addConstantPoolIndex(CPI)); 1983 1984 // ldr SR0, [SR0] 1985 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) 1986 .addReg(ScratchReg0).addImm(0)); 1987 } else { 1988 // Get TLS base address from the coprocessor 1989 // mrc p15, #0, SR0, c13, c0, #3 1990 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0) 1991 .addImm(15) 1992 .addImm(0) 1993 .addImm(13) 1994 .addImm(0) 1995 .addImm(3)); 1996 1997 // Use the last tls slot on android and a private field of the TCP on linux. 1998 assert(ST->isTargetAndroid() || ST->isTargetLinux()); 1999 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1; 2000 2001 // Get the stack limit from the right offset 2002 // ldr SR0, [sr0, #4 * TlsOffset] 2003 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0) 2004 .addReg(ScratchReg0).addImm(4 * TlsOffset)); 2005 } 2006 2007 // Compare stack limit with stack size requested. 2008 // cmp SR0, SR1 2009 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; 2010 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode)) 2011 .addReg(ScratchReg0) 2012 .addReg(ScratchReg1)); 2013 2014 // This jump is taken if StackLimit < SP - stack required. 2015 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; 2016 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB) 2017 .addImm(ARMCC::LO) 2018 .addReg(ARM::CPSR); 2019 2020 2021 // Calling __morestack(StackSize, Size of stack arguments). 2022 // __morestack knows that the stack size requested is in SR0(r4) 2023 // and amount size of stack arguments is in SR1(r5). 2024 2025 // Pass first argument for the __morestack by Scratch Register #0. 2026 // The amount size of stack required 2027 if (Thumb) { 2028 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), 2029 ScratchReg0)).addImm(AlignedStackSize)); 2030 } else { 2031 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) 2032 .addImm(AlignedStackSize)).addReg(0); 2033 } 2034 // Pass second argument for the __morestack by Scratch Register #1. 2035 // The amount size of stack consumed to save function arguments. 2036 if (Thumb) { 2037 AddDefaultPred( 2038 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)) 2039 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))); 2040 } else { 2041 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) 2042 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))) 2043 .addReg(0); 2044 } 2045 2046 // push {lr} - Save return address of this function. 2047 if (Thumb) { 2048 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))) 2049 .addReg(ARM::LR); 2050 } else { 2051 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) 2052 .addReg(ARM::SP, RegState::Define) 2053 .addReg(ARM::SP)) 2054 .addReg(ARM::LR); 2055 } 2056 2057 // Emit the DWARF info about the change in stack as well as where to find the 2058 // previous link register 2059 CFIIndex = 2060 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12)); 2061 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2062 .addCFIIndex(CFIIndex); 2063 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 2064 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); 2065 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2066 .addCFIIndex(CFIIndex); 2067 2068 // Call __morestack(). 2069 if (Thumb) { 2070 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL))) 2071 .addExternalSymbol("__morestack"); 2072 } else { 2073 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) 2074 .addExternalSymbol("__morestack"); 2075 } 2076 2077 // pop {lr} - Restore return address of this original function. 2078 if (Thumb) { 2079 if (ST->isThumb1Only()) { 2080 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) 2081 .addReg(ScratchReg0); 2082 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) 2083 .addReg(ScratchReg0)); 2084 } else { 2085 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) 2086 .addReg(ARM::LR, RegState::Define) 2087 .addReg(ARM::SP, RegState::Define) 2088 .addReg(ARM::SP) 2089 .addImm(4)); 2090 } 2091 } else { 2092 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) 2093 .addReg(ARM::SP, RegState::Define) 2094 .addReg(ARM::SP)) 2095 .addReg(ARM::LR); 2096 } 2097 2098 // Restore SR0 and SR1 in case of __morestack() was called. 2099 // __morestack() will skip PostStackMBB block so we need to restore 2100 // scratch registers from here. 2101 // pop {SR0, SR1} 2102 if (Thumb) { 2103 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) 2104 .addReg(ScratchReg0) 2105 .addReg(ScratchReg1); 2106 } else { 2107 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) 2108 .addReg(ARM::SP, RegState::Define) 2109 .addReg(ARM::SP)) 2110 .addReg(ScratchReg0) 2111 .addReg(ScratchReg1); 2112 } 2113 2114 // Update the CFA offset now that we've popped 2115 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); 2116 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2117 .addCFIIndex(CFIIndex); 2118 2119 // bx lr - Return from this function. 2120 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET; 2121 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode))); 2122 2123 // Restore SR0 and SR1 in case of __morestack() was not called. 2124 // pop {SR0, SR1} 2125 if (Thumb) { 2126 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))) 2127 .addReg(ScratchReg0) 2128 .addReg(ScratchReg1); 2129 } else { 2130 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) 2131 .addReg(ARM::SP, RegState::Define) 2132 .addReg(ARM::SP)) 2133 .addReg(ScratchReg0) 2134 .addReg(ScratchReg1); 2135 } 2136 2137 // Update the CFA offset now that we've popped 2138 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); 2139 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2140 .addCFIIndex(CFIIndex); 2141 2142 // Tell debuggers that r4 and r5 are now the same as they were in the 2143 // previous function, that they're the "Same Value". 2144 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue( 2145 nullptr, MRI->getDwarfRegNum(ScratchReg0, true))); 2146 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2147 .addCFIIndex(CFIIndex); 2148 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue( 2149 nullptr, MRI->getDwarfRegNum(ScratchReg1, true))); 2150 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2151 .addCFIIndex(CFIIndex); 2152 2153 // Organizing MBB lists 2154 PostStackMBB->addSuccessor(&PrologueMBB); 2155 2156 AllocMBB->addSuccessor(PostStackMBB); 2157 2158 GetMBB->addSuccessor(PostStackMBB); 2159 GetMBB->addSuccessor(AllocMBB); 2160 2161 McrMBB->addSuccessor(GetMBB); 2162 2163 PrevStackMBB->addSuccessor(McrMBB); 2164 2165 #ifdef XDEBUG 2166 MF.verify(); 2167 #endif 2168 } 2169