1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction 2 operand description table. 3 Copyright (C) 2012-2016 Free Software Foundation, Inc. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "aarch64-opc.h" 23 24 #ifndef VERIFIER 25 #error VERIFIER must be defined. 26 #endif 27 28 /* Operand type. */ 29 30 #define OPND(x) AARCH64_OPND_##x 31 #define OP0() {} 32 #define OP1(a) {OPND(a)} 33 #define OP2(a,b) {OPND(a), OPND(b)} 34 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)} 35 #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)} 36 #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)} 37 38 #define QLF(x) AARCH64_OPND_QLF_##x 39 #define QLF1(a) {QLF(a)} 40 #define QLF2(a,b) {QLF(a), QLF(b)} 41 #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} 42 #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} 43 #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} 44 45 /* Qualifiers list. */ 46 47 /* e.g. MSR <systemreg>, <Xt>. */ 48 #define QL_SRC_X \ 49 { \ 50 QLF2(NIL,X), \ 51 } 52 53 /* e.g. MRS <Xt>, <systemreg>. */ 54 #define QL_DST_X \ 55 { \ 56 QLF2(X,NIL), \ 57 } 58 59 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 60 #define QL_SYS \ 61 { \ 62 QLF5(NIL,NIL,NIL,NIL,X), \ 63 } 64 65 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ 66 #define QL_SYSL \ 67 { \ 68 QLF5(X,NIL,NIL,NIL,NIL), \ 69 } 70 71 /* e.g. ADRP <Xd>, <label>. */ 72 #define QL_ADRP \ 73 { \ 74 QLF2(X,NIL), \ 75 } 76 77 /* e.g. B.<cond> <label>. */ 78 #define QL_PCREL_NIL \ 79 { \ 80 QLF1(NIL), \ 81 } 82 83 /* e.g. TBZ <Xt>, #<imm>, <label>. */ 84 #define QL_PCREL_14 \ 85 { \ 86 QLF3(X,imm_0_63,NIL), \ 87 } 88 89 /* e.g. BL <label>. */ 90 #define QL_PCREL_26 \ 91 { \ 92 QLF1(NIL), \ 93 } 94 95 /* e.g. LDRSW <Xt>, <label>. */ 96 #define QL_X_PCREL \ 97 { \ 98 QLF2(X,NIL), \ 99 } 100 101 /* e.g. LDR <Wt>, <label>. */ 102 #define QL_R_PCREL \ 103 { \ 104 QLF2(W,NIL), \ 105 QLF2(X,NIL), \ 106 } 107 108 /* e.g. LDR <Dt>, <label>. */ 109 #define QL_FP_PCREL \ 110 { \ 111 QLF2(S_S,NIL), \ 112 QLF2(S_D,NIL), \ 113 QLF2(S_Q,NIL), \ 114 } 115 116 /* e.g. PRFM <prfop>, <label>. */ 117 #define QL_PRFM_PCREL \ 118 { \ 119 QLF2(NIL,NIL), \ 120 } 121 122 /* e.g. BR <Xn>. */ 123 #define QL_I1X \ 124 { \ 125 QLF1(X), \ 126 } 127 128 /* e.g. RBIT <Wd>, <Wn>. */ 129 #define QL_I2SAME \ 130 { \ 131 QLF2(W,W), \ 132 QLF2(X,X), \ 133 } 134 135 /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */ 136 #define QL_I2_EXT \ 137 { \ 138 QLF2(W,W), \ 139 QLF2(X,W), \ 140 QLF2(X,X), \ 141 } 142 143 /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */ 144 #define QL_I2SP \ 145 { \ 146 QLF2(WSP,W), \ 147 QLF2(W,WSP), \ 148 QLF2(SP,X), \ 149 QLF2(X,SP), \ 150 } 151 152 /* e.g. REV <Wd>, <Wn>. */ 153 #define QL_I2SAMEW \ 154 { \ 155 QLF2(W,W), \ 156 } 157 158 /* e.g. REV32 <Xd>, <Xn>. */ 159 #define QL_I2SAMEX \ 160 { \ 161 QLF2(X,X), \ 162 } 163 164 #define QL_I2SAMER \ 165 { \ 166 QLF2(W,W), \ 167 QLF2(X,X), \ 168 } 169 170 /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */ 171 #define QL_I3SAMEW \ 172 { \ 173 QLF3(W,W,W), \ 174 } 175 176 /* e.g. SMULH <Xd>, <Xn>, <Xm>. */ 177 #define QL_I3SAMEX \ 178 { \ 179 QLF3(X,X,X), \ 180 } 181 182 /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */ 183 #define QL_I3WWX \ 184 { \ 185 QLF3(W,W,X), \ 186 } 187 188 /* e.g. UDIV <Xd>, <Xn>, <Xm>. */ 189 #define QL_I3SAMER \ 190 { \ 191 QLF3(W,W,W), \ 192 QLF3(X,X,X), \ 193 } 194 195 /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */ 196 #define QL_I3_EXT \ 197 { \ 198 QLF3(W,W,W), \ 199 QLF3(X,X,W), \ 200 QLF3(X,X,X), \ 201 } 202 203 /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */ 204 #define QL_I4SAMER \ 205 { \ 206 QLF4(W,W,W,W), \ 207 QLF4(X,X,X,X), \ 208 } 209 210 /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ 211 #define QL_I3SAMEL \ 212 { \ 213 QLF3(X,W,W), \ 214 } 215 216 /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */ 217 #define QL_I4SAMEL \ 218 { \ 219 QLF4(X,W,W,X), \ 220 } 221 222 /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */ 223 #define QL_CSEL \ 224 { \ 225 QLF4(W, W, W, NIL), \ 226 QLF4(X, X, X, NIL), \ 227 } 228 229 /* e.g. CSET <Wd>, <cond>. */ 230 #define QL_DST_R \ 231 { \ 232 QLF2(W, NIL), \ 233 QLF2(X, NIL), \ 234 } 235 236 /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */ 237 #define QL_BF \ 238 { \ 239 QLF4(W,W,imm_0_31,imm_0_31), \ 240 QLF4(X,X,imm_0_63,imm_0_63), \ 241 } 242 243 /* e.g. BFC <Wd>, #<immr>, #<imms>. */ 244 #define QL_BF1 \ 245 { \ 246 QLF3 (W, imm_0_31, imm_1_32), \ 247 QLF3 (X, imm_0_63, imm_1_64), \ 248 } 249 250 /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */ 251 #define QL_BF2 \ 252 { \ 253 QLF4(W,W,imm_0_31,imm_1_32), \ 254 QLF4(X,X,imm_0_63,imm_1_64), \ 255 } 256 257 /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */ 258 #define QL_FIX2FP \ 259 { \ 260 QLF3(S_D,W,imm_1_32), \ 261 QLF3(S_S,W,imm_1_32), \ 262 QLF3(S_D,X,imm_1_64), \ 263 QLF3(S_S,X,imm_1_64), \ 264 } 265 266 /* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */ 267 #define QL_FIX2FP_H \ 268 { \ 269 QLF3 (S_H, W, imm_1_32), \ 270 QLF3 (S_H, X, imm_1_64), \ 271 } 272 273 /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */ 274 #define QL_FP2FIX \ 275 { \ 276 QLF3(W,S_D,imm_1_32), \ 277 QLF3(W,S_S,imm_1_32), \ 278 QLF3(X,S_D,imm_1_64), \ 279 QLF3(X,S_S,imm_1_64), \ 280 } 281 282 /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */ 283 #define QL_FP2FIX_H \ 284 { \ 285 QLF3 (W, S_H, imm_1_32), \ 286 QLF3 (X, S_H, imm_1_64), \ 287 } 288 289 /* e.g. SCVTF <Dd>, <Wn>. */ 290 #define QL_INT2FP \ 291 { \ 292 QLF2(S_D,W), \ 293 QLF2(S_S,W), \ 294 QLF2(S_D,X), \ 295 QLF2(S_S,X), \ 296 } 297 298 /* e.g. SCVTF <Hd>, <Wn>. */ 299 #define QL_INT2FP_H \ 300 { \ 301 QLF2 (S_H, W), \ 302 QLF2 (S_H, X), \ 303 } 304 305 /* e.g. FCVTNS <Xd>, <Dn>. */ 306 #define QL_FP2INT \ 307 { \ 308 QLF2(W,S_D), \ 309 QLF2(W,S_S), \ 310 QLF2(X,S_D), \ 311 QLF2(X,S_S), \ 312 } 313 314 /* e.g. FCVTNS <Hd>, <Wn>. */ 315 #define QL_FP2INT_H \ 316 { \ 317 QLF2 (W, S_H), \ 318 QLF2 (X, S_H), \ 319 } 320 321 /* e.g. FMOV <Xd>, <Vn>.D[1]. */ 322 #define QL_XVD1 \ 323 { \ 324 QLF2(X,S_D), \ 325 } 326 327 /* e.g. FMOV <Vd>.D[1], <Xn>. */ 328 #define QL_VD1X \ 329 { \ 330 QLF2(S_D,X), \ 331 } 332 333 /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */ 334 #define QL_EXTR \ 335 { \ 336 QLF4(W,W,W,imm_0_31), \ 337 QLF4(X,X,X,imm_0_63), \ 338 } 339 340 /* e.g. LSL <Wd>, <Wn>, #<uimm>. */ 341 #define QL_SHIFT \ 342 { \ 343 QLF3(W,W,imm_0_31), \ 344 QLF3(X,X,imm_0_63), \ 345 } 346 347 /* e.g. UXTH <Xd>, <Wn>. */ 348 #define QL_EXT \ 349 { \ 350 QLF2(W,W), \ 351 QLF2(X,W), \ 352 } 353 354 /* e.g. UXTW <Xd>, <Wn>. */ 355 #define QL_EXT_W \ 356 { \ 357 QLF2(X,W), \ 358 } 359 360 /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */ 361 #define QL_SSHIFT \ 362 { \ 363 QLF3(S_B , S_B , S_B ), \ 364 QLF3(S_H , S_H , S_H ), \ 365 QLF3(S_S , S_S , S_S ), \ 366 QLF3(S_D , S_D , S_D ) \ 367 } 368 369 /* e.g. SSHR <V><d>, <V><n>, #<shift>. */ 370 #define QL_SSHIFT_D \ 371 { \ 372 QLF3(S_D , S_D , S_D ) \ 373 } 374 375 /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ 376 #define QL_SSHIFT_SD \ 377 { \ 378 QLF3(S_S , S_S , S_S ), \ 379 QLF3(S_D , S_D , S_D ) \ 380 } 381 382 /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ 383 #define QL_SSHIFT_H \ 384 { \ 385 QLF3 (S_H, S_H, S_H) \ 386 } 387 388 /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ 389 #define QL_SSHIFTN \ 390 { \ 391 QLF3(S_B , S_H , S_B ), \ 392 QLF3(S_H , S_S , S_H ), \ 393 QLF3(S_S , S_D , S_S ), \ 394 } 395 396 /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>. 397 The register operand variant qualifiers are deliberately used for the 398 immediate operand to ease the operand encoding/decoding and qualifier 399 sequence matching. */ 400 #define QL_VSHIFT \ 401 { \ 402 QLF3(V_8B , V_8B , V_8B ), \ 403 QLF3(V_16B, V_16B, V_16B), \ 404 QLF3(V_4H , V_4H , V_4H ), \ 405 QLF3(V_8H , V_8H , V_8H ), \ 406 QLF3(V_2S , V_2S , V_2S ), \ 407 QLF3(V_4S , V_4S , V_4S ), \ 408 QLF3(V_2D , V_2D , V_2D ) \ 409 } 410 411 /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ 412 #define QL_VSHIFT_SD \ 413 { \ 414 QLF3(V_2S , V_2S , V_2S ), \ 415 QLF3(V_4S , V_4S , V_4S ), \ 416 QLF3(V_2D , V_2D , V_2D ) \ 417 } 418 419 /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */ 420 #define QL_VSHIFT_H \ 421 { \ 422 QLF3 (V_4H, V_4H, V_4H), \ 423 QLF3 (V_8H, V_8H, V_8H) \ 424 } 425 426 /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ 427 #define QL_VSHIFTN \ 428 { \ 429 QLF3(V_8B , V_8H , V_8B ), \ 430 QLF3(V_4H , V_4S , V_4H ), \ 431 QLF3(V_2S , V_2D , V_2S ), \ 432 } 433 434 /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */ 435 #define QL_VSHIFTN2 \ 436 { \ 437 QLF3(V_16B, V_8H, V_16B), \ 438 QLF3(V_8H , V_4S , V_8H ), \ 439 QLF3(V_4S , V_2D , V_4S ), \ 440 } 441 442 /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. 443 the 3rd qualifier is used to help the encoding. */ 444 #define QL_VSHIFTL \ 445 { \ 446 QLF3(V_8H , V_8B , V_8B ), \ 447 QLF3(V_4S , V_4H , V_4H ), \ 448 QLF3(V_2D , V_2S , V_2S ), \ 449 } 450 451 /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ 452 #define QL_VSHIFTL2 \ 453 { \ 454 QLF3(V_8H , V_16B, V_16B), \ 455 QLF3(V_4S , V_8H , V_8H ), \ 456 QLF3(V_2D , V_4S , V_4S ), \ 457 } 458 459 /* e.g. TBL. */ 460 #define QL_TABLE \ 461 { \ 462 QLF3(V_8B , V_16B, V_8B ), \ 463 QLF3(V_16B, V_16B, V_16B), \ 464 } 465 466 /* e.g. SHA1H. */ 467 #define QL_2SAMES \ 468 { \ 469 QLF2(S_S, S_S), \ 470 } 471 472 /* e.g. ABS <V><d>, <V><n>. */ 473 #define QL_2SAMED \ 474 { \ 475 QLF2(S_D, S_D), \ 476 } 477 478 /* e.g. CMGT <V><d>, <V><n>, #0. */ 479 #define QL_SISD_CMP_0 \ 480 { \ 481 QLF3(S_D, S_D, NIL), \ 482 } 483 484 /* e.g. FCMEQ <V><d>, <V><n>, #0. */ 485 #define QL_SISD_FCMP_0 \ 486 { \ 487 QLF3(S_S, S_S, NIL), \ 488 QLF3(S_D, S_D, NIL), \ 489 } 490 491 /* e.g. FCMEQ <V><d>, <V><n>, #0. */ 492 #define QL_SISD_FCMP_H_0 \ 493 { \ 494 QLF3 (S_H, S_H, NIL), \ 495 } 496 497 /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ 498 #define QL_SISD_PAIR \ 499 { \ 500 QLF2(S_S, V_2S), \ 501 QLF2(S_D, V_2D), \ 502 } 503 504 /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */ 505 #define QL_SISD_PAIR_H \ 506 { \ 507 QLF2 (S_H, V_2H), \ 508 } 509 510 /* e.g. ADDP <V><d>, <Vn>.<T>. */ 511 #define QL_SISD_PAIR_D \ 512 { \ 513 QLF2(S_D, V_2D), \ 514 } 515 516 /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */ 517 #define QL_S_2SAME \ 518 { \ 519 QLF2(S_B, S_B), \ 520 QLF2(S_H, S_H), \ 521 QLF2(S_S, S_S), \ 522 QLF2(S_D, S_D), \ 523 } 524 525 /* e.g. FCVTNS <V><d>, <V><n>. */ 526 #define QL_S_2SAMESD \ 527 { \ 528 QLF2(S_S, S_S), \ 529 QLF2(S_D, S_D), \ 530 } 531 532 /* e.g. FCVTNS <V><d>, <V><n>. */ 533 #define QL_S_2SAMEH \ 534 { \ 535 QLF2 (S_H, S_H), \ 536 } 537 538 /* e.g. SQXTN <Vb><d>, <Va><n>. */ 539 #define QL_SISD_NARROW \ 540 { \ 541 QLF2(S_B, S_H), \ 542 QLF2(S_H, S_S), \ 543 QLF2(S_S, S_D), \ 544 } 545 546 /* e.g. FCVTXN <Vb><d>, <Va><n>. */ 547 #define QL_SISD_NARROW_S \ 548 { \ 549 QLF2(S_S, S_D), \ 550 } 551 552 /* e.g. FCVT. */ 553 #define QL_FCVT \ 554 { \ 555 QLF2(S_S, S_H), \ 556 QLF2(S_S, S_D), \ 557 QLF2(S_D, S_H), \ 558 QLF2(S_D, S_S), \ 559 QLF2(S_H, S_S), \ 560 QLF2(S_H, S_D), \ 561 } 562 563 /* FMOV <Dd>, <Dn>. */ 564 #define QL_FP2 \ 565 { \ 566 QLF2(S_S, S_S), \ 567 QLF2(S_D, S_D), \ 568 } 569 570 /* FMOV <Hd>, <Hn>. */ 571 #define QL_FP2_H \ 572 { \ 573 QLF2 (S_H, S_H), \ 574 } 575 576 /* e.g. SQADD <V><d>, <V><n>, <V><m>. */ 577 #define QL_S_3SAME \ 578 { \ 579 QLF3(S_B, S_B, S_B), \ 580 QLF3(S_H, S_H, S_H), \ 581 QLF3(S_S, S_S, S_S), \ 582 QLF3(S_D, S_D, S_D), \ 583 } 584 585 /* e.g. CMGE <V><d>, <V><n>, <V><m>. */ 586 #define QL_S_3SAMED \ 587 { \ 588 QLF3(S_D, S_D, S_D), \ 589 } 590 591 /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */ 592 #define QL_SISD_HS \ 593 { \ 594 QLF3(S_H, S_H, S_H), \ 595 QLF3(S_S, S_S, S_S), \ 596 } 597 598 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */ 599 #define QL_SISDL_HS \ 600 { \ 601 QLF3(S_S, S_H, S_H), \ 602 QLF3(S_D, S_S, S_S), \ 603 } 604 605 /* FMUL <Sd>, <Sn>, <Sm>. */ 606 #define QL_FP3 \ 607 { \ 608 QLF3(S_S, S_S, S_S), \ 609 QLF3(S_D, S_D, S_D), \ 610 } 611 612 /* FMUL <Hd>, <Hn>, <Hm>. */ 613 #define QL_FP3_H \ 614 { \ 615 QLF3 (S_H, S_H, S_H), \ 616 } 617 618 /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */ 619 #define QL_FP4 \ 620 { \ 621 QLF4(S_S, S_S, S_S, S_S), \ 622 QLF4(S_D, S_D, S_D, S_D), \ 623 } 624 625 /* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */ 626 #define QL_FP4_H \ 627 { \ 628 QLF4 (S_H, S_H, S_H, S_H), \ 629 } 630 631 /* e.g. FCMP <Dn>, #0.0. */ 632 #define QL_DST_SD \ 633 { \ 634 QLF2(S_S, NIL), \ 635 QLF2(S_D, NIL), \ 636 } 637 638 /* e.g. FCMP <Hn>, #0.0. */ 639 #define QL_DST_H \ 640 { \ 641 QLF2 (S_H, NIL), \ 642 } 643 644 /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */ 645 #define QL_FP_COND \ 646 { \ 647 QLF4(S_S, S_S, S_S, NIL), \ 648 QLF4(S_D, S_D, S_D, NIL), \ 649 } 650 651 /* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */ 652 #define QL_FP_COND_H \ 653 { \ 654 QLF4 (S_H, S_H, S_H, NIL), \ 655 } 656 657 /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */ 658 #define QL_CCMP \ 659 { \ 660 QLF4(W, W, NIL, NIL), \ 661 QLF4(X, X, NIL, NIL), \ 662 } 663 664 /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */ 665 #define QL_CCMP_IMM \ 666 { \ 667 QLF4(W, NIL, NIL, NIL), \ 668 QLF4(X, NIL, NIL, NIL), \ 669 } 670 671 /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ 672 #define QL_FCCMP \ 673 { \ 674 QLF4(S_S, S_S, NIL, NIL), \ 675 QLF4(S_D, S_D, NIL, NIL), \ 676 } 677 678 /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */ 679 #define QL_FCCMP_H \ 680 { \ 681 QLF4 (S_H, S_H, NIL, NIL), \ 682 } 683 684 /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */ 685 #define QL_DUP_VX \ 686 { \ 687 QLF2(V_8B , S_B ), \ 688 QLF2(V_16B, S_B ), \ 689 QLF2(V_4H , S_H ), \ 690 QLF2(V_8H , S_H ), \ 691 QLF2(V_2S , S_S ), \ 692 QLF2(V_4S , S_S ), \ 693 QLF2(V_2D , S_D ), \ 694 } 695 696 /* e.g. DUP <Vd>.<T>, <Wn>. */ 697 #define QL_DUP_VR \ 698 { \ 699 QLF2(V_8B , W ), \ 700 QLF2(V_16B, W ), \ 701 QLF2(V_4H , W ), \ 702 QLF2(V_8H , W ), \ 703 QLF2(V_2S , W ), \ 704 QLF2(V_4S , W ), \ 705 QLF2(V_2D , X ), \ 706 } 707 708 /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */ 709 #define QL_INS_XR \ 710 { \ 711 QLF2(S_H , W ), \ 712 QLF2(S_S , W ), \ 713 QLF2(S_D , X ), \ 714 QLF2(S_B , W ), \ 715 } 716 717 /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */ 718 #define QL_SMOV \ 719 { \ 720 QLF2(W , S_H), \ 721 QLF2(X , S_H), \ 722 QLF2(X , S_S), \ 723 QLF2(W , S_B), \ 724 QLF2(X , S_B), \ 725 } 726 727 /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */ 728 #define QL_UMOV \ 729 { \ 730 QLF2(W , S_H), \ 731 QLF2(W , S_S), \ 732 QLF2(X , S_D), \ 733 QLF2(W , S_B), \ 734 } 735 736 /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */ 737 #define QL_MOV \ 738 { \ 739 QLF2(W , S_S), \ 740 QLF2(X , S_D), \ 741 } 742 743 /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */ 744 #define QL_V2SAME \ 745 { \ 746 QLF2(V_8B , V_8B ), \ 747 QLF2(V_16B, V_16B), \ 748 QLF2(V_4H , V_4H ), \ 749 QLF2(V_8H , V_8H ), \ 750 QLF2(V_2S , V_2S ), \ 751 QLF2(V_4S , V_4S ), \ 752 QLF2(V_2D , V_2D ), \ 753 } 754 755 /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */ 756 #define QL_V2SAMES \ 757 { \ 758 QLF2(V_2S , V_2S ), \ 759 QLF2(V_4S , V_4S ), \ 760 } 761 762 /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */ 763 #define QL_V2SAMEBH \ 764 { \ 765 QLF2(V_8B , V_8B ), \ 766 QLF2(V_16B, V_16B), \ 767 QLF2(V_4H , V_4H ), \ 768 QLF2(V_8H , V_8H ), \ 769 } 770 771 /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */ 772 #define QL_V2SAMESD \ 773 { \ 774 QLF2(V_2S , V_2S ), \ 775 QLF2(V_4S , V_4S ), \ 776 QLF2(V_2D , V_2D ), \ 777 } 778 779 /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */ 780 #define QL_V2SAMEBHS \ 781 { \ 782 QLF2(V_8B , V_8B ), \ 783 QLF2(V_16B, V_16B), \ 784 QLF2(V_4H , V_4H ), \ 785 QLF2(V_8H , V_8H ), \ 786 QLF2(V_2S , V_2S ), \ 787 QLF2(V_4S , V_4S ), \ 788 } 789 790 /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */ 791 #define QL_V2SAMEH \ 792 { \ 793 QLF2 (V_4H, V_4H), \ 794 QLF2 (V_8H, V_8H), \ 795 } 796 797 /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */ 798 #define QL_V2SAMEB \ 799 { \ 800 QLF2(V_8B , V_8B ), \ 801 QLF2(V_16B, V_16B), \ 802 } 803 804 /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */ 805 #define QL_V2PAIRWISELONGBHS \ 806 { \ 807 QLF2(V_4H , V_8B ), \ 808 QLF2(V_8H , V_16B), \ 809 QLF2(V_2S , V_4H ), \ 810 QLF2(V_4S , V_8H ), \ 811 QLF2(V_1D , V_2S ), \ 812 QLF2(V_2D , V_4S ), \ 813 } 814 815 /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ 816 #define QL_V2LONGBHS \ 817 { \ 818 QLF2(V_8H , V_8B ), \ 819 QLF2(V_4S , V_4H ), \ 820 QLF2(V_2D , V_2S ), \ 821 } 822 823 /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */ 824 #define QL_V2LONGBHS2 \ 825 { \ 826 QLF2(V_8H , V_16B), \ 827 QLF2(V_4S , V_8H ), \ 828 QLF2(V_2D , V_4S ), \ 829 } 830 831 /* */ 832 #define QL_V3SAME \ 833 { \ 834 QLF3(V_8B , V_8B , V_8B ), \ 835 QLF3(V_16B, V_16B, V_16B), \ 836 QLF3(V_4H , V_4H , V_4H ), \ 837 QLF3(V_8H , V_8H , V_8H ), \ 838 QLF3(V_2S , V_2S , V_2S ), \ 839 QLF3(V_4S , V_4S , V_4S ), \ 840 QLF3(V_2D , V_2D , V_2D ) \ 841 } 842 843 /* e.g. SHADD. */ 844 #define QL_V3SAMEBHS \ 845 { \ 846 QLF3(V_8B , V_8B , V_8B ), \ 847 QLF3(V_16B, V_16B, V_16B), \ 848 QLF3(V_4H , V_4H , V_4H ), \ 849 QLF3(V_8H , V_8H , V_8H ), \ 850 QLF3(V_2S , V_2S , V_2S ), \ 851 QLF3(V_4S , V_4S , V_4S ), \ 852 } 853 854 /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 855 #define QL_V2NARRS \ 856 { \ 857 QLF2(V_2S , V_2D ), \ 858 } 859 860 /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 861 #define QL_V2NARRS2 \ 862 { \ 863 QLF2(V_4S , V_2D ), \ 864 } 865 866 /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 867 #define QL_V2NARRHS \ 868 { \ 869 QLF2(V_4H , V_4S ), \ 870 QLF2(V_2S , V_2D ), \ 871 } 872 873 /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 874 #define QL_V2NARRHS2 \ 875 { \ 876 QLF2(V_8H , V_4S ), \ 877 QLF2(V_4S , V_2D ), \ 878 } 879 880 /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ 881 #define QL_V2LONGHS \ 882 { \ 883 QLF2(V_4S , V_4H ), \ 884 QLF2(V_2D , V_2S ), \ 885 } 886 887 /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ 888 #define QL_V2LONGHS2 \ 889 { \ 890 QLF2(V_4S , V_8H ), \ 891 QLF2(V_2D , V_4S ), \ 892 } 893 894 /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 895 #define QL_V2NARRBHS \ 896 { \ 897 QLF2(V_8B , V_8H ), \ 898 QLF2(V_4H , V_4S ), \ 899 QLF2(V_2S , V_2D ), \ 900 } 901 902 /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ 903 #define QL_V2NARRBHS2 \ 904 { \ 905 QLF2(V_16B, V_8H ), \ 906 QLF2(V_8H , V_4S ), \ 907 QLF2(V_4S , V_2D ), \ 908 } 909 910 /* e.g. ORR. */ 911 #define QL_V2SAMEB \ 912 { \ 913 QLF2(V_8B , V_8B ), \ 914 QLF2(V_16B, V_16B), \ 915 } 916 917 /* e.g. AESE. */ 918 #define QL_V2SAME16B \ 919 { \ 920 QLF2(V_16B, V_16B), \ 921 } 922 923 /* e.g. SHA1SU1. */ 924 #define QL_V2SAME4S \ 925 { \ 926 QLF2(V_4S, V_4S), \ 927 } 928 929 /* e.g. SHA1SU0. */ 930 #define QL_V3SAME4S \ 931 { \ 932 QLF3(V_4S, V_4S, V_4S), \ 933 } 934 935 /* e.g. SHADD. */ 936 #define QL_V3SAMEB \ 937 { \ 938 QLF3(V_8B , V_8B , V_8B ), \ 939 QLF3(V_16B, V_16B, V_16B), \ 940 } 941 942 /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */ 943 #define QL_VEXT \ 944 { \ 945 QLF4(V_8B , V_8B , V_8B , imm_0_7), \ 946 QLF4(V_16B, V_16B, V_16B, imm_0_15), \ 947 } 948 949 /* e.g. . */ 950 #define QL_V3SAMEHS \ 951 { \ 952 QLF3(V_4H , V_4H , V_4H ), \ 953 QLF3(V_8H , V_8H , V_8H ), \ 954 QLF3(V_2S , V_2S , V_2S ), \ 955 QLF3(V_4S , V_4S , V_4S ), \ 956 } 957 958 /* */ 959 #define QL_V3SAMESD \ 960 { \ 961 QLF3(V_2S , V_2S , V_2S ), \ 962 QLF3(V_4S , V_4S , V_4S ), \ 963 QLF3(V_2D , V_2D , V_2D ) \ 964 } 965 966 /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */ 967 #define QL_V3SAMEH \ 968 { \ 969 QLF3 (V_4H , V_4H , V_4H ), \ 970 QLF3 (V_8H , V_8H , V_8H ), \ 971 } 972 973 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ 974 #define QL_V3LONGHS \ 975 { \ 976 QLF3(V_4S , V_4H , V_4H ), \ 977 QLF3(V_2D , V_2S , V_2S ), \ 978 } 979 980 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ 981 #define QL_V3LONGHS2 \ 982 { \ 983 QLF3(V_4S , V_8H , V_8H ), \ 984 QLF3(V_2D , V_4S , V_4S ), \ 985 } 986 987 /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ 988 #define QL_V3LONGBHS \ 989 { \ 990 QLF3(V_8H , V_8B , V_8B ), \ 991 QLF3(V_4S , V_4H , V_4H ), \ 992 QLF3(V_2D , V_2S , V_2S ), \ 993 } 994 995 /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */ 996 #define QL_V3LONGBHS2 \ 997 { \ 998 QLF3(V_8H , V_16B , V_16B ), \ 999 QLF3(V_4S , V_8H , V_8H ), \ 1000 QLF3(V_2D , V_4S , V_4S ), \ 1001 } 1002 1003 /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ 1004 #define QL_V3WIDEBHS \ 1005 { \ 1006 QLF3(V_8H , V_8H , V_8B ), \ 1007 QLF3(V_4S , V_4S , V_4H ), \ 1008 QLF3(V_2D , V_2D , V_2S ), \ 1009 } 1010 1011 /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */ 1012 #define QL_V3WIDEBHS2 \ 1013 { \ 1014 QLF3(V_8H , V_8H , V_16B ), \ 1015 QLF3(V_4S , V_4S , V_8H ), \ 1016 QLF3(V_2D , V_2D , V_4S ), \ 1017 } 1018 1019 /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ 1020 #define QL_V3NARRBHS \ 1021 { \ 1022 QLF3(V_8B , V_8H , V_8H ), \ 1023 QLF3(V_4H , V_4S , V_4S ), \ 1024 QLF3(V_2S , V_2D , V_2D ), \ 1025 } 1026 1027 /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */ 1028 #define QL_V3NARRBHS2 \ 1029 { \ 1030 QLF3(V_16B , V_8H , V_8H ), \ 1031 QLF3(V_8H , V_4S , V_4S ), \ 1032 QLF3(V_4S , V_2D , V_2D ), \ 1033 } 1034 1035 /* e.g. PMULL. */ 1036 #define QL_V3LONGB \ 1037 { \ 1038 QLF3(V_8H , V_8B , V_8B ), \ 1039 } 1040 1041 /* e.g. PMULL crypto. */ 1042 #define QL_V3LONGD \ 1043 { \ 1044 QLF3(V_1Q , V_1D , V_1D ), \ 1045 } 1046 1047 /* e.g. PMULL2. */ 1048 #define QL_V3LONGB2 \ 1049 { \ 1050 QLF3(V_8H , V_16B, V_16B), \ 1051 } 1052 1053 /* e.g. PMULL2 crypto. */ 1054 #define QL_V3LONGD2 \ 1055 { \ 1056 QLF3(V_1Q , V_2D , V_2D ), \ 1057 } 1058 1059 /* e.g. SHA1C. */ 1060 #define QL_SHAUPT \ 1061 { \ 1062 QLF3(S_Q, S_S, V_4S), \ 1063 } 1064 1065 /* e.g. SHA256H2. */ 1066 #define QL_SHA256UPT \ 1067 { \ 1068 QLF3(S_Q, S_Q, V_4S), \ 1069 } 1070 1071 /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */ 1072 #define QL_W1_LDST_EXC \ 1073 { \ 1074 QLF2(W, NIL), \ 1075 } 1076 1077 /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */ 1078 #define QL_R1NIL \ 1079 { \ 1080 QLF2(W, NIL), \ 1081 QLF2(X, NIL), \ 1082 } 1083 1084 /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ 1085 #define QL_W2_LDST_EXC \ 1086 { \ 1087 QLF3(W, W, NIL), \ 1088 } 1089 1090 /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */ 1091 #define QL_R2_LDST_EXC \ 1092 { \ 1093 QLF3(W, W, NIL), \ 1094 QLF3(W, X, NIL), \ 1095 } 1096 1097 /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ 1098 #define QL_R2NIL \ 1099 { \ 1100 QLF3(W, W, NIL), \ 1101 QLF3(X, X, NIL), \ 1102 } 1103 1104 /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ 1105 #define QL_R4NIL \ 1106 { \ 1107 QLF5(W, W, W, W, NIL), \ 1108 QLF5(X, X, X, X, NIL), \ 1109 } 1110 1111 /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ 1112 #define QL_R3_LDST_EXC \ 1113 { \ 1114 QLF4(W, W, W, NIL), \ 1115 QLF4(W, X, X, NIL), \ 1116 } 1117 1118 /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1119 #define QL_LDST_FP \ 1120 { \ 1121 QLF2(S_B, S_B), \ 1122 QLF2(S_H, S_H), \ 1123 QLF2(S_S, S_S), \ 1124 QLF2(S_D, S_D), \ 1125 QLF2(S_Q, S_Q), \ 1126 } 1127 1128 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1129 #define QL_LDST_R \ 1130 { \ 1131 QLF2(W, S_S), \ 1132 QLF2(X, S_D), \ 1133 } 1134 1135 /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1136 #define QL_LDST_W8 \ 1137 { \ 1138 QLF2(W, S_B), \ 1139 } 1140 1141 /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1142 #define QL_LDST_R8 \ 1143 { \ 1144 QLF2(W, S_B), \ 1145 QLF2(X, S_B), \ 1146 } 1147 1148 /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1149 #define QL_LDST_W16 \ 1150 { \ 1151 QLF2(W, S_H), \ 1152 } 1153 1154 /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1155 #define QL_LDST_X32 \ 1156 { \ 1157 QLF2(X, S_S), \ 1158 } 1159 1160 /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1161 #define QL_LDST_R16 \ 1162 { \ 1163 QLF2(W, S_H), \ 1164 QLF2(X, S_H), \ 1165 } 1166 1167 /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ 1168 #define QL_LDST_PRFM \ 1169 { \ 1170 QLF2(NIL, S_D), \ 1171 } 1172 1173 /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */ 1174 #define QL_LDST_PAIR_X32 \ 1175 { \ 1176 QLF3(X, X, S_S), \ 1177 } 1178 1179 /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */ 1180 #define QL_LDST_PAIR_R \ 1181 { \ 1182 QLF3(W, W, S_S), \ 1183 QLF3(X, X, S_D), \ 1184 } 1185 1186 /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */ 1187 #define QL_LDST_PAIR_FP \ 1188 { \ 1189 QLF3(S_S, S_S, S_S), \ 1190 QLF3(S_D, S_D, S_D), \ 1191 QLF3(S_Q, S_Q, S_Q), \ 1192 } 1193 1194 /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ 1195 #define QL_SIMD_LDST \ 1196 { \ 1197 QLF2(V_8B, NIL), \ 1198 QLF2(V_16B, NIL), \ 1199 QLF2(V_4H, NIL), \ 1200 QLF2(V_8H, NIL), \ 1201 QLF2(V_2S, NIL), \ 1202 QLF2(V_4S, NIL), \ 1203 QLF2(V_2D, NIL), \ 1204 } 1205 1206 /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */ 1207 #define QL_SIMD_LDST_ANY \ 1208 { \ 1209 QLF2(V_8B, NIL), \ 1210 QLF2(V_16B, NIL), \ 1211 QLF2(V_4H, NIL), \ 1212 QLF2(V_8H, NIL), \ 1213 QLF2(V_2S, NIL), \ 1214 QLF2(V_4S, NIL), \ 1215 QLF2(V_1D, NIL), \ 1216 QLF2(V_2D, NIL), \ 1217 } 1218 1219 /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */ 1220 #define QL_SIMD_LDSTONE \ 1221 { \ 1222 QLF2(S_B, NIL), \ 1223 QLF2(S_H, NIL), \ 1224 QLF2(S_S, NIL), \ 1225 QLF2(S_D, NIL), \ 1226 } 1227 1228 /* e.g. ADDV <V><d>, <Vn>.<T>. */ 1229 #define QL_XLANES \ 1230 { \ 1231 QLF2(S_B, V_8B), \ 1232 QLF2(S_B, V_16B), \ 1233 QLF2(S_H, V_4H), \ 1234 QLF2(S_H, V_8H), \ 1235 QLF2(S_S, V_4S), \ 1236 } 1237 1238 /* e.g. FMINV <V><d>, <Vn>.<T>. */ 1239 #define QL_XLANES_FP \ 1240 { \ 1241 QLF2(S_S, V_4S), \ 1242 } 1243 1244 /* e.g. FMINV <V><d>, <Vn>.<T>. */ 1245 #define QL_XLANES_FP_H \ 1246 { \ 1247 QLF2 (S_H, V_4H), \ 1248 QLF2 (S_H, V_8H), \ 1249 } 1250 1251 /* e.g. SADDLV <V><d>, <Vn>.<T>. */ 1252 #define QL_XLANES_L \ 1253 { \ 1254 QLF2(S_H, V_8B), \ 1255 QLF2(S_H, V_16B), \ 1256 QLF2(S_S, V_4H), \ 1257 QLF2(S_S, V_8H), \ 1258 QLF2(S_D, V_4S), \ 1259 } 1260 1261 /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */ 1262 #define QL_ELEMENT \ 1263 { \ 1264 QLF3(V_4H, V_4H, S_H), \ 1265 QLF3(V_8H, V_8H, S_H), \ 1266 QLF3(V_2S, V_2S, S_S), \ 1267 QLF3(V_4S, V_4S, S_S), \ 1268 } 1269 1270 /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ 1271 #define QL_ELEMENT_L \ 1272 { \ 1273 QLF3(V_4S, V_4H, S_H), \ 1274 QLF3(V_2D, V_2S, S_S), \ 1275 } 1276 1277 /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */ 1278 #define QL_ELEMENT_L2 \ 1279 { \ 1280 QLF3(V_4S, V_8H, S_H), \ 1281 QLF3(V_2D, V_4S, S_S), \ 1282 } 1283 1284 /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ 1285 #define QL_ELEMENT_FP \ 1286 { \ 1287 QLF3(V_2S, V_2S, S_S), \ 1288 QLF3(V_4S, V_4S, S_S), \ 1289 QLF3(V_2D, V_2D, S_D), \ 1290 } 1291 1292 /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */ 1293 #define QL_ELEMENT_FP_H \ 1294 { \ 1295 QLF3 (V_4H, V_4H, S_H), \ 1296 QLF3 (V_8H, V_8H, S_H), \ 1297 } 1298 1299 /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */ 1300 #define QL_SIMD_IMM_S0W \ 1301 { \ 1302 QLF2(V_2S, LSL), \ 1303 QLF2(V_4S, LSL), \ 1304 } 1305 1306 /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */ 1307 #define QL_SIMD_IMM_S1W \ 1308 { \ 1309 QLF2(V_2S, MSL), \ 1310 QLF2(V_4S, MSL), \ 1311 } 1312 1313 /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */ 1314 #define QL_SIMD_IMM_S0H \ 1315 { \ 1316 QLF2(V_4H, LSL), \ 1317 QLF2(V_8H, LSL), \ 1318 } 1319 1320 /* e.g. FMOV <Vd>.<T>, #<imm>. */ 1321 #define QL_SIMD_IMM_S \ 1322 { \ 1323 QLF2(V_2S, NIL), \ 1324 QLF2(V_4S, NIL), \ 1325 } 1326 1327 /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ 1328 #define QL_SIMD_IMM_B \ 1329 { \ 1330 QLF2(V_8B, LSL), \ 1331 QLF2(V_16B, LSL), \ 1332 } 1333 /* e.g. MOVI <Dd>, #<imm>. */ 1334 #define QL_SIMD_IMM_D \ 1335 { \ 1336 QLF2(S_D, NIL), \ 1337 } 1338 1339 /* e.g. FMOV <Vd>.<T>, #<imm>. */ 1340 #define QL_SIMD_IMM_H \ 1341 { \ 1342 QLF2 (V_4H, NIL), \ 1343 QLF2 (V_8H, NIL), \ 1344 } 1345 1346 /* e.g. MOVI <Vd>.2D, #<imm>. */ 1347 #define QL_SIMD_IMM_V2D \ 1348 { \ 1349 QLF2(V_2D, NIL), \ 1350 } 1351 1352 /* Opcode table. */ 1354 1355 static const aarch64_feature_set aarch64_feature_v8 = 1356 AARCH64_FEATURE (AARCH64_FEATURE_V8, 0); 1357 static const aarch64_feature_set aarch64_feature_fp = 1358 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0); 1359 static const aarch64_feature_set aarch64_feature_simd = 1360 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0); 1361 static const aarch64_feature_set aarch64_feature_crypto = 1362 AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0); 1363 static const aarch64_feature_set aarch64_feature_crc = 1364 AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0); 1365 static const aarch64_feature_set aarch64_feature_lse = 1366 AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0); 1367 static const aarch64_feature_set aarch64_feature_lor = 1368 AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0); 1369 static const aarch64_feature_set aarch64_feature_rdma = 1370 AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0); 1371 static const aarch64_feature_set aarch64_feature_ras = 1372 AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0); 1373 static const aarch64_feature_set aarch64_feature_v8_2 = 1374 AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0); 1375 static const aarch64_feature_set aarch64_feature_fp_f16 = 1376 AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0); 1377 static const aarch64_feature_set aarch64_feature_simd_f16 = 1378 AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0); 1379 static const aarch64_feature_set aarch64_feature_stat_profile = 1380 AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0); 1381 1382 #define CORE &aarch64_feature_v8 1383 #define FP &aarch64_feature_fp 1384 #define SIMD &aarch64_feature_simd 1385 #define CRYPTO &aarch64_feature_crypto 1386 #define CRC &aarch64_feature_crc 1387 #define LSE &aarch64_feature_lse 1388 #define LOR &aarch64_feature_lor 1389 #define RDMA &aarch64_feature_rdma 1390 #define FP_F16 &aarch64_feature_fp_f16 1391 #define SIMD_F16 &aarch64_feature_simd_f16 1392 #define RAS &aarch64_feature_ras 1393 #define STAT_PROFILE &aarch64_feature_stat_profile 1394 #define ARMV8_2 &aarch64_feature_v8_2 1395 1396 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1397 { NAME, OPCODE, MASK, CLASS, 0, CORE, OPS, QUALS, FLAGS, NULL } 1398 #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1399 { NAME, OPCODE, MASK, CLASS, 0, FP, OPS, QUALS, FLAGS, NULL } 1400 #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1401 { NAME, OPCODE, MASK, CLASS, 0, SIMD, OPS, QUALS, FLAGS, NULL } 1402 #define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1403 { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, NULL } 1404 #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1405 { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, NULL } 1406 #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1407 { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, NULL } 1408 #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1409 { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, NULL } 1410 #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1411 { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, NULL } 1412 #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1413 { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, NULL } 1414 #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ 1415 { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, NULL } 1416 1417 struct aarch64_opcode aarch64_opcode_table[] = 1418 { 1419 /* Add/subtract (with carry). */ 1420 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), 1421 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), 1422 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), 1423 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 1424 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF), 1425 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 1426 /* Add/subtract (extended register). */ 1427 CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), 1428 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), 1429 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 1430 CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF), 1431 CORE_INSN ("subs", 0x6b200000, 0x7fe00000, addsub_ext, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF), 1432 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF), 1433 /* Add/subtract (immediate). */ 1434 { "add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF, NULL}, 1435 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF), 1436 CORE_INSN ("adds", 0x31000000, 0x7f000000, addsub_imm, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), 1437 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 1438 CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF), 1439 CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), 1440 CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF), 1441 /* Add/subtract (shifted register). */ 1442 CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), 1443 CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), 1444 CORE_INSN ("cmn", 0x2b00001f, 0x7f20001f, addsub_shift, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 1445 CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), 1446 CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 1447 CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), 1448 CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 1449 CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF), 1450 /* AdvSIMD across lanes. */ 1451 SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), 1452 SIMD_INSN ("smaxv", 0x0e30a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), 1453 SIMD_INSN ("sminv", 0x0e31a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), 1454 SIMD_INSN ("addv", 0x0e31b800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), 1455 SIMD_INSN ("uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ), 1456 SIMD_INSN ("umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), 1457 SIMD_INSN ("uminv", 0x2e31a800, 0xbf3ffc00, asimdall, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ), 1458 SIMD_INSN ("fmaxnmv",0x2e30c800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), 1459 SF16_INSN ("fmaxnmv",0x0e30c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), 1460 SIMD_INSN ("fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), 1461 SF16_INSN ("fmaxv", 0x0e30f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), 1462 SIMD_INSN ("fminnmv",0x2eb0c800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), 1463 SF16_INSN ("fminnmv",0x0eb0c800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), 1464 SIMD_INSN ("fminv", 0x2eb0f800, 0xbfbffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ), 1465 SF16_INSN ("fminv", 0x0eb0f800, 0xbffffc00, asimdall, OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ), 1466 /* AdvSIMD three different. */ 1467 SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1468 SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1469 SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), 1470 SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), 1471 SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1472 SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1473 SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), 1474 SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), 1475 SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), 1476 SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), 1477 SIMD_INSN ("sabal", 0x0e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1478 SIMD_INSN ("sabal2", 0x4e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1479 SIMD_INSN ("subhn", 0x0e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), 1480 SIMD_INSN ("subhn2", 0x4e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), 1481 SIMD_INSN ("sabdl", 0x0e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1482 SIMD_INSN ("sabdl2", 0x4e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1483 SIMD_INSN ("smlal", 0x0e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1484 SIMD_INSN ("smlal2", 0x4e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1485 SIMD_INSN ("sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), 1486 SIMD_INSN ("sqdmlal2",0x4e209000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), 1487 SIMD_INSN ("smlsl", 0x0e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1488 SIMD_INSN ("smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1489 SIMD_INSN ("sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), 1490 SIMD_INSN ("sqdmlsl2",0x4e20b000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), 1491 SIMD_INSN ("smull", 0x0e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1492 SIMD_INSN ("smull2", 0x4e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1493 SIMD_INSN ("sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ), 1494 SIMD_INSN ("sqdmull2",0x4e20d000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ), 1495 SIMD_INSN ("pmull", 0x0e20e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0), 1496 CRYP_INSN ("pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0), 1497 SIMD_INSN ("pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0), 1498 CRYP_INSN ("pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0), 1499 SIMD_INSN ("uaddl", 0x2e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1500 SIMD_INSN ("uaddl2", 0x6e200000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1501 SIMD_INSN ("uaddw", 0x2e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), 1502 SIMD_INSN ("uaddw2", 0x6e201000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), 1503 SIMD_INSN ("usubl", 0x2e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1504 SIMD_INSN ("usubl2", 0x6e202000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1505 SIMD_INSN ("usubw", 0x2e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ), 1506 SIMD_INSN ("usubw2", 0x6e203000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ), 1507 SIMD_INSN ("raddhn", 0x2e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), 1508 SIMD_INSN ("raddhn2", 0x6e204000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), 1509 SIMD_INSN ("uabal", 0x2e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1510 SIMD_INSN ("uabal2", 0x6e205000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1511 SIMD_INSN ("rsubhn", 0x2e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ), 1512 SIMD_INSN ("rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ), 1513 SIMD_INSN ("uabdl", 0x2e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1514 SIMD_INSN ("uabdl2", 0x6e207000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1515 SIMD_INSN ("umlal", 0x2e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1516 SIMD_INSN ("umlal2", 0x6e208000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1517 SIMD_INSN ("umlsl", 0x2e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1518 SIMD_INSN ("umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1519 SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ), 1520 SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ), 1521 /* AdvSIMD vector x indexed element. */ 1522 SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1523 SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1524 SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1525 SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1526 SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1527 SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1528 SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1529 SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1530 SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1531 SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1532 SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1533 SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1534 SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1535 SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1536 SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1537 SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), 1538 SF16_INSN ("fmla", 0x0f001000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), 1539 SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), 1540 SF16_INSN ("fmls", 0x0f005000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), 1541 SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), 1542 SF16_INSN ("fmul", 0x0f009000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), 1543 SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1544 SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1545 SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1546 SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1547 SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1548 SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1549 SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), 1550 SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), 1551 SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), 1552 SF16_INSN ("fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ), 1553 RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1554 RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), 1555 /* AdvSIMD EXT. */ 1556 SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ), 1557 /* AdvSIMD modified immediate. */ 1558 SIMD_INSN ("movi", 0x0f000400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), 1559 SIMD_INSN ("orr", 0x0f001400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), 1560 SIMD_INSN ("movi", 0x0f008400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), 1561 SIMD_INSN ("orr", 0x0f009400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), 1562 SIMD_INSN ("movi", 0x0f00c400, 0xbff8ec00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), 1563 SIMD_INSN ("movi", 0x0f00e400, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ), 1564 SIMD_INSN ("fmov", 0x0f00f400, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ), 1565 SF16_INSN ("fmov", 0x0f00fc00, 0xbff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ), 1566 SIMD_INSN ("mvni", 0x2f000400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), 1567 SIMD_INSN ("bic", 0x2f001400, 0xbff89c00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ), 1568 SIMD_INSN ("mvni", 0x2f008400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), 1569 SIMD_INSN ("bic", 0x2f009400, 0xbff8dc00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ), 1570 SIMD_INSN ("mvni", 0x2f00c400, 0xbff8ec00, asimdimm, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ), 1571 SIMD_INSN ("movi", 0x2f00e400, 0xfff8fc00, asimdimm, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ), 1572 SIMD_INSN ("movi", 0x6f00e400, 0xfff8fc00, asimdimm, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ), 1573 SIMD_INSN ("fmov", 0x6f00f400, 0xfff8fc00, asimdimm, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ), 1574 /* AdvSIMD copy. */ 1575 SIMD_INSN ("dup", 0x0e000400, 0xbfe0fc00, asimdins, OP2 (Vd, En), QL_DUP_VX, F_T), 1576 SIMD_INSN ("dup", 0x0e000c00, 0xbfe0fc00, asimdins, OP2 (Vd, Rn), QL_DUP_VR, F_T), 1577 SIMD_INSN ("smov",0x0e002c00, 0xbfe0fc00, asimdins, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q), 1578 SIMD_INSN ("umov",0x0e003c00, 0xbfe0fc00, asimdins, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q), 1579 SIMD_INSN ("mov", 0x0e003c00, 0xbfe0fc00, asimdins, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q), 1580 SIMD_INSN ("ins", 0x4e001c00, 0xffe0fc00, asimdins, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS), 1581 SIMD_INSN ("mov", 0x4e001c00, 0xffe0fc00, asimdins, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS), 1582 SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS), 1583 SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, OP2 (Ed, En), QL_S_2SAME, F_ALIAS), 1584 /* AdvSIMD two-reg misc. */ 1585 SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), 1586 SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), 1587 SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), 1588 SIMD_INSN ("suqadd",0x0e203800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), 1589 SIMD_INSN ("cls", 0x0e204800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), 1590 SIMD_INSN ("cnt", 0x0e205800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), 1591 SIMD_INSN ("sadalp",0x0e206800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), 1592 SIMD_INSN ("sqabs", 0x0e207800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), 1593 SIMD_INSN ("cmgt", 0x0e208800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), 1594 SIMD_INSN ("cmeq", 0x0e209800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), 1595 SIMD_INSN ("cmlt", 0x0e20a800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), 1596 SIMD_INSN ("abs", 0x0e20b800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), 1597 SIMD_INSN ("xtn", 0x0e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), 1598 SIMD_INSN ("xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), 1599 SIMD_INSN ("sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), 1600 SIMD_INSN ("sqxtn2",0x4e214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), 1601 {"fcvtn", 0x0e216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC, NULL}, 1602 {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC, NULL}, 1603 {"fcvtl", 0x0e217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC, NULL}, 1604 {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC, NULL}, 1605 SIMD_INSN ("frintn", 0x0e218800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1606 SF16_INSN ("frintn", 0x0e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1607 SIMD_INSN ("frintm", 0x0e219800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1608 SF16_INSN ("frintm", 0x0e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1609 SIMD_INSN ("fcvtns", 0x0e21a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1610 SF16_INSN ("fcvtns", 0x0e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1611 SIMD_INSN ("fcvtms", 0x0e21b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1612 SF16_INSN ("fcvtms", 0x0e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1613 SIMD_INSN ("fcvtas", 0x0e21c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1614 SF16_INSN ("fcvtas", 0x0e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1615 SIMD_INSN ("scvtf", 0x0e21d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1616 SF16_INSN ("scvtf", 0x0e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1617 SIMD_INSN ("fcmgt", 0x0ea0c800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), 1618 SF16_INSN ("fcmgt", 0x0ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), 1619 SIMD_INSN ("fcmeq", 0x0ea0d800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), 1620 SF16_INSN ("fcmeq", 0x0ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), 1621 SIMD_INSN ("fcmlt", 0x0ea0e800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), 1622 SF16_INSN ("fcmlt", 0x0ef8e800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), 1623 SIMD_INSN ("fabs", 0x0ea0f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1624 SF16_INSN ("fabs", 0x0ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1625 SIMD_INSN ("frintp", 0x0ea18800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1626 SF16_INSN ("frintp", 0x0ef98800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1627 SIMD_INSN ("frintz", 0x0ea19800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1628 SF16_INSN ("frintz", 0x0ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1629 SIMD_INSN ("fcvtps", 0x0ea1a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1630 SF16_INSN ("fcvtps", 0x0ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1631 SIMD_INSN ("fcvtzs", 0x0ea1b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1632 SF16_INSN ("fcvtzs", 0x0ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1633 SIMD_INSN ("urecpe", 0x0ea1c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), 1634 SIMD_INSN ("frecpe", 0x0ea1d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1635 SF16_INSN ("frecpe", 0x0ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1636 SIMD_INSN ("rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ), 1637 SIMD_INSN ("uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), 1638 SIMD_INSN ("usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), 1639 SIMD_INSN ("clz", 0x2e204800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ), 1640 SIMD_INSN ("uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ), 1641 SIMD_INSN ("sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), 1642 SIMD_INSN ("cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), 1643 SIMD_INSN ("cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ), 1644 SIMD_INSN ("neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ), 1645 SIMD_INSN ("sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), 1646 SIMD_INSN ("sqxtun2",0x6e212800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), 1647 SIMD_INSN ("shll", 0x2e213800, 0xff3ffc00, asimdmisc, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ), 1648 SIMD_INSN ("shll2", 0x6e213800, 0xff3ffc00, asimdmisc, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ), 1649 SIMD_INSN ("uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ), 1650 SIMD_INSN ("uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ), 1651 SIMD_INSN ("fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRS, 0), 1652 SIMD_INSN ("fcvtxn2",0x6e616800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2NARRS2, 0), 1653 SIMD_INSN ("frinta", 0x2e218800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1654 SF16_INSN ("frinta", 0x2e798800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1655 SIMD_INSN ("frintx", 0x2e219800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1656 SF16_INSN ("frintx", 0x2e799800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1657 SIMD_INSN ("fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1658 SF16_INSN ("fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1659 SIMD_INSN ("fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1660 SF16_INSN ("fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1661 SIMD_INSN ("fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1662 SF16_INSN ("fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1663 SIMD_INSN ("ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1664 SF16_INSN ("ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1665 SIMD_INSN ("not", 0x2e205800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS), 1666 SIMD_INSN ("mvn", 0x2e205800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS), 1667 SIMD_INSN ("rbit", 0x2e605800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ), 1668 SIMD_INSN ("fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), 1669 SF16_INSN ("fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), 1670 SIMD_INSN ("fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ), 1671 SF16_INSN ("fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ), 1672 SIMD_INSN ("fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1673 SF16_INSN ("fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1674 SIMD_INSN ("frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1675 SF16_INSN ("frinti", 0x2ef99800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1676 SIMD_INSN ("fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1677 SF16_INSN ("fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1678 SIMD_INSN ("fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1679 SF16_INSN ("fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1680 SIMD_INSN ("ursqrte",0x2ea1c800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ), 1681 SIMD_INSN ("frsqrte",0x2ea1d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1682 SF16_INSN ("frsqrte",0x2ef9d800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1683 SIMD_INSN ("fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ), 1684 SF16_INSN ("fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ), 1685 /* AdvSIMD ZIP/UZP/TRN. */ 1686 SIMD_INSN ("uzp1", 0xe001800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1687 SIMD_INSN ("trn1", 0xe002800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1688 SIMD_INSN ("zip1", 0xe003800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1689 SIMD_INSN ("uzp2", 0xe005800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1690 SIMD_INSN ("trn2", 0xe006800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1691 SIMD_INSN ("zip2", 0xe007800, 0xbf20fc00, asimdperm, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1692 /* AdvSIMD three same. */ 1693 SIMD_INSN ("shadd", 0xe200400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1694 SIMD_INSN ("sqadd", 0xe200c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1695 SIMD_INSN ("srhadd", 0xe201400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1696 SIMD_INSN ("shsub", 0xe202400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1697 SIMD_INSN ("sqsub", 0xe202c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1698 SIMD_INSN ("cmgt", 0xe203400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1699 SIMD_INSN ("cmge", 0xe203c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1700 SIMD_INSN ("sshl", 0xe204400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1701 SIMD_INSN ("sqshl", 0xe204c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1702 SIMD_INSN ("srshl", 0xe205400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1703 SIMD_INSN ("sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1704 SIMD_INSN ("smax", 0xe206400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1705 SIMD_INSN ("smin", 0xe206c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1706 SIMD_INSN ("sabd", 0xe207400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1707 SIMD_INSN ("saba", 0xe207c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1708 SIMD_INSN ("add", 0xe208400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1709 SIMD_INSN ("cmtst", 0xe208c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1710 SIMD_INSN ("mla", 0xe209400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1711 SIMD_INSN ("mul", 0xe209c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1712 SIMD_INSN ("smaxp", 0xe20a400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1713 SIMD_INSN ("sminp", 0xe20ac00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1714 SIMD_INSN ("sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), 1715 SIMD_INSN ("addp", 0xe20bc00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1716 SIMD_INSN ("fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1717 SF16_INSN ("fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1718 SIMD_INSN ("fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1719 SF16_INSN ("fmla", 0xe400c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1720 SIMD_INSN ("fadd", 0xe20d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1721 SF16_INSN ("fadd", 0xe401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1722 SIMD_INSN ("fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1723 SF16_INSN ("fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1724 SIMD_INSN ("fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1725 SF16_INSN ("fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1726 SIMD_INSN ("fmax", 0xe20f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1727 SF16_INSN ("fmax", 0xe403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1728 SIMD_INSN ("frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1729 SF16_INSN ("frecps", 0xe403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1730 SIMD_INSN ("and", 0xe201c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1731 SIMD_INSN ("bic", 0xe601c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1732 SIMD_INSN ("fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1733 SF16_INSN ("fminnm", 0xec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1734 SIMD_INSN ("fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1735 SF16_INSN ("fmls", 0xec00c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1736 SIMD_INSN ("fsub", 0xea0d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1737 SF16_INSN ("fsub", 0xec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1738 SIMD_INSN ("fmin", 0xea0f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1739 SF16_INSN ("fmin", 0xec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1740 SIMD_INSN ("frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1741 SF16_INSN ("frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1742 SIMD_INSN ("orr", 0xea01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ), 1743 {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV, NULL}, 1744 SIMD_INSN ("orn", 0xee01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1745 SIMD_INSN ("uhadd", 0x2e200400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1746 SIMD_INSN ("uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1747 SIMD_INSN ("urhadd", 0x2e201400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1748 SIMD_INSN ("uhsub", 0x2e202400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1749 SIMD_INSN ("uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1750 SIMD_INSN ("cmhi", 0x2e203400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1751 SIMD_INSN ("cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1752 SIMD_INSN ("ushl", 0x2e204400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1753 SIMD_INSN ("uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1754 SIMD_INSN ("urshl", 0x2e205400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1755 SIMD_INSN ("uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1756 SIMD_INSN ("umax", 0x2e206400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1757 SIMD_INSN ("umin", 0x2e206c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1758 SIMD_INSN ("uabd", 0x2e207400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1759 SIMD_INSN ("uaba", 0x2e207c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1760 SIMD_INSN ("sub", 0x2e208400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1761 SIMD_INSN ("cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ), 1762 SIMD_INSN ("mls", 0x2e209400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1763 SIMD_INSN ("pmul", 0x2e209c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1764 SIMD_INSN ("umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1765 SIMD_INSN ("uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ), 1766 SIMD_INSN ("sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), 1767 SIMD_INSN ("fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1768 SF16_INSN ("fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1769 SIMD_INSN ("faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1770 SF16_INSN ("faddp", 0x2e401400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1771 SIMD_INSN ("fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1772 SF16_INSN ("fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1773 SIMD_INSN ("fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1774 SF16_INSN ("fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1775 SIMD_INSN ("facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1776 SF16_INSN ("facge", 0x2e402c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1777 SIMD_INSN ("fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1778 SF16_INSN ("fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1779 SIMD_INSN ("fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1780 SF16_INSN ("fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1781 SIMD_INSN ("eor", 0x2e201c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1782 SIMD_INSN ("bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1783 SIMD_INSN ("fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1784 SF16_INSN ("fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1785 SIMD_INSN ("fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1786 SF16_INSN ("fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1787 SIMD_INSN ("fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1788 SF16_INSN ("fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1789 SIMD_INSN ("facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1790 SF16_INSN ("facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1791 SIMD_INSN ("fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ), 1792 SF16_INSN ("fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ), 1793 SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1794 SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ), 1795 /* AdvSIMD three same extension. */ 1796 RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), 1797 RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ), 1798 /* AdvSIMD shift by immediate. */ 1799 SIMD_INSN ("sshr", 0xf000400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1800 SIMD_INSN ("ssra", 0xf001400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1801 SIMD_INSN ("srshr", 0xf002400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1802 SIMD_INSN ("srsra", 0xf003400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1803 SIMD_INSN ("shl", 0xf005400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), 1804 SIMD_INSN ("sqshl", 0xf007400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), 1805 SIMD_INSN ("shrn", 0xf008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1806 SIMD_INSN ("shrn2", 0x4f008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1807 SIMD_INSN ("rshrn", 0xf008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1808 SIMD_INSN ("rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1809 SIMD_INSN ("sqshrn", 0xf009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1810 SIMD_INSN ("sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1811 SIMD_INSN ("sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1812 SIMD_INSN ("sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1813 SIMD_INSN ("sshll", 0xf00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), 1814 {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV, NULL}, 1815 SIMD_INSN ("sshll2", 0x4f00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), 1816 {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV, NULL}, 1817 SIMD_INSN ("scvtf", 0xf00e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), 1818 SF16_INSN ("scvtf", 0xf10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), 1819 SIMD_INSN ("fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), 1820 SF16_INSN ("fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), 1821 SIMD_INSN ("ushr", 0x2f000400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1822 SIMD_INSN ("usra", 0x2f001400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1823 SIMD_INSN ("urshr", 0x2f002400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1824 SIMD_INSN ("ursra", 0x2f003400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1825 SIMD_INSN ("sri", 0x2f004400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0), 1826 SIMD_INSN ("sli", 0x2f005400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), 1827 SIMD_INSN ("sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), 1828 SIMD_INSN ("uqshl", 0x2f007400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0), 1829 SIMD_INSN ("sqshrun", 0x2f008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1830 SIMD_INSN ("sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1831 SIMD_INSN ("sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1832 SIMD_INSN ("sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1833 SIMD_INSN ("uqshrn", 0x2f009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1834 SIMD_INSN ("uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1835 SIMD_INSN ("uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0), 1836 SIMD_INSN ("uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0), 1837 SIMD_INSN ("ushll", 0x2f00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS), 1838 {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV, NULL}, 1839 SIMD_INSN ("ushll2", 0x6f00a400, 0xff80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS), 1840 {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV, NULL}, 1841 SIMD_INSN ("ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), 1842 SF16_INSN ("ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), 1843 SIMD_INSN ("fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0), 1844 SF16_INSN ("fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0), 1845 /* AdvSIMD TBL/TBX. */ 1846 SIMD_INSN ("tbl", 0xe000000, 0xbfe09c00, asimdtbl, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), 1847 SIMD_INSN ("tbx", 0xe001000, 0xbfe09c00, asimdtbl, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ), 1848 /* AdvSIMD scalar three different. */ 1849 SIMD_INSN ("sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), 1850 SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), 1851 SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), 1852 /* AdvSIMD scalar x indexed element. */ 1853 SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE), 1854 SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE), 1855 SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE), 1856 SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), 1857 SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), 1858 SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), 1859 SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), 1860 SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), 1861 SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), 1862 SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), 1863 SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), 1864 SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), 1865 SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE), 1866 RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), 1867 RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), 1868 /* AdvSIMD load/store multiple structures. */ 1869 SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), 1870 SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), 1871 SIMD_INSN ("st2", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), 1872 SIMD_INSN ("st3", 0xc000000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), 1873 SIMD_INSN ("ld4", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), 1874 SIMD_INSN ("ld1", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), 1875 SIMD_INSN ("ld2", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), 1876 SIMD_INSN ("ld3", 0xc400000, 0xbfff0000, asisdlse, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), 1877 /* AdvSIMD load/store multiple structures (post-indexed). */ 1878 SIMD_INSN ("st4", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), 1879 SIMD_INSN ("st1", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), 1880 SIMD_INSN ("st2", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), 1881 SIMD_INSN ("st3", 0xc800000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), 1882 SIMD_INSN ("ld4", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)), 1883 SIMD_INSN ("ld1", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), 1884 SIMD_INSN ("ld2", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)), 1885 SIMD_INSN ("ld3", 0xcc00000, 0xbfe00000, asisdlsep, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)), 1886 /* AdvSIMD load/store single structure. */ 1887 SIMD_INSN ("st1", 0xd000000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), 1888 SIMD_INSN ("st3", 0xd002000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), 1889 SIMD_INSN ("st2", 0xd200000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), 1890 SIMD_INSN ("st4", 0xd202000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), 1891 SIMD_INSN ("ld1", 0xd400000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)), 1892 SIMD_INSN ("ld3", 0xd402000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)), 1893 SIMD_INSN ("ld1r", 0xd40c000, 0xbfffe000, asisdlso, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), 1894 SIMD_INSN ("ld3r", 0xd40e000, 0xbfffe000, asisdlso, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), 1895 SIMD_INSN ("ld2", 0xd600000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)), 1896 SIMD_INSN ("ld4", 0xd602000, 0xbfff2000, asisdlso, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)), 1897 SIMD_INSN ("ld2r", 0xd60c000, 0xbfffe000, asisdlso, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), 1898 SIMD_INSN ("ld4r", 0xd60e000, 0xbfffe000, asisdlso, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), 1899 /* AdvSIMD load/store single structure (post-indexed). */ 1900 SIMD_INSN ("st1", 0xd800000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), 1901 SIMD_INSN ("st3", 0xd802000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), 1902 SIMD_INSN ("st2", 0xda00000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), 1903 SIMD_INSN ("st4", 0xda02000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), 1904 SIMD_INSN ("ld1", 0xdc00000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)), 1905 SIMD_INSN ("ld3", 0xdc02000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)), 1906 SIMD_INSN ("ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)), 1907 SIMD_INSN ("ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)), 1908 SIMD_INSN ("ld2", 0xde00000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)), 1909 SIMD_INSN ("ld4", 0xde02000, 0xbfe02000, asisdlsop, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)), 1910 SIMD_INSN ("ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)), 1911 SIMD_INSN ("ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)), 1912 /* AdvSIMD scalar two-reg misc. */ 1913 SIMD_INSN ("suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), 1914 SIMD_INSN ("sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), 1915 SIMD_INSN ("cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), 1916 SIMD_INSN ("cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), 1917 SIMD_INSN ("cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), 1918 SIMD_INSN ("abs", 0x5e20b800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), 1919 SIMD_INSN ("sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), 1920 SIMD_INSN ("fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1921 SF16_INSN ("fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1922 SIMD_INSN ("fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1923 SF16_INSN ("fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1924 SIMD_INSN ("fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1925 SF16_INSN ("fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1926 SIMD_INSN ("scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1927 SF16_INSN ("scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1928 SIMD_INSN ("fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), 1929 SF16_INSN ("fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), 1930 SIMD_INSN ("fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), 1931 SF16_INSN ("fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), 1932 SIMD_INSN ("fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), 1933 SF16_INSN ("fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), 1934 SIMD_INSN ("fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1935 SF16_INSN ("fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1936 SIMD_INSN ("fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1937 SF16_INSN ("fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1938 SIMD_INSN ("frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1939 SF16_INSN ("frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1940 SIMD_INSN ("frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1941 SF16_INSN ("frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1942 SIMD_INSN ("usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), 1943 SIMD_INSN ("sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE), 1944 SIMD_INSN ("cmge", 0x7e208800, 0xff3ffc00, asisdmisc, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), 1945 SIMD_INSN ("cmle", 0x7e209800, 0xff3ffc00, asisdmisc, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE), 1946 SIMD_INSN ("neg", 0x7e20b800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE), 1947 SIMD_INSN ("sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), 1948 SIMD_INSN ("uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE), 1949 {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC, NULL}, 1950 SIMD_INSN ("fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1951 SF16_INSN ("fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1952 SIMD_INSN ("fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1953 SF16_INSN ("fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1954 SIMD_INSN ("fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1955 SF16_INSN ("fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1956 SIMD_INSN ("ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1957 SF16_INSN ("ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1958 SIMD_INSN ("fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), 1959 SF16_INSN ("fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), 1960 SIMD_INSN ("fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE), 1961 SF16_INSN ("fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE), 1962 SIMD_INSN ("fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1963 SF16_INSN ("fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE), 1964 SIMD_INSN ("fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1965 SF16_INSN ("fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1966 SIMD_INSN ("frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE), 1967 SF16_INSN ("frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE), 1968 /* AdvSIMD scalar copy. */ 1969 SIMD_INSN ("dup", 0x5e000400, 0xffe0fc00, asisdone, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS), 1970 SIMD_INSN ("mov", 0x5e000400, 0xffe0fc00, asisdone, OP2 (Sd, En), QL_S_2SAME, F_ALIAS), 1971 /* AdvSIMD scalar pairwise. */ 1972 SIMD_INSN ("addp", 0x5e31b800, 0xff3ffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ), 1973 SIMD_INSN ("fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), 1974 SF16_INSN ("fmaxnmp", 0x5e30c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), 1975 SIMD_INSN ("faddp", 0x7e30d800, 0xffbffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), 1976 SF16_INSN ("faddp", 0x5e30d800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), 1977 SIMD_INSN ("fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), 1978 SF16_INSN ("fmaxp", 0x5e30f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), 1979 SIMD_INSN ("fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), 1980 SF16_INSN ("fminnmp", 0x5eb0c800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), 1981 SIMD_INSN ("fminp", 0x7eb0f800, 0xffbffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ), 1982 SF16_INSN ("fminp", 0x5eb0f800, 0xfffffc00, asisdpair, OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ), 1983 /* AdvSIMD scalar three same. */ 1984 SIMD_INSN ("sqadd", 0x5e200c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 1985 SIMD_INSN ("sqsub", 0x5e202c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 1986 SIMD_INSN ("sqshl", 0x5e204c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 1987 SIMD_INSN ("sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 1988 SIMD_INSN ("sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), 1989 SIMD_INSN ("fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 1990 SF16_INSN ("fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 1991 SIMD_INSN ("fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 1992 SF16_INSN ("fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 1993 SIMD_INSN ("frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 1994 SF16_INSN ("frecps", 0x5e403c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 1995 SIMD_INSN ("frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 1996 SF16_INSN ("frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 1997 SIMD_INSN ("cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 1998 SIMD_INSN ("cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 1999 SIMD_INSN ("sshl", 0x5ee04400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2000 SIMD_INSN ("srshl", 0x5ee05400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2001 SIMD_INSN ("add", 0x5ee08400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2002 SIMD_INSN ("cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2003 SIMD_INSN ("uqadd", 0x7e200c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 2004 SIMD_INSN ("uqsub", 0x7e202c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 2005 SIMD_INSN ("uqshl", 0x7e204c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 2006 SIMD_INSN ("uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE), 2007 SIMD_INSN ("sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), 2008 SIMD_INSN ("fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 2009 SF16_INSN ("fcmge", 0x7e402400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 2010 SIMD_INSN ("facge", 0x7e20ec00, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 2011 SF16_INSN ("facge", 0x7e402c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 2012 SIMD_INSN ("fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 2013 SF16_INSN ("fabd", 0x7ec01400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 2014 SIMD_INSN ("fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 2015 SF16_INSN ("fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 2016 SIMD_INSN ("facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE), 2017 SF16_INSN ("facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE), 2018 SIMD_INSN ("cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2019 SIMD_INSN ("cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2020 SIMD_INSN ("ushl", 0x7ee04400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2021 SIMD_INSN ("urshl", 0x7ee05400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2022 SIMD_INSN ("sub", 0x7ee08400, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2023 SIMD_INSN ("cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE), 2024 /* AdvSIMDs scalar three same extension. */ 2025 RDMA_INSN ("sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), 2026 RDMA_INSN ("sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE), 2027 /* AdvSIMD scalar shift by immediate. */ 2028 SIMD_INSN ("sshr", 0x5f000400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2029 SIMD_INSN ("ssra", 0x5f001400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2030 SIMD_INSN ("srshr", 0x5f002400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2031 SIMD_INSN ("srsra", 0x5f003400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2032 SIMD_INSN ("shl", 0x5f005400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), 2033 SIMD_INSN ("sqshl", 0x5f007400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), 2034 SIMD_INSN ("sqshrn", 0x5f009400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), 2035 SIMD_INSN ("sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), 2036 SIMD_INSN ("scvtf", 0x5f00e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), 2037 SF16_INSN ("scvtf", 0x5f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), 2038 SIMD_INSN ("fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), 2039 SF16_INSN ("fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), 2040 SIMD_INSN ("ushr", 0x7f000400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2041 SIMD_INSN ("usra", 0x7f001400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2042 SIMD_INSN ("urshr", 0x7f002400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2043 SIMD_INSN ("ursra", 0x7f003400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2044 SIMD_INSN ("sri", 0x7f004400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0), 2045 SIMD_INSN ("sli", 0x7f005400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0), 2046 SIMD_INSN ("sqshlu", 0x7f006400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), 2047 SIMD_INSN ("uqshl", 0x7f007400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0), 2048 SIMD_INSN ("sqshrun", 0x7f008400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), 2049 SIMD_INSN ("sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), 2050 SIMD_INSN ("uqshrn", 0x7f009400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), 2051 SIMD_INSN ("uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0), 2052 SIMD_INSN ("ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), 2053 SF16_INSN ("ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), 2054 SIMD_INSN ("fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0), 2055 SF16_INSN ("fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0), 2056 /* Bitfield. */ 2057 CORE_INSN ("sbfm", 0x13000000, 0x7f800000, bitfield, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), 2058 {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV, NULL}, 2059 {"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV, NULL}, 2060 CORE_INSN ("sxtb", 0x13001c00, 0x7fbffc00, bitfield, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), 2061 CORE_INSN ("sxth", 0x13003c00, 0x7fbffc00, bitfield, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N), 2062 CORE_INSN ("sxtw", 0x93407c00, 0xfffffc00, bitfield, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3), 2063 {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV, NULL}, 2064 CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), 2065 {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV, NULL}, 2066 {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV, NULL}, 2067 {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV, NULL}, 2068 CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N), 2069 {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV, NULL}, 2070 {"ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV, NULL}, 2071 {"uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3, NULL}, 2072 {"uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3, NULL}, 2073 {"lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV, NULL}, 2074 {"lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV, NULL}, 2075 /* Unconditional branch (immediate). */ 2076 {"b", 0x14000000, 0xfc000000, branch_imm, OP_B, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0, NULL}, 2077 {"bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0, NULL}, 2078 /* Unconditional branch (register). */ 2079 CORE_INSN ("br", 0xd61f0000, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), 2080 CORE_INSN ("blr", 0xd63f0000, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0), 2081 CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)), 2082 CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, OP0 (), {}, 0), 2083 CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, OP0 (), {}, 0), 2084 /* Compare & branch (immediate). */ 2085 CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 2086 CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF), 2087 /* Conditional branch (immediate). */ 2088 CORE_INSN ("b.c", 0x54000000, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND), 2089 /* Conditional compare (immediate). */ 2090 CORE_INSN ("ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), 2091 CORE_INSN ("ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF), 2092 /* Conditional compare (register). */ 2093 CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), 2094 CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF), 2095 /* Conditional select. */ 2096 CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF), 2097 CORE_INSN ("csinc", 0x1a800400, 0x7fe00c00, condsel, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), 2098 {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV, NULL}, 2099 {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV, NULL}, 2100 CORE_INSN ("csinv", 0x5a800000, 0x7fe00c00, condsel, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), 2101 {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV, NULL}, 2102 {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV, NULL}, 2103 CORE_INSN ("csneg", 0x5a800400, 0x7fe00c00, condsel, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF), 2104 {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV, NULL}, 2105 /* Crypto AES. */ 2106 CRYP_INSN ("aese", 0x4e284800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), 2107 CRYP_INSN ("aesd", 0x4e285800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), 2108 CRYP_INSN ("aesmc", 0x4e286800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), 2109 CRYP_INSN ("aesimc", 0x4e287800, 0xfffffc00, cryptoaes, OP2 (Vd, Vn), QL_V2SAME16B, 0), 2110 /* Crypto two-reg SHA. */ 2111 CRYP_INSN ("sha1h", 0x5e280800, 0xfffffc00, cryptosha2, OP2 (Fd, Fn), QL_2SAMES, 0), 2112 CRYP_INSN ("sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), 2113 CRYP_INSN ("sha256su0",0x5e282800, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME4S, 0), 2114 /* Crypto three-reg SHA. */ 2115 CRYP_INSN ("sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), 2116 CRYP_INSN ("sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), 2117 CRYP_INSN ("sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0), 2118 CRYP_INSN ("sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), 2119 CRYP_INSN ("sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), 2120 CRYP_INSN ("sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0), 2121 CRYP_INSN ("sha256su1",0x5e006000, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0), 2122 /* Data-processing (1 source). */ 2123 CORE_INSN ("rbit", 0x5ac00000, 0x7ffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAME, F_SF), 2124 CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAME, F_SF), 2125 CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAMEW, 0), 2126 CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1), 2127 {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS, NULL}, 2128 CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAME, F_SF), 2129 CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAME, F_SF), 2130 CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, OP2 (Rd, Rn), QL_I2SAMEX, 0), 2131 /* Data-processing (2 source). */ 2132 CORE_INSN ("udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), 2133 CORE_INSN ("sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF), 2134 CORE_INSN ("lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), 2135 CORE_INSN ("lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), 2136 CORE_INSN ("lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), 2137 CORE_INSN ("lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), 2138 CORE_INSN ("asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), 2139 CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), 2140 CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS), 2141 CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS), 2142 /* CRC instructions. */ 2143 _CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), 2144 _CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), 2145 _CRC_INSN ("crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), 2146 _CRC_INSN ("crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), 2147 _CRC_INSN ("crc32cb",0x1ac05000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), 2148 _CRC_INSN ("crc32ch",0x1ac05400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), 2149 _CRC_INSN ("crc32cw",0x1ac05800, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0), 2150 _CRC_INSN ("crc32cx",0x9ac05c00, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3WWX, 0), 2151 /* Data-processing (3 source). */ 2152 CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), 2153 CORE_INSN ("mul", 0x1b007c00, 0x7fe0fc00, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), 2154 CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF), 2155 CORE_INSN ("mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF), 2156 CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), 2157 CORE_INSN ("smull", 0x9b207c00, 0xffe0fc00, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), 2158 CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), 2159 CORE_INSN ("smnegl",0x9b20fc00, 0xffe0fc00, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), 2160 CORE_INSN ("smulh", 0x9b407c00, 0xffe08000, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), 2161 CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), 2162 CORE_INSN ("umull", 0x9ba07c00, 0xffe0fc00, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), 2163 CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS), 2164 CORE_INSN ("umnegl",0x9ba0fc00, 0xffe0fc00, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS), 2165 CORE_INSN ("umulh", 0x9bc07c00, 0xffe08000, dp_3src, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0), 2166 /* Excep'n generation. */ 2167 CORE_INSN ("svc", 0xd4000001, 0xffe0001f, exception, OP1 (EXCEPTION), {}, 0), 2168 CORE_INSN ("hvc", 0xd4000002, 0xffe0001f, exception, OP1 (EXCEPTION), {}, 0), 2169 CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, OP1 (EXCEPTION), {}, 0), 2170 CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, OP1 (EXCEPTION), {}, 0), 2171 CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, OP1 (EXCEPTION), {}, 0), 2172 CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), 2173 CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), 2174 CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), 2175 /* Extract. */ 2176 CORE_INSN ("extr", 0x13800000, 0x7fa00000, extract, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N), 2177 {"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV, NULL}, 2178 /* Floating-point<->fixed-point conversions. */ 2179 __FP_INSN ("scvtf", 0x1e020000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), 2180 FF16_INSN ("scvtf", 0x1ec20000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), 2181 __FP_INSN ("ucvtf", 0x1e030000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF), 2182 FF16_INSN ("ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF), 2183 __FP_INSN ("fcvtzs",0x1e180000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), 2184 FF16_INSN ("fcvtzs",0x1ed80000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), 2185 __FP_INSN ("fcvtzu",0x1e190000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF), 2186 FF16_INSN ("fcvtzu",0x1ed90000, 0x7f3f0000, float2fix, OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF), 2187 /* Floating-point<->integer conversions. */ 2188 __FP_INSN ("fcvtns",0x1e200000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2189 FF16_INSN ("fcvtns",0x1ee00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2190 __FP_INSN ("fcvtnu",0x1e210000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2191 FF16_INSN ("fcvtnu",0x1ee10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2192 __FP_INSN ("scvtf", 0x1e220000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), 2193 FF16_INSN ("scvtf", 0x1ee20000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), 2194 __FP_INSN ("ucvtf", 0x1e230000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), 2195 FF16_INSN ("ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), 2196 __FP_INSN ("fcvtas",0x1e240000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2197 FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2198 __FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2199 FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2200 __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2201 FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2202 __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF), 2203 FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF), 2204 __FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2205 FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2206 __FP_INSN ("fcvtpu",0x1e290000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2207 FF16_INSN ("fcvtpu",0x1ee90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2208 __FP_INSN ("fcvtms",0x1e300000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2209 FF16_INSN ("fcvtms",0x1ef00000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2210 __FP_INSN ("fcvtmu",0x1e310000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2211 FF16_INSN ("fcvtmu",0x1ef10000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2212 __FP_INSN ("fcvtzs",0x1e380000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2213 FF16_INSN ("fcvtzs",0x1ef80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2214 __FP_INSN ("fcvtzu",0x1e390000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF), 2215 FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), 2216 __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, OP2 (Rd, VnD1), QL_XVD1, 0), 2217 __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, OP2 (VdD1, Rn), QL_VD1X, 0), 2218 /* Floating-point conditional compare. */ 2219 __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), 2220 FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), 2221 __FP_INSN ("fccmpe",0x1e200410, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), 2222 FF16_INSN ("fccmpe",0x1ee00410, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), 2223 /* Floating-point compare. */ 2224 __FP_INSN ("fcmp", 0x1e202000, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), 2225 FF16_INSN ("fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), 2226 __FP_INSN ("fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2, F_FPTYPE), 2227 FF16_INSN ("fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE), 2228 __FP_INSN ("fcmp", 0x1e202008, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), 2229 FF16_INSN ("fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), 2230 __FP_INSN ("fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE), 2231 FF16_INSN ("fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE), 2232 /* Floating-point data-processing (1 source). */ 2233 __FP_INSN ("fmov", 0x1e204000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2234 FF16_INSN ("fmov", 0x1ee04000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2235 __FP_INSN ("fabs", 0x1e20c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2236 FF16_INSN ("fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2237 __FP_INSN ("fneg", 0x1e214000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2238 FF16_INSN ("fneg", 0x1ee14000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2239 __FP_INSN ("fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2240 FF16_INSN ("fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2241 {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC, NULL }, 2242 __FP_INSN ("frintn",0x1e244000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2243 FF16_INSN ("frintn",0x1ee44000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2244 __FP_INSN ("frintp",0x1e24c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2245 FF16_INSN ("frintp",0x1ee4c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2246 __FP_INSN ("frintm",0x1e254000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2247 FF16_INSN ("frintm",0x1ee54000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2248 __FP_INSN ("frintz",0x1e25c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2249 FF16_INSN ("frintz",0x1ee5c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2250 __FP_INSN ("frinta",0x1e264000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2251 FF16_INSN ("frinta",0x1ee64000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2252 __FP_INSN ("frintx",0x1e274000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2253 FF16_INSN ("frintx",0x1ee74000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2254 __FP_INSN ("frinti",0x1e27c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE), 2255 FF16_INSN ("frinti",0x1ee7c000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE), 2256 /* Floating-point data-processing (2 source). */ 2257 __FP_INSN ("fmul", 0x1e200800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2258 FF16_INSN ("fmul", 0x1ee00800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2259 __FP_INSN ("fdiv", 0x1e201800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2260 FF16_INSN ("fdiv", 0x1ee01800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2261 __FP_INSN ("fadd", 0x1e202800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2262 FF16_INSN ("fadd", 0x1ee02800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2263 __FP_INSN ("fsub", 0x1e203800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2264 FF16_INSN ("fsub", 0x1ee03800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2265 __FP_INSN ("fmax", 0x1e204800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2266 FF16_INSN ("fmax", 0x1ee04800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2267 __FP_INSN ("fmin", 0x1e205800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2268 FF16_INSN ("fmin", 0x1ee05800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2269 __FP_INSN ("fmaxnm",0x1e206800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2270 FF16_INSN ("fmaxnm",0x1ee06800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2271 __FP_INSN ("fminnm",0x1e207800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2272 FF16_INSN ("fminnm",0x1ee07800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2273 __FP_INSN ("fnmul", 0x1e208800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE), 2274 FF16_INSN ("fnmul", 0x1ee08800, 0xff20fc00, floatdp2, OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE), 2275 /* Floating-point data-processing (3 source). */ 2276 __FP_INSN ("fmadd", 0x1f000000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), 2277 FF16_INSN ("fmadd", 0x1fc00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), 2278 __FP_INSN ("fmsub", 0x1f008000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), 2279 FF16_INSN ("fmsub", 0x1fc08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), 2280 __FP_INSN ("fnmadd",0x1f200000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), 2281 FF16_INSN ("fnmadd",0x1fe00000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), 2282 __FP_INSN ("fnmsub",0x1f208000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE), 2283 FF16_INSN ("fnmsub",0x1fe08000, 0xff208000, floatdp3, OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE), 2284 /* Floating-point immediate. */ 2285 __FP_INSN ("fmov", 0x1e201000, 0xff201fe0, floatimm, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE), 2286 FF16_INSN ("fmov", 0x1ee01000, 0xff201fe0, floatimm, OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE), 2287 /* Floating-point conditional select. */ 2288 __FP_INSN ("fcsel", 0x1e200c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE), 2289 FF16_INSN ("fcsel", 0x1ee00c00, 0xff200c00, floatsel, OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE), 2290 /* Load/store register (immediate indexed). */ 2291 CORE_INSN ("strb", 0x38000400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 2292 CORE_INSN ("ldrb", 0x38400400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 2293 CORE_INSN ("ldrsb", 0x38800400, 0xffa00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), 2294 CORE_INSN ("str", 0x3c000400, 0x3f600400, ldst_imm9, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), 2295 CORE_INSN ("ldr", 0x3c400400, 0x3f600400, ldst_imm9, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0), 2296 CORE_INSN ("strh", 0x78000400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 2297 CORE_INSN ("ldrh", 0x78400400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 2298 CORE_INSN ("ldrsh", 0x78800400, 0xffa00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), 2299 CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 2300 CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 2301 CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), 2302 /* Load/store register (unsigned immediate). */ 2303 {"strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0, NULL}, 2304 {"ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0, NULL}, 2305 {"ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE, NULL}, 2306 {"str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0, NULL}, 2307 {"ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0, NULL}, 2308 {"strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0, NULL}, 2309 {"ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0, NULL}, 2310 {"ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE, NULL}, 2311 {"str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q, NULL}, 2312 {"ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q, NULL}, 2313 {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0, NULL}, 2314 {"prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, CORE, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0, NULL}, 2315 /* Load/store register (register offset). */ 2316 CORE_INSN ("strb", 0x38200800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), 2317 CORE_INSN ("ldrb", 0x38600800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0), 2318 CORE_INSN ("ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE), 2319 CORE_INSN ("str", 0x3c200800, 0x3f600c00, ldst_regoff, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), 2320 CORE_INSN ("ldr", 0x3c600800, 0x3f600c00, ldst_regoff, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0), 2321 CORE_INSN ("strh", 0x78200800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), 2322 CORE_INSN ("ldrh", 0x78600800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0), 2323 CORE_INSN ("ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE), 2324 CORE_INSN ("str", 0xb8200800, 0xbfe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), 2325 CORE_INSN ("ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q), 2326 CORE_INSN ("ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0), 2327 CORE_INSN ("prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0), 2328 /* Load/store register (unprivileged). */ 2329 CORE_INSN ("sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 2330 CORE_INSN ("ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0), 2331 CORE_INSN ("ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE), 2332 CORE_INSN ("sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 2333 CORE_INSN ("ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0), 2334 CORE_INSN ("ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE), 2335 CORE_INSN ("sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 2336 CORE_INSN ("ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q), 2337 CORE_INSN ("ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0), 2338 /* Load/store register (unscaled immediate). */ 2339 {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0, NULL}, 2340 {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0, NULL}, 2341 {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE, NULL}, 2342 {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0, NULL}, 2343 {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0, NULL}, 2344 {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0, NULL}, 2345 {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0, NULL}, 2346 {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE, NULL}, 2347 {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q, NULL}, 2348 {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q, NULL}, 2349 {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0, NULL}, 2350 {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, CORE, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0, NULL}, 2351 /* Load/store exclusive. */ 2352 CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2353 CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2354 CORE_INSN ("ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2355 CORE_INSN ("ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2356 CORE_INSN ("stlrb", 0x89ffc00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2357 CORE_INSN ("ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2358 CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2359 CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2360 CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2361 CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2362 CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2363 CORE_INSN ("ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2364 CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), 2365 CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), 2366 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), 2367 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), 2368 CORE_INSN ("ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), 2369 CORE_INSN ("ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), 2370 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), 2371 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), 2372 CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), 2373 CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), 2374 /* Limited Ordering Regions load/store instructions. */ 2375 _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), 2376 _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2377 _LOR_INSN ("ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2378 _LOR_INSN ("stllr", 0x889f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), 2379 _LOR_INSN ("stllrb", 0x089f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2380 _LOR_INSN ("stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), 2381 /* Load/store no-allocate pair (offset). */ 2382 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), 2383 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), 2384 CORE_INSN ("stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), 2385 CORE_INSN ("ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), 2386 /* Load/store register pair (offset). */ 2387 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), 2388 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), 2389 CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), 2390 CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), 2391 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)}, 2392 /* Load/store register pair (indexed). */ 2393 CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), 2394 CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF), 2395 CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), 2396 CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0), 2397 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)}, 2398 /* Load register (literal). */ 2399 {"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q, NULL}, 2400 {"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0, NULL}, 2401 {"ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0, NULL}, 2402 {"prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, CORE, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0, NULL}, 2403 /* Logical (immediate). */ 2404 CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), 2405 {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF, NULL}, 2406 CORE_INSN ("orr", 0x32000000, 0x7f800000, log_imm, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), 2407 {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV, NULL}, 2408 CORE_INSN ("eor", 0x52000000, 0x7f800000, log_imm, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF), 2409 CORE_INSN ("ands", 0x72000000, 0x7f800000, log_imm, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), 2410 CORE_INSN ("tst", 0x7200001f, 0x7f80001f, log_imm, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF), 2411 /* Logical (shifted register). */ 2412 CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), 2413 CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), 2414 CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), 2415 CORE_INSN ("mov", 0x2a0003e0, 0x7f2003e0, log_shift, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), 2416 {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO, NULL}, 2417 CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), 2418 CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), 2419 CORE_INSN ("eor", 0x4a000000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), 2420 CORE_INSN ("eon", 0x4a200000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), 2421 CORE_INSN ("ands", 0x6a000000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF), 2422 CORE_INSN ("tst", 0x6a00001f, 0x7f20001f, log_shift, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF), 2423 CORE_INSN ("bics", 0x6a200000, 0x7f200000, log_shift, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF), 2424 /* LSE extension (atomic). */ 2425 _LSE_INSN ("casb", 0x8a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2426 _LSE_INSN ("cash", 0x48a07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2427 _LSE_INSN ("cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2428 _LSE_INSN ("casab", 0x8e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2429 _LSE_INSN ("caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2430 _LSE_INSN ("casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2431 _LSE_INSN ("casah", 0x48e07c00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2432 _LSE_INSN ("caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2433 _LSE_INSN ("casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2434 _LSE_INSN ("casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2435 _LSE_INSN ("casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2436 _LSE_INSN ("casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2437 _LSE_INSN ("casp", 0x8207c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), 2438 _LSE_INSN ("caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), 2439 _LSE_INSN ("caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), 2440 _LSE_INSN ("caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ), 2441 _LSE_INSN ("swpb", 0x38208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2442 _LSE_INSN ("swph", 0x78208000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2443 _LSE_INSN ("swp", 0xb8208000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2444 _LSE_INSN ("swpab", 0x38a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2445 _LSE_INSN ("swplb", 0x38608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2446 _LSE_INSN ("swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2447 _LSE_INSN ("swpah", 0x78a08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2448 _LSE_INSN ("swplh", 0x78608000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2449 _LSE_INSN ("swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2450 _LSE_INSN ("swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2451 _LSE_INSN ("swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2452 _LSE_INSN ("swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2453 _LSE_INSN ("ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2454 _LSE_INSN ("ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2455 _LSE_INSN ("ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2456 _LSE_INSN ("ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2457 _LSE_INSN ("ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2458 _LSE_INSN ("ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2459 _LSE_INSN ("ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2460 _LSE_INSN ("ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2461 _LSE_INSN ("ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2462 _LSE_INSN ("ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2463 _LSE_INSN ("ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2464 _LSE_INSN ("ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2465 _LSE_INSN ("ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2466 _LSE_INSN ("ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2467 _LSE_INSN ("ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2468 _LSE_INSN ("ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2469 _LSE_INSN ("ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2470 _LSE_INSN ("ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2471 _LSE_INSN ("ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2472 _LSE_INSN ("ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2473 _LSE_INSN ("ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2474 _LSE_INSN ("ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2475 _LSE_INSN ("ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2476 _LSE_INSN ("ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2477 _LSE_INSN ("ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2478 _LSE_INSN ("ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2479 _LSE_INSN ("ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2480 _LSE_INSN ("ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2481 _LSE_INSN ("ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2482 _LSE_INSN ("ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2483 _LSE_INSN ("ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2484 _LSE_INSN ("ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2485 _LSE_INSN ("ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2486 _LSE_INSN ("ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2487 _LSE_INSN ("ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2488 _LSE_INSN ("ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2489 _LSE_INSN ("ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2490 _LSE_INSN ("ldseth", 0x78203000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2491 _LSE_INSN ("ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2492 _LSE_INSN ("ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2493 _LSE_INSN ("ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2494 _LSE_INSN ("ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2495 _LSE_INSN ("ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2496 _LSE_INSN ("ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2497 _LSE_INSN ("ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2498 _LSE_INSN ("ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2499 _LSE_INSN ("ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2500 _LSE_INSN ("ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2501 _LSE_INSN ("ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2502 _LSE_INSN ("ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2503 _LSE_INSN ("ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2504 _LSE_INSN ("ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2505 _LSE_INSN ("ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2506 _LSE_INSN ("ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2507 _LSE_INSN ("ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2508 _LSE_INSN ("ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2509 _LSE_INSN ("ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2510 _LSE_INSN ("ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2511 _LSE_INSN ("ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2512 _LSE_INSN ("ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2513 _LSE_INSN ("ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2514 _LSE_INSN ("ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2515 _LSE_INSN ("ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2516 _LSE_INSN ("ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2517 _LSE_INSN ("ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2518 _LSE_INSN ("ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2519 _LSE_INSN ("ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2520 _LSE_INSN ("ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2521 _LSE_INSN ("ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2522 _LSE_INSN ("ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2523 _LSE_INSN ("ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2524 _LSE_INSN ("ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2525 _LSE_INSN ("ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2526 _LSE_INSN ("ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2527 _LSE_INSN ("ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2528 _LSE_INSN ("ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2529 _LSE_INSN ("ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2530 _LSE_INSN ("ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2531 _LSE_INSN ("ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2532 _LSE_INSN ("ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2533 _LSE_INSN ("ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2534 _LSE_INSN ("ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2535 _LSE_INSN ("ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2536 _LSE_INSN ("ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2537 _LSE_INSN ("lduminb", 0x38207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2538 _LSE_INSN ("lduminh", 0x78207000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2539 _LSE_INSN ("ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2540 _LSE_INSN ("lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2541 _LSE_INSN ("lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2542 _LSE_INSN ("lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2543 _LSE_INSN ("lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2544 _LSE_INSN ("lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS), 2545 _LSE_INSN ("lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0), 2546 _LSE_INSN ("ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2547 _LSE_INSN ("lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS), 2548 _LSE_INSN ("lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ), 2549 _LSE_INSN ("staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2550 _LSE_INSN ("staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2551 _LSE_INSN ("stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2552 _LSE_INSN ("staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2553 _LSE_INSN ("staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2554 _LSE_INSN ("staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2555 _LSE_INSN ("stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2556 _LSE_INSN ("stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2557 _LSE_INSN ("stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2558 _LSE_INSN ("stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2559 _LSE_INSN ("stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2560 _LSE_INSN ("stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2561 _LSE_INSN ("steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2562 _LSE_INSN ("steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2563 _LSE_INSN ("steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2564 _LSE_INSN ("steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2565 _LSE_INSN ("steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2566 _LSE_INSN ("steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2567 _LSE_INSN ("stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2568 _LSE_INSN ("stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2569 _LSE_INSN ("stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2570 _LSE_INSN ("stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2571 _LSE_INSN ("stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2572 _LSE_INSN ("stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2573 _LSE_INSN ("stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2574 _LSE_INSN ("stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2575 _LSE_INSN ("stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2576 _LSE_INSN ("stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2577 _LSE_INSN ("stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2578 _LSE_INSN ("stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2579 _LSE_INSN ("stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2580 _LSE_INSN ("stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2581 _LSE_INSN ("stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2582 _LSE_INSN ("stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2583 _LSE_INSN ("stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2584 _LSE_INSN ("stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2585 _LSE_INSN ("stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2586 _LSE_INSN ("stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2587 _LSE_INSN ("stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2588 _LSE_INSN ("stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2589 _LSE_INSN ("stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2590 _LSE_INSN ("stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2591 _LSE_INSN ("stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2592 _LSE_INSN ("stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2593 _LSE_INSN ("stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2594 _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2595 _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS), 2596 _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS), 2597 /* Move wide (immediate). */ 2598 {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS, NULL}, 2599 {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV, NULL}, 2600 {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS, NULL}, 2601 {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV, NULL}, 2602 {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF, NULL}, 2603 /* PC-rel. addressing. */ 2604 CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0), 2605 CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0), 2606 /* System. */ 2607 CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, OP2 (PSTATEFIELD, UIMM4), {}, 0), 2608 CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, OP1 (UIMM7), {}, F_HAS_ALIAS), 2609 CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), 2610 CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), 2611 CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), 2612 CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), 2613 CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), 2614 CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS), 2615 {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, NULL}, 2616 {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, NULL}, 2617 CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), 2618 CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, OP1 (BARRIER), {}, 0), 2619 CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, OP1 (BARRIER), {}, 0), 2620 CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)), 2621 CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), 2622 CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), 2623 CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), 2624 CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), 2625 CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), 2626 CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, OP2 (SYSREG, Rt), QL_SRC_X, 0), 2627 CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0), 2628 CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, OP2 (Rt, SYSREG), QL_DST_X, 0), 2629 /* Test & branch (immediate). */ 2630 CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), 2631 CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0), 2632 /* The old UAL conditional branch mnemonics (to aid portability). */ 2633 CORE_INSN ("beq", 0x54000000, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2634 CORE_INSN ("bne", 0x54000001, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2635 CORE_INSN ("bcs", 0x54000002, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2636 CORE_INSN ("bhs", 0x54000002, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2637 CORE_INSN ("bcc", 0x54000003, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2638 CORE_INSN ("blo", 0x54000003, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2639 CORE_INSN ("bmi", 0x54000004, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2640 CORE_INSN ("bpl", 0x54000005, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2641 CORE_INSN ("bvs", 0x54000006, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2642 CORE_INSN ("bvc", 0x54000007, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2643 CORE_INSN ("bhi", 0x54000008, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2644 CORE_INSN ("bls", 0x54000009, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2645 CORE_INSN ("bge", 0x5400000a, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2646 CORE_INSN ("blt", 0x5400000b, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2647 CORE_INSN ("bgt", 0x5400000c, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2648 CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO), 2649 2650 {0, 0, 0, 0, 0, 0, {}, {}, 0, NULL}, 2651 }; 2652 2653 #ifdef AARCH64_OPERANDS 2654 #undef AARCH64_OPERANDS 2655 #endif 2656 2657 /* Macro-based operand decription; this will be fed into aarch64-gen for it 2658 to generate the structure aarch64_operands and the function 2659 aarch64_insert_operand and aarch64_extract_operand. 2660 2661 These inserters and extracters in the description execute the conversion 2662 between the aarch64_opnd_info and value in the operand-related instruction 2663 field(s). */ 2664 2665 /* Y expects arguments (left to right) to be operand class, inserter/extractor 2666 name suffix, operand name, flags, related bitfield(s) and description. 2667 X only differs from Y by having the operand inserter and extractor names 2668 listed separately. */ 2669 2670 #define AARCH64_OPERANDS \ 2671 Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \ 2672 Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ 2673 Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ 2674 Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ 2675 Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ 2676 Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ 2677 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \ 2678 X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \ 2679 "an integer register") \ 2680 Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \ 2681 "an integer or stack pointer register") \ 2682 Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ 2683 "an integer or stack pointer register") \ 2684 X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ 2685 "the second reg of a pair") \ 2686 Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \ 2687 "an integer register with optional extension") \ 2688 Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \ 2689 "an integer register with optional shift") \ 2690 Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \ 2691 Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \ 2692 Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \ 2693 Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \ 2694 Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \ 2695 Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \ 2696 Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \ 2697 Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \ 2698 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \ 2699 Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \ 2700 Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \ 2701 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \ 2702 Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \ 2703 "the top half of a 128-bit FP/SIMD register") \ 2704 Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \ 2705 "the top half of a 128-bit FP/SIMD register") \ 2706 Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \ 2707 "a SIMD vector element") \ 2708 Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \ 2709 "a SIMD vector element") \ 2710 Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ 2711 "a SIMD vector element") \ 2712 Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ 2713 "a SIMD vector register list") \ 2714 Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ 2715 "a SIMD vector register list") \ 2716 Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \ 2717 "a SIMD vector register list") \ 2718 Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \ 2719 "a SIMD vector element list") \ 2720 Y(CP_REG, regno, "Cn", 0, F(FLD_CRn), \ 2721 "a 4-bit opcode field named for historical reasons C0 - C15") \ 2722 Y(CP_REG, regno, "Cm", 0, F(FLD_CRm), \ 2723 "a 4-bit opcode field named for historical reasons C0 - C15") \ 2724 Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \ 2725 "an immediate as the index of the least significant byte") \ 2726 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ 2727 "a left shift amount for an AdvSIMD register") \ 2728 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \ 2729 "a right shift amount for an AdvSIMD register") \ 2730 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \ 2731 "an immediate") \ 2732 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \ 2733 "an 8-bit unsigned immediate with optional shift") \ 2734 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \ 2735 "an 8-bit floating-point constant") \ 2736 X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \ 2737 "an immediate shift amount of 8, 16 or 32") \ 2738 X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \ 2739 X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \ 2740 Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8), \ 2741 "an 8-bit floating-point constant") \ 2742 Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ 2743 "the right rotate amount") \ 2744 Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \ 2745 "the leftmost bit number to be moved from the source") \ 2746 Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \ 2747 "the width of the bit-field") \ 2748 Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \ 2749 Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ 2750 "a 3-bit unsigned immediate") \ 2751 Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ 2752 "a 3-bit unsigned immediate") \ 2753 Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ 2754 "a 4-bit unsigned immediate") \ 2755 Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ 2756 "a 7-bit unsigned immediate") \ 2757 Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ 2758 "the bit number to be tested") \ 2759 Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ 2760 "a 16-bit unsigned immediate") \ 2761 Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ 2762 "a 5-bit unsigned immediate") \ 2763 Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ 2764 "a flag bit specifier giving an alternative value for each flag") \ 2765 Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ 2766 "Logical immediate") \ 2767 Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ 2768 "a 12-bit unsigned immediate with optional left shift of 12 bits")\ 2769 Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \ 2770 "a 16-bit immediate with optional left shift") \ 2771 Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ 2772 "the number of bits after the binary point in the fixed-point value")\ 2773 X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \ 2774 Y(COND, cond, "COND", 0, F(), "a condition") \ 2775 Y(COND, cond, "COND1", 0, F(), \ 2776 "one of the standard conditions, excluding AL and NV.") \ 2777 X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\ 2778 "21-bit PC-relative address of a 4KB page") \ 2779 Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ 2780 F(FLD_imm14), "14-bit PC-relative address") \ 2781 Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ 2782 F(FLD_imm19), "19-bit PC-relative address") \ 2783 Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \ 2784 "21-bit PC-relative address") \ 2785 Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ 2786 F(FLD_imm26), "26-bit PC-relative address") \ 2787 Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ 2788 "an address with base register (no offset)") \ 2789 Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ 2790 "an address with register offset") \ 2791 Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ 2792 "an address with 7-bit signed immediate offset") \ 2793 Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ 2794 "an address with 9-bit signed immediate offset") \ 2795 Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \ 2796 "an address with 9-bit negative or unaligned immediate offset") \ 2797 Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \ 2798 "an address with scaled, unsigned immediate offset") \ 2799 Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \ 2800 "an address with base register (no offset)") \ 2801 Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \ 2802 "a post-indexed address with immediate or register increment") \ 2803 Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \ 2804 Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \ 2805 "a PSTATE field name") \ 2806 Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \ 2807 "an address translation operation specifier") \ 2808 Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \ 2809 "a data cache maintenance operation specifier") \ 2810 Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \ 2811 "an instruction cache maintenance operation specifier") \ 2812 Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ 2813 "a TBL invalidation operation specifier") \ 2814 Y(SYSTEM, barrier, "BARRIER", 0, F(), \ 2815 "a barrier option name") \ 2816 Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ 2817 "the ISB option name SY or an optional 4-bit unsigned immediate") \ 2818 Y(SYSTEM, prfop, "PRFOP", 0, F(), \ 2819 "a prefetch operation specifier") \ 2820 Y (SYSTEM, hint, "BARRIER_PSB", 0, F (), \ 2821 "the PSB option name CSYNC") 2822
