| /external/v8/src/crankshaft/ |
| hydrogen-dehoist.cc | 16 if (!index->IsAdd() && !index->IsSub()) return;
34 int32_t sign = binary_operation->IsSub() ? -1 : 1;
|
| hydrogen-bce.cc | 48 } else if (check->index()->IsSub()) {
230 if (index_raw->IsAdd() || index_raw->IsSub()) {
|
| hydrogen-range-analysis.cc | 265 } else if (value->IsAdd() || value->IsSub()) {
|
| /art/compiler/optimizing/ |
| instruction_simplifier_shared.h | 46 instr->IsOr() || instr->IsSub() || instr->IsXor();
|
| instruction_simplifier_shared.cc | 29 DCHECK(input_binop->IsAdd() || input_binop->IsSub());
53 DCHECK(input_binop->IsSub());
112 if (use->IsAdd() || use->IsSub()) {
177 if ((right->IsAdd() || right->IsSub()) &&
181 if ((left->IsAdd() || left->IsSub()) &&
|
| instruction_simplifier.cc | 173 DCHECK(binop->IsAdd() || binop->IsSub());
388 shift_amount->IsSub()) {
454 } else if (ushr->GetRight()->IsSub() || shl->GetRight()->IsSub()) {
540 DCHECK(ushr->GetRight()->IsSub() || shl->GetRight()->IsSub());
544 if ((shl_shift->IsSub() && IsSubRegBitsMinusOther(shl_shift->AsSub(), reg_bits, ushr_shift)) ||
545 (ushr_shift->IsSub() && IsSubRegBitsMinusOther(ushr_shift->AsSub(), reg_bits, shl_shift))) {
[all...] |
| load_store_analysis.cc | 34 return instruction->IsAdd() || instruction->IsSub();
|
| induction_var_range_test.cc | [all...] |
| common_arm64.h | 275 instr->IsSub())
352 return instruction->IsAdd() || instruction->IsSub();
|
| instruction_simplifier_arm.cc | 127 if (!use->IsAdd() && (!use->IsSub() || use->GetType() != DataType::Type::kInt64)) {
|
| scheduler.cc | 687 instruction->IsSub() ||
|
| loop_optimization.cc | 343 } else if (reduction->IsSub()) {
[all...] |
| induction_var_analysis.cc | 362 } else if (instruction->IsSub()) {
446 } else if (instruction->IsSub()) {
[all...] |
| code_generator_mips64.cc | [all...] |
| bounds_check_elimination.cc | 73 while (instruction->IsAdd() || instruction->IsSub()) {
[all...] |
| code_generator_mips.cc | [all...] |
| induction_var_range.cc | 676 } else if (instruction->IsSub()) {
[all...] |
| /external/tensorflow/tensorflow/core/grappler/ |
| op_types.h | 122 bool IsSub(const NodeDef& node);
|
| op_types.cc | 306 bool IsSub(const NodeDef& node) { return node.op() == "Sub"; }
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 594 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
595 assert(IsSub && "Expecting group subregister");
596 if (!IsSub)
[all...] |
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 583 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
586 // assert(IsSub && "Expecting group subregister");
587 if (!IsSub)
[all...] |
| /external/v8/src/crankshaft/arm64/ |
| lithium-arm64.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 253 bool isSub = NumBytes < 0;
254 uint64_t Offset = isSub ? -NumBytes : NumBytes;
265 if (isSub && !isEAXLiveIn(MBB))
274 Opc = isSub
289 unsigned Reg = isSub
293 unsigned Opc = isSub
297 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
298 if (isSub)
308 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
[all...] |
| /external/tensorflow/tensorflow/core/grappler/optimizers/ |
| constant_folding.cc | [all...] |
| /external/v8/src/crankshaft/arm/ |
| lithium-arm.cc | [all...] |
