| /external/llvm/lib/Target/AMDGPU/ |
| SIInsertWaits.cpp | 440 unsigned Imm = I->getOperand(0).getImm();
443 Counts.Named.VM = Imm & 0xF;
444 Counts.Named.EXP = (Imm >> 4) & 0x7;
445 Counts.Named.LGKM = (Imm >> 8) & 0xF;
|
| R600InstrInfo.h | 113 /// If register is ALU_LITERAL, second member is IMM.
280 uint64_t Imm) const;
297 void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
|
| R600ISelLowering.h | 95 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.h | 110 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 18 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
22 if (Bits == 0 || Imm.getActiveBits() >= 64)
25 int64_t SImmVal = Imm.getSExtValue();
26 uint64_t ZImmVal = Imm.getZExtValue();
54 const APInt &Imm, Type *Ty) {
55 if (Imm.isNonNegative() && Imm.getLimitedValue() < 256)
61 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
72 return getIntImmCost(Imm, Ty);
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 104 // Imm is an immediate operand, and Sym is an optional TLS symbol
107 const MCExpr *Imm;
115 const MCExpr *Imm;
161 Op->Imm = Expr;
178 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
181 Op->ImmTLS.Imm = Imm;
218 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
222 return Imm;
304 addExpr(Inst, ImmTLS.Imm);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 236 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
277 // r4 = add sp, imm
278 // r4 = add r4, imm
343 unsigned DestReg, int Imm,
347 bool isSub = Imm < 0;
348 if (isSub) Imm = -Imm;
351 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
352 Imm -= ThisVal
[all...] |
| ARMISelLowering.h | 281 virtual bool isLegalICmpImmediate(int64_t Imm) const;
287 virtual bool isLegalAddImmediate(int64_t Imm) const;
359 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| XmmArith.cpp | 174 #define TestPArithXmmImm(Dst, Value0, Imm, Inst, Op, Type, Size) \
177 "(" #Dst ", " #Value0 ", " #Imm ", " #Inst ", " #Op ", " #Type \
183 __ Inst(IceType_i##Size, XmmRegister::Encoded_Reg_##Dst, Immediate(Imm)); \
189 ASSERT_EQ(packedAs<Type##Size##_t>(V0) Op Imm, test.Dst<Dqword>()) \
[all...] |
| GPRArith.cpp | 358 #define TestImplRegImm(Dst, Value0, Imm, Size) \
362 "(" #Dst ", " #Value0 ", " #Imm ", " #Size ")"; \
369 Immediate((Imm)&Mask##Size)); \
381 ASSERT_EQ(((Value0)&Mask##Size) & ((Imm)&Mask##Size) ? ValueIfTrue \
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 604 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
622 MI.addOperand(MCOperand::createImm(Imm));
633 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
653 MI.addOperand(MCOperand::createImm(Imm));
674 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
692 MI.addOperand(MCOperand::createImm(Imm));
703 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
723 MI.addOperand(MCOperand::createImm(Imm));
745 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
766 MI.addOperand(MCOperand::createImm(Imm));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 206 int64_t Imm = Inst.getOperand(0).getImm();
208 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
| intel.go | 62 if imm, ok := iargs[0].(Imm); ok {
64 iargs[0] = Imm(uint32(int8(imm)))
66 iargs[0] = Imm(uint16(int8(imm)))
71 if imm, ok := iargs[0].(Imm); ok {
72 iargs[0] = Imm(uint32(imm))
[all...] |
| inst.go | 136 // one of these types: Reg, Mem, Imm, Rel.
388 // An Imm is an integer constant.
389 type Imm int64
391 func (Imm) isArg() {}
393 func (i Imm) String() string {
436 _, ok := a.(Imm)
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
| intel.go | 62 if imm, ok := iargs[0].(Imm); ok {
64 iargs[0] = Imm(uint32(int8(imm)))
66 iargs[0] = Imm(uint16(int8(imm)))
71 if imm, ok := iargs[0].(Imm); ok {
72 iargs[0] = Imm(uint32(imm))
[all...] |
| inst.go | 136 // one of these types: Reg, Mem, Imm, Rel.
388 // An Imm is an integer constant.
389 type Imm int64
391 func (Imm) isArg() {}
393 func (i Imm) String() string {
436 _, ok := a.(Imm)
|
| /external/capstone/arch/ARM/ |
| ARMInstPrinter.c | 144 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
169 static unsigned translateShiftImm(unsigned imm)
172 //assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
173 if (imm == 0)
175 return imm;
703 int32_t imm; local
723 imm = (int32_t)MCOperand_getImm(Op);
746 imm += address;
748 if (imm > HEX_THRESHOLD)
749 SStream_concat(O, "#0x%x", imm);
1650 unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); local
1662 unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 165 bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
193 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
206 bool LHSIsKill, uint64_t Imm);
210 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
220 uint64_t Imm, bool IsZExt = true);
224 uint64_t Imm, bool IsZExt = true);
228 uint64_t Imm, bool IsZExt = false);
366 int Imm =
368 assert((Imm != -1) && "Cannot encode floating-point constant.")
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstX86BaseImpl.h | 606 } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Target)) {
610 Asm->jmp(AssemblerImmediate(Imm->getValue()));
663 } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
664 Asm->call(AssemblerImmediate(Imm->getValue()));
753 } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
754 (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
755 } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
757 assert(Utils::IsInt(32, Imm->getValue()));
758 (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
784 } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src))
[all...] |
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| GPRArith.cpp | 389 #define TestImplRegImm(Dst, Value0, Imm, Size) \
393 "(" #Dst ", " #Value0 ", " #Imm ", " #Size ")"; \
399 Immediate((Imm)&Mask##Size)); \
409 ASSERT_EQ(((Value0)&Mask##Size) & ((Imm)&Mask##Size) ? ValueIfTrue \
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 531 unsigned Imm;
548 unsigned Imm;
575 struct ImmOp Imm;
631 return Imm.Val;
636 return Imm.Val;
702 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
703 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
716 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
717 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
729 // with two bits of shift. textually it may be either [pc, #imm], #imm or
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86RegisterInfo.cpp | 491 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
493 if (isInt<8>(Imm))
497 if (isInt<8>(Imm))
503 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
505 if (isInt<8>(Imm))
509 if (isInt<8>(Imm))
634 int Imm = (int)(MI.getOperand(i + 3).getImm());
635 int Offset = FIOffset + Imm;
636 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 392 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
393 bool isLegalICmpImmediate(int64_t Imm) const override;
394 bool isLegalAddImmediate(int64_t Imm) const override;
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 159 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
317 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
321 if (isInt<16>(Imm)) {
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
325 } else if (isUInt<16>(Imm)) {
326 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
329 unsigned Lo = Imm & 0xFFFF;
330 unsigned Hi = (Imm >> 16) & 0xFFFF;
345 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
349 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass)
[all...] |
