| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| r6-branch-constraints.s | 8 bgec $0,$2,.
9 bgec $2,$0,.
10 bgec $2,$2,.
|
| r6-branch-constraints.l | 8 .*:8: Error: invalid operands `bgec \$0,\$2,.'
9 .*:9: Error: invalid operands `bgec \$2,\$0,.'
10 .*:10: Error: invalid operands `bgec \$2,\$2,.'
|
| r6.s | 170 bgec $2, $3, ext
171 bgec $2, $3, . + 4 + (-32768 << 2)
172 bgec $2, $3, . + 4 + (32767 << 2)
173 bgec $2, $3, 1f
174 bgec $3, $2, 1f
|
| r6-n32.d | 295 0+0378 <[^>]*> 58430000 bgec v0,v1,0000037c <[^>]*>
298 0+0380 <[^>]*> 58430000 bgec v0,v1,00000384 <[^>]*>
301 0+0388 <[^>]*> 58430000 bgec v0,v1,0000038c <[^>]*>
304 0+0390 <[^>]*> 58430000 bgec v0,v1,00000394 <[^>]*>
307 0+0398 <[^>]*> 58620000 bgec v1,v0,0000039c <[^>]*>
|
| r6.d | 294 0+0378 <[^>]*> 5843ffff bgec v0,v1,00000378 <[^>]*>
297 0+0380 <[^>]*> 58438000 bgec v0,v1,fffe0384 <[^>]*>
300 0+0388 <[^>]*> 58437fff bgec v0,v1,00020388 <[^>]*>
303 0+0390 <[^>]*> 5843ffff bgec v0,v1,00000390 <[^>]*>
306 0+0398 <[^>]*> 5862ffff bgec v1,v0,00000398 <[^>]*>
|
| r6-n64.d | 419 0+0378 <[^>]*> 58430000 bgec v0,v1,0+037c <[^>]*>
424 0+0380 <[^>]*> 58430000 bgec v0,v1,0+0384 <[^>]*>
429 0+0388 <[^>]*> 58430000 bgec v0,v1,0+038c <[^>]*>
434 0+0390 <[^>]*> 58430000 bgec v0,v1,0+0394 <[^>]*>
439 0+0398 <[^>]*> 58620000 bgec v1,v0,0+039c <[^>]*>
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 64 * idioms, which should translate into bgec and bltc respectively with swapped
69 bgec \rreg, \lreg, \target
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 318 return Mips::BGEC;
421 case Mips::BGEC:
|
| Mips32r6InstrInfo.td | 395 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
760 def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-mips32r6-el.txt | 26 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 260
27 0xfa 0xff 0x43 0x58 # CHECK: bgec $2, $3, -20
|
| valid-mips32r6.txt | 156 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
157 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-mips64r6-el.txt | 24 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 260
25 0xfa 0xff 0x43 0x58 # CHECK: bgec $2, $3, -20
|
| valid-mips64r6.txt | 175 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
176 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid.s | 48 bgec $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
54 bgec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
|
| valid.s | 45 bgec $2, $3, 256 # CHECK: bgec $2, $3, 256 # encoding: [0x58,0x43,0x00,0x40]
|
| /art/compiler/utils/mips/ |
| assembler_mips32r6_test.cc | [all...] |
| assembler_mips.h | 427 void Bgec(Register rs, Register rt, uint16_t imm16); // R6
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | 624 void bgec(Register rs, Register rt, int16_t offset);
625 inline void bgec(Register rs, Register rt, Label* L) {
626 bgec(rs, rt, shifted_branch_offset(L));
[all...] |
| constants-mips.h | 404 POP26 = BLEZL, // bgezc, blezc, bgec/blec
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 628 void bgec(Register rs, Register rt, int16_t offset);
629 inline void bgec(Register rs, Register rt, Label* L) {
630 bgec(rs, rt, shifted_branch_offset(L));
[all...] |
| constants-mips64.h | 387 POP26 = BLEZL, // bgezc, blezc, bgec/blec
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 41 bgec $2, $3, 256 # CHECK: bgec $2, $3, 256 # encoding: [0x58,0x43,0x00,0x40]
|
| invalid.s | 50 bgec $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 560 void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 741 // BGEC if rs != rt && rs != 0 && rt != 0
756 MI.setOpcode(Mips::BGEC);
[all...] |
