| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen8_ds_state.c | 47 OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
48 OUT_BATCH(stage_state->prog_offset);
49 OUT_BATCH(0);
50 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
59 OUT_BATCH(0);
60 OUT_BATCH(0);
62 OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg,
67 OUT_BATCH(GEN7_DS_ENABLE |
74 OUT_BATCH(SET_FIELD(vue_prog_data->cull_distance_mask,
79 OUT_BATCH(0)
[all...] |
| gen8_hs_state.c | 43 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
44 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
48 OUT_BATCH(GEN7_HS_ENABLE |
53 OUT_BATCH(stage_state->prog_offset);
54 OUT_BATCH(0);
60 OUT_BATCH(0);
61 OUT_BATCH(0);
63 OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
66 OUT_BATCH(0); /* MBZ */
70 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2))
[all...] |
| gen6_gs_state.c | 74 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
75 OUT_BATCH(brw->ff_gs.prog_offset);
76 OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE);
77 OUT_BATCH(0); /* no scratch space */
78 OUT_BATCH((2 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
80 OUT_BATCH(((devinfo->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) |
84 OUT_BATCH(GEN6_GS_SVBI_PAYLOAD_ENABLE |
107 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
108 OUT_BATCH(0);
109 OUT_BATCH(0)
[all...] |
| gen8_gs_state.c | 52 OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2));
53 OUT_BATCH(stage_state->prog_offset);
54 OUT_BATCH(0);
55 OUT_BATCH(gs_prog_data->vertices_in |
66 OUT_BATCH(0);
67 OUT_BATCH(0);
71 OUT_BATCH(((gs_prog_data->output_vertex_size_hwords * 2 - 1) <<
109 OUT_BATCH(dw7);
112 OUT_BATCH(dw8);
115 OUT_BATCH(vue_prog_data->cull_distance_mask
[all...] |
| gen8_sol_state.c | 58 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (8 - 2));
59 OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
60 OUT_BATCH(0);
61 OUT_BATCH(0);
62 OUT_BATCH(0);
63 OUT_BATCH(0);
64 OUT_BATCH(0);
65 OUT_BATCH(0);
78 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (8 - 2));
79 OUT_BATCH(GEN8_SO_BUFFER_ENABLE | (i << SO_BUFFER_INDEX_SHIFT)
[all...] |
| brw_compute.c | 58 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
59 OUT_BATCH(MI_PREDICATE_SRC0 + 4);
60 OUT_BATCH(0u);
61 OUT_BATCH(MI_PREDICATE_SRC1 + 0);
62 OUT_BATCH(0u);
63 OUT_BATCH(MI_PREDICATE_SRC1 + 4);
64 OUT_BATCH(0u);
74 OUT_BATCH(GEN7_MI_PREDICATE |
87 OUT_BATCH(GEN7_MI_PREDICATE |
100 OUT_BATCH(GEN7_MI_PREDICATE
[all...] |
| gen8_multisample_state.c | 41 OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE << 16 | (2 - 2));
42 OUT_BATCH(MS_PIXEL_LOCATION_CENTER | log2_samples << 1);
53 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
56 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */
57 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */
58 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */
59 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */
62 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */
63 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */
66 OUT_BATCH(brw_multisample_positions_4x)
[all...] |
| gen6_constant_state.c | 42 OUT_BATCH(opcode << 16 | (dwords - 2));
56 OUT_BATCH(0);
57 OUT_BATCH(stage_state->push_const_size);
59 OUT_BATCH(active ? stage_state->push_const_size : 0);
60 OUT_BATCH(0);
66 OUT_BATCH(0);
67 OUT_BATCH(0);
68 OUT_BATCH(0);
69 OUT_BATCH(0);
75 OUT_BATCH(0)
[all...] |
| hsw_sol.c | 108 OUT_BATCH(HSW_MI_MATH | (9 - 2));
110 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2));
111 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1));
112 OUT_BATCH(MI_MATH_ALU0(SUB));
113 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU));
115 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0));
116 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1));
117 OUT_BATCH(MI_MATH_ALU0(ADD));
118 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU));
131 OUT_BATCH(HSW_MI_MATH | (5 - 2))
[all...] |
| gen7_hs_state.c | 77 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
78 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
83 OUT_BATCH(GEN7_HS_ENABLE |
87 OUT_BATCH(stage_state->prog_offset);
93 OUT_BATCH(0);
95 OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES |
99 OUT_BATCH(0);
103 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
104 OUT_BATCH(0);
105 OUT_BATCH(0)
[all...] |
| gen8_vs_state.c | 51 OUT_BATCH(_3DSTATE_VS << 16 | (9 - 2));
52 OUT_BATCH(stage_state->prog_offset);
53 OUT_BATCH(0);
54 OUT_BATCH(floating_point_mode |
65 OUT_BATCH(0);
66 OUT_BATCH(0);
69 OUT_BATCH((prog_data->dispatch_grf_start_reg <<
78 OUT_BATCH(((devinfo->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) |
83 OUT_BATCH(vue_prog_data->cull_distance_mask);
|
| gen7_misc_state.c | 105 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
108 OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
121 OUT_BATCH(0);
125 OUT_BATCH(((width - 1) << 4) |
130 OUT_BATCH(((depth - 1) << 21) |
135 OUT_BATCH(0);
138 OUT_BATCH((depth - 1) << 21);
143 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
144 OUT_BATCH(0);
145 OUT_BATCH(0)
[all...] |
| gen6_depth_state.c | 112 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
115 OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
130 OUT_BATCH(0);
134 OUT_BATCH(((width - 1) << 6) |
139 OUT_BATCH((depth - 1) << 21 |
144 OUT_BATCH(0);
148 OUT_BATCH(0);
175 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
176 OUT_BATCH(hiz_mt->pitch - 1);
183 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2))
[all...] |
| gen7_ds_state.c | 80 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
81 OUT_BATCH(stage_state->prog_offset);
82 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4),
91 OUT_BATCH(0);
93 OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg,
98 OUT_BATCH(GEN7_DS_ENABLE |
106 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
107 OUT_BATCH(0);
108 OUT_BATCH(0);
109 OUT_BATCH(0)
[all...] |
| gen8_draw_upload.c | 97 OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
98 OUT_BATCH(dw1);
102 OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
103 OUT_BATCH(vue | GEN8_VF_INSTANCING_ENABLE);
104 OUT_BATCH(0);
108 OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
109 OUT_BATCH(0);
138 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (3 - 2));
139 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
143 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT)
[all...] |
| gen8_depth_state.c | 64 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
65 OUT_BATCH(depth_surface_type << 29 |
75 OUT_BATCH(0);
76 OUT_BATCH(0);
78 OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
79 OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
80 OUT_BATCH(0);
81 OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 : 0));
86 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
87 OUT_BATCH(0)
[all...] |
| brw_misc_state.c | 56 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
57 OUT_BATCH(0); /* xmin, ymin */
58 OUT_BATCH(((fb_width - 1) & 0xffff) | ((fb_height - 1) << 16));
59 OUT_BATCH(0);
84 OUT_BATCH(MI_FLUSH);
89 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
96 OUT_BATCH(0);
604 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
605 OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
619 OUT_BATCH(0)
[all...] |
| brw_pipe_control.c | 132 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
133 OUT_BATCH(flags);
134 OUT_BATCH(0);
135 OUT_BATCH(0);
136 OUT_BATCH(0);
137 OUT_BATCH(0);
154 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
155 OUT_BATCH(flags);
156 OUT_BATCH(0);
157 OUT_BATCH(0)
[all...] |
| gen6_vs_state.c | 98 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
99 OUT_BATCH(0);
100 OUT_BATCH(0);
101 OUT_BATCH(0);
102 OUT_BATCH(0);
106 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
112 OUT_BATCH(stage_state->push_const_offset +
114 OUT_BATCH(0);
115 OUT_BATCH(0);
116 OUT_BATCH(0)
[all...] |
| gen6_wm_state.c | 94 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
95 OUT_BATCH(0);
96 OUT_BATCH(0);
97 OUT_BATCH(0);
98 OUT_BATCH(0);
102 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
108 OUT_BATCH(stage_state->push_const_offset +
110 OUT_BATCH(0);
111 OUT_BATCH(0);
112 OUT_BATCH(0)
[all...] |
| gen7_gs_state.c | 62 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
63 OUT_BATCH(stage_state->prog_offset);
64 OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) <<
74 OUT_BATCH(0);
135 OUT_BATCH(dw4);
136 OUT_BATCH(dw5);
137 OUT_BATCH(dw6);
141 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
142 OUT_BATCH(0); /* prog_bo */
143 OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT)
[all...] |
| gen7_vs_state.c | 51 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
52 OUT_BATCH(stage_state->prog_offset);
53 OUT_BATCH(floating_point_mode |
64 OUT_BATCH(0);
67 OUT_BATCH((prog_data->dispatch_grf_start_reg <<
72 OUT_BATCH(((devinfo->max_vs_threads - 1) << max_threads_shift) |
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_clear.c | 133 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
135 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
136 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT);
138 OUT_BATCH(clear_color);
139 OUT_BATCH(clear_depth);
141 OUT_BATCH(clear_color8888);
143 OUT_BATCH(clear_stencil);
145 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
153 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
154 OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR)
[all...] |
| i915_blit.c | 78 OUT_BATCH(CMD);
79 OUT_BATCH(BR13);
80 OUT_BATCH((y << 16) | x);
81 OUT_BATCH(((y + h) << 16) | (x + w));
83 OUT_BATCH(color);
150 OUT_BATCH(CMD);
151 OUT_BATCH(BR13);
152 OUT_BATCH((dst_y << 16) | dst_x);
153 OUT_BATCH((dst_y2 << 16) | dst_x2);
155 OUT_BATCH((src_y << 16) | src_x)
[all...] |
| i915_state_emit.c | 68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE);
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE);
172 OUT_BATCH(fixup_imm);
192 OUT_BATCH(imm);
207 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
215 OUT_BATCH(0);
225 OUT_BATCH(i915->current.immediate[i]);
242 OUT_BATCH(i915->current.dynamic[i]);
274 OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
275 OUT_BATCH(i915->current.cbuf_flags)
[all...] |
