1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the MachineRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/IndexedMap.h" 19 #include "llvm/ADT/PointerUnion.h" 20 #include "llvm/ADT/iterator_range.h" 21 // PointerUnion needs to have access to the full RegisterBank type. 22 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineInstrBundle.h" 25 #include "llvm/Target/TargetRegisterInfo.h" 26 #include "llvm/Target/TargetSubtargetInfo.h" 27 #include <vector> 28 29 namespace llvm { 30 class PSetIterator; 31 32 /// Convenient type to represent either a register class or a register bank. 33 typedef PointerUnion<const TargetRegisterClass *, const RegisterBank *> 34 RegClassOrRegBank; 35 36 /// MachineRegisterInfo - Keep track of information for virtual and physical 37 /// registers, including vreg register classes, use/def chains for registers, 38 /// etc. 39 class MachineRegisterInfo { 40 public: 41 class Delegate { 42 virtual void anchor(); 43 public: 44 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0; 45 46 virtual ~Delegate() {} 47 }; 48 49 private: 50 MachineFunction *MF; 51 Delegate *TheDelegate; 52 53 /// True if subregister liveness is tracked. 54 bool TracksSubRegLiveness; 55 56 /// VRegInfo - Information we keep for each virtual register. 57 /// 58 /// Each element in this list contains the register class of the vreg and the 59 /// start of the use/def list for the register. 60 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>, 61 VirtReg2IndexFunctor> 62 VRegInfo; 63 64 /// RegAllocHints - This vector records register allocation hints for virtual 65 /// registers. For each virtual register, it keeps a register and hint type 66 /// pair making up the allocation hint. Hint type is target specific except 67 /// for the value 0 which means the second value of the pair is the preferred 68 /// register for allocation. For example, if the hint is <0, 1024>, it means 69 /// the allocator should prefer the physical register allocated to the virtual 70 /// register of the hint. 71 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 72 73 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 74 /// physical registers. 75 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists; 76 77 /// getRegUseDefListHead - Return the head pointer for the register use/def 78 /// list for the specified virtual or physical register. 79 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 80 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 81 return VRegInfo[RegNo].second; 82 return PhysRegUseDefLists[RegNo]; 83 } 84 85 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 86 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 87 return VRegInfo[RegNo].second; 88 return PhysRegUseDefLists[RegNo]; 89 } 90 91 /// Get the next element in the use-def chain. 92 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 93 assert(MO && MO->isReg() && "This is not a register operand!"); 94 return MO->Contents.Reg.Next; 95 } 96 97 /// UsedPhysRegMask - Additional used physregs including aliases. 98 /// This bit vector represents all the registers clobbered by function calls. 99 BitVector UsedPhysRegMask; 100 101 /// ReservedRegs - This is a bit vector of reserved registers. The target 102 /// may change its mind about which registers should be reserved. This 103 /// vector is the frozen set of reserved registers when register allocation 104 /// started. 105 BitVector ReservedRegs; 106 107 typedef DenseMap<unsigned, unsigned> VRegToSizeMap; 108 /// Map generic virtual registers to their actual size. 109 mutable std::unique_ptr<VRegToSizeMap> VRegToSize; 110 111 /// Accessor for VRegToSize. This accessor should only be used 112 /// by global-isel related work. 113 VRegToSizeMap &getVRegToSize() const { 114 if (!VRegToSize) 115 VRegToSize.reset(new VRegToSizeMap); 116 return *VRegToSize.get(); 117 } 118 119 /// Keep track of the physical registers that are live in to the function. 120 /// Live in values are typically arguments in registers. LiveIn values are 121 /// allowed to have virtual registers associated with them, stored in the 122 /// second element. 123 std::vector<std::pair<unsigned, unsigned> > LiveIns; 124 125 MachineRegisterInfo(const MachineRegisterInfo&) = delete; 126 void operator=(const MachineRegisterInfo&) = delete; 127 public: 128 explicit MachineRegisterInfo(MachineFunction *MF); 129 130 const TargetRegisterInfo *getTargetRegisterInfo() const { 131 return MF->getSubtarget().getRegisterInfo(); 132 } 133 134 void resetDelegate(Delegate *delegate) { 135 // Ensure another delegate does not take over unless the current 136 // delegate first unattaches itself. If we ever need to multicast 137 // notifications, we will need to change to using a list. 138 assert(TheDelegate == delegate && 139 "Only the current delegate can perform reset!"); 140 TheDelegate = nullptr; 141 } 142 143 void setDelegate(Delegate *delegate) { 144 assert(delegate && !TheDelegate && 145 "Attempted to set delegate to null, or to change it without " 146 "first resetting it!"); 147 148 TheDelegate = delegate; 149 } 150 151 //===--------------------------------------------------------------------===// 152 // Function State 153 //===--------------------------------------------------------------------===// 154 155 // isSSA - Returns true when the machine function is in SSA form. Early 156 // passes require the machine function to be in SSA form where every virtual 157 // register has a single defining instruction. 158 // 159 // The TwoAddressInstructionPass and PHIElimination passes take the machine 160 // function out of SSA form when they introduce multiple defs per virtual 161 // register. 162 bool isSSA() const { 163 return MF->getProperties().hasProperty( 164 MachineFunctionProperties::Property::IsSSA); 165 } 166 167 // leaveSSA - Indicates that the machine function is no longer in SSA form. 168 void leaveSSA() { 169 MF->getProperties().clear(MachineFunctionProperties::Property::IsSSA); 170 } 171 172 /// tracksLiveness - Returns true when tracking register liveness accurately. 173 /// (see MachineFUnctionProperties::Property description for details) 174 bool tracksLiveness() const { 175 return MF->getProperties().hasProperty( 176 MachineFunctionProperties::Property::TracksLiveness); 177 } 178 179 /// invalidateLiveness - Indicates that register liveness is no longer being 180 /// tracked accurately. 181 /// 182 /// This should be called by late passes that invalidate the liveness 183 /// information. 184 void invalidateLiveness() { 185 MF->getProperties().clear( 186 MachineFunctionProperties::Property::TracksLiveness); 187 } 188 189 /// Returns true if liveness for register class @p RC should be tracked at 190 /// the subregister level. 191 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const { 192 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; 193 } 194 bool shouldTrackSubRegLiveness(unsigned VReg) const { 195 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg"); 196 return shouldTrackSubRegLiveness(*getRegClass(VReg)); 197 } 198 bool subRegLivenessEnabled() const { 199 return TracksSubRegLiveness; 200 } 201 202 void enableSubRegLiveness(bool Enable = true) { 203 TracksSubRegLiveness = Enable; 204 } 205 206 //===--------------------------------------------------------------------===// 207 // Register Info 208 //===--------------------------------------------------------------------===// 209 210 // Strictly for use by MachineInstr.cpp. 211 void addRegOperandToUseList(MachineOperand *MO); 212 213 // Strictly for use by MachineInstr.cpp. 214 void removeRegOperandFromUseList(MachineOperand *MO); 215 216 // Strictly for use by MachineInstr.cpp. 217 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 218 219 /// Verify the sanity of the use list for Reg. 220 void verifyUseList(unsigned Reg) const; 221 222 /// Verify the use list of all registers. 223 void verifyUseLists() const; 224 225 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 226 /// and uses of a register within the MachineFunction that corresponds to this 227 /// MachineRegisterInfo object. 228 template<bool Uses, bool Defs, bool SkipDebug, 229 bool ByOperand, bool ByInstr, bool ByBundle> 230 class defusechain_iterator; 231 template<bool Uses, bool Defs, bool SkipDebug, 232 bool ByOperand, bool ByInstr, bool ByBundle> 233 class defusechain_instr_iterator; 234 235 // Make it a friend so it can access getNextOperandForReg(). 236 template<bool, bool, bool, bool, bool, bool> 237 friend class defusechain_iterator; 238 template<bool, bool, bool, bool, bool, bool> 239 friend class defusechain_instr_iterator; 240 241 242 243 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 244 /// register. 245 typedef defusechain_iterator<true,true,false,true,false,false> 246 reg_iterator; 247 reg_iterator reg_begin(unsigned RegNo) const { 248 return reg_iterator(getRegUseDefListHead(RegNo)); 249 } 250 static reg_iterator reg_end() { return reg_iterator(nullptr); } 251 252 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { 253 return make_range(reg_begin(Reg), reg_end()); 254 } 255 256 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses 257 /// of the specified register, stepping by MachineInstr. 258 typedef defusechain_instr_iterator<true,true,false,false,true,false> 259 reg_instr_iterator; 260 reg_instr_iterator reg_instr_begin(unsigned RegNo) const { 261 return reg_instr_iterator(getRegUseDefListHead(RegNo)); 262 } 263 static reg_instr_iterator reg_instr_end() { 264 return reg_instr_iterator(nullptr); 265 } 266 267 inline iterator_range<reg_instr_iterator> 268 reg_instructions(unsigned Reg) const { 269 return make_range(reg_instr_begin(Reg), reg_instr_end()); 270 } 271 272 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses 273 /// of the specified register, stepping by bundle. 274 typedef defusechain_instr_iterator<true,true,false,false,false,true> 275 reg_bundle_iterator; 276 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const { 277 return reg_bundle_iterator(getRegUseDefListHead(RegNo)); 278 } 279 static reg_bundle_iterator reg_bundle_end() { 280 return reg_bundle_iterator(nullptr); 281 } 282 283 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { 284 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); 285 } 286 287 /// reg_empty - Return true if there are no instructions using or defining the 288 /// specified register (it may be live-in). 289 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 290 291 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 292 /// of the specified register, skipping those marked as Debug. 293 typedef defusechain_iterator<true,true,true,true,false,false> 294 reg_nodbg_iterator; 295 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 296 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 297 } 298 static reg_nodbg_iterator reg_nodbg_end() { 299 return reg_nodbg_iterator(nullptr); 300 } 301 302 inline iterator_range<reg_nodbg_iterator> 303 reg_nodbg_operands(unsigned Reg) const { 304 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end()); 305 } 306 307 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk 308 /// all defs and uses of the specified register, stepping by MachineInstr, 309 /// skipping those marked as Debug. 310 typedef defusechain_instr_iterator<true,true,true,false,true,false> 311 reg_instr_nodbg_iterator; 312 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const { 313 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 314 } 315 static reg_instr_nodbg_iterator reg_instr_nodbg_end() { 316 return reg_instr_nodbg_iterator(nullptr); 317 } 318 319 inline iterator_range<reg_instr_nodbg_iterator> 320 reg_nodbg_instructions(unsigned Reg) const { 321 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end()); 322 } 323 324 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk 325 /// all defs and uses of the specified register, stepping by bundle, 326 /// skipping those marked as Debug. 327 typedef defusechain_instr_iterator<true,true,true,false,false,true> 328 reg_bundle_nodbg_iterator; 329 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const { 330 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 331 } 332 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() { 333 return reg_bundle_nodbg_iterator(nullptr); 334 } 335 336 inline iterator_range<reg_bundle_nodbg_iterator> 337 reg_nodbg_bundles(unsigned Reg) const { 338 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end()); 339 } 340 341 /// reg_nodbg_empty - Return true if the only instructions using or defining 342 /// Reg are Debug instructions. 343 bool reg_nodbg_empty(unsigned RegNo) const { 344 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 345 } 346 347 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 348 typedef defusechain_iterator<false,true,false,true,false,false> 349 def_iterator; 350 def_iterator def_begin(unsigned RegNo) const { 351 return def_iterator(getRegUseDefListHead(RegNo)); 352 } 353 static def_iterator def_end() { return def_iterator(nullptr); } 354 355 inline iterator_range<def_iterator> def_operands(unsigned Reg) const { 356 return make_range(def_begin(Reg), def_end()); 357 } 358 359 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the 360 /// specified register, stepping by MachineInst. 361 typedef defusechain_instr_iterator<false,true,false,false,true,false> 362 def_instr_iterator; 363 def_instr_iterator def_instr_begin(unsigned RegNo) const { 364 return def_instr_iterator(getRegUseDefListHead(RegNo)); 365 } 366 static def_instr_iterator def_instr_end() { 367 return def_instr_iterator(nullptr); 368 } 369 370 inline iterator_range<def_instr_iterator> 371 def_instructions(unsigned Reg) const { 372 return make_range(def_instr_begin(Reg), def_instr_end()); 373 } 374 375 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the 376 /// specified register, stepping by bundle. 377 typedef defusechain_instr_iterator<false,true,false,false,false,true> 378 def_bundle_iterator; 379 def_bundle_iterator def_bundle_begin(unsigned RegNo) const { 380 return def_bundle_iterator(getRegUseDefListHead(RegNo)); 381 } 382 static def_bundle_iterator def_bundle_end() { 383 return def_bundle_iterator(nullptr); 384 } 385 386 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const { 387 return make_range(def_bundle_begin(Reg), def_bundle_end()); 388 } 389 390 /// def_empty - Return true if there are no instructions defining the 391 /// specified register (it may be live-in). 392 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 393 394 /// Return true if there is exactly one operand defining the specified 395 /// register. 396 bool hasOneDef(unsigned RegNo) const { 397 def_iterator DI = def_begin(RegNo); 398 if (DI == def_end()) 399 return false; 400 return ++DI == def_end(); 401 } 402 403 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 404 typedef defusechain_iterator<true,false,false,true,false,false> 405 use_iterator; 406 use_iterator use_begin(unsigned RegNo) const { 407 return use_iterator(getRegUseDefListHead(RegNo)); 408 } 409 static use_iterator use_end() { return use_iterator(nullptr); } 410 411 inline iterator_range<use_iterator> use_operands(unsigned Reg) const { 412 return make_range(use_begin(Reg), use_end()); 413 } 414 415 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the 416 /// specified register, stepping by MachineInstr. 417 typedef defusechain_instr_iterator<true,false,false,false,true,false> 418 use_instr_iterator; 419 use_instr_iterator use_instr_begin(unsigned RegNo) const { 420 return use_instr_iterator(getRegUseDefListHead(RegNo)); 421 } 422 static use_instr_iterator use_instr_end() { 423 return use_instr_iterator(nullptr); 424 } 425 426 inline iterator_range<use_instr_iterator> 427 use_instructions(unsigned Reg) const { 428 return make_range(use_instr_begin(Reg), use_instr_end()); 429 } 430 431 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the 432 /// specified register, stepping by bundle. 433 typedef defusechain_instr_iterator<true,false,false,false,false,true> 434 use_bundle_iterator; 435 use_bundle_iterator use_bundle_begin(unsigned RegNo) const { 436 return use_bundle_iterator(getRegUseDefListHead(RegNo)); 437 } 438 static use_bundle_iterator use_bundle_end() { 439 return use_bundle_iterator(nullptr); 440 } 441 442 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const { 443 return make_range(use_bundle_begin(Reg), use_bundle_end()); 444 } 445 446 /// use_empty - Return true if there are no instructions using the specified 447 /// register. 448 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 449 450 /// hasOneUse - Return true if there is exactly one instruction using the 451 /// specified register. 452 bool hasOneUse(unsigned RegNo) const { 453 use_iterator UI = use_begin(RegNo); 454 if (UI == use_end()) 455 return false; 456 return ++UI == use_end(); 457 } 458 459 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 460 /// specified register, skipping those marked as Debug. 461 typedef defusechain_iterator<true,false,true,true,false,false> 462 use_nodbg_iterator; 463 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 464 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 465 } 466 static use_nodbg_iterator use_nodbg_end() { 467 return use_nodbg_iterator(nullptr); 468 } 469 470 inline iterator_range<use_nodbg_iterator> 471 use_nodbg_operands(unsigned Reg) const { 472 return make_range(use_nodbg_begin(Reg), use_nodbg_end()); 473 } 474 475 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk 476 /// all uses of the specified register, stepping by MachineInstr, skipping 477 /// those marked as Debug. 478 typedef defusechain_instr_iterator<true,false,true,false,true,false> 479 use_instr_nodbg_iterator; 480 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const { 481 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 482 } 483 static use_instr_nodbg_iterator use_instr_nodbg_end() { 484 return use_instr_nodbg_iterator(nullptr); 485 } 486 487 inline iterator_range<use_instr_nodbg_iterator> 488 use_nodbg_instructions(unsigned Reg) const { 489 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end()); 490 } 491 492 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk 493 /// all uses of the specified register, stepping by bundle, skipping 494 /// those marked as Debug. 495 typedef defusechain_instr_iterator<true,false,true,false,false,true> 496 use_bundle_nodbg_iterator; 497 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const { 498 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 499 } 500 static use_bundle_nodbg_iterator use_bundle_nodbg_end() { 501 return use_bundle_nodbg_iterator(nullptr); 502 } 503 504 inline iterator_range<use_bundle_nodbg_iterator> 505 use_nodbg_bundles(unsigned Reg) const { 506 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end()); 507 } 508 509 /// use_nodbg_empty - Return true if there are no non-Debug instructions 510 /// using the specified register. 511 bool use_nodbg_empty(unsigned RegNo) const { 512 return use_nodbg_begin(RegNo) == use_nodbg_end(); 513 } 514 515 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 516 /// instruction using the specified register. 517 bool hasOneNonDBGUse(unsigned RegNo) const; 518 519 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 520 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 521 /// except that it also changes any definitions of the register as well. 522 /// 523 /// Note that it is usually necessary to first constrain ToReg's register 524 /// class to match the FromReg constraints using: 525 /// 526 /// constrainRegClass(ToReg, getRegClass(FromReg)) 527 /// 528 /// That function will return NULL if the virtual registers have incompatible 529 /// constraints. 530 /// 531 /// Note that if ToReg is a physical register the function will replace and 532 /// apply sub registers to ToReg in order to obtain a final/proper physical 533 /// register. 534 void replaceRegWith(unsigned FromReg, unsigned ToReg); 535 536 /// getVRegDef - Return the machine instr that defines the specified virtual 537 /// register or null if none is found. This assumes that the code is in SSA 538 /// form, so there should only be one definition. 539 MachineInstr *getVRegDef(unsigned Reg) const; 540 541 /// getUniqueVRegDef - Return the unique machine instr that defines the 542 /// specified virtual register or null if none is found. If there are 543 /// multiple definitions or no definition, return null. 544 MachineInstr *getUniqueVRegDef(unsigned Reg) const; 545 546 /// clearKillFlags - Iterate over all the uses of the given register and 547 /// clear the kill flag from the MachineOperand. This function is used by 548 /// optimization passes which extend register lifetimes and need only 549 /// preserve conservative kill flag information. 550 void clearKillFlags(unsigned Reg) const; 551 552 #ifndef NDEBUG 553 void dumpUses(unsigned RegNo) const; 554 #endif 555 556 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 557 /// throughout the function. It is safe to move instructions that read such 558 /// a physreg. 559 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 560 561 /// Get an iterator over the pressure sets affected by the given physical or 562 /// virtual register. If RegUnit is physical, it must be a register unit (from 563 /// MCRegUnitIterator). 564 PSetIterator getPressureSets(unsigned RegUnit) const; 565 566 //===--------------------------------------------------------------------===// 567 // Virtual Register Info 568 //===--------------------------------------------------------------------===// 569 570 /// Return the register class of the specified virtual register. 571 /// This shouldn't be used directly unless \p Reg has a register class. 572 /// \see getRegClassOrNull when this might happen. 573 /// 574 const TargetRegisterClass *getRegClass(unsigned Reg) const { 575 assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() && 576 "Register class not set, wrong accessor"); 577 return VRegInfo[Reg].first.get<const TargetRegisterClass *>(); 578 } 579 580 /// Return the register class of \p Reg, or null if Reg has not been assigned 581 /// a register class yet. 582 /// 583 /// \note A null register class can only happen when these two 584 /// conditions are met: 585 /// 1. Generic virtual registers are created. 586 /// 2. The machine function has not completely been through the 587 /// instruction selection process. 588 /// None of this condition is possible without GlobalISel for now. 589 /// In other words, if GlobalISel is not used or if the query happens after 590 /// the select pass, using getRegClass is safe. 591 const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const { 592 const RegClassOrRegBank &Val = VRegInfo[Reg].first; 593 return Val.dyn_cast<const TargetRegisterClass *>(); 594 } 595 596 /// Return the register bank of \p Reg, or null if Reg has not been assigned 597 /// a register bank or has been assigned a register class. 598 /// \note It is possible to get the register bank from the register class via 599 /// RegisterBankInfo::getRegBankFromRegClass. 600 /// 601 const RegisterBank *getRegBankOrNull(unsigned Reg) const { 602 const RegClassOrRegBank &Val = VRegInfo[Reg].first; 603 return Val.dyn_cast<const RegisterBank *>(); 604 } 605 606 /// Return the register bank or register class of \p Reg. 607 /// \note Before the register bank gets assigned (i.e., before the 608 /// RegBankSelect pass) \p Reg may not have either. 609 /// 610 const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const { 611 return VRegInfo[Reg].first; 612 } 613 614 /// setRegClass - Set the register class of the specified virtual register. 615 /// 616 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 617 618 /// Set the register bank to \p RegBank for \p Reg. 619 /// 620 void setRegBank(unsigned Reg, const RegisterBank &RegBank); 621 622 /// constrainRegClass - Constrain the register class of the specified virtual 623 /// register to be a common subclass of RC and the current register class, 624 /// but only if the new class has at least MinNumRegs registers. Return the 625 /// new register class, or NULL if no such class exists. 626 /// This should only be used when the constraint is known to be trivial, like 627 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 628 /// 629 const TargetRegisterClass *constrainRegClass(unsigned Reg, 630 const TargetRegisterClass *RC, 631 unsigned MinNumRegs = 0); 632 633 /// recomputeRegClass - Try to find a legal super-class of Reg's register 634 /// class that still satisfies the constraints from the instructions using 635 /// Reg. Returns true if Reg was upgraded. 636 /// 637 /// This method can be used after constraints have been removed from a 638 /// virtual register, for example after removing instructions or splitting 639 /// the live range. 640 /// 641 bool recomputeRegClass(unsigned Reg); 642 643 /// createVirtualRegister - Create and return a new virtual register in the 644 /// function with the specified register class. 645 /// 646 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 647 648 /// Get the size in bits of \p VReg or 0 if VReg is not a generic 649 /// (target independent) virtual register. 650 unsigned getSize(unsigned VReg) const; 651 652 /// Set the size in bits of \p VReg to \p Size. 653 /// Although the size should be set at build time, mir infrastructure 654 /// is not yet able to do it. 655 void setSize(unsigned VReg, unsigned Size); 656 657 /// Create and return a new generic virtual register with a size of \p Size. 658 /// \pre Size > 0. 659 unsigned createGenericVirtualRegister(unsigned Size); 660 661 /// getNumVirtRegs - Return the number of virtual registers created. 662 /// 663 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 664 665 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 666 void clearVirtRegs(); 667 668 /// setRegAllocationHint - Specify a register allocation hint for the 669 /// specified virtual register. 670 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { 671 assert(TargetRegisterInfo::isVirtualRegister(VReg)); 672 RegAllocHints[VReg].first = Type; 673 RegAllocHints[VReg].second = PrefReg; 674 } 675 676 /// Specify the preferred register allocation hint for the specified virtual 677 /// register. 678 void setSimpleHint(unsigned VReg, unsigned PrefReg) { 679 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); 680 } 681 682 /// getRegAllocationHint - Return the register allocation hint for the 683 /// specified virtual register. 684 std::pair<unsigned, unsigned> 685 getRegAllocationHint(unsigned VReg) const { 686 assert(TargetRegisterInfo::isVirtualRegister(VReg)); 687 return RegAllocHints[VReg]; 688 } 689 690 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 691 /// standard simple hint (Type == 0) is not set. 692 unsigned getSimpleHint(unsigned VReg) const { 693 assert(TargetRegisterInfo::isVirtualRegister(VReg)); 694 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg); 695 return Hint.first ? 0 : Hint.second; 696 } 697 698 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 699 /// specified register as undefined which causes the DBG_VALUE to be 700 /// deleted during LiveDebugVariables analysis. 701 void markUsesInDebugValueAsUndef(unsigned Reg) const; 702 703 /// Return true if the specified register is modified in this function. 704 /// This checks that no defining machine operands exist for the register or 705 /// any of its aliases. Definitions found on functions marked noreturn are 706 /// ignored, to consider them pass 'true' for optional parameter 707 /// SkipNoReturnDef. The register is also considered modified when it is set 708 /// in the UsedPhysRegMask. 709 bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const; 710 711 /// Return true if the specified register is modified or read in this 712 /// function. This checks that no machine operands exist for the register or 713 /// any of its aliases. The register is also considered used when it is set 714 /// in the UsedPhysRegMask. 715 bool isPhysRegUsed(unsigned PhysReg) const; 716 717 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 718 /// This corresponds to the bit mask attached to register mask operands. 719 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 720 UsedPhysRegMask.setBitsNotInMask(RegMask); 721 } 722 723 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; } 724 725 void setUsedPhysRegMask(BitVector &Mask) { UsedPhysRegMask = Mask; } 726 727 //===--------------------------------------------------------------------===// 728 // Reserved Register Info 729 //===--------------------------------------------------------------------===// 730 // 731 // The set of reserved registers must be invariant during register 732 // allocation. For example, the target cannot suddenly decide it needs a 733 // frame pointer when the register allocator has already used the frame 734 // pointer register for something else. 735 // 736 // These methods can be used by target hooks like hasFP() to avoid changing 737 // the reserved register set during register allocation. 738 739 /// freezeReservedRegs - Called by the register allocator to freeze the set 740 /// of reserved registers before allocation begins. 741 void freezeReservedRegs(const MachineFunction&); 742 743 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 744 /// to ensure the set of reserved registers stays constant. 745 bool reservedRegsFrozen() const { 746 return !ReservedRegs.empty(); 747 } 748 749 /// canReserveReg - Returns true if PhysReg can be used as a reserved 750 /// register. Any register can be reserved before freezeReservedRegs() is 751 /// called. 752 bool canReserveReg(unsigned PhysReg) const { 753 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 754 } 755 756 /// getReservedRegs - Returns a reference to the frozen set of reserved 757 /// registers. This method should always be preferred to calling 758 /// TRI::getReservedRegs() when possible. 759 const BitVector &getReservedRegs() const { 760 assert(reservedRegsFrozen() && 761 "Reserved registers haven't been frozen yet. " 762 "Use TRI::getReservedRegs()."); 763 return ReservedRegs; 764 } 765 766 /// isReserved - Returns true when PhysReg is a reserved register. 767 /// 768 /// Reserved registers may belong to an allocatable register class, but the 769 /// target has explicitly requested that they are not used. 770 /// 771 bool isReserved(unsigned PhysReg) const { 772 return getReservedRegs().test(PhysReg); 773 } 774 775 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 776 /// register class and it hasn't been reserved. 777 /// 778 /// Allocatable registers may show up in the allocation order of some virtual 779 /// register, so a register allocator needs to track its liveness and 780 /// availability. 781 bool isAllocatable(unsigned PhysReg) const { 782 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 783 !isReserved(PhysReg); 784 } 785 786 //===--------------------------------------------------------------------===// 787 // LiveIn Management 788 //===--------------------------------------------------------------------===// 789 790 /// addLiveIn - Add the specified register as a live-in. Note that it 791 /// is an error to add the same register to the same set more than once. 792 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 793 LiveIns.push_back(std::make_pair(Reg, vreg)); 794 } 795 796 // Iteration support for the live-ins set. It's kept in sorted order 797 // by register number. 798 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 799 livein_iterator; 800 livein_iterator livein_begin() const { return LiveIns.begin(); } 801 livein_iterator livein_end() const { return LiveIns.end(); } 802 bool livein_empty() const { return LiveIns.empty(); } 803 804 bool isLiveIn(unsigned Reg) const; 805 806 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 807 /// corresponding live-in physical register. 808 unsigned getLiveInPhysReg(unsigned VReg) const; 809 810 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 811 /// corresponding live-in physical register. 812 unsigned getLiveInVirtReg(unsigned PReg) const; 813 814 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 815 /// into the given entry block. 816 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 817 const TargetRegisterInfo &TRI, 818 const TargetInstrInfo &TII); 819 820 /// Returns a mask covering all bits that can appear in lane masks of 821 /// subregisters of the virtual register @p Reg. 822 LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const; 823 824 /// defusechain_iterator - This class provides iterator support for machine 825 /// operands in the function that use or define a specific register. If 826 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 827 /// returns defs. If neither are true then you are silly and it always 828 /// returns end(). If SkipDebug is true it skips uses marked Debug 829 /// when incrementing. 830 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug, 831 bool ByOperand, bool ByInstr, bool ByBundle> 832 class defusechain_iterator 833 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 834 MachineOperand *Op; 835 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 836 // If the first node isn't one we're interested in, advance to one that 837 // we are interested in. 838 if (op) { 839 if ((!ReturnUses && op->isUse()) || 840 (!ReturnDefs && op->isDef()) || 841 (SkipDebug && op->isDebug())) 842 advance(); 843 } 844 } 845 friend class MachineRegisterInfo; 846 847 void advance() { 848 assert(Op && "Cannot increment end iterator!"); 849 Op = getNextOperandForReg(Op); 850 851 // All defs come before the uses, so stop def_iterator early. 852 if (!ReturnUses) { 853 if (Op) { 854 if (Op->isUse()) 855 Op = nullptr; 856 else 857 assert(!Op->isDebug() && "Can't have debug defs"); 858 } 859 } else { 860 // If this is an operand we don't care about, skip it. 861 while (Op && ((!ReturnDefs && Op->isDef()) || 862 (SkipDebug && Op->isDebug()))) 863 Op = getNextOperandForReg(Op); 864 } 865 } 866 public: 867 typedef std::iterator<std::forward_iterator_tag, 868 MachineInstr, ptrdiff_t>::reference reference; 869 typedef std::iterator<std::forward_iterator_tag, 870 MachineInstr, ptrdiff_t>::pointer pointer; 871 872 defusechain_iterator() : Op(nullptr) {} 873 874 bool operator==(const defusechain_iterator &x) const { 875 return Op == x.Op; 876 } 877 bool operator!=(const defusechain_iterator &x) const { 878 return !operator==(x); 879 } 880 881 /// atEnd - return true if this iterator is equal to reg_end() on the value. 882 bool atEnd() const { return Op == nullptr; } 883 884 // Iterator traversal: forward iteration only 885 defusechain_iterator &operator++() { // Preincrement 886 assert(Op && "Cannot increment end iterator!"); 887 if (ByOperand) 888 advance(); 889 else if (ByInstr) { 890 MachineInstr *P = Op->getParent(); 891 do { 892 advance(); 893 } while (Op && Op->getParent() == P); 894 } else if (ByBundle) { 895 MachineInstr &P = getBundleStart(*Op->getParent()); 896 do { 897 advance(); 898 } while (Op && &getBundleStart(*Op->getParent()) == &P); 899 } 900 901 return *this; 902 } 903 defusechain_iterator operator++(int) { // Postincrement 904 defusechain_iterator tmp = *this; ++*this; return tmp; 905 } 906 907 /// getOperandNo - Return the operand # of this MachineOperand in its 908 /// MachineInstr. 909 unsigned getOperandNo() const { 910 assert(Op && "Cannot dereference end iterator!"); 911 return Op - &Op->getParent()->getOperand(0); 912 } 913 914 // Retrieve a reference to the current operand. 915 MachineOperand &operator*() const { 916 assert(Op && "Cannot dereference end iterator!"); 917 return *Op; 918 } 919 920 MachineOperand *operator->() const { 921 assert(Op && "Cannot dereference end iterator!"); 922 return Op; 923 } 924 }; 925 926 /// defusechain_iterator - This class provides iterator support for machine 927 /// operands in the function that use or define a specific register. If 928 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 929 /// returns defs. If neither are true then you are silly and it always 930 /// returns end(). If SkipDebug is true it skips uses marked Debug 931 /// when incrementing. 932 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug, 933 bool ByOperand, bool ByInstr, bool ByBundle> 934 class defusechain_instr_iterator 935 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 936 MachineOperand *Op; 937 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) { 938 // If the first node isn't one we're interested in, advance to one that 939 // we are interested in. 940 if (op) { 941 if ((!ReturnUses && op->isUse()) || 942 (!ReturnDefs && op->isDef()) || 943 (SkipDebug && op->isDebug())) 944 advance(); 945 } 946 } 947 friend class MachineRegisterInfo; 948 949 void advance() { 950 assert(Op && "Cannot increment end iterator!"); 951 Op = getNextOperandForReg(Op); 952 953 // All defs come before the uses, so stop def_iterator early. 954 if (!ReturnUses) { 955 if (Op) { 956 if (Op->isUse()) 957 Op = nullptr; 958 else 959 assert(!Op->isDebug() && "Can't have debug defs"); 960 } 961 } else { 962 // If this is an operand we don't care about, skip it. 963 while (Op && ((!ReturnDefs && Op->isDef()) || 964 (SkipDebug && Op->isDebug()))) 965 Op = getNextOperandForReg(Op); 966 } 967 } 968 public: 969 typedef std::iterator<std::forward_iterator_tag, 970 MachineInstr, ptrdiff_t>::reference reference; 971 typedef std::iterator<std::forward_iterator_tag, 972 MachineInstr, ptrdiff_t>::pointer pointer; 973 974 defusechain_instr_iterator() : Op(nullptr) {} 975 976 bool operator==(const defusechain_instr_iterator &x) const { 977 return Op == x.Op; 978 } 979 bool operator!=(const defusechain_instr_iterator &x) const { 980 return !operator==(x); 981 } 982 983 /// atEnd - return true if this iterator is equal to reg_end() on the value. 984 bool atEnd() const { return Op == nullptr; } 985 986 // Iterator traversal: forward iteration only 987 defusechain_instr_iterator &operator++() { // Preincrement 988 assert(Op && "Cannot increment end iterator!"); 989 if (ByOperand) 990 advance(); 991 else if (ByInstr) { 992 MachineInstr *P = Op->getParent(); 993 do { 994 advance(); 995 } while (Op && Op->getParent() == P); 996 } else if (ByBundle) { 997 MachineInstr &P = getBundleStart(*Op->getParent()); 998 do { 999 advance(); 1000 } while (Op && &getBundleStart(*Op->getParent()) == &P); 1001 } 1002 1003 return *this; 1004 } 1005 defusechain_instr_iterator operator++(int) { // Postincrement 1006 defusechain_instr_iterator tmp = *this; ++*this; return tmp; 1007 } 1008 1009 // Retrieve a reference to the current operand. 1010 MachineInstr &operator*() const { 1011 assert(Op && "Cannot dereference end iterator!"); 1012 if (ByBundle) 1013 return getBundleStart(*Op->getParent()); 1014 return *Op->getParent(); 1015 } 1016 1017 MachineInstr *operator->() const { return &operator*(); } 1018 }; 1019 }; 1020 1021 /// Iterate over the pressure sets affected by the given physical or virtual 1022 /// register. If Reg is physical, it must be a register unit (from 1023 /// MCRegUnitIterator). 1024 class PSetIterator { 1025 const int *PSet; 1026 unsigned Weight; 1027 public: 1028 PSetIterator(): PSet(nullptr), Weight(0) {} 1029 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { 1030 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 1031 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { 1032 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); 1033 PSet = TRI->getRegClassPressureSets(RC); 1034 Weight = TRI->getRegClassWeight(RC).RegWeight; 1035 } 1036 else { 1037 PSet = TRI->getRegUnitPressureSets(RegUnit); 1038 Weight = TRI->getRegUnitWeight(RegUnit); 1039 } 1040 if (*PSet == -1) 1041 PSet = nullptr; 1042 } 1043 bool isValid() const { return PSet; } 1044 1045 unsigned getWeight() const { return Weight; } 1046 1047 unsigned operator*() const { return *PSet; } 1048 1049 void operator++() { 1050 assert(isValid() && "Invalid PSetIterator."); 1051 ++PSet; 1052 if (*PSet == -1) 1053 PSet = nullptr; 1054 } 1055 }; 1056 1057 inline PSetIterator MachineRegisterInfo:: 1058 getPressureSets(unsigned RegUnit) const { 1059 return PSetIterator(RegUnit, this); 1060 } 1061 1062 } // End llvm namespace 1063 1064 #endif 1065