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      1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
     11 // selection DAG.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef NVPTXISELLOWERING_H
     16 #define NVPTXISELLOWERING_H
     17 
     18 #include "NVPTX.h"
     19 #include "NVPTXSubtarget.h"
     20 #include "llvm/CodeGen/SelectionDAG.h"
     21 #include "llvm/Target/TargetLowering.h"
     22 
     23 namespace llvm {
     24 namespace NVPTXISD {
     25 enum NodeType {
     26   // Start the numbering from where ISD NodeType finishes.
     27   FIRST_NUMBER = ISD::BUILTIN_OP_END,
     28   Wrapper,
     29   CALL,
     30   RET_FLAG,
     31   LOAD_PARAM,
     32   NVBuiltin,
     33   DeclareParam,
     34   DeclareScalarParam,
     35   DeclareRetParam,
     36   DeclareRet,
     37   DeclareScalarRet,
     38   LoadParam,
     39   StoreParam,
     40   StoreParamS32, // to sext and store a <32bit value, not used currently
     41   StoreParamU32, // to zext and store a <32bit value, not used currently
     42   MoveToParam,
     43   PrintCall,
     44   PrintCallUni,
     45   CallArgBegin,
     46   CallArg,
     47   LastCallArg,
     48   CallArgEnd,
     49   CallVoid,
     50   CallVal,
     51   CallSymbol,
     52   Prototype,
     53   MoveParam,
     54   MoveRetval,
     55   MoveToRetval,
     56   StoreRetval,
     57   PseudoUseParam,
     58   RETURN,
     59   CallSeqBegin,
     60   CallSeqEnd,
     61   Dummy
     62 };
     63 }
     64 
     65 //===--------------------------------------------------------------------===//
     66 // TargetLowering Implementation
     67 //===--------------------------------------------------------------------===//
     68 class NVPTXTargetLowering : public TargetLowering {
     69 public:
     70   explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
     71   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
     72 
     73   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
     74   SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
     75                              SelectionDAG &DAG) const;
     76 
     77   virtual const char *getTargetNodeName(unsigned Opcode) const;
     78 
     79   bool isTypeSupportedInIntrinsic(MVT VT) const;
     80 
     81   bool getTgtMemIntrinsic(IntrinsicInfo& Info, const CallInst &I,
     82                           unsigned Intrinsic) const;
     83 
     84   /// isLegalAddressingMode - Return true if the addressing mode represented
     85   /// by AM is legal for this target, for a load/store of the specified type
     86   /// Used to guide target specific optimizations, like loop strength
     87   /// reduction (LoopStrengthReduce.cpp) and memory optimization for
     88   /// address mode (CodeGenPrepare.cpp)
     89   virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
     90 
     91   /// getFunctionAlignment - Return the Log2 alignment of this function.
     92   virtual unsigned getFunctionAlignment(const Function *F) const;
     93 
     94   virtual EVT getSetCCResultType(EVT VT) const {
     95     return MVT::i1;
     96   }
     97 
     98   ConstraintType getConstraintType(const std::string &Constraint) const;
     99   std::pair<unsigned, const TargetRegisterClass*>
    100   getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
    101 
    102   virtual SDValue
    103   LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
    104                        const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl,
    105                        SelectionDAG &DAG,
    106                        SmallVectorImpl<SDValue> &InVals) const;
    107 
    108   virtual SDValue
    109   LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
    110 
    111   std::string getPrototype(Type *, const ArgListTy &,
    112                            const SmallVectorImpl<ISD::OutputArg> &,
    113                            unsigned retAlignment) const;
    114 
    115   virtual SDValue
    116   LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
    117               const SmallVectorImpl<ISD::OutputArg> &Outs,
    118               const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
    119               SelectionDAG &DAG) const;
    120 
    121   virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
    122                                             std::vector<SDValue> &Ops,
    123                                             SelectionDAG &DAG) const;
    124 
    125   NVPTXTargetMachine *nvTM;
    126 
    127   // PTX always uses 32-bit shift amounts
    128   virtual MVT getShiftAmountTy(EVT LHSTy) const {
    129     return MVT::i32;
    130   }
    131 
    132 private:
    133   const NVPTXSubtarget &nvptxSubtarget;  // cache the subtarget here
    134 
    135   SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx, EVT =
    136                          MVT::i32) const;
    137   SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT = MVT::i32) const;
    138   SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
    139 
    140   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
    141 };
    142 } // namespace llvm
    143 
    144 #endif // NVPTXISELLOWERING_H
    145