1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 76 /// first (possible) on-stack argument. This is needed for correct stack 77 /// adjustment during unwind. 78 FRAME_TO_ARGS_OFFSET, 79 80 /// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the 81 /// address of the exception block on entry to an landing pad block. 82 EXCEPTIONADDR, 83 84 /// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the 85 /// address of the Language Specific Data Area for the enclosing function. 86 LSDAADDR, 87 88 /// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node 89 /// represents the selection index of the exception thrown. 90 EHSELECTION, 91 92 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 93 /// 'eh_return' gcc dwarf builtin, which is used to return from 94 /// exception. The general meaning is: adjust stack by OFFSET and pass 95 /// execution to HANDLER. Many platform-related details also :) 96 EH_RETURN, 97 98 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 99 /// This corresponds to the eh.sjlj.setjmp intrinsic. 100 /// It takes an input chain and a pointer to the jump buffer as inputs 101 /// and returns an outchain. 102 EH_SJLJ_SETJMP, 103 104 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 105 /// This corresponds to the eh.sjlj.longjmp intrinsic. 106 /// It takes an input chain and a pointer to the jump buffer as inputs 107 /// and returns an outchain. 108 EH_SJLJ_LONGJMP, 109 110 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 111 /// simplification, or lowering of the constant. They are used for constants 112 /// which are known to fit in the immediate fields of their users, or for 113 /// carrying magic numbers which are not values which need to be 114 /// materialized in registers. 115 TargetConstant, 116 TargetConstantFP, 117 118 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 119 /// anything else with this node, and this is valid in the target-specific 120 /// dag, turning into a GlobalAddress operand. 121 TargetGlobalAddress, 122 TargetGlobalTLSAddress, 123 TargetFrameIndex, 124 TargetJumpTable, 125 TargetConstantPool, 126 TargetExternalSymbol, 127 TargetBlockAddress, 128 129 /// TargetIndex - Like a constant pool entry, but with completely 130 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 131 /// 64-bit index. Targets can use this however they like. 132 TargetIndex, 133 134 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 135 /// This node represents a target intrinsic function with no side effects. 136 /// The first operand is the ID number of the intrinsic from the 137 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 138 /// node returns the result of the intrinsic. 139 INTRINSIC_WO_CHAIN, 140 141 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 142 /// This node represents a target intrinsic function with side effects that 143 /// returns a result. The first operand is a chain pointer. The second is 144 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 145 /// operands to the intrinsic follow. The node has two results, the result 146 /// of the intrinsic and an output chain. 147 INTRINSIC_W_CHAIN, 148 149 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 150 /// This node represents a target intrinsic function with side effects that 151 /// does not return a result. The first operand is a chain pointer. The 152 /// second is the ID number of the intrinsic from the llvm::Intrinsic 153 /// namespace. The operands to the intrinsic follow. 154 INTRINSIC_VOID, 155 156 /// CopyToReg - This node has three operands: a chain, a register number to 157 /// set to this value, and a value. 158 CopyToReg, 159 160 /// CopyFromReg - This node indicates that the input value is a virtual or 161 /// physical register that is defined outside of the scope of this 162 /// SelectionDAG. The register is available from the RegisterSDNode object. 163 CopyFromReg, 164 165 /// UNDEF - An undefined node. 166 UNDEF, 167 168 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 169 /// a Constant, which is required to be operand #1) half of the integer or 170 /// float value specified as operand #0. This is only for use before 171 /// legalization, for values that will be broken into multiple registers. 172 EXTRACT_ELEMENT, 173 174 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 175 /// Given two values of the same integer value type, this produces a value 176 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 177 /// legalization. 178 BUILD_PAIR, 179 180 /// MERGE_VALUES - This node takes multiple discrete operands and returns 181 /// them all as its individual results. This nodes has exactly the same 182 /// number of inputs and outputs. This node is useful for some pieces of the 183 /// code generator that want to think about a single node with multiple 184 /// results, not multiple nodes. 185 MERGE_VALUES, 186 187 /// Simple integer binary arithmetic operators. 188 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 189 190 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 191 /// a signed/unsigned value of type i[2*N], and return the full value as 192 /// two results, each of type iN. 193 SMUL_LOHI, UMUL_LOHI, 194 195 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 196 /// remainder result. 197 SDIVREM, UDIVREM, 198 199 /// CARRY_FALSE - This node is used when folding other nodes, 200 /// like ADDC/SUBC, which indicate the carry result is always false. 201 CARRY_FALSE, 202 203 /// Carry-setting nodes for multiple precision addition and subtraction. 204 /// These nodes take two operands of the same value type, and produce two 205 /// results. The first result is the normal add or sub result, the second 206 /// result is the carry flag result. 207 ADDC, SUBC, 208 209 /// Carry-using nodes for multiple precision addition and subtraction. These 210 /// nodes take three operands: The first two are the normal lhs and rhs to 211 /// the add or sub, and the third is the input carry flag. These nodes 212 /// produce two results; the normal result of the add or sub, and the output 213 /// carry flag. These nodes both read and write a carry flag to allow them 214 /// to them to be chained together for add and sub of arbitrarily large 215 /// values. 216 ADDE, SUBE, 217 218 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 219 /// These nodes take two operands: the normal LHS and RHS to the add. They 220 /// produce two results: the normal result of the add, and a boolean that 221 /// indicates if an overflow occurred (*not* a flag, because it may be store 222 /// to memory, etc.). If the type of the boolean is not i1 then the high 223 /// bits conform to getBooleanContents. 224 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 225 SADDO, UADDO, 226 227 /// Same for subtraction. 228 SSUBO, USUBO, 229 230 /// Same for multiplication. 231 SMULO, UMULO, 232 233 /// Simple binary floating point operators. 234 FADD, FSUB, FMUL, FMA, FDIV, FREM, 235 236 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 237 /// DAG node does not require that X and Y have the same type, just that the 238 /// are both floating point. X and the result must have the same type. 239 /// FCOPYSIGN(f32, f64) is allowed. 240 FCOPYSIGN, 241 242 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 243 /// value as an integer 0/1 value. 244 FGETSIGN, 245 246 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 247 /// specified, possibly variable, elements. The number of elements is 248 /// required to be a power of two. The types of the operands must all be 249 /// the same and must match the vector element type, except that integer 250 /// types are allowed to be larger than the element type, in which case 251 /// the operands are implicitly truncated. 252 BUILD_VECTOR, 253 254 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 255 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 256 /// element type then VAL is truncated before replacement. 257 INSERT_VECTOR_ELT, 258 259 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 260 /// identified by the (potentially variable) element number IDX. If the 261 /// return type is an integer type larger than the element type of the 262 /// vector, the result is extended to the width of the return type. 263 EXTRACT_VECTOR_ELT, 264 265 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 266 /// vector type with the same length and element type, this produces a 267 /// concatenated vector result value, with length equal to the sum of the 268 /// lengths of the input vectors. 269 CONCAT_VECTORS, 270 271 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 272 /// with VECTOR2 inserted into VECTOR1 at the (potentially 273 /// variable) element number IDX, which must be a multiple of the 274 /// VECTOR2 vector length. The elements of VECTOR1 starting at 275 /// IDX are overwritten with VECTOR2. Elements IDX through 276 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 277 INSERT_SUBVECTOR, 278 279 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 280 /// vector value) starting with the element number IDX, which must be a 281 /// constant multiple of the result vector length. 282 EXTRACT_SUBVECTOR, 283 284 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 285 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 286 /// values that indicate which value (or undef) each result element will 287 /// get. These constant ints are accessible through the 288 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 289 /// 'vperm' instruction, except that the indices must be constants and are 290 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 291 VECTOR_SHUFFLE, 292 293 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 294 /// scalar value into element 0 of the resultant vector type. The top 295 /// elements 1 to N-1 of the N-element vector are undefined. The type 296 /// of the operand must match the vector element type, except when they 297 /// are integer types. In this case the operand is allowed to be wider 298 /// than the vector element type, and is implicitly truncated to it. 299 SCALAR_TO_VECTOR, 300 301 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 302 /// producing an unsigned/signed value of type i[2*N], then return the top 303 /// part. 304 MULHU, MULHS, 305 306 /// Bitwise operators - logical and, logical or, logical xor. 307 AND, OR, XOR, 308 309 /// Shift and rotation operations. After legalization, the type of the 310 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 311 /// the shift amount can be any type, but care must be taken to ensure it is 312 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 313 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 314 /// to represent the shift amount. By convention, DAGCombine and 315 /// SelectionDAGBuilder forces these shift amounts to i32 for simplicity. 316 SHL, SRA, SRL, ROTL, ROTR, 317 318 /// Byte Swap and Counting operators. 319 BSWAP, CTTZ, CTLZ, CTPOP, 320 321 /// Bit counting operators with an undefined result for zero inputs. 322 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 323 324 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 325 /// i1 then the high bits must conform to getBooleanContents. 326 SELECT, 327 328 /// Select with a vector condition (op #0) and two vector operands (ops #1 329 /// and #2), returning a vector result. All vectors have the same length. 330 /// Much like the scalar select and setcc, each bit in the condition selects 331 /// whether the corresponding result element is taken from op #1 or op #2. 332 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 333 /// change the condition type in order to match the VSELECT node using a 334 /// pattern. The condition follows the BooleanContent format of the target. 335 VSELECT, 336 337 /// Select with condition operator - This selects between a true value and 338 /// a false value (ops #2 and #3) based on the boolean result of comparing 339 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 340 /// condition code in op #4, a CondCodeSDNode. 341 SELECT_CC, 342 343 /// SetCC operator - This evaluates to a true value iff the condition is 344 /// true. If the result value type is not i1 then the high bits conform 345 /// to getBooleanContents. The operands to this are the left and right 346 /// operands to compare (ops #0, and #1) and the condition code to compare 347 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 348 /// then the result type must also be a vector type. 349 SETCC, 350 351 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 352 /// integer shift operations, just like ADD/SUB_PARTS. The operation 353 /// ordering is: 354 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 355 SHL_PARTS, SRA_PARTS, SRL_PARTS, 356 357 /// Conversion operators. These are all single input single output 358 /// operations. For all of these, the result type must be strictly 359 /// wider or narrower (depending on the operation) than the source 360 /// type. 361 362 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 363 /// into new bits. 364 SIGN_EXTEND, 365 366 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 367 ZERO_EXTEND, 368 369 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 370 ANY_EXTEND, 371 372 /// TRUNCATE - Completely drop the high bits. 373 TRUNCATE, 374 375 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 376 /// depends on the first letter) to floating point. 377 SINT_TO_FP, 378 UINT_TO_FP, 379 380 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 381 /// sign extend a small value in a large integer register (e.g. sign 382 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 383 /// with the 7th bit). The size of the smaller type is indicated by the 1th 384 /// operand, a ValueType node. 385 SIGN_EXTEND_INREG, 386 387 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 388 /// integer. 389 FP_TO_SINT, 390 FP_TO_UINT, 391 392 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 393 /// down to the precision of the destination VT. TRUNC is a flag, which is 394 /// always an integer that is zero or one. If TRUNC is 0, this is a 395 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 396 /// value of Y. 397 /// 398 /// The TRUNC = 1 case is used in cases where we know that the value will 399 /// not be modified by the node, because Y is not using any of the extra 400 /// precision of source type. This allows certain transformations like 401 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 402 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 403 FP_ROUND, 404 405 /// FLT_ROUNDS_ - Returns current rounding mode: 406 /// -1 Undefined 407 /// 0 Round to 0 408 /// 1 Round to nearest 409 /// 2 Round to +inf 410 /// 3 Round to -inf 411 FLT_ROUNDS_, 412 413 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 414 /// rounds it to a floating point value. It then promotes it and returns it 415 /// in a register of the same size. This operation effectively just 416 /// discards excess precision. The type to round down to is specified by 417 /// the VT operand, a VTSDNode. 418 FP_ROUND_INREG, 419 420 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 421 FP_EXTEND, 422 423 /// BITCAST - This operator converts between integer, vector and FP 424 /// values, as if the value was stored to memory with one type and loaded 425 /// from the same address with the other type (or equivalently for vector 426 /// format conversions, etc). The source and result are required to have 427 /// the same bit size (e.g. f32 <-> i32). This can also be used for 428 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 429 /// getNode(). 430 BITCAST, 431 432 /// CONVERT_RNDSAT - This operator is used to support various conversions 433 /// between various types (float, signed, unsigned and vectors of those 434 /// types) with rounding and saturation. NOTE: Avoid using this operator as 435 /// most target don't support it and the operator might be removed in the 436 /// future. It takes the following arguments: 437 /// 0) value 438 /// 1) dest type (type to convert to) 439 /// 2) src type (type to convert from) 440 /// 3) rounding imm 441 /// 4) saturation imm 442 /// 5) ISD::CvtCode indicating the type of conversion to do 443 CONVERT_RNDSAT, 444 445 /// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform 446 /// promotions and truncation for half-precision (16 bit) floating 447 /// numbers. We need special nodes since FP16 is a storage-only type with 448 /// special semantics of operations. 449 FP16_TO_FP32, FP32_TO_FP16, 450 451 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 452 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 453 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary 454 /// floating point operations. These are inspired by libm. 455 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 456 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 457 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, 458 459 /// LOAD and STORE have token chains as their first operand, then the same 460 /// operands as an LLVM load/store instruction, then an offset node that 461 /// is added / subtracted from the base pointer to form the address (for 462 /// indexed memory ops). 463 LOAD, STORE, 464 465 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 466 /// to a specified boundary. This node always has two return values: a new 467 /// stack pointer value and a chain. The first operand is the token chain, 468 /// the second is the number of bytes to allocate, and the third is the 469 /// alignment boundary. The size is guaranteed to be a multiple of the 470 /// stack alignment, and the alignment is guaranteed to be bigger than the 471 /// stack alignment (if required) or 0 to get standard stack alignment. 472 DYNAMIC_STACKALLOC, 473 474 /// Control flow instructions. These all have token chains. 475 476 /// BR - Unconditional branch. The first operand is the chain 477 /// operand, the second is the MBB to branch to. 478 BR, 479 480 /// BRIND - Indirect branch. The first operand is the chain, the second 481 /// is the value to branch to, which must be of the same type as the 482 /// target's pointer type. 483 BRIND, 484 485 /// BR_JT - Jumptable branch. The first operand is the chain, the second 486 /// is the jumptable index, the last one is the jumptable entry index. 487 BR_JT, 488 489 /// BRCOND - Conditional branch. The first operand is the chain, the 490 /// second is the condition, the third is the block to branch to if the 491 /// condition is true. If the type of the condition is not i1, then the 492 /// high bits must conform to getBooleanContents. 493 BRCOND, 494 495 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 496 /// that the condition is represented as condition code, and two nodes to 497 /// compare, rather than as a combined SetCC node. The operands in order 498 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 499 BR_CC, 500 501 /// INLINEASM - Represents an inline asm block. This node always has two 502 /// return values: a chain and a flag result. The inputs are as follows: 503 /// Operand #0 : Input chain. 504 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 505 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 506 /// Operand #3 : HasSideEffect, IsAlignStack bits. 507 /// After this, it is followed by a list of operands with this format: 508 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 509 /// of operands that follow, etc. See InlineAsm.h. 510 /// ... however many operands ... 511 /// Operand #last: Optional, an incoming flag. 512 /// 513 /// The variable width operands are required to represent target addressing 514 /// modes as a single "operand", even though they may have multiple 515 /// SDOperands. 516 INLINEASM, 517 518 /// EH_LABEL - Represents a label in mid basic block used to track 519 /// locations needed for debug and exception handling tables. These nodes 520 /// take a chain as input and return a chain. 521 EH_LABEL, 522 523 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 524 /// value, the same type as the pointer type for the system, and an output 525 /// chain. 526 STACKSAVE, 527 528 /// STACKRESTORE has two operands, an input chain and a pointer to restore 529 /// to it returns an output chain. 530 STACKRESTORE, 531 532 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 533 /// of a call sequence, and carry arbitrary information that target might 534 /// want to know. The first operand is a chain, the rest are specified by 535 /// the target and not touched by the DAG optimizers. 536 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 537 CALLSEQ_START, // Beginning of a call sequence 538 CALLSEQ_END, // End of a call sequence 539 540 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 541 /// and the alignment. It returns a pair of values: the vaarg value and a 542 /// new chain. 543 VAARG, 544 545 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 546 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 547 /// source. 548 VACOPY, 549 550 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 551 /// pointer, and a SRCVALUE. 552 VAEND, VASTART, 553 554 /// SRCVALUE - This is a node type that holds a Value* that is used to 555 /// make reference to a value in the LLVM IR. 556 SRCVALUE, 557 558 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 559 /// reference metadata in the IR. 560 MDNODE_SDNODE, 561 562 /// PCMARKER - This corresponds to the pcmarker intrinsic. 563 PCMARKER, 564 565 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 566 /// The only operand is a chain and a value and a chain are produced. The 567 /// value is the contents of the architecture specific cycle counter like 568 /// register (or other high accuracy low latency clock source) 569 READCYCLECOUNTER, 570 571 /// HANDLENODE node - Used as a handle for various purposes. 572 HANDLENODE, 573 574 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 575 /// takes as input a token chain, the pointer to the trampoline, the pointer 576 /// to the nested function, the pointer to pass for the 'nest' parameter, a 577 /// SRCVALUE for the trampoline and another for the nested function 578 /// (allowing targets to access the original Function*). 579 /// It produces a token chain as output. 580 INIT_TRAMPOLINE, 581 582 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 583 /// It takes a pointer to the trampoline and produces a (possibly) new 584 /// pointer to the same trampoline with platform-specific adjustments 585 /// applied. The pointer it returns points to an executable block of code. 586 ADJUST_TRAMPOLINE, 587 588 /// TRAP - Trapping instruction 589 TRAP, 590 591 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 592 DEBUGTRAP, 593 594 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 595 /// is the chain. The other operands are the address to prefetch, 596 /// read / write specifier, locality specifier and instruction / data cache 597 /// specifier. 598 PREFETCH, 599 600 /// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, 601 /// store-store, device) 602 /// This corresponds to the memory.barrier intrinsic. 603 /// it takes an input chain, 4 operands to specify the type of barrier, an 604 /// operand specifying if the barrier applies to device and uncached memory 605 /// and produces an output chain. 606 MEMBARRIER, 607 608 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 609 /// This corresponds to the fence instruction. It takes an input chain, and 610 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 611 ATOMIC_FENCE, 612 613 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 614 /// This corresponds to "load atomic" instruction. 615 ATOMIC_LOAD, 616 617 /// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) 618 /// This corresponds to "store atomic" instruction. 619 ATOMIC_STORE, 620 621 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 622 /// This corresponds to the cmpxchg instruction. 623 ATOMIC_CMP_SWAP, 624 625 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 626 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 627 /// These correspond to the atomicrmw instruction. 628 ATOMIC_SWAP, 629 ATOMIC_LOAD_ADD, 630 ATOMIC_LOAD_SUB, 631 ATOMIC_LOAD_AND, 632 ATOMIC_LOAD_OR, 633 ATOMIC_LOAD_XOR, 634 ATOMIC_LOAD_NAND, 635 ATOMIC_LOAD_MIN, 636 ATOMIC_LOAD_MAX, 637 ATOMIC_LOAD_UMIN, 638 ATOMIC_LOAD_UMAX, 639 640 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 641 /// is the chain and the second operand is the alloca pointer. 642 LIFETIME_START, LIFETIME_END, 643 644 /// BUILTIN_OP_END - This must be the last enum value in this list. 645 /// The target-specific pre-isel opcode values start here. 646 BUILTIN_OP_END 647 }; 648 649 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 650 /// which do not reference a specific memory location should be less than 651 /// this value. Those that do must not be less than this value, and can 652 /// be used with SelectionDAG::getMemIntrinsicNode. 653 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150; 654 655 //===--------------------------------------------------------------------===// 656 /// MemIndexedMode enum - This enum defines the load / store indexed 657 /// addressing modes. 658 /// 659 /// UNINDEXED "Normal" load / store. The effective address is already 660 /// computed and is available in the base pointer. The offset 661 /// operand is always undefined. In addition to producing a 662 /// chain, an unindexed load produces one value (result of the 663 /// load); an unindexed store does not produce a value. 664 /// 665 /// PRE_INC Similar to the unindexed mode where the effective address is 666 /// PRE_DEC the value of the base pointer add / subtract the offset. 667 /// It considers the computation as being folded into the load / 668 /// store operation (i.e. the load / store does the address 669 /// computation as well as performing the memory transaction). 670 /// The base operand is always undefined. In addition to 671 /// producing a chain, pre-indexed load produces two values 672 /// (result of the load and the result of the address 673 /// computation); a pre-indexed store produces one value (result 674 /// of the address computation). 675 /// 676 /// POST_INC The effective address is the value of the base pointer. The 677 /// POST_DEC value of the offset operand is then added to / subtracted 678 /// from the base after memory transaction. In addition to 679 /// producing a chain, post-indexed load produces two values 680 /// (the result of the load and the result of the base +/- offset 681 /// computation); a post-indexed store produces one value (the 682 /// the result of the base +/- offset computation). 683 enum MemIndexedMode { 684 UNINDEXED = 0, 685 PRE_INC, 686 PRE_DEC, 687 POST_INC, 688 POST_DEC, 689 LAST_INDEXED_MODE 690 }; 691 692 //===--------------------------------------------------------------------===// 693 /// LoadExtType enum - This enum defines the three variants of LOADEXT 694 /// (load with extension). 695 /// 696 /// SEXTLOAD loads the integer operand and sign extends it to a larger 697 /// integer result type. 698 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 699 /// integer result type. 700 /// EXTLOAD is used for two things: floating point extending loads and 701 /// integer extending loads [the top bits are undefined]. 702 enum LoadExtType { 703 NON_EXTLOAD = 0, 704 EXTLOAD, 705 SEXTLOAD, 706 ZEXTLOAD, 707 LAST_LOADEXT_TYPE 708 }; 709 710 //===--------------------------------------------------------------------===// 711 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 712 /// below work out, when considering SETFALSE (something that never exists 713 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 714 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 715 /// to. If the "N" column is 1, the result of the comparison is undefined if 716 /// the input is a NAN. 717 /// 718 /// All of these (except for the 'always folded ops') should be handled for 719 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 720 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 721 /// 722 /// Note that these are laid out in a specific order to allow bit-twiddling 723 /// to transform conditions. 724 enum CondCode { 725 // Opcode N U L G E Intuitive operation 726 SETFALSE, // 0 0 0 0 Always false (always folded) 727 SETOEQ, // 0 0 0 1 True if ordered and equal 728 SETOGT, // 0 0 1 0 True if ordered and greater than 729 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 730 SETOLT, // 0 1 0 0 True if ordered and less than 731 SETOLE, // 0 1 0 1 True if ordered and less than or equal 732 SETONE, // 0 1 1 0 True if ordered and operands are unequal 733 SETO, // 0 1 1 1 True if ordered (no nans) 734 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 735 SETUEQ, // 1 0 0 1 True if unordered or equal 736 SETUGT, // 1 0 1 0 True if unordered or greater than 737 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 738 SETULT, // 1 1 0 0 True if unordered or less than 739 SETULE, // 1 1 0 1 True if unordered, less than, or equal 740 SETUNE, // 1 1 1 0 True if unordered or not equal 741 SETTRUE, // 1 1 1 1 Always true (always folded) 742 // Don't care operations: undefined if the input is a nan. 743 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 744 SETEQ, // 1 X 0 0 1 True if equal 745 SETGT, // 1 X 0 1 0 True if greater than 746 SETGE, // 1 X 0 1 1 True if greater than or equal 747 SETLT, // 1 X 1 0 0 True if less than 748 SETLE, // 1 X 1 0 1 True if less than or equal 749 SETNE, // 1 X 1 1 0 True if not equal 750 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 751 752 SETCC_INVALID // Marker value. 753 }; 754 755 /// isSignedIntSetCC - Return true if this is a setcc instruction that 756 /// performs a signed comparison when used with integer operands. 757 inline bool isSignedIntSetCC(CondCode Code) { 758 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 759 } 760 761 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 762 /// performs an unsigned comparison when used with integer operands. 763 inline bool isUnsignedIntSetCC(CondCode Code) { 764 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 765 } 766 767 /// isTrueWhenEqual - Return true if the specified condition returns true if 768 /// the two operands to the condition are equal. Note that if one of the two 769 /// operands is a NaN, this value is meaningless. 770 inline bool isTrueWhenEqual(CondCode Cond) { 771 return ((int)Cond & 1) != 0; 772 } 773 774 /// getUnorderedFlavor - This function returns 0 if the condition is always 775 /// false if an operand is a NaN, 1 if the condition is always true if the 776 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 777 /// NaN. 778 inline unsigned getUnorderedFlavor(CondCode Cond) { 779 return ((int)Cond >> 3) & 3; 780 } 781 782 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 783 /// 'op' is a valid SetCC operation. 784 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 785 786 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 787 /// when given the operation for (X op Y). 788 CondCode getSetCCSwappedOperands(CondCode Operation); 789 790 /// getSetCCOrOperation - Return the result of a logical OR between different 791 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 792 /// function returns SETCC_INVALID if it is not possible to represent the 793 /// resultant comparison. 794 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 795 796 /// getSetCCAndOperation - Return the result of a logical AND between 797 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 798 /// function returns SETCC_INVALID if it is not possible to represent the 799 /// resultant comparison. 800 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 801 802 //===--------------------------------------------------------------------===// 803 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 804 /// supports. 805 enum CvtCode { 806 CVT_FF, /// Float from Float 807 CVT_FS, /// Float from Signed 808 CVT_FU, /// Float from Unsigned 809 CVT_SF, /// Signed from Float 810 CVT_UF, /// Unsigned from Float 811 CVT_SS, /// Signed from Signed 812 CVT_SU, /// Signed from Unsigned 813 CVT_US, /// Unsigned from Signed 814 CVT_UU, /// Unsigned from Unsigned 815 CVT_INVALID /// Marker - Invalid opcode 816 }; 817 818 } // end llvm::ISD namespace 819 820 } // end llvm namespace 821 822 #endif 823
