1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "HexagonInstrInfo.h" 15 #include "HexagonRegisterInfo.h" 16 #include "HexagonSubtarget.h" 17 #include "Hexagon.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/DFAPacketizer.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineMemOperand.h" 25 #include "llvm/CodeGen/PseudoSourceValue.h" 26 #include "llvm/Support/MathExtras.h" 27 #define GET_INSTRINFO_CTOR 28 #include "HexagonGenInstrInfo.inc" 29 #include "HexagonGenDFAPacketizer.inc" 30 31 using namespace llvm; 32 33 /// 34 /// Constants for Hexagon instructions. 35 /// 36 const int Hexagon_MEMW_OFFSET_MAX = 4095; 37 const int Hexagon_MEMW_OFFSET_MIN = -4096; 38 const int Hexagon_MEMD_OFFSET_MAX = 8191; 39 const int Hexagon_MEMD_OFFSET_MIN = -8192; 40 const int Hexagon_MEMH_OFFSET_MAX = 2047; 41 const int Hexagon_MEMH_OFFSET_MIN = -2048; 42 const int Hexagon_MEMB_OFFSET_MAX = 1023; 43 const int Hexagon_MEMB_OFFSET_MIN = -1024; 44 const int Hexagon_ADDI_OFFSET_MAX = 32767; 45 const int Hexagon_ADDI_OFFSET_MIN = -32768; 46 const int Hexagon_MEMD_AUTOINC_MAX = 56; 47 const int Hexagon_MEMD_AUTOINC_MIN = -64; 48 const int Hexagon_MEMW_AUTOINC_MAX = 28; 49 const int Hexagon_MEMW_AUTOINC_MIN = -32; 50 const int Hexagon_MEMH_AUTOINC_MAX = 14; 51 const int Hexagon_MEMH_AUTOINC_MIN = -16; 52 const int Hexagon_MEMB_AUTOINC_MAX = 7; 53 const int Hexagon_MEMB_AUTOINC_MIN = -8; 54 55 56 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) 57 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), 58 RI(ST, *this), Subtarget(ST) { 59 } 60 61 62 /// isLoadFromStackSlot - If the specified machine instruction is a direct 63 /// load from a stack slot, return the virtual or physical register number of 64 /// the destination along with the FrameIndex of the loaded stack slot. If 65 /// not, return 0. This predicate must return 0 if the instruction has 66 /// any side effects other than loading from the stack slot. 67 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 68 int &FrameIndex) const { 69 70 71 switch (MI->getOpcode()) { 72 default: break; 73 case Hexagon::LDriw: 74 case Hexagon::LDrid: 75 case Hexagon::LDrih: 76 case Hexagon::LDrib: 77 case Hexagon::LDriub: 78 if (MI->getOperand(2).isFI() && 79 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 80 FrameIndex = MI->getOperand(2).getIndex(); 81 return MI->getOperand(0).getReg(); 82 } 83 break; 84 } 85 return 0; 86 } 87 88 89 /// isStoreToStackSlot - If the specified machine instruction is a direct 90 /// store to a stack slot, return the virtual or physical register number of 91 /// the source reg along with the FrameIndex of the loaded stack slot. If 92 /// not, return 0. This predicate must return 0 if the instruction has 93 /// any side effects other than storing to the stack slot. 94 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 95 int &FrameIndex) const { 96 switch (MI->getOpcode()) { 97 default: break; 98 case Hexagon::STriw: 99 case Hexagon::STrid: 100 case Hexagon::STrih: 101 case Hexagon::STrib: 102 if (MI->getOperand(2).isFI() && 103 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 104 FrameIndex = MI->getOperand(0).getIndex(); 105 return MI->getOperand(2).getReg(); 106 } 107 break; 108 } 109 return 0; 110 } 111 112 113 unsigned 114 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 115 MachineBasicBlock *FBB, 116 const SmallVectorImpl<MachineOperand> &Cond, 117 DebugLoc DL) const{ 118 119 int BOpc = Hexagon::JMP; 120 int BccOpc = Hexagon::JMP_c; 121 122 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 123 124 int regPos = 0; 125 // Check if ReverseBranchCondition has asked to reverse this branch 126 // If we want to reverse the branch an odd number of times, we want 127 // JMP_cNot. 128 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 129 BccOpc = Hexagon::JMP_cNot; 130 regPos = 1; 131 } 132 133 if (FBB == 0) { 134 if (Cond.empty()) { 135 // Due to a bug in TailMerging/CFG Optimization, we need to add a 136 // special case handling of a predicated jump followed by an 137 // unconditional jump. If not, Tail Merging and CFG Optimization go 138 // into an infinite loop. 139 MachineBasicBlock *NewTBB, *NewFBB; 140 SmallVector<MachineOperand, 4> Cond; 141 MachineInstr *Term = MBB.getFirstTerminator(); 142 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, 143 false)) { 144 MachineBasicBlock *NextBB = 145 llvm::next(MachineFunction::iterator(&MBB)); 146 if (NewTBB == NextBB) { 147 ReverseBranchCondition(Cond); 148 RemoveBranch(MBB); 149 return InsertBranch(MBB, TBB, 0, Cond, DL); 150 } 151 } 152 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 153 } else { 154 BuildMI(&MBB, DL, 155 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 156 } 157 return 1; 158 } 159 160 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 161 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 162 163 return 2; 164 } 165 166 167 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 168 MachineBasicBlock *&TBB, 169 MachineBasicBlock *&FBB, 170 SmallVectorImpl<MachineOperand> &Cond, 171 bool AllowModify) const { 172 TBB = NULL; 173 FBB = NULL; 174 175 // If the block has no terminators, it just falls into the block after it. 176 MachineBasicBlock::iterator I = MBB.end(); 177 if (I == MBB.begin()) 178 return false; 179 180 // A basic block may looks like this: 181 // 182 // [ insn 183 // EH_LABEL 184 // insn 185 // insn 186 // insn 187 // EH_LABEL 188 // insn ] 189 // 190 // It has two succs but does not have a terminator 191 // Don't know how to handle it. 192 do { 193 --I; 194 if (I->isEHLabel()) 195 return true; 196 } while (I != MBB.begin()); 197 198 I = MBB.end(); 199 --I; 200 201 while (I->isDebugValue()) { 202 if (I == MBB.begin()) 203 return false; 204 --I; 205 } 206 if (!isUnpredicatedTerminator(I)) 207 return false; 208 209 // Get the last instruction in the block. 210 MachineInstr *LastInst = I; 211 212 // If there is only one terminator instruction, process it. 213 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 214 if (LastInst->getOpcode() == Hexagon::JMP) { 215 TBB = LastInst->getOperand(0).getMBB(); 216 return false; 217 } 218 if (LastInst->getOpcode() == Hexagon::JMP_c) { 219 // Block ends with fall-through true condbranch. 220 TBB = LastInst->getOperand(1).getMBB(); 221 Cond.push_back(LastInst->getOperand(0)); 222 return false; 223 } 224 if (LastInst->getOpcode() == Hexagon::JMP_cNot) { 225 // Block ends with fall-through false condbranch. 226 TBB = LastInst->getOperand(1).getMBB(); 227 Cond.push_back(MachineOperand::CreateImm(0)); 228 Cond.push_back(LastInst->getOperand(0)); 229 return false; 230 } 231 // Otherwise, don't know what this is. 232 return true; 233 } 234 235 // Get the instruction before it if it's a terminator. 236 MachineInstr *SecondLastInst = I; 237 238 // If there are three terminators, we don't know what sort of block this is. 239 if (SecondLastInst && I != MBB.begin() && 240 isUnpredicatedTerminator(--I)) 241 return true; 242 243 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it. 244 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) || 245 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) && 246 LastInst->getOpcode() == Hexagon::JMP) { 247 TBB = SecondLastInst->getOperand(1).getMBB(); 248 Cond.push_back(SecondLastInst->getOperand(0)); 249 FBB = LastInst->getOperand(0).getMBB(); 250 return false; 251 } 252 253 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it. 254 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) && 255 LastInst->getOpcode() == Hexagon::JMP) { 256 TBB = SecondLastInst->getOperand(1).getMBB(); 257 Cond.push_back(MachineOperand::CreateImm(0)); 258 Cond.push_back(SecondLastInst->getOperand(0)); 259 FBB = LastInst->getOperand(0).getMBB(); 260 return false; 261 } 262 263 // If the block ends with two Hexagon:JMPs, handle it. The second one is not 264 // executed, so remove it. 265 if (SecondLastInst->getOpcode() == Hexagon::JMP && 266 LastInst->getOpcode() == Hexagon::JMP) { 267 TBB = SecondLastInst->getOperand(0).getMBB(); 268 I = LastInst; 269 if (AllowModify) 270 I->eraseFromParent(); 271 return false; 272 } 273 274 // Otherwise, can't handle this. 275 return true; 276 } 277 278 279 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 280 int BOpc = Hexagon::JMP; 281 int BccOpc = Hexagon::JMP_c; 282 int BccOpcNot = Hexagon::JMP_cNot; 283 284 MachineBasicBlock::iterator I = MBB.end(); 285 if (I == MBB.begin()) return 0; 286 --I; 287 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc && 288 I->getOpcode() != BccOpcNot) 289 return 0; 290 291 // Remove the branch. 292 I->eraseFromParent(); 293 294 I = MBB.end(); 295 296 if (I == MBB.begin()) return 1; 297 --I; 298 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot) 299 return 1; 300 301 // Remove the branch. 302 I->eraseFromParent(); 303 return 2; 304 } 305 306 307 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 308 MachineBasicBlock::iterator I, DebugLoc DL, 309 unsigned DestReg, unsigned SrcReg, 310 bool KillSrc) const { 311 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { 312 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); 313 return; 314 } 315 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { 316 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg); 317 return; 318 } 319 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { 320 // Map Pd = Ps to Pd = or(Ps, Ps). 321 BuildMI(MBB, I, DL, get(Hexagon::OR_pp), 322 DestReg).addReg(SrcReg).addReg(SrcReg); 323 return; 324 } 325 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && 326 Hexagon::IntRegsRegClass.contains(SrcReg)) { 327 // We can have an overlap between single and double reg: r1:0 = r0. 328 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 329 // r1:0 = r0 330 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 331 Hexagon::subreg_hireg))).addImm(0); 332 } else { 333 // r1:0 = r1 or no overlap. 334 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg, 335 Hexagon::subreg_loreg))).addReg(SrcReg); 336 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 337 Hexagon::subreg_hireg))).addImm(0); 338 } 339 return; 340 } 341 if (Hexagon::CRRegsRegClass.contains(DestReg) && 342 Hexagon::IntRegsRegClass.contains(SrcReg)) { 343 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); 344 return; 345 } 346 347 llvm_unreachable("Unimplemented"); 348 } 349 350 351 void HexagonInstrInfo:: 352 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 353 unsigned SrcReg, bool isKill, int FI, 354 const TargetRegisterClass *RC, 355 const TargetRegisterInfo *TRI) const { 356 357 DebugLoc DL = MBB.findDebugLoc(I); 358 MachineFunction &MF = *MBB.getParent(); 359 MachineFrameInfo &MFI = *MF.getFrameInfo(); 360 unsigned Align = MFI.getObjectAlignment(FI); 361 362 MachineMemOperand *MMO = 363 MF.getMachineMemOperand( 364 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 365 MachineMemOperand::MOStore, 366 MFI.getObjectSize(FI), 367 Align); 368 369 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 370 BuildMI(MBB, I, DL, get(Hexagon::STriw)) 371 .addFrameIndex(FI).addImm(0) 372 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 373 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 374 BuildMI(MBB, I, DL, get(Hexagon::STrid)) 375 .addFrameIndex(FI).addImm(0) 376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 377 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 378 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) 379 .addFrameIndex(FI).addImm(0) 380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 381 } else { 382 llvm_unreachable("Unimplemented"); 383 } 384 } 385 386 387 void HexagonInstrInfo::storeRegToAddr( 388 MachineFunction &MF, unsigned SrcReg, 389 bool isKill, 390 SmallVectorImpl<MachineOperand> &Addr, 391 const TargetRegisterClass *RC, 392 SmallVectorImpl<MachineInstr*> &NewMIs) const 393 { 394 llvm_unreachable("Unimplemented"); 395 } 396 397 398 void HexagonInstrInfo:: 399 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 400 unsigned DestReg, int FI, 401 const TargetRegisterClass *RC, 402 const TargetRegisterInfo *TRI) const { 403 DebugLoc DL = MBB.findDebugLoc(I); 404 MachineFunction &MF = *MBB.getParent(); 405 MachineFrameInfo &MFI = *MF.getFrameInfo(); 406 unsigned Align = MFI.getObjectAlignment(FI); 407 408 MachineMemOperand *MMO = 409 MF.getMachineMemOperand( 410 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 411 MachineMemOperand::MOLoad, 412 MFI.getObjectSize(FI), 413 Align); 414 if (RC == &Hexagon::IntRegsRegClass) { 415 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) 416 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 417 } else if (RC == &Hexagon::DoubleRegsRegClass) { 418 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) 419 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 420 } else if (RC == &Hexagon::PredRegsRegClass) { 421 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) 422 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 423 } else { 424 llvm_unreachable("Can't store this register to stack slot"); 425 } 426 } 427 428 429 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 430 SmallVectorImpl<MachineOperand> &Addr, 431 const TargetRegisterClass *RC, 432 SmallVectorImpl<MachineInstr*> &NewMIs) const { 433 llvm_unreachable("Unimplemented"); 434 } 435 436 437 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 438 MachineInstr* MI, 439 const SmallVectorImpl<unsigned> &Ops, 440 int FI) const { 441 // Hexagon_TODO: Implement. 442 return(0); 443 } 444 445 446 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { 447 448 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 449 const TargetRegisterClass *TRC; 450 if (VT == MVT::i1) { 451 TRC = &Hexagon::PredRegsRegClass; 452 } else if (VT == MVT::i32 || VT == MVT::f32) { 453 TRC = &Hexagon::IntRegsRegClass; 454 } else if (VT == MVT::i64 || VT == MVT::f64) { 455 TRC = &Hexagon::DoubleRegsRegClass; 456 } else { 457 llvm_unreachable("Cannot handle this register class"); 458 } 459 460 unsigned NewReg = RegInfo.createVirtualRegister(TRC); 461 return NewReg; 462 } 463 464 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { 465 switch(MI->getOpcode()) { 466 default: return false; 467 // JMP_EQri 468 case Hexagon::JMP_EQriPt_nv_V4: 469 case Hexagon::JMP_EQriPnt_nv_V4: 470 case Hexagon::JMP_EQriNotPt_nv_V4: 471 case Hexagon::JMP_EQriNotPnt_nv_V4: 472 473 // JMP_EQri - with -1 474 case Hexagon::JMP_EQriPtneg_nv_V4: 475 case Hexagon::JMP_EQriPntneg_nv_V4: 476 case Hexagon::JMP_EQriNotPtneg_nv_V4: 477 case Hexagon::JMP_EQriNotPntneg_nv_V4: 478 479 // JMP_EQrr 480 case Hexagon::JMP_EQrrPt_nv_V4: 481 case Hexagon::JMP_EQrrPnt_nv_V4: 482 case Hexagon::JMP_EQrrNotPt_nv_V4: 483 case Hexagon::JMP_EQrrNotPnt_nv_V4: 484 485 // JMP_GTri 486 case Hexagon::JMP_GTriPt_nv_V4: 487 case Hexagon::JMP_GTriPnt_nv_V4: 488 case Hexagon::JMP_GTriNotPt_nv_V4: 489 case Hexagon::JMP_GTriNotPnt_nv_V4: 490 491 // JMP_GTri - with -1 492 case Hexagon::JMP_GTriPtneg_nv_V4: 493 case Hexagon::JMP_GTriPntneg_nv_V4: 494 case Hexagon::JMP_GTriNotPtneg_nv_V4: 495 case Hexagon::JMP_GTriNotPntneg_nv_V4: 496 497 // JMP_GTrr 498 case Hexagon::JMP_GTrrPt_nv_V4: 499 case Hexagon::JMP_GTrrPnt_nv_V4: 500 case Hexagon::JMP_GTrrNotPt_nv_V4: 501 case Hexagon::JMP_GTrrNotPnt_nv_V4: 502 503 // JMP_GTrrdn 504 case Hexagon::JMP_GTrrdnPt_nv_V4: 505 case Hexagon::JMP_GTrrdnPnt_nv_V4: 506 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 507 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 508 509 // JMP_GTUri 510 case Hexagon::JMP_GTUriPt_nv_V4: 511 case Hexagon::JMP_GTUriPnt_nv_V4: 512 case Hexagon::JMP_GTUriNotPt_nv_V4: 513 case Hexagon::JMP_GTUriNotPnt_nv_V4: 514 515 // JMP_GTUrr 516 case Hexagon::JMP_GTUrrPt_nv_V4: 517 case Hexagon::JMP_GTUrrPnt_nv_V4: 518 case Hexagon::JMP_GTUrrNotPt_nv_V4: 519 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 520 521 // JMP_GTUrrdn 522 case Hexagon::JMP_GTUrrdnPt_nv_V4: 523 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 524 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 525 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 526 527 // TFR_FI 528 case Hexagon::TFR_FI: 529 return true; 530 } 531 } 532 533 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { 534 switch(MI->getOpcode()) { 535 default: return false; 536 // JMP_EQri 537 case Hexagon::JMP_EQriPt_ie_nv_V4: 538 case Hexagon::JMP_EQriPnt_ie_nv_V4: 539 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 540 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 541 542 // JMP_EQri - with -1 543 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 544 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 545 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 546 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 547 548 // JMP_EQrr 549 case Hexagon::JMP_EQrrPt_ie_nv_V4: 550 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 551 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 552 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 553 554 // JMP_GTri 555 case Hexagon::JMP_GTriPt_ie_nv_V4: 556 case Hexagon::JMP_GTriPnt_ie_nv_V4: 557 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 558 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 559 560 // JMP_GTri - with -1 561 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 562 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 563 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 564 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 565 566 // JMP_GTrr 567 case Hexagon::JMP_GTrrPt_ie_nv_V4: 568 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 569 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 570 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 571 572 // JMP_GTrrdn 573 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 574 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 575 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 576 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 577 578 // JMP_GTUri 579 case Hexagon::JMP_GTUriPt_ie_nv_V4: 580 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 581 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 582 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 583 584 // JMP_GTUrr 585 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 586 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 587 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 588 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 589 590 // JMP_GTUrrdn 591 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 592 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 593 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 594 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 595 596 // V4 absolute set addressing. 597 case Hexagon::LDrid_abs_setimm_V4: 598 case Hexagon::LDriw_abs_setimm_V4: 599 case Hexagon::LDrih_abs_setimm_V4: 600 case Hexagon::LDrib_abs_setimm_V4: 601 case Hexagon::LDriuh_abs_setimm_V4: 602 case Hexagon::LDriub_abs_setimm_V4: 603 604 case Hexagon::STrid_abs_setimm_V4: 605 case Hexagon::STrib_abs_setimm_V4: 606 case Hexagon::STrih_abs_setimm_V4: 607 case Hexagon::STriw_abs_setimm_V4: 608 609 // V4 global address load. 610 case Hexagon::LDrid_GP_cPt_V4 : 611 case Hexagon::LDrid_GP_cNotPt_V4 : 612 case Hexagon::LDrid_GP_cdnPt_V4 : 613 case Hexagon::LDrid_GP_cdnNotPt_V4 : 614 case Hexagon::LDrib_GP_cPt_V4 : 615 case Hexagon::LDrib_GP_cNotPt_V4 : 616 case Hexagon::LDrib_GP_cdnPt_V4 : 617 case Hexagon::LDrib_GP_cdnNotPt_V4 : 618 case Hexagon::LDriub_GP_cPt_V4 : 619 case Hexagon::LDriub_GP_cNotPt_V4 : 620 case Hexagon::LDriub_GP_cdnPt_V4 : 621 case Hexagon::LDriub_GP_cdnNotPt_V4 : 622 case Hexagon::LDrih_GP_cPt_V4 : 623 case Hexagon::LDrih_GP_cNotPt_V4 : 624 case Hexagon::LDrih_GP_cdnPt_V4 : 625 case Hexagon::LDrih_GP_cdnNotPt_V4 : 626 case Hexagon::LDriuh_GP_cPt_V4 : 627 case Hexagon::LDriuh_GP_cNotPt_V4 : 628 case Hexagon::LDriuh_GP_cdnPt_V4 : 629 case Hexagon::LDriuh_GP_cdnNotPt_V4 : 630 case Hexagon::LDriw_GP_cPt_V4 : 631 case Hexagon::LDriw_GP_cNotPt_V4 : 632 case Hexagon::LDriw_GP_cdnPt_V4 : 633 case Hexagon::LDriw_GP_cdnNotPt_V4 : 634 case Hexagon::LDd_GP_cPt_V4 : 635 case Hexagon::LDd_GP_cNotPt_V4 : 636 case Hexagon::LDd_GP_cdnPt_V4 : 637 case Hexagon::LDd_GP_cdnNotPt_V4 : 638 case Hexagon::LDb_GP_cPt_V4 : 639 case Hexagon::LDb_GP_cNotPt_V4 : 640 case Hexagon::LDb_GP_cdnPt_V4 : 641 case Hexagon::LDb_GP_cdnNotPt_V4 : 642 case Hexagon::LDub_GP_cPt_V4 : 643 case Hexagon::LDub_GP_cNotPt_V4 : 644 case Hexagon::LDub_GP_cdnPt_V4 : 645 case Hexagon::LDub_GP_cdnNotPt_V4 : 646 case Hexagon::LDh_GP_cPt_V4 : 647 case Hexagon::LDh_GP_cNotPt_V4 : 648 case Hexagon::LDh_GP_cdnPt_V4 : 649 case Hexagon::LDh_GP_cdnNotPt_V4 : 650 case Hexagon::LDuh_GP_cPt_V4 : 651 case Hexagon::LDuh_GP_cNotPt_V4 : 652 case Hexagon::LDuh_GP_cdnPt_V4 : 653 case Hexagon::LDuh_GP_cdnNotPt_V4 : 654 case Hexagon::LDw_GP_cPt_V4 : 655 case Hexagon::LDw_GP_cNotPt_V4 : 656 case Hexagon::LDw_GP_cdnPt_V4 : 657 case Hexagon::LDw_GP_cdnNotPt_V4 : 658 659 // V4 global address store. 660 case Hexagon::STrid_GP_cPt_V4 : 661 case Hexagon::STrid_GP_cNotPt_V4 : 662 case Hexagon::STrid_GP_cdnPt_V4 : 663 case Hexagon::STrid_GP_cdnNotPt_V4 : 664 case Hexagon::STrib_GP_cPt_V4 : 665 case Hexagon::STrib_GP_cNotPt_V4 : 666 case Hexagon::STrib_GP_cdnPt_V4 : 667 case Hexagon::STrib_GP_cdnNotPt_V4 : 668 case Hexagon::STrih_GP_cPt_V4 : 669 case Hexagon::STrih_GP_cNotPt_V4 : 670 case Hexagon::STrih_GP_cdnPt_V4 : 671 case Hexagon::STrih_GP_cdnNotPt_V4 : 672 case Hexagon::STriw_GP_cPt_V4 : 673 case Hexagon::STriw_GP_cNotPt_V4 : 674 case Hexagon::STriw_GP_cdnPt_V4 : 675 case Hexagon::STriw_GP_cdnNotPt_V4 : 676 case Hexagon::STd_GP_cPt_V4 : 677 case Hexagon::STd_GP_cNotPt_V4 : 678 case Hexagon::STd_GP_cdnPt_V4 : 679 case Hexagon::STd_GP_cdnNotPt_V4 : 680 case Hexagon::STb_GP_cPt_V4 : 681 case Hexagon::STb_GP_cNotPt_V4 : 682 case Hexagon::STb_GP_cdnPt_V4 : 683 case Hexagon::STb_GP_cdnNotPt_V4 : 684 case Hexagon::STh_GP_cPt_V4 : 685 case Hexagon::STh_GP_cNotPt_V4 : 686 case Hexagon::STh_GP_cdnPt_V4 : 687 case Hexagon::STh_GP_cdnNotPt_V4 : 688 case Hexagon::STw_GP_cPt_V4 : 689 case Hexagon::STw_GP_cNotPt_V4 : 690 case Hexagon::STw_GP_cdnPt_V4 : 691 case Hexagon::STw_GP_cdnNotPt_V4 : 692 693 // V4 predicated global address new value store. 694 case Hexagon::STrib_GP_cPt_nv_V4 : 695 case Hexagon::STrib_GP_cNotPt_nv_V4 : 696 case Hexagon::STrib_GP_cdnPt_nv_V4 : 697 case Hexagon::STrib_GP_cdnNotPt_nv_V4 : 698 case Hexagon::STrih_GP_cPt_nv_V4 : 699 case Hexagon::STrih_GP_cNotPt_nv_V4 : 700 case Hexagon::STrih_GP_cdnPt_nv_V4 : 701 case Hexagon::STrih_GP_cdnNotPt_nv_V4 : 702 case Hexagon::STriw_GP_cPt_nv_V4 : 703 case Hexagon::STriw_GP_cNotPt_nv_V4 : 704 case Hexagon::STriw_GP_cdnPt_nv_V4 : 705 case Hexagon::STriw_GP_cdnNotPt_nv_V4 : 706 case Hexagon::STb_GP_cPt_nv_V4 : 707 case Hexagon::STb_GP_cNotPt_nv_V4 : 708 case Hexagon::STb_GP_cdnPt_nv_V4 : 709 case Hexagon::STb_GP_cdnNotPt_nv_V4 : 710 case Hexagon::STh_GP_cPt_nv_V4 : 711 case Hexagon::STh_GP_cNotPt_nv_V4 : 712 case Hexagon::STh_GP_cdnPt_nv_V4 : 713 case Hexagon::STh_GP_cdnNotPt_nv_V4 : 714 case Hexagon::STw_GP_cPt_nv_V4 : 715 case Hexagon::STw_GP_cNotPt_nv_V4 : 716 case Hexagon::STw_GP_cdnPt_nv_V4 : 717 case Hexagon::STw_GP_cdnNotPt_nv_V4 : 718 719 // TFR_FI 720 case Hexagon::TFR_FI_immext_V4: 721 722 // TFRI_F 723 case Hexagon::TFRI_f: 724 case Hexagon::TFRI_cPt_f: 725 case Hexagon::TFRI_cNotPt_f: 726 case Hexagon::CONST64_Float_Real: 727 return true; 728 } 729 } 730 731 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { 732 switch (MI->getOpcode()) { 733 default: return false; 734 // JMP_EQri 735 case Hexagon::JMP_EQriPt_nv_V4: 736 case Hexagon::JMP_EQriPnt_nv_V4: 737 case Hexagon::JMP_EQriNotPt_nv_V4: 738 case Hexagon::JMP_EQriNotPnt_nv_V4: 739 case Hexagon::JMP_EQriPt_ie_nv_V4: 740 case Hexagon::JMP_EQriPnt_ie_nv_V4: 741 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 742 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 743 744 // JMP_EQri - with -1 745 case Hexagon::JMP_EQriPtneg_nv_V4: 746 case Hexagon::JMP_EQriPntneg_nv_V4: 747 case Hexagon::JMP_EQriNotPtneg_nv_V4: 748 case Hexagon::JMP_EQriNotPntneg_nv_V4: 749 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 750 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 751 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 752 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 753 754 // JMP_EQrr 755 case Hexagon::JMP_EQrrPt_nv_V4: 756 case Hexagon::JMP_EQrrPnt_nv_V4: 757 case Hexagon::JMP_EQrrNotPt_nv_V4: 758 case Hexagon::JMP_EQrrNotPnt_nv_V4: 759 case Hexagon::JMP_EQrrPt_ie_nv_V4: 760 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 761 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 762 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 763 764 // JMP_GTri 765 case Hexagon::JMP_GTriPt_nv_V4: 766 case Hexagon::JMP_GTriPnt_nv_V4: 767 case Hexagon::JMP_GTriNotPt_nv_V4: 768 case Hexagon::JMP_GTriNotPnt_nv_V4: 769 case Hexagon::JMP_GTriPt_ie_nv_V4: 770 case Hexagon::JMP_GTriPnt_ie_nv_V4: 771 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 772 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 773 774 // JMP_GTri - with -1 775 case Hexagon::JMP_GTriPtneg_nv_V4: 776 case Hexagon::JMP_GTriPntneg_nv_V4: 777 case Hexagon::JMP_GTriNotPtneg_nv_V4: 778 case Hexagon::JMP_GTriNotPntneg_nv_V4: 779 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 780 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 781 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 782 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 783 784 // JMP_GTrr 785 case Hexagon::JMP_GTrrPt_nv_V4: 786 case Hexagon::JMP_GTrrPnt_nv_V4: 787 case Hexagon::JMP_GTrrNotPt_nv_V4: 788 case Hexagon::JMP_GTrrNotPnt_nv_V4: 789 case Hexagon::JMP_GTrrPt_ie_nv_V4: 790 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 791 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 792 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 793 794 // JMP_GTrrdn 795 case Hexagon::JMP_GTrrdnPt_nv_V4: 796 case Hexagon::JMP_GTrrdnPnt_nv_V4: 797 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 798 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 799 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 800 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 801 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 802 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 803 804 // JMP_GTUri 805 case Hexagon::JMP_GTUriPt_nv_V4: 806 case Hexagon::JMP_GTUriPnt_nv_V4: 807 case Hexagon::JMP_GTUriNotPt_nv_V4: 808 case Hexagon::JMP_GTUriNotPnt_nv_V4: 809 case Hexagon::JMP_GTUriPt_ie_nv_V4: 810 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 811 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 812 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 813 814 // JMP_GTUrr 815 case Hexagon::JMP_GTUrrPt_nv_V4: 816 case Hexagon::JMP_GTUrrPnt_nv_V4: 817 case Hexagon::JMP_GTUrrNotPt_nv_V4: 818 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 819 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 820 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 821 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 822 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 823 824 // JMP_GTUrrdn 825 case Hexagon::JMP_GTUrrdnPt_nv_V4: 826 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 827 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 828 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 829 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 830 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 831 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 832 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 833 return true; 834 } 835 } 836 837 unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const { 838 switch(MI->getOpcode()) { 839 default: llvm_unreachable("Unknown type of instruction."); 840 // JMP_EQri 841 case Hexagon::JMP_EQriPt_nv_V4: 842 return Hexagon::JMP_EQriPt_ie_nv_V4; 843 case Hexagon::JMP_EQriNotPt_nv_V4: 844 return Hexagon::JMP_EQriNotPt_ie_nv_V4; 845 case Hexagon::JMP_EQriPnt_nv_V4: 846 return Hexagon::JMP_EQriPnt_ie_nv_V4; 847 case Hexagon::JMP_EQriNotPnt_nv_V4: 848 return Hexagon::JMP_EQriNotPnt_ie_nv_V4; 849 850 // JMP_EQri -- with -1 851 case Hexagon::JMP_EQriPtneg_nv_V4: 852 return Hexagon::JMP_EQriPtneg_ie_nv_V4; 853 case Hexagon::JMP_EQriNotPtneg_nv_V4: 854 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4; 855 case Hexagon::JMP_EQriPntneg_nv_V4: 856 return Hexagon::JMP_EQriPntneg_ie_nv_V4; 857 case Hexagon::JMP_EQriNotPntneg_nv_V4: 858 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4; 859 860 // JMP_EQrr 861 case Hexagon::JMP_EQrrPt_nv_V4: 862 return Hexagon::JMP_EQrrPt_ie_nv_V4; 863 case Hexagon::JMP_EQrrNotPt_nv_V4: 864 return Hexagon::JMP_EQrrNotPt_ie_nv_V4; 865 case Hexagon::JMP_EQrrPnt_nv_V4: 866 return Hexagon::JMP_EQrrPnt_ie_nv_V4; 867 case Hexagon::JMP_EQrrNotPnt_nv_V4: 868 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4; 869 870 // JMP_GTri 871 case Hexagon::JMP_GTriPt_nv_V4: 872 return Hexagon::JMP_GTriPt_ie_nv_V4; 873 case Hexagon::JMP_GTriNotPt_nv_V4: 874 return Hexagon::JMP_GTriNotPt_ie_nv_V4; 875 case Hexagon::JMP_GTriPnt_nv_V4: 876 return Hexagon::JMP_GTriPnt_ie_nv_V4; 877 case Hexagon::JMP_GTriNotPnt_nv_V4: 878 return Hexagon::JMP_GTriNotPnt_ie_nv_V4; 879 880 // JMP_GTri -- with -1 881 case Hexagon::JMP_GTriPtneg_nv_V4: 882 return Hexagon::JMP_GTriPtneg_ie_nv_V4; 883 case Hexagon::JMP_GTriNotPtneg_nv_V4: 884 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4; 885 case Hexagon::JMP_GTriPntneg_nv_V4: 886 return Hexagon::JMP_GTriPntneg_ie_nv_V4; 887 case Hexagon::JMP_GTriNotPntneg_nv_V4: 888 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4; 889 890 // JMP_GTrr 891 case Hexagon::JMP_GTrrPt_nv_V4: 892 return Hexagon::JMP_GTrrPt_ie_nv_V4; 893 case Hexagon::JMP_GTrrNotPt_nv_V4: 894 return Hexagon::JMP_GTrrNotPt_ie_nv_V4; 895 case Hexagon::JMP_GTrrPnt_nv_V4: 896 return Hexagon::JMP_GTrrPnt_ie_nv_V4; 897 case Hexagon::JMP_GTrrNotPnt_nv_V4: 898 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4; 899 900 // JMP_GTrrdn 901 case Hexagon::JMP_GTrrdnPt_nv_V4: 902 return Hexagon::JMP_GTrrdnPt_ie_nv_V4; 903 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 904 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4; 905 case Hexagon::JMP_GTrrdnPnt_nv_V4: 906 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4; 907 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 908 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4; 909 910 // JMP_GTUri 911 case Hexagon::JMP_GTUriPt_nv_V4: 912 return Hexagon::JMP_GTUriPt_ie_nv_V4; 913 case Hexagon::JMP_GTUriNotPt_nv_V4: 914 return Hexagon::JMP_GTUriNotPt_ie_nv_V4; 915 case Hexagon::JMP_GTUriPnt_nv_V4: 916 return Hexagon::JMP_GTUriPnt_ie_nv_V4; 917 case Hexagon::JMP_GTUriNotPnt_nv_V4: 918 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4; 919 920 // JMP_GTUrr 921 case Hexagon::JMP_GTUrrPt_nv_V4: 922 return Hexagon::JMP_GTUrrPt_ie_nv_V4; 923 case Hexagon::JMP_GTUrrNotPt_nv_V4: 924 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4; 925 case Hexagon::JMP_GTUrrPnt_nv_V4: 926 return Hexagon::JMP_GTUrrPnt_ie_nv_V4; 927 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 928 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4; 929 930 // JMP_GTUrrdn 931 case Hexagon::JMP_GTUrrdnPt_nv_V4: 932 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4; 933 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 934 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4; 935 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 936 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4; 937 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 938 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4; 939 940 case Hexagon::TFR_FI: 941 return Hexagon::TFR_FI_immext_V4; 942 943 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 944 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 945 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 946 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 947 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 948 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 949 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 950 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 951 case Hexagon::MEMw_ADDi_MEM_V4 : 952 case Hexagon::MEMw_SUBi_MEM_V4 : 953 case Hexagon::MEMw_ADDr_MEM_V4 : 954 case Hexagon::MEMw_SUBr_MEM_V4 : 955 case Hexagon::MEMw_ANDr_MEM_V4 : 956 case Hexagon::MEMw_ORr_MEM_V4 : 957 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 958 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 959 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 960 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 961 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 962 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 963 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 964 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 965 case Hexagon::MEMh_ADDi_MEM_V4 : 966 case Hexagon::MEMh_SUBi_MEM_V4 : 967 case Hexagon::MEMh_ADDr_MEM_V4 : 968 case Hexagon::MEMh_SUBr_MEM_V4 : 969 case Hexagon::MEMh_ANDr_MEM_V4 : 970 case Hexagon::MEMh_ORr_MEM_V4 : 971 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 972 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 973 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 974 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 975 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 976 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 977 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 978 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 979 case Hexagon::MEMb_ADDi_MEM_V4 : 980 case Hexagon::MEMb_SUBi_MEM_V4 : 981 case Hexagon::MEMb_ADDr_MEM_V4 : 982 case Hexagon::MEMb_SUBr_MEM_V4 : 983 case Hexagon::MEMb_ANDr_MEM_V4 : 984 case Hexagon::MEMb_ORr_MEM_V4 : 985 llvm_unreachable("Needs implementing."); 986 } 987 } 988 989 unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const { 990 switch(MI->getOpcode()) { 991 default: llvm_unreachable("Unknown type of jump instruction."); 992 // JMP_EQri 993 case Hexagon::JMP_EQriPt_ie_nv_V4: 994 return Hexagon::JMP_EQriPt_nv_V4; 995 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 996 return Hexagon::JMP_EQriNotPt_nv_V4; 997 case Hexagon::JMP_EQriPnt_ie_nv_V4: 998 return Hexagon::JMP_EQriPnt_nv_V4; 999 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 1000 return Hexagon::JMP_EQriNotPnt_nv_V4; 1001 1002 // JMP_EQri -- with -1 1003 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 1004 return Hexagon::JMP_EQriPtneg_nv_V4; 1005 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 1006 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1007 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 1008 return Hexagon::JMP_EQriPntneg_nv_V4; 1009 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 1010 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1011 1012 // JMP_EQrr 1013 case Hexagon::JMP_EQrrPt_ie_nv_V4: 1014 return Hexagon::JMP_EQrrPt_nv_V4; 1015 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 1016 return Hexagon::JMP_EQrrNotPt_nv_V4; 1017 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 1018 return Hexagon::JMP_EQrrPnt_nv_V4; 1019 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 1020 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1021 1022 // JMP_GTri 1023 case Hexagon::JMP_GTriPt_ie_nv_V4: 1024 return Hexagon::JMP_GTriPt_nv_V4; 1025 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 1026 return Hexagon::JMP_GTriNotPt_nv_V4; 1027 case Hexagon::JMP_GTriPnt_ie_nv_V4: 1028 return Hexagon::JMP_GTriPnt_nv_V4; 1029 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 1030 return Hexagon::JMP_GTriNotPnt_nv_V4; 1031 1032 // JMP_GTri -- with -1 1033 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 1034 return Hexagon::JMP_GTriPtneg_nv_V4; 1035 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 1036 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1037 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 1038 return Hexagon::JMP_GTriPntneg_nv_V4; 1039 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 1040 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1041 1042 // JMP_GTrr 1043 case Hexagon::JMP_GTrrPt_ie_nv_V4: 1044 return Hexagon::JMP_GTrrPt_nv_V4; 1045 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 1046 return Hexagon::JMP_GTrrNotPt_nv_V4; 1047 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 1048 return Hexagon::JMP_GTrrPnt_nv_V4; 1049 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 1050 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1051 1052 // JMP_GTrrdn 1053 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 1054 return Hexagon::JMP_GTrrdnPt_nv_V4; 1055 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 1056 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1057 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 1058 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1059 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 1060 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1061 1062 // JMP_GTUri 1063 case Hexagon::JMP_GTUriPt_ie_nv_V4: 1064 return Hexagon::JMP_GTUriPt_nv_V4; 1065 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 1066 return Hexagon::JMP_GTUriNotPt_nv_V4; 1067 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 1068 return Hexagon::JMP_GTUriPnt_nv_V4; 1069 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 1070 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1071 1072 // JMP_GTUrr 1073 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 1074 return Hexagon::JMP_GTUrrPt_nv_V4; 1075 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 1076 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1077 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 1078 return Hexagon::JMP_GTUrrPnt_nv_V4; 1079 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 1080 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1081 1082 // JMP_GTUrrdn 1083 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 1084 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1085 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 1086 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1087 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 1088 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1089 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 1090 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1091 } 1092 } 1093 1094 1095 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { 1096 switch (MI->getOpcode()) { 1097 default: return false; 1098 // Store Byte 1099 case Hexagon::STrib_nv_V4: 1100 case Hexagon::STrib_indexed_nv_V4: 1101 case Hexagon::STrib_indexed_shl_nv_V4: 1102 case Hexagon::STrib_shl_nv_V4: 1103 case Hexagon::STrib_GP_nv_V4: 1104 case Hexagon::STb_GP_nv_V4: 1105 case Hexagon::POST_STbri_nv_V4: 1106 case Hexagon::STrib_cPt_nv_V4: 1107 case Hexagon::STrib_cdnPt_nv_V4: 1108 case Hexagon::STrib_cNotPt_nv_V4: 1109 case Hexagon::STrib_cdnNotPt_nv_V4: 1110 case Hexagon::STrib_indexed_cPt_nv_V4: 1111 case Hexagon::STrib_indexed_cdnPt_nv_V4: 1112 case Hexagon::STrib_indexed_cNotPt_nv_V4: 1113 case Hexagon::STrib_indexed_cdnNotPt_nv_V4: 1114 case Hexagon::STrib_indexed_shl_cPt_nv_V4: 1115 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4: 1116 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4: 1117 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4: 1118 case Hexagon::POST_STbri_cPt_nv_V4: 1119 case Hexagon::POST_STbri_cdnPt_nv_V4: 1120 case Hexagon::POST_STbri_cNotPt_nv_V4: 1121 case Hexagon::POST_STbri_cdnNotPt_nv_V4: 1122 case Hexagon::STb_GP_cPt_nv_V4: 1123 case Hexagon::STb_GP_cNotPt_nv_V4: 1124 case Hexagon::STb_GP_cdnPt_nv_V4: 1125 case Hexagon::STb_GP_cdnNotPt_nv_V4: 1126 case Hexagon::STrib_GP_cPt_nv_V4: 1127 case Hexagon::STrib_GP_cNotPt_nv_V4: 1128 case Hexagon::STrib_GP_cdnPt_nv_V4: 1129 case Hexagon::STrib_GP_cdnNotPt_nv_V4: 1130 case Hexagon::STrib_abs_nv_V4: 1131 case Hexagon::STrib_abs_cPt_nv_V4: 1132 case Hexagon::STrib_abs_cdnPt_nv_V4: 1133 case Hexagon::STrib_abs_cNotPt_nv_V4: 1134 case Hexagon::STrib_abs_cdnNotPt_nv_V4: 1135 case Hexagon::STrib_imm_abs_nv_V4: 1136 case Hexagon::STrib_imm_abs_cPt_nv_V4: 1137 case Hexagon::STrib_imm_abs_cdnPt_nv_V4: 1138 case Hexagon::STrib_imm_abs_cNotPt_nv_V4: 1139 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4: 1140 1141 // Store Halfword 1142 case Hexagon::STrih_nv_V4: 1143 case Hexagon::STrih_indexed_nv_V4: 1144 case Hexagon::STrih_indexed_shl_nv_V4: 1145 case Hexagon::STrih_shl_nv_V4: 1146 case Hexagon::STrih_GP_nv_V4: 1147 case Hexagon::STh_GP_nv_V4: 1148 case Hexagon::POST_SThri_nv_V4: 1149 case Hexagon::STrih_cPt_nv_V4: 1150 case Hexagon::STrih_cdnPt_nv_V4: 1151 case Hexagon::STrih_cNotPt_nv_V4: 1152 case Hexagon::STrih_cdnNotPt_nv_V4: 1153 case Hexagon::STrih_indexed_cPt_nv_V4: 1154 case Hexagon::STrih_indexed_cdnPt_nv_V4: 1155 case Hexagon::STrih_indexed_cNotPt_nv_V4: 1156 case Hexagon::STrih_indexed_cdnNotPt_nv_V4: 1157 case Hexagon::STrih_indexed_shl_cPt_nv_V4: 1158 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4: 1159 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4: 1160 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4: 1161 case Hexagon::POST_SThri_cPt_nv_V4: 1162 case Hexagon::POST_SThri_cdnPt_nv_V4: 1163 case Hexagon::POST_SThri_cNotPt_nv_V4: 1164 case Hexagon::POST_SThri_cdnNotPt_nv_V4: 1165 case Hexagon::STh_GP_cPt_nv_V4: 1166 case Hexagon::STh_GP_cNotPt_nv_V4: 1167 case Hexagon::STh_GP_cdnPt_nv_V4: 1168 case Hexagon::STh_GP_cdnNotPt_nv_V4: 1169 case Hexagon::STrih_GP_cPt_nv_V4: 1170 case Hexagon::STrih_GP_cNotPt_nv_V4: 1171 case Hexagon::STrih_GP_cdnPt_nv_V4: 1172 case Hexagon::STrih_GP_cdnNotPt_nv_V4: 1173 case Hexagon::STrih_abs_nv_V4: 1174 case Hexagon::STrih_abs_cPt_nv_V4: 1175 case Hexagon::STrih_abs_cdnPt_nv_V4: 1176 case Hexagon::STrih_abs_cNotPt_nv_V4: 1177 case Hexagon::STrih_abs_cdnNotPt_nv_V4: 1178 case Hexagon::STrih_imm_abs_nv_V4: 1179 case Hexagon::STrih_imm_abs_cPt_nv_V4: 1180 case Hexagon::STrih_imm_abs_cdnPt_nv_V4: 1181 case Hexagon::STrih_imm_abs_cNotPt_nv_V4: 1182 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4: 1183 1184 // Store Word 1185 case Hexagon::STriw_nv_V4: 1186 case Hexagon::STriw_indexed_nv_V4: 1187 case Hexagon::STriw_indexed_shl_nv_V4: 1188 case Hexagon::STriw_shl_nv_V4: 1189 case Hexagon::STriw_GP_nv_V4: 1190 case Hexagon::STw_GP_nv_V4: 1191 case Hexagon::POST_STwri_nv_V4: 1192 case Hexagon::STriw_cPt_nv_V4: 1193 case Hexagon::STriw_cdnPt_nv_V4: 1194 case Hexagon::STriw_cNotPt_nv_V4: 1195 case Hexagon::STriw_cdnNotPt_nv_V4: 1196 case Hexagon::STriw_indexed_cPt_nv_V4: 1197 case Hexagon::STriw_indexed_cdnPt_nv_V4: 1198 case Hexagon::STriw_indexed_cNotPt_nv_V4: 1199 case Hexagon::STriw_indexed_cdnNotPt_nv_V4: 1200 case Hexagon::STriw_indexed_shl_cPt_nv_V4: 1201 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4: 1202 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4: 1203 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4: 1204 case Hexagon::POST_STwri_cPt_nv_V4: 1205 case Hexagon::POST_STwri_cdnPt_nv_V4: 1206 case Hexagon::POST_STwri_cNotPt_nv_V4: 1207 case Hexagon::POST_STwri_cdnNotPt_nv_V4: 1208 case Hexagon::STw_GP_cPt_nv_V4: 1209 case Hexagon::STw_GP_cNotPt_nv_V4: 1210 case Hexagon::STw_GP_cdnPt_nv_V4: 1211 case Hexagon::STw_GP_cdnNotPt_nv_V4: 1212 case Hexagon::STriw_GP_cPt_nv_V4: 1213 case Hexagon::STriw_GP_cNotPt_nv_V4: 1214 case Hexagon::STriw_GP_cdnPt_nv_V4: 1215 case Hexagon::STriw_GP_cdnNotPt_nv_V4: 1216 case Hexagon::STriw_abs_nv_V4: 1217 case Hexagon::STriw_abs_cPt_nv_V4: 1218 case Hexagon::STriw_abs_cdnPt_nv_V4: 1219 case Hexagon::STriw_abs_cNotPt_nv_V4: 1220 case Hexagon::STriw_abs_cdnNotPt_nv_V4: 1221 case Hexagon::STriw_imm_abs_nv_V4: 1222 case Hexagon::STriw_imm_abs_cPt_nv_V4: 1223 case Hexagon::STriw_imm_abs_cdnPt_nv_V4: 1224 case Hexagon::STriw_imm_abs_cNotPt_nv_V4: 1225 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4: 1226 return true; 1227 } 1228 } 1229 1230 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { 1231 switch (MI->getOpcode()) 1232 { 1233 default: return false; 1234 // Load Byte 1235 case Hexagon::POST_LDrib: 1236 case Hexagon::POST_LDrib_cPt: 1237 case Hexagon::POST_LDrib_cNotPt: 1238 case Hexagon::POST_LDrib_cdnPt_V4: 1239 case Hexagon::POST_LDrib_cdnNotPt_V4: 1240 1241 // Load unsigned byte 1242 case Hexagon::POST_LDriub: 1243 case Hexagon::POST_LDriub_cPt: 1244 case Hexagon::POST_LDriub_cNotPt: 1245 case Hexagon::POST_LDriub_cdnPt_V4: 1246 case Hexagon::POST_LDriub_cdnNotPt_V4: 1247 1248 // Load halfword 1249 case Hexagon::POST_LDrih: 1250 case Hexagon::POST_LDrih_cPt: 1251 case Hexagon::POST_LDrih_cNotPt: 1252 case Hexagon::POST_LDrih_cdnPt_V4: 1253 case Hexagon::POST_LDrih_cdnNotPt_V4: 1254 1255 // Load unsigned halfword 1256 case Hexagon::POST_LDriuh: 1257 case Hexagon::POST_LDriuh_cPt: 1258 case Hexagon::POST_LDriuh_cNotPt: 1259 case Hexagon::POST_LDriuh_cdnPt_V4: 1260 case Hexagon::POST_LDriuh_cdnNotPt_V4: 1261 1262 // Load word 1263 case Hexagon::POST_LDriw: 1264 case Hexagon::POST_LDriw_cPt: 1265 case Hexagon::POST_LDriw_cNotPt: 1266 case Hexagon::POST_LDriw_cdnPt_V4: 1267 case Hexagon::POST_LDriw_cdnNotPt_V4: 1268 1269 // Load double word 1270 case Hexagon::POST_LDrid: 1271 case Hexagon::POST_LDrid_cPt: 1272 case Hexagon::POST_LDrid_cNotPt: 1273 case Hexagon::POST_LDrid_cdnPt_V4: 1274 case Hexagon::POST_LDrid_cdnNotPt_V4: 1275 1276 // Store byte 1277 case Hexagon::POST_STbri: 1278 case Hexagon::POST_STbri_cPt: 1279 case Hexagon::POST_STbri_cNotPt: 1280 case Hexagon::POST_STbri_cdnPt_V4: 1281 case Hexagon::POST_STbri_cdnNotPt_V4: 1282 1283 // Store halfword 1284 case Hexagon::POST_SThri: 1285 case Hexagon::POST_SThri_cPt: 1286 case Hexagon::POST_SThri_cNotPt: 1287 case Hexagon::POST_SThri_cdnPt_V4: 1288 case Hexagon::POST_SThri_cdnNotPt_V4: 1289 1290 // Store word 1291 case Hexagon::POST_STwri: 1292 case Hexagon::POST_STwri_cPt: 1293 case Hexagon::POST_STwri_cNotPt: 1294 case Hexagon::POST_STwri_cdnPt_V4: 1295 case Hexagon::POST_STwri_cdnNotPt_V4: 1296 1297 // Store double word 1298 case Hexagon::POST_STdri: 1299 case Hexagon::POST_STdri_cPt: 1300 case Hexagon::POST_STdri_cNotPt: 1301 case Hexagon::POST_STdri_cdnPt_V4: 1302 case Hexagon::POST_STdri_cdnNotPt_V4: 1303 return true; 1304 } 1305 } 1306 1307 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { 1308 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4; 1309 } 1310 1311 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { 1312 bool isPred = MI->getDesc().isPredicable(); 1313 1314 if (!isPred) 1315 return false; 1316 1317 const int Opc = MI->getOpcode(); 1318 1319 switch(Opc) { 1320 case Hexagon::TFRI: 1321 return isInt<12>(MI->getOperand(1).getImm()); 1322 1323 case Hexagon::STrid: 1324 case Hexagon::STrid_indexed: 1325 return isShiftedUInt<6,3>(MI->getOperand(1).getImm()); 1326 1327 case Hexagon::STriw: 1328 case Hexagon::STriw_indexed: 1329 case Hexagon::STriw_nv_V4: 1330 return isShiftedUInt<6,2>(MI->getOperand(1).getImm()); 1331 1332 case Hexagon::STrih: 1333 case Hexagon::STrih_indexed: 1334 case Hexagon::STrih_nv_V4: 1335 return isShiftedUInt<6,1>(MI->getOperand(1).getImm()); 1336 1337 case Hexagon::STrib: 1338 case Hexagon::STrib_indexed: 1339 case Hexagon::STrib_nv_V4: 1340 return isUInt<6>(MI->getOperand(1).getImm()); 1341 1342 case Hexagon::LDrid: 1343 case Hexagon::LDrid_indexed: 1344 return isShiftedUInt<6,3>(MI->getOperand(2).getImm()); 1345 1346 case Hexagon::LDriw: 1347 case Hexagon::LDriw_indexed: 1348 return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); 1349 1350 case Hexagon::LDrih: 1351 case Hexagon::LDriuh: 1352 case Hexagon::LDrih_indexed: 1353 case Hexagon::LDriuh_indexed: 1354 return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); 1355 1356 case Hexagon::LDrib: 1357 case Hexagon::LDriub: 1358 case Hexagon::LDrib_indexed: 1359 case Hexagon::LDriub_indexed: 1360 return isUInt<6>(MI->getOperand(2).getImm()); 1361 1362 case Hexagon::POST_LDrid: 1363 return isShiftedInt<4,3>(MI->getOperand(3).getImm()); 1364 1365 case Hexagon::POST_LDriw: 1366 return isShiftedInt<4,2>(MI->getOperand(3).getImm()); 1367 1368 case Hexagon::POST_LDrih: 1369 case Hexagon::POST_LDriuh: 1370 return isShiftedInt<4,1>(MI->getOperand(3).getImm()); 1371 1372 case Hexagon::POST_LDrib: 1373 case Hexagon::POST_LDriub: 1374 return isInt<4>(MI->getOperand(3).getImm()); 1375 1376 case Hexagon::STrib_imm_V4: 1377 case Hexagon::STrih_imm_V4: 1378 case Hexagon::STriw_imm_V4: 1379 return (isUInt<6>(MI->getOperand(1).getImm()) && 1380 isInt<6>(MI->getOperand(2).getImm())); 1381 1382 case Hexagon::ADD_ri: 1383 return isInt<8>(MI->getOperand(2).getImm()); 1384 1385 case Hexagon::ASLH: 1386 case Hexagon::ASRH: 1387 case Hexagon::SXTB: 1388 case Hexagon::SXTH: 1389 case Hexagon::ZXTB: 1390 case Hexagon::ZXTH: 1391 return Subtarget.hasV4TOps(); 1392 1393 case Hexagon::JMPR: 1394 return false; 1395 } 1396 1397 return true; 1398 } 1399 1400 // This function performs the following inversiones: 1401 // 1402 // cPt ---> cNotPt 1403 // cNotPt ---> cPt 1404 // 1405 // however, these inversiones are NOT included: 1406 // 1407 // cdnPt -X-> cdnNotPt 1408 // cdnNotPt -X-> cdnPt 1409 // cPt_nv -X-> cNotPt_nv (new value stores) 1410 // cNotPt_nv -X-> cPt_nv (new value stores) 1411 // 1412 // because only the following transformations are allowed: 1413 // 1414 // cNotPt ---> cdnNotPt 1415 // cPt ---> cdnPt 1416 // cNotPt ---> cNotPt_nv 1417 // cPt ---> cPt_nv 1418 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { 1419 switch(Opc) { 1420 default: llvm_unreachable("Unexpected predicated instruction"); 1421 case Hexagon::TFR_cPt: 1422 return Hexagon::TFR_cNotPt; 1423 case Hexagon::TFR_cNotPt: 1424 return Hexagon::TFR_cPt; 1425 1426 case Hexagon::TFRI_cPt: 1427 return Hexagon::TFRI_cNotPt; 1428 case Hexagon::TFRI_cNotPt: 1429 return Hexagon::TFRI_cPt; 1430 1431 case Hexagon::JMP_c: 1432 return Hexagon::JMP_cNot; 1433 case Hexagon::JMP_cNot: 1434 return Hexagon::JMP_c; 1435 1436 case Hexagon::ADD_ri_cPt: 1437 return Hexagon::ADD_ri_cNotPt; 1438 case Hexagon::ADD_ri_cNotPt: 1439 return Hexagon::ADD_ri_cPt; 1440 1441 case Hexagon::ADD_rr_cPt: 1442 return Hexagon::ADD_rr_cNotPt; 1443 case Hexagon::ADD_rr_cNotPt: 1444 return Hexagon::ADD_rr_cPt; 1445 1446 case Hexagon::XOR_rr_cPt: 1447 return Hexagon::XOR_rr_cNotPt; 1448 case Hexagon::XOR_rr_cNotPt: 1449 return Hexagon::XOR_rr_cPt; 1450 1451 case Hexagon::AND_rr_cPt: 1452 return Hexagon::AND_rr_cNotPt; 1453 case Hexagon::AND_rr_cNotPt: 1454 return Hexagon::AND_rr_cPt; 1455 1456 case Hexagon::OR_rr_cPt: 1457 return Hexagon::OR_rr_cNotPt; 1458 case Hexagon::OR_rr_cNotPt: 1459 return Hexagon::OR_rr_cPt; 1460 1461 case Hexagon::SUB_rr_cPt: 1462 return Hexagon::SUB_rr_cNotPt; 1463 case Hexagon::SUB_rr_cNotPt: 1464 return Hexagon::SUB_rr_cPt; 1465 1466 case Hexagon::COMBINE_rr_cPt: 1467 return Hexagon::COMBINE_rr_cNotPt; 1468 case Hexagon::COMBINE_rr_cNotPt: 1469 return Hexagon::COMBINE_rr_cPt; 1470 1471 case Hexagon::ASLH_cPt_V4: 1472 return Hexagon::ASLH_cNotPt_V4; 1473 case Hexagon::ASLH_cNotPt_V4: 1474 return Hexagon::ASLH_cPt_V4; 1475 1476 case Hexagon::ASRH_cPt_V4: 1477 return Hexagon::ASRH_cNotPt_V4; 1478 case Hexagon::ASRH_cNotPt_V4: 1479 return Hexagon::ASRH_cPt_V4; 1480 1481 case Hexagon::SXTB_cPt_V4: 1482 return Hexagon::SXTB_cNotPt_V4; 1483 case Hexagon::SXTB_cNotPt_V4: 1484 return Hexagon::SXTB_cPt_V4; 1485 1486 case Hexagon::SXTH_cPt_V4: 1487 return Hexagon::SXTH_cNotPt_V4; 1488 case Hexagon::SXTH_cNotPt_V4: 1489 return Hexagon::SXTH_cPt_V4; 1490 1491 case Hexagon::ZXTB_cPt_V4: 1492 return Hexagon::ZXTB_cNotPt_V4; 1493 case Hexagon::ZXTB_cNotPt_V4: 1494 return Hexagon::ZXTB_cPt_V4; 1495 1496 case Hexagon::ZXTH_cPt_V4: 1497 return Hexagon::ZXTH_cNotPt_V4; 1498 case Hexagon::ZXTH_cNotPt_V4: 1499 return Hexagon::ZXTH_cPt_V4; 1500 1501 1502 case Hexagon::JMPR_cPt: 1503 return Hexagon::JMPR_cNotPt; 1504 case Hexagon::JMPR_cNotPt: 1505 return Hexagon::JMPR_cPt; 1506 1507 // V4 indexed+scaled load. 1508 case Hexagon::LDrid_indexed_cPt_V4: 1509 return Hexagon::LDrid_indexed_cNotPt_V4; 1510 case Hexagon::LDrid_indexed_cNotPt_V4: 1511 return Hexagon::LDrid_indexed_cPt_V4; 1512 1513 case Hexagon::LDrid_indexed_shl_cPt_V4: 1514 return Hexagon::LDrid_indexed_shl_cNotPt_V4; 1515 case Hexagon::LDrid_indexed_shl_cNotPt_V4: 1516 return Hexagon::LDrid_indexed_shl_cPt_V4; 1517 1518 case Hexagon::LDrib_indexed_cPt_V4: 1519 return Hexagon::LDrib_indexed_cNotPt_V4; 1520 case Hexagon::LDrib_indexed_cNotPt_V4: 1521 return Hexagon::LDrib_indexed_cPt_V4; 1522 1523 case Hexagon::LDriub_indexed_cPt_V4: 1524 return Hexagon::LDriub_indexed_cNotPt_V4; 1525 case Hexagon::LDriub_indexed_cNotPt_V4: 1526 return Hexagon::LDriub_indexed_cPt_V4; 1527 1528 case Hexagon::LDrib_indexed_shl_cPt_V4: 1529 return Hexagon::LDrib_indexed_shl_cNotPt_V4; 1530 case Hexagon::LDrib_indexed_shl_cNotPt_V4: 1531 return Hexagon::LDrib_indexed_shl_cPt_V4; 1532 1533 case Hexagon::LDriub_indexed_shl_cPt_V4: 1534 return Hexagon::LDriub_indexed_shl_cNotPt_V4; 1535 case Hexagon::LDriub_indexed_shl_cNotPt_V4: 1536 return Hexagon::LDriub_indexed_shl_cPt_V4; 1537 1538 case Hexagon::LDrih_indexed_cPt_V4: 1539 return Hexagon::LDrih_indexed_cNotPt_V4; 1540 case Hexagon::LDrih_indexed_cNotPt_V4: 1541 return Hexagon::LDrih_indexed_cPt_V4; 1542 1543 case Hexagon::LDriuh_indexed_cPt_V4: 1544 return Hexagon::LDriuh_indexed_cNotPt_V4; 1545 case Hexagon::LDriuh_indexed_cNotPt_V4: 1546 return Hexagon::LDriuh_indexed_cPt_V4; 1547 1548 case Hexagon::LDrih_indexed_shl_cPt_V4: 1549 return Hexagon::LDrih_indexed_shl_cNotPt_V4; 1550 case Hexagon::LDrih_indexed_shl_cNotPt_V4: 1551 return Hexagon::LDrih_indexed_shl_cPt_V4; 1552 1553 case Hexagon::LDriuh_indexed_shl_cPt_V4: 1554 return Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1555 case Hexagon::LDriuh_indexed_shl_cNotPt_V4: 1556 return Hexagon::LDriuh_indexed_shl_cPt_V4; 1557 1558 case Hexagon::LDriw_indexed_cPt_V4: 1559 return Hexagon::LDriw_indexed_cNotPt_V4; 1560 case Hexagon::LDriw_indexed_cNotPt_V4: 1561 return Hexagon::LDriw_indexed_cPt_V4; 1562 1563 case Hexagon::LDriw_indexed_shl_cPt_V4: 1564 return Hexagon::LDriw_indexed_shl_cNotPt_V4; 1565 case Hexagon::LDriw_indexed_shl_cNotPt_V4: 1566 return Hexagon::LDriw_indexed_shl_cPt_V4; 1567 1568 // Byte. 1569 case Hexagon::POST_STbri_cPt: 1570 return Hexagon::POST_STbri_cNotPt; 1571 case Hexagon::POST_STbri_cNotPt: 1572 return Hexagon::POST_STbri_cPt; 1573 1574 case Hexagon::STrib_cPt: 1575 return Hexagon::STrib_cNotPt; 1576 case Hexagon::STrib_cNotPt: 1577 return Hexagon::STrib_cPt; 1578 1579 case Hexagon::STrib_indexed_cPt: 1580 return Hexagon::STrib_indexed_cNotPt; 1581 case Hexagon::STrib_indexed_cNotPt: 1582 return Hexagon::STrib_indexed_cPt; 1583 1584 case Hexagon::STrib_imm_cPt_V4: 1585 return Hexagon::STrib_imm_cNotPt_V4; 1586 case Hexagon::STrib_imm_cNotPt_V4: 1587 return Hexagon::STrib_imm_cPt_V4; 1588 1589 case Hexagon::STrib_indexed_shl_cPt_V4: 1590 return Hexagon::STrib_indexed_shl_cNotPt_V4; 1591 case Hexagon::STrib_indexed_shl_cNotPt_V4: 1592 return Hexagon::STrib_indexed_shl_cPt_V4; 1593 1594 // Halfword. 1595 case Hexagon::POST_SThri_cPt: 1596 return Hexagon::POST_SThri_cNotPt; 1597 case Hexagon::POST_SThri_cNotPt: 1598 return Hexagon::POST_SThri_cPt; 1599 1600 case Hexagon::STrih_cPt: 1601 return Hexagon::STrih_cNotPt; 1602 case Hexagon::STrih_cNotPt: 1603 return Hexagon::STrih_cPt; 1604 1605 case Hexagon::STrih_indexed_cPt: 1606 return Hexagon::STrih_indexed_cNotPt; 1607 case Hexagon::STrih_indexed_cNotPt: 1608 return Hexagon::STrih_indexed_cPt; 1609 1610 case Hexagon::STrih_imm_cPt_V4: 1611 return Hexagon::STrih_imm_cNotPt_V4; 1612 case Hexagon::STrih_imm_cNotPt_V4: 1613 return Hexagon::STrih_imm_cPt_V4; 1614 1615 case Hexagon::STrih_indexed_shl_cPt_V4: 1616 return Hexagon::STrih_indexed_shl_cNotPt_V4; 1617 case Hexagon::STrih_indexed_shl_cNotPt_V4: 1618 return Hexagon::STrih_indexed_shl_cPt_V4; 1619 1620 // Word. 1621 case Hexagon::POST_STwri_cPt: 1622 return Hexagon::POST_STwri_cNotPt; 1623 case Hexagon::POST_STwri_cNotPt: 1624 return Hexagon::POST_STwri_cPt; 1625 1626 case Hexagon::STriw_cPt: 1627 return Hexagon::STriw_cNotPt; 1628 case Hexagon::STriw_cNotPt: 1629 return Hexagon::STriw_cPt; 1630 1631 case Hexagon::STriw_indexed_cPt: 1632 return Hexagon::STriw_indexed_cNotPt; 1633 case Hexagon::STriw_indexed_cNotPt: 1634 return Hexagon::STriw_indexed_cPt; 1635 1636 case Hexagon::STriw_indexed_shl_cPt_V4: 1637 return Hexagon::STriw_indexed_shl_cNotPt_V4; 1638 case Hexagon::STriw_indexed_shl_cNotPt_V4: 1639 return Hexagon::STriw_indexed_shl_cPt_V4; 1640 1641 case Hexagon::STriw_imm_cPt_V4: 1642 return Hexagon::STriw_imm_cNotPt_V4; 1643 case Hexagon::STriw_imm_cNotPt_V4: 1644 return Hexagon::STriw_imm_cPt_V4; 1645 1646 // Double word. 1647 case Hexagon::POST_STdri_cPt: 1648 return Hexagon::POST_STdri_cNotPt; 1649 case Hexagon::POST_STdri_cNotPt: 1650 return Hexagon::POST_STdri_cPt; 1651 1652 case Hexagon::STrid_cPt: 1653 return Hexagon::STrid_cNotPt; 1654 case Hexagon::STrid_cNotPt: 1655 return Hexagon::STrid_cPt; 1656 1657 case Hexagon::STrid_indexed_cPt: 1658 return Hexagon::STrid_indexed_cNotPt; 1659 case Hexagon::STrid_indexed_cNotPt: 1660 return Hexagon::STrid_indexed_cPt; 1661 1662 case Hexagon::STrid_indexed_shl_cPt_V4: 1663 return Hexagon::STrid_indexed_shl_cNotPt_V4; 1664 case Hexagon::STrid_indexed_shl_cNotPt_V4: 1665 return Hexagon::STrid_indexed_shl_cPt_V4; 1666 1667 // V4 Store to global address. 1668 case Hexagon::STd_GP_cPt_V4: 1669 return Hexagon::STd_GP_cNotPt_V4; 1670 case Hexagon::STd_GP_cNotPt_V4: 1671 return Hexagon::STd_GP_cPt_V4; 1672 1673 case Hexagon::STb_GP_cPt_V4: 1674 return Hexagon::STb_GP_cNotPt_V4; 1675 case Hexagon::STb_GP_cNotPt_V4: 1676 return Hexagon::STb_GP_cPt_V4; 1677 1678 case Hexagon::STh_GP_cPt_V4: 1679 return Hexagon::STh_GP_cNotPt_V4; 1680 case Hexagon::STh_GP_cNotPt_V4: 1681 return Hexagon::STh_GP_cPt_V4; 1682 1683 case Hexagon::STw_GP_cPt_V4: 1684 return Hexagon::STw_GP_cNotPt_V4; 1685 case Hexagon::STw_GP_cNotPt_V4: 1686 return Hexagon::STw_GP_cPt_V4; 1687 1688 case Hexagon::STrid_GP_cPt_V4: 1689 return Hexagon::STrid_GP_cNotPt_V4; 1690 case Hexagon::STrid_GP_cNotPt_V4: 1691 return Hexagon::STrid_GP_cPt_V4; 1692 1693 case Hexagon::STrib_GP_cPt_V4: 1694 return Hexagon::STrib_GP_cNotPt_V4; 1695 case Hexagon::STrib_GP_cNotPt_V4: 1696 return Hexagon::STrib_GP_cPt_V4; 1697 1698 case Hexagon::STrih_GP_cPt_V4: 1699 return Hexagon::STrih_GP_cNotPt_V4; 1700 case Hexagon::STrih_GP_cNotPt_V4: 1701 return Hexagon::STrih_GP_cPt_V4; 1702 1703 case Hexagon::STriw_GP_cPt_V4: 1704 return Hexagon::STriw_GP_cNotPt_V4; 1705 case Hexagon::STriw_GP_cNotPt_V4: 1706 return Hexagon::STriw_GP_cPt_V4; 1707 1708 // Load. 1709 case Hexagon::LDrid_cPt: 1710 return Hexagon::LDrid_cNotPt; 1711 case Hexagon::LDrid_cNotPt: 1712 return Hexagon::LDrid_cPt; 1713 1714 case Hexagon::LDriw_cPt: 1715 return Hexagon::LDriw_cNotPt; 1716 case Hexagon::LDriw_cNotPt: 1717 return Hexagon::LDriw_cPt; 1718 1719 case Hexagon::LDrih_cPt: 1720 return Hexagon::LDrih_cNotPt; 1721 case Hexagon::LDrih_cNotPt: 1722 return Hexagon::LDrih_cPt; 1723 1724 case Hexagon::LDriuh_cPt: 1725 return Hexagon::LDriuh_cNotPt; 1726 case Hexagon::LDriuh_cNotPt: 1727 return Hexagon::LDriuh_cPt; 1728 1729 case Hexagon::LDrib_cPt: 1730 return Hexagon::LDrib_cNotPt; 1731 case Hexagon::LDrib_cNotPt: 1732 return Hexagon::LDrib_cPt; 1733 1734 case Hexagon::LDriub_cPt: 1735 return Hexagon::LDriub_cNotPt; 1736 case Hexagon::LDriub_cNotPt: 1737 return Hexagon::LDriub_cPt; 1738 1739 // Load Indexed. 1740 case Hexagon::LDrid_indexed_cPt: 1741 return Hexagon::LDrid_indexed_cNotPt; 1742 case Hexagon::LDrid_indexed_cNotPt: 1743 return Hexagon::LDrid_indexed_cPt; 1744 1745 case Hexagon::LDriw_indexed_cPt: 1746 return Hexagon::LDriw_indexed_cNotPt; 1747 case Hexagon::LDriw_indexed_cNotPt: 1748 return Hexagon::LDriw_indexed_cPt; 1749 1750 case Hexagon::LDrih_indexed_cPt: 1751 return Hexagon::LDrih_indexed_cNotPt; 1752 case Hexagon::LDrih_indexed_cNotPt: 1753 return Hexagon::LDrih_indexed_cPt; 1754 1755 case Hexagon::LDriuh_indexed_cPt: 1756 return Hexagon::LDriuh_indexed_cNotPt; 1757 case Hexagon::LDriuh_indexed_cNotPt: 1758 return Hexagon::LDriuh_indexed_cPt; 1759 1760 case Hexagon::LDrib_indexed_cPt: 1761 return Hexagon::LDrib_indexed_cNotPt; 1762 case Hexagon::LDrib_indexed_cNotPt: 1763 return Hexagon::LDrib_indexed_cPt; 1764 1765 case Hexagon::LDriub_indexed_cPt: 1766 return Hexagon::LDriub_indexed_cNotPt; 1767 case Hexagon::LDriub_indexed_cNotPt: 1768 return Hexagon::LDriub_indexed_cPt; 1769 1770 // Post Inc Load. 1771 case Hexagon::POST_LDrid_cPt: 1772 return Hexagon::POST_LDrid_cNotPt; 1773 case Hexagon::POST_LDriw_cNotPt: 1774 return Hexagon::POST_LDriw_cPt; 1775 1776 case Hexagon::POST_LDrih_cPt: 1777 return Hexagon::POST_LDrih_cNotPt; 1778 case Hexagon::POST_LDrih_cNotPt: 1779 return Hexagon::POST_LDrih_cPt; 1780 1781 case Hexagon::POST_LDriuh_cPt: 1782 return Hexagon::POST_LDriuh_cNotPt; 1783 case Hexagon::POST_LDriuh_cNotPt: 1784 return Hexagon::POST_LDriuh_cPt; 1785 1786 case Hexagon::POST_LDrib_cPt: 1787 return Hexagon::POST_LDrib_cNotPt; 1788 case Hexagon::POST_LDrib_cNotPt: 1789 return Hexagon::POST_LDrib_cPt; 1790 1791 case Hexagon::POST_LDriub_cPt: 1792 return Hexagon::POST_LDriub_cNotPt; 1793 case Hexagon::POST_LDriub_cNotPt: 1794 return Hexagon::POST_LDriub_cPt; 1795 1796 // Dealloc_return. 1797 case Hexagon::DEALLOC_RET_cPt_V4: 1798 return Hexagon::DEALLOC_RET_cNotPt_V4; 1799 case Hexagon::DEALLOC_RET_cNotPt_V4: 1800 return Hexagon::DEALLOC_RET_cPt_V4; 1801 1802 // New Value Jump. 1803 // JMPEQ_ri - with -1. 1804 case Hexagon::JMP_EQriPtneg_nv_V4: 1805 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1806 case Hexagon::JMP_EQriNotPtneg_nv_V4: 1807 return Hexagon::JMP_EQriPtneg_nv_V4; 1808 1809 case Hexagon::JMP_EQriPntneg_nv_V4: 1810 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1811 case Hexagon::JMP_EQriNotPntneg_nv_V4: 1812 return Hexagon::JMP_EQriPntneg_nv_V4; 1813 1814 // JMPEQ_ri. 1815 case Hexagon::JMP_EQriPt_nv_V4: 1816 return Hexagon::JMP_EQriNotPt_nv_V4; 1817 case Hexagon::JMP_EQriNotPt_nv_V4: 1818 return Hexagon::JMP_EQriPt_nv_V4; 1819 1820 case Hexagon::JMP_EQriPnt_nv_V4: 1821 return Hexagon::JMP_EQriNotPnt_nv_V4; 1822 case Hexagon::JMP_EQriNotPnt_nv_V4: 1823 return Hexagon::JMP_EQriPnt_nv_V4; 1824 1825 // JMPEQ_rr. 1826 case Hexagon::JMP_EQrrPt_nv_V4: 1827 return Hexagon::JMP_EQrrNotPt_nv_V4; 1828 case Hexagon::JMP_EQrrNotPt_nv_V4: 1829 return Hexagon::JMP_EQrrPt_nv_V4; 1830 1831 case Hexagon::JMP_EQrrPnt_nv_V4: 1832 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1833 case Hexagon::JMP_EQrrNotPnt_nv_V4: 1834 return Hexagon::JMP_EQrrPnt_nv_V4; 1835 1836 // JMPGT_ri - with -1. 1837 case Hexagon::JMP_GTriPtneg_nv_V4: 1838 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1839 case Hexagon::JMP_GTriNotPtneg_nv_V4: 1840 return Hexagon::JMP_GTriPtneg_nv_V4; 1841 1842 case Hexagon::JMP_GTriPntneg_nv_V4: 1843 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1844 case Hexagon::JMP_GTriNotPntneg_nv_V4: 1845 return Hexagon::JMP_GTriPntneg_nv_V4; 1846 1847 // JMPGT_ri. 1848 case Hexagon::JMP_GTriPt_nv_V4: 1849 return Hexagon::JMP_GTriNotPt_nv_V4; 1850 case Hexagon::JMP_GTriNotPt_nv_V4: 1851 return Hexagon::JMP_GTriPt_nv_V4; 1852 1853 case Hexagon::JMP_GTriPnt_nv_V4: 1854 return Hexagon::JMP_GTriNotPnt_nv_V4; 1855 case Hexagon::JMP_GTriNotPnt_nv_V4: 1856 return Hexagon::JMP_GTriPnt_nv_V4; 1857 1858 // JMPGT_rr. 1859 case Hexagon::JMP_GTrrPt_nv_V4: 1860 return Hexagon::JMP_GTrrNotPt_nv_V4; 1861 case Hexagon::JMP_GTrrNotPt_nv_V4: 1862 return Hexagon::JMP_GTrrPt_nv_V4; 1863 1864 case Hexagon::JMP_GTrrPnt_nv_V4: 1865 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1866 case Hexagon::JMP_GTrrNotPnt_nv_V4: 1867 return Hexagon::JMP_GTrrPnt_nv_V4; 1868 1869 // JMPGT_rrdn. 1870 case Hexagon::JMP_GTrrdnPt_nv_V4: 1871 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1872 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 1873 return Hexagon::JMP_GTrrdnPt_nv_V4; 1874 1875 case Hexagon::JMP_GTrrdnPnt_nv_V4: 1876 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1877 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 1878 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1879 1880 // JMPGTU_ri. 1881 case Hexagon::JMP_GTUriPt_nv_V4: 1882 return Hexagon::JMP_GTUriNotPt_nv_V4; 1883 case Hexagon::JMP_GTUriNotPt_nv_V4: 1884 return Hexagon::JMP_GTUriPt_nv_V4; 1885 1886 case Hexagon::JMP_GTUriPnt_nv_V4: 1887 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1888 case Hexagon::JMP_GTUriNotPnt_nv_V4: 1889 return Hexagon::JMP_GTUriPnt_nv_V4; 1890 1891 // JMPGTU_rr. 1892 case Hexagon::JMP_GTUrrPt_nv_V4: 1893 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1894 case Hexagon::JMP_GTUrrNotPt_nv_V4: 1895 return Hexagon::JMP_GTUrrPt_nv_V4; 1896 1897 case Hexagon::JMP_GTUrrPnt_nv_V4: 1898 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1899 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 1900 return Hexagon::JMP_GTUrrPnt_nv_V4; 1901 1902 // JMPGTU_rrdn. 1903 case Hexagon::JMP_GTUrrdnPt_nv_V4: 1904 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1905 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 1906 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1907 1908 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 1909 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1910 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 1911 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1912 } 1913 } 1914 1915 1916 int HexagonInstrInfo:: 1917 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { 1918 switch(Opc) { 1919 case Hexagon::TFR: 1920 return !invertPredicate ? Hexagon::TFR_cPt : 1921 Hexagon::TFR_cNotPt; 1922 case Hexagon::TFRI_f: 1923 return !invertPredicate ? Hexagon::TFRI_cPt_f : 1924 Hexagon::TFRI_cNotPt_f; 1925 case Hexagon::TFRI: 1926 return !invertPredicate ? Hexagon::TFRI_cPt : 1927 Hexagon::TFRI_cNotPt; 1928 case Hexagon::JMP: 1929 return !invertPredicate ? Hexagon::JMP_c : 1930 Hexagon::JMP_cNot; 1931 case Hexagon::JMP_EQrrPt_nv_V4: 1932 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 : 1933 Hexagon::JMP_EQrrNotPt_nv_V4; 1934 case Hexagon::JMP_EQriPt_nv_V4: 1935 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : 1936 Hexagon::JMP_EQriNotPt_nv_V4; 1937 case Hexagon::ADD_ri: 1938 return !invertPredicate ? Hexagon::ADD_ri_cPt : 1939 Hexagon::ADD_ri_cNotPt; 1940 case Hexagon::ADD_rr: 1941 return !invertPredicate ? Hexagon::ADD_rr_cPt : 1942 Hexagon::ADD_rr_cNotPt; 1943 case Hexagon::XOR_rr: 1944 return !invertPredicate ? Hexagon::XOR_rr_cPt : 1945 Hexagon::XOR_rr_cNotPt; 1946 case Hexagon::AND_rr: 1947 return !invertPredicate ? Hexagon::AND_rr_cPt : 1948 Hexagon::AND_rr_cNotPt; 1949 case Hexagon::OR_rr: 1950 return !invertPredicate ? Hexagon::OR_rr_cPt : 1951 Hexagon::OR_rr_cNotPt; 1952 case Hexagon::SUB_rr: 1953 return !invertPredicate ? Hexagon::SUB_rr_cPt : 1954 Hexagon::SUB_rr_cNotPt; 1955 case Hexagon::COMBINE_rr: 1956 return !invertPredicate ? Hexagon::COMBINE_rr_cPt : 1957 Hexagon::COMBINE_rr_cNotPt; 1958 case Hexagon::ASLH: 1959 return !invertPredicate ? Hexagon::ASLH_cPt_V4 : 1960 Hexagon::ASLH_cNotPt_V4; 1961 case Hexagon::ASRH: 1962 return !invertPredicate ? Hexagon::ASRH_cPt_V4 : 1963 Hexagon::ASRH_cNotPt_V4; 1964 case Hexagon::SXTB: 1965 return !invertPredicate ? Hexagon::SXTB_cPt_V4 : 1966 Hexagon::SXTB_cNotPt_V4; 1967 case Hexagon::SXTH: 1968 return !invertPredicate ? Hexagon::SXTH_cPt_V4 : 1969 Hexagon::SXTH_cNotPt_V4; 1970 case Hexagon::ZXTB: 1971 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 : 1972 Hexagon::ZXTB_cNotPt_V4; 1973 case Hexagon::ZXTH: 1974 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 : 1975 Hexagon::ZXTH_cNotPt_V4; 1976 1977 case Hexagon::JMPR: 1978 return !invertPredicate ? Hexagon::JMPR_cPt : 1979 Hexagon::JMPR_cNotPt; 1980 1981 // V4 indexed+scaled load. 1982 case Hexagon::LDrid_indexed_V4: 1983 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 : 1984 Hexagon::LDrid_indexed_cNotPt_V4; 1985 case Hexagon::LDrid_indexed_shl_V4: 1986 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 : 1987 Hexagon::LDrid_indexed_shl_cNotPt_V4; 1988 case Hexagon::LDrib_indexed_V4: 1989 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 : 1990 Hexagon::LDrib_indexed_cNotPt_V4; 1991 case Hexagon::LDriub_indexed_V4: 1992 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 : 1993 Hexagon::LDriub_indexed_cNotPt_V4; 1994 case Hexagon::LDriub_ae_indexed_V4: 1995 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 : 1996 Hexagon::LDriub_indexed_cNotPt_V4; 1997 case Hexagon::LDrib_indexed_shl_V4: 1998 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 : 1999 Hexagon::LDrib_indexed_shl_cNotPt_V4; 2000 case Hexagon::LDriub_indexed_shl_V4: 2001 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 2002 Hexagon::LDriub_indexed_shl_cNotPt_V4; 2003 case Hexagon::LDriub_ae_indexed_shl_V4: 2004 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 2005 Hexagon::LDriub_indexed_shl_cNotPt_V4; 2006 case Hexagon::LDrih_indexed_V4: 2007 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 : 2008 Hexagon::LDrih_indexed_cNotPt_V4; 2009 case Hexagon::LDriuh_indexed_V4: 2010 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 : 2011 Hexagon::LDriuh_indexed_cNotPt_V4; 2012 case Hexagon::LDriuh_ae_indexed_V4: 2013 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 : 2014 Hexagon::LDriuh_indexed_cNotPt_V4; 2015 case Hexagon::LDrih_indexed_shl_V4: 2016 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 : 2017 Hexagon::LDrih_indexed_shl_cNotPt_V4; 2018 case Hexagon::LDriuh_indexed_shl_V4: 2019 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 2020 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 2021 case Hexagon::LDriuh_ae_indexed_shl_V4: 2022 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 2023 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 2024 case Hexagon::LDriw_indexed_V4: 2025 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 : 2026 Hexagon::LDriw_indexed_cNotPt_V4; 2027 case Hexagon::LDriw_indexed_shl_V4: 2028 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 : 2029 Hexagon::LDriw_indexed_shl_cNotPt_V4; 2030 2031 // V4 Load from global address 2032 case Hexagon::LDrid_GP_V4: 2033 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 : 2034 Hexagon::LDrid_GP_cNotPt_V4; 2035 case Hexagon::LDrib_GP_V4: 2036 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 : 2037 Hexagon::LDrib_GP_cNotPt_V4; 2038 case Hexagon::LDriub_GP_V4: 2039 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 : 2040 Hexagon::LDriub_GP_cNotPt_V4; 2041 case Hexagon::LDrih_GP_V4: 2042 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 : 2043 Hexagon::LDrih_GP_cNotPt_V4; 2044 case Hexagon::LDriuh_GP_V4: 2045 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 : 2046 Hexagon::LDriuh_GP_cNotPt_V4; 2047 case Hexagon::LDriw_GP_V4: 2048 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 : 2049 Hexagon::LDriw_GP_cNotPt_V4; 2050 2051 case Hexagon::LDd_GP_V4: 2052 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 : 2053 Hexagon::LDd_GP_cNotPt_V4; 2054 case Hexagon::LDb_GP_V4: 2055 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 : 2056 Hexagon::LDb_GP_cNotPt_V4; 2057 case Hexagon::LDub_GP_V4: 2058 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 : 2059 Hexagon::LDub_GP_cNotPt_V4; 2060 case Hexagon::LDh_GP_V4: 2061 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 : 2062 Hexagon::LDh_GP_cNotPt_V4; 2063 case Hexagon::LDuh_GP_V4: 2064 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 : 2065 Hexagon::LDuh_GP_cNotPt_V4; 2066 case Hexagon::LDw_GP_V4: 2067 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 : 2068 Hexagon::LDw_GP_cNotPt_V4; 2069 2070 // Byte. 2071 case Hexagon::POST_STbri: 2072 return !invertPredicate ? Hexagon::POST_STbri_cPt : 2073 Hexagon::POST_STbri_cNotPt; 2074 case Hexagon::STrib: 2075 return !invertPredicate ? Hexagon::STrib_cPt : 2076 Hexagon::STrib_cNotPt; 2077 case Hexagon::STrib_indexed: 2078 return !invertPredicate ? Hexagon::STrib_indexed_cPt : 2079 Hexagon::STrib_indexed_cNotPt; 2080 case Hexagon::STrib_imm_V4: 2081 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 : 2082 Hexagon::STrib_imm_cNotPt_V4; 2083 case Hexagon::STrib_indexed_shl_V4: 2084 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 : 2085 Hexagon::STrib_indexed_shl_cNotPt_V4; 2086 // Halfword. 2087 case Hexagon::POST_SThri: 2088 return !invertPredicate ? Hexagon::POST_SThri_cPt : 2089 Hexagon::POST_SThri_cNotPt; 2090 case Hexagon::STrih: 2091 return !invertPredicate ? Hexagon::STrih_cPt : 2092 Hexagon::STrih_cNotPt; 2093 case Hexagon::STrih_indexed: 2094 return !invertPredicate ? Hexagon::STrih_indexed_cPt : 2095 Hexagon::STrih_indexed_cNotPt; 2096 case Hexagon::STrih_imm_V4: 2097 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 : 2098 Hexagon::STrih_imm_cNotPt_V4; 2099 case Hexagon::STrih_indexed_shl_V4: 2100 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 : 2101 Hexagon::STrih_indexed_shl_cNotPt_V4; 2102 // Word. 2103 case Hexagon::POST_STwri: 2104 return !invertPredicate ? Hexagon::POST_STwri_cPt : 2105 Hexagon::POST_STwri_cNotPt; 2106 case Hexagon::STriw: 2107 return !invertPredicate ? Hexagon::STriw_cPt : 2108 Hexagon::STriw_cNotPt; 2109 case Hexagon::STriw_indexed: 2110 return !invertPredicate ? Hexagon::STriw_indexed_cPt : 2111 Hexagon::STriw_indexed_cNotPt; 2112 case Hexagon::STriw_indexed_shl_V4: 2113 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 : 2114 Hexagon::STriw_indexed_shl_cNotPt_V4; 2115 case Hexagon::STriw_imm_V4: 2116 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 : 2117 Hexagon::STriw_imm_cNotPt_V4; 2118 // Double word. 2119 case Hexagon::POST_STdri: 2120 return !invertPredicate ? Hexagon::POST_STdri_cPt : 2121 Hexagon::POST_STdri_cNotPt; 2122 case Hexagon::STrid: 2123 return !invertPredicate ? Hexagon::STrid_cPt : 2124 Hexagon::STrid_cNotPt; 2125 case Hexagon::STrid_indexed: 2126 return !invertPredicate ? Hexagon::STrid_indexed_cPt : 2127 Hexagon::STrid_indexed_cNotPt; 2128 case Hexagon::STrid_indexed_shl_V4: 2129 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 : 2130 Hexagon::STrid_indexed_shl_cNotPt_V4; 2131 2132 // V4 Store to global address 2133 case Hexagon::STrid_GP_V4: 2134 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 : 2135 Hexagon::STrid_GP_cNotPt_V4; 2136 case Hexagon::STrib_GP_V4: 2137 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 : 2138 Hexagon::STrib_GP_cNotPt_V4; 2139 case Hexagon::STrih_GP_V4: 2140 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 : 2141 Hexagon::STrih_GP_cNotPt_V4; 2142 case Hexagon::STriw_GP_V4: 2143 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 : 2144 Hexagon::STriw_GP_cNotPt_V4; 2145 2146 case Hexagon::STd_GP_V4: 2147 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 : 2148 Hexagon::STd_GP_cNotPt_V4; 2149 case Hexagon::STb_GP_V4: 2150 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 : 2151 Hexagon::STb_GP_cNotPt_V4; 2152 case Hexagon::STh_GP_V4: 2153 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 : 2154 Hexagon::STh_GP_cNotPt_V4; 2155 case Hexagon::STw_GP_V4: 2156 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 : 2157 Hexagon::STw_GP_cNotPt_V4; 2158 2159 // Load. 2160 case Hexagon::LDrid: 2161 return !invertPredicate ? Hexagon::LDrid_cPt : 2162 Hexagon::LDrid_cNotPt; 2163 case Hexagon::LDriw: 2164 return !invertPredicate ? Hexagon::LDriw_cPt : 2165 Hexagon::LDriw_cNotPt; 2166 case Hexagon::LDrih: 2167 return !invertPredicate ? Hexagon::LDrih_cPt : 2168 Hexagon::LDrih_cNotPt; 2169 case Hexagon::LDriuh: 2170 return !invertPredicate ? Hexagon::LDriuh_cPt : 2171 Hexagon::LDriuh_cNotPt; 2172 case Hexagon::LDrib: 2173 return !invertPredicate ? Hexagon::LDrib_cPt : 2174 Hexagon::LDrib_cNotPt; 2175 case Hexagon::LDriub: 2176 return !invertPredicate ? Hexagon::LDriub_cPt : 2177 Hexagon::LDriub_cNotPt; 2178 // Load Indexed. 2179 case Hexagon::LDrid_indexed: 2180 return !invertPredicate ? Hexagon::LDrid_indexed_cPt : 2181 Hexagon::LDrid_indexed_cNotPt; 2182 case Hexagon::LDriw_indexed: 2183 return !invertPredicate ? Hexagon::LDriw_indexed_cPt : 2184 Hexagon::LDriw_indexed_cNotPt; 2185 case Hexagon::LDrih_indexed: 2186 return !invertPredicate ? Hexagon::LDrih_indexed_cPt : 2187 Hexagon::LDrih_indexed_cNotPt; 2188 case Hexagon::LDriuh_indexed: 2189 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt : 2190 Hexagon::LDriuh_indexed_cNotPt; 2191 case Hexagon::LDrib_indexed: 2192 return !invertPredicate ? Hexagon::LDrib_indexed_cPt : 2193 Hexagon::LDrib_indexed_cNotPt; 2194 case Hexagon::LDriub_indexed: 2195 return !invertPredicate ? Hexagon::LDriub_indexed_cPt : 2196 Hexagon::LDriub_indexed_cNotPt; 2197 // Post Increment Load. 2198 case Hexagon::POST_LDrid: 2199 return !invertPredicate ? Hexagon::POST_LDrid_cPt : 2200 Hexagon::POST_LDrid_cNotPt; 2201 case Hexagon::POST_LDriw: 2202 return !invertPredicate ? Hexagon::POST_LDriw_cPt : 2203 Hexagon::POST_LDriw_cNotPt; 2204 case Hexagon::POST_LDrih: 2205 return !invertPredicate ? Hexagon::POST_LDrih_cPt : 2206 Hexagon::POST_LDrih_cNotPt; 2207 case Hexagon::POST_LDriuh: 2208 return !invertPredicate ? Hexagon::POST_LDriuh_cPt : 2209 Hexagon::POST_LDriuh_cNotPt; 2210 case Hexagon::POST_LDrib: 2211 return !invertPredicate ? Hexagon::POST_LDrib_cPt : 2212 Hexagon::POST_LDrib_cNotPt; 2213 case Hexagon::POST_LDriub: 2214 return !invertPredicate ? Hexagon::POST_LDriub_cPt : 2215 Hexagon::POST_LDriub_cNotPt; 2216 // DEALLOC_RETURN. 2217 case Hexagon::DEALLOC_RET_V4: 2218 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 : 2219 Hexagon::DEALLOC_RET_cNotPt_V4; 2220 } 2221 llvm_unreachable("Unexpected predicable instruction"); 2222 } 2223 2224 2225 bool HexagonInstrInfo:: 2226 PredicateInstruction(MachineInstr *MI, 2227 const SmallVectorImpl<MachineOperand> &Cond) const { 2228 int Opc = MI->getOpcode(); 2229 assert (isPredicable(MI) && "Expected predicable instruction"); 2230 bool invertJump = (!Cond.empty() && Cond[0].isImm() && 2231 (Cond[0].getImm() == 0)); 2232 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump))); 2233 // 2234 // This assumes that the predicate is always the first operand 2235 // in the set of inputs. 2236 // 2237 MI->addOperand(MI->getOperand(MI->getNumOperands()-1)); 2238 int oper; 2239 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) { 2240 MachineOperand MO = MI->getOperand(oper); 2241 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) { 2242 break; 2243 } 2244 2245 if (MO.isReg()) { 2246 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(), 2247 MO.isImplicit(), MO.isKill(), 2248 MO.isDead(), MO.isUndef(), 2249 MO.isDebug()); 2250 } else if (MO.isImm()) { 2251 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm()); 2252 } else { 2253 llvm_unreachable("Unexpected operand type"); 2254 } 2255 } 2256 2257 int regPos = invertJump ? 1 : 0; 2258 MachineOperand PredMO = Cond[regPos]; 2259 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(), 2260 PredMO.isImplicit(), PredMO.isKill(), 2261 PredMO.isDead(), PredMO.isUndef(), 2262 PredMO.isDebug()); 2263 2264 return true; 2265 } 2266 2267 2268 bool 2269 HexagonInstrInfo:: 2270 isProfitableToIfCvt(MachineBasicBlock &MBB, 2271 unsigned NumCycles, 2272 unsigned ExtraPredCycles, 2273 const BranchProbability &Probability) const { 2274 return true; 2275 } 2276 2277 2278 bool 2279 HexagonInstrInfo:: 2280 isProfitableToIfCvt(MachineBasicBlock &TMBB, 2281 unsigned NumTCycles, 2282 unsigned ExtraTCycles, 2283 MachineBasicBlock &FMBB, 2284 unsigned NumFCycles, 2285 unsigned ExtraFCycles, 2286 const BranchProbability &Probability) const { 2287 return true; 2288 } 2289 2290 2291 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { 2292 const uint64_t F = MI->getDesc().TSFlags; 2293 2294 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); 2295 } 2296 2297 bool 2298 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, 2299 std::vector<MachineOperand> &Pred) const { 2300 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) { 2301 MachineOperand MO = MI->getOperand(oper); 2302 if (MO.isReg() && MO.isDef()) { 2303 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); 2304 if (RC == &Hexagon::PredRegsRegClass) { 2305 Pred.push_back(MO); 2306 return true; 2307 } 2308 } 2309 } 2310 return false; 2311 } 2312 2313 2314 bool 2315 HexagonInstrInfo:: 2316 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 2317 const SmallVectorImpl<MachineOperand> &Pred2) const { 2318 // TODO: Fix this 2319 return false; 2320 } 2321 2322 2323 // 2324 // We indicate that we want to reverse the branch by 2325 // inserting a 0 at the beginning of the Cond vector. 2326 // 2327 bool HexagonInstrInfo:: 2328 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2329 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 2330 Cond.erase(Cond.begin()); 2331 } else { 2332 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0)); 2333 } 2334 return false; 2335 } 2336 2337 2338 bool HexagonInstrInfo:: 2339 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs, 2340 const BranchProbability &Probability) const { 2341 return (NumInstrs <= 4); 2342 } 2343 2344 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { 2345 switch (MI->getOpcode()) { 2346 default: return false; 2347 case Hexagon::DEALLOC_RET_V4 : 2348 case Hexagon::DEALLOC_RET_cPt_V4 : 2349 case Hexagon::DEALLOC_RET_cNotPt_V4 : 2350 case Hexagon::DEALLOC_RET_cdnPnt_V4 : 2351 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 : 2352 case Hexagon::DEALLOC_RET_cdnPt_V4 : 2353 case Hexagon::DEALLOC_RET_cNotdnPt_V4 : 2354 return true; 2355 } 2356 } 2357 2358 2359 bool HexagonInstrInfo:: 2360 isValidOffset(const int Opcode, const int Offset) const { 2361 // This function is to check whether the "Offset" is in the correct range of 2362 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is 2363 // inserted to calculate the final address. Due to this reason, the function 2364 // assumes that the "Offset" has correct alignment. 2365 2366 switch(Opcode) { 2367 2368 case Hexagon::LDriw: 2369 case Hexagon::LDriw_f: 2370 case Hexagon::STriw: 2371 case Hexagon::STriw_f: 2372 assert((Offset % 4 == 0) && "Offset has incorrect alignment"); 2373 return (Offset >= Hexagon_MEMW_OFFSET_MIN) && 2374 (Offset <= Hexagon_MEMW_OFFSET_MAX); 2375 2376 case Hexagon::LDrid: 2377 case Hexagon::LDrid_f: 2378 case Hexagon::STrid: 2379 case Hexagon::STrid_f: 2380 assert((Offset % 8 == 0) && "Offset has incorrect alignment"); 2381 return (Offset >= Hexagon_MEMD_OFFSET_MIN) && 2382 (Offset <= Hexagon_MEMD_OFFSET_MAX); 2383 2384 case Hexagon::LDrih: 2385 case Hexagon::LDriuh: 2386 case Hexagon::STrih: 2387 assert((Offset % 2 == 0) && "Offset has incorrect alignment"); 2388 return (Offset >= Hexagon_MEMH_OFFSET_MIN) && 2389 (Offset <= Hexagon_MEMH_OFFSET_MAX); 2390 2391 case Hexagon::LDrib: 2392 case Hexagon::STrib: 2393 case Hexagon::LDriub: 2394 return (Offset >= Hexagon_MEMB_OFFSET_MIN) && 2395 (Offset <= Hexagon_MEMB_OFFSET_MAX); 2396 2397 case Hexagon::ADD_ri: 2398 case Hexagon::TFR_FI: 2399 return (Offset >= Hexagon_ADDI_OFFSET_MIN) && 2400 (Offset <= Hexagon_ADDI_OFFSET_MAX); 2401 2402 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 2403 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2404 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2405 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2406 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2407 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2408 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2409 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 2410 case Hexagon::MEMw_ADDi_MEM_V4 : 2411 case Hexagon::MEMw_SUBi_MEM_V4 : 2412 case Hexagon::MEMw_ADDr_MEM_V4 : 2413 case Hexagon::MEMw_SUBr_MEM_V4 : 2414 case Hexagon::MEMw_ANDr_MEM_V4 : 2415 case Hexagon::MEMw_ORr_MEM_V4 : 2416 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." ); 2417 return (0 <= Offset && Offset <= 255); 2418 2419 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 2420 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2421 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2422 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2423 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2424 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2425 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2426 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 2427 case Hexagon::MEMh_ADDi_MEM_V4 : 2428 case Hexagon::MEMh_SUBi_MEM_V4 : 2429 case Hexagon::MEMh_ADDr_MEM_V4 : 2430 case Hexagon::MEMh_SUBr_MEM_V4 : 2431 case Hexagon::MEMh_ANDr_MEM_V4 : 2432 case Hexagon::MEMh_ORr_MEM_V4 : 2433 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." ); 2434 return (0 <= Offset && Offset <= 127); 2435 2436 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 2437 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2438 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2439 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2440 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2441 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2442 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2443 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 2444 case Hexagon::MEMb_ADDi_MEM_V4 : 2445 case Hexagon::MEMb_SUBi_MEM_V4 : 2446 case Hexagon::MEMb_ADDr_MEM_V4 : 2447 case Hexagon::MEMb_SUBr_MEM_V4 : 2448 case Hexagon::MEMb_ANDr_MEM_V4 : 2449 case Hexagon::MEMb_ORr_MEM_V4 : 2450 return (0 <= Offset && Offset <= 63); 2451 2452 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of 2453 // any size. Later pass knows how to handle it. 2454 case Hexagon::STriw_pred: 2455 case Hexagon::LDriw_pred: 2456 return true; 2457 2458 // INLINEASM is very special. 2459 case Hexagon::INLINEASM: 2460 return true; 2461 } 2462 2463 llvm_unreachable("No offset range is defined for this opcode. " 2464 "Please define it in the above switch statement!"); 2465 } 2466 2467 2468 // 2469 // Check if the Offset is a valid auto-inc imm by Load/Store Type. 2470 // 2471 bool HexagonInstrInfo:: 2472 isValidAutoIncImm(const EVT VT, const int Offset) const { 2473 2474 if (VT == MVT::i64) { 2475 return (Offset >= Hexagon_MEMD_AUTOINC_MIN && 2476 Offset <= Hexagon_MEMD_AUTOINC_MAX && 2477 (Offset & 0x7) == 0); 2478 } 2479 if (VT == MVT::i32) { 2480 return (Offset >= Hexagon_MEMW_AUTOINC_MIN && 2481 Offset <= Hexagon_MEMW_AUTOINC_MAX && 2482 (Offset & 0x3) == 0); 2483 } 2484 if (VT == MVT::i16) { 2485 return (Offset >= Hexagon_MEMH_AUTOINC_MIN && 2486 Offset <= Hexagon_MEMH_AUTOINC_MAX && 2487 (Offset & 0x1) == 0); 2488 } 2489 if (VT == MVT::i8) { 2490 return (Offset >= Hexagon_MEMB_AUTOINC_MIN && 2491 Offset <= Hexagon_MEMB_AUTOINC_MAX); 2492 } 2493 llvm_unreachable("Not an auto-inc opc!"); 2494 } 2495 2496 2497 bool HexagonInstrInfo:: 2498 isMemOp(const MachineInstr *MI) const { 2499 switch (MI->getOpcode()) 2500 { 2501 default: return false; 2502 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 2503 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2504 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2505 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2506 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2507 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2508 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2509 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 2510 case Hexagon::MEMw_ADDi_MEM_V4 : 2511 case Hexagon::MEMw_SUBi_MEM_V4 : 2512 case Hexagon::MEMw_ADDr_MEM_V4 : 2513 case Hexagon::MEMw_SUBr_MEM_V4 : 2514 case Hexagon::MEMw_ANDr_MEM_V4 : 2515 case Hexagon::MEMw_ORr_MEM_V4 : 2516 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 2517 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2518 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2519 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2520 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2521 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2522 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2523 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 2524 case Hexagon::MEMh_ADDi_MEM_V4 : 2525 case Hexagon::MEMh_SUBi_MEM_V4 : 2526 case Hexagon::MEMh_ADDr_MEM_V4 : 2527 case Hexagon::MEMh_SUBr_MEM_V4 : 2528 case Hexagon::MEMh_ANDr_MEM_V4 : 2529 case Hexagon::MEMh_ORr_MEM_V4 : 2530 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 2531 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2532 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2533 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2534 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2535 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2536 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2537 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 2538 case Hexagon::MEMb_ADDi_MEM_V4 : 2539 case Hexagon::MEMb_SUBi_MEM_V4 : 2540 case Hexagon::MEMb_ADDr_MEM_V4 : 2541 case Hexagon::MEMb_SUBr_MEM_V4 : 2542 case Hexagon::MEMb_ANDr_MEM_V4 : 2543 case Hexagon::MEMb_ORr_MEM_V4 : 2544 return true; 2545 } 2546 } 2547 2548 2549 bool HexagonInstrInfo:: 2550 isSpillPredRegOp(const MachineInstr *MI) const { 2551 switch (MI->getOpcode()) { 2552 default: return false; 2553 case Hexagon::STriw_pred : 2554 case Hexagon::LDriw_pred : 2555 return true; 2556 } 2557 } 2558 2559 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { 2560 switch (MI->getOpcode()) { 2561 default: return false; 2562 case Hexagon::CMPEQrr: 2563 case Hexagon::CMPEQri: 2564 case Hexagon::CMPLTrr: 2565 case Hexagon::CMPGTrr: 2566 case Hexagon::CMPGTri: 2567 case Hexagon::CMPLTUrr: 2568 case Hexagon::CMPGTUrr: 2569 case Hexagon::CMPGTUri: 2570 case Hexagon::CMPGEri: 2571 case Hexagon::CMPGEUri: 2572 return true; 2573 } 2574 } 2575 2576 bool HexagonInstrInfo:: 2577 isConditionalTransfer (const MachineInstr *MI) const { 2578 switch (MI->getOpcode()) { 2579 default: return false; 2580 case Hexagon::TFR_cPt: 2581 case Hexagon::TFR_cNotPt: 2582 case Hexagon::TFRI_cPt: 2583 case Hexagon::TFRI_cNotPt: 2584 case Hexagon::TFR_cdnPt: 2585 case Hexagon::TFR_cdnNotPt: 2586 case Hexagon::TFRI_cdnPt: 2587 case Hexagon::TFRI_cdnNotPt: 2588 return true; 2589 } 2590 } 2591 2592 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { 2593 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2594 switch (MI->getOpcode()) 2595 { 2596 default: return false; 2597 case Hexagon::ADD_ri_cPt: 2598 case Hexagon::ADD_ri_cNotPt: 2599 case Hexagon::ADD_rr_cPt: 2600 case Hexagon::ADD_rr_cNotPt: 2601 case Hexagon::XOR_rr_cPt: 2602 case Hexagon::XOR_rr_cNotPt: 2603 case Hexagon::AND_rr_cPt: 2604 case Hexagon::AND_rr_cNotPt: 2605 case Hexagon::OR_rr_cPt: 2606 case Hexagon::OR_rr_cNotPt: 2607 case Hexagon::SUB_rr_cPt: 2608 case Hexagon::SUB_rr_cNotPt: 2609 case Hexagon::COMBINE_rr_cPt: 2610 case Hexagon::COMBINE_rr_cNotPt: 2611 return true; 2612 case Hexagon::ASLH_cPt_V4: 2613 case Hexagon::ASLH_cNotPt_V4: 2614 case Hexagon::ASRH_cPt_V4: 2615 case Hexagon::ASRH_cNotPt_V4: 2616 case Hexagon::SXTB_cPt_V4: 2617 case Hexagon::SXTB_cNotPt_V4: 2618 case Hexagon::SXTH_cPt_V4: 2619 case Hexagon::SXTH_cNotPt_V4: 2620 case Hexagon::ZXTB_cPt_V4: 2621 case Hexagon::ZXTB_cNotPt_V4: 2622 case Hexagon::ZXTH_cPt_V4: 2623 case Hexagon::ZXTH_cNotPt_V4: 2624 return QRI.Subtarget.hasV4TOps(); 2625 } 2626 } 2627 2628 bool HexagonInstrInfo:: 2629 isConditionalLoad (const MachineInstr* MI) const { 2630 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2631 switch (MI->getOpcode()) 2632 { 2633 default: return false; 2634 case Hexagon::LDrid_cPt : 2635 case Hexagon::LDrid_cNotPt : 2636 case Hexagon::LDrid_indexed_cPt : 2637 case Hexagon::LDrid_indexed_cNotPt : 2638 case Hexagon::LDriw_cPt : 2639 case Hexagon::LDriw_cNotPt : 2640 case Hexagon::LDriw_indexed_cPt : 2641 case Hexagon::LDriw_indexed_cNotPt : 2642 case Hexagon::LDrih_cPt : 2643 case Hexagon::LDrih_cNotPt : 2644 case Hexagon::LDrih_indexed_cPt : 2645 case Hexagon::LDrih_indexed_cNotPt : 2646 case Hexagon::LDrib_cPt : 2647 case Hexagon::LDrib_cNotPt : 2648 case Hexagon::LDrib_indexed_cPt : 2649 case Hexagon::LDrib_indexed_cNotPt : 2650 case Hexagon::LDriuh_cPt : 2651 case Hexagon::LDriuh_cNotPt : 2652 case Hexagon::LDriuh_indexed_cPt : 2653 case Hexagon::LDriuh_indexed_cNotPt : 2654 case Hexagon::LDriub_cPt : 2655 case Hexagon::LDriub_cNotPt : 2656 case Hexagon::LDriub_indexed_cPt : 2657 case Hexagon::LDriub_indexed_cNotPt : 2658 return true; 2659 case Hexagon::POST_LDrid_cPt : 2660 case Hexagon::POST_LDrid_cNotPt : 2661 case Hexagon::POST_LDriw_cPt : 2662 case Hexagon::POST_LDriw_cNotPt : 2663 case Hexagon::POST_LDrih_cPt : 2664 case Hexagon::POST_LDrih_cNotPt : 2665 case Hexagon::POST_LDrib_cPt : 2666 case Hexagon::POST_LDrib_cNotPt : 2667 case Hexagon::POST_LDriuh_cPt : 2668 case Hexagon::POST_LDriuh_cNotPt : 2669 case Hexagon::POST_LDriub_cPt : 2670 case Hexagon::POST_LDriub_cNotPt : 2671 return QRI.Subtarget.hasV4TOps(); 2672 case Hexagon::LDrid_indexed_cPt_V4 : 2673 case Hexagon::LDrid_indexed_cNotPt_V4 : 2674 case Hexagon::LDrid_indexed_shl_cPt_V4 : 2675 case Hexagon::LDrid_indexed_shl_cNotPt_V4 : 2676 case Hexagon::LDrib_indexed_cPt_V4 : 2677 case Hexagon::LDrib_indexed_cNotPt_V4 : 2678 case Hexagon::LDrib_indexed_shl_cPt_V4 : 2679 case Hexagon::LDrib_indexed_shl_cNotPt_V4 : 2680 case Hexagon::LDriub_indexed_cPt_V4 : 2681 case Hexagon::LDriub_indexed_cNotPt_V4 : 2682 case Hexagon::LDriub_indexed_shl_cPt_V4 : 2683 case Hexagon::LDriub_indexed_shl_cNotPt_V4 : 2684 case Hexagon::LDrih_indexed_cPt_V4 : 2685 case Hexagon::LDrih_indexed_cNotPt_V4 : 2686 case Hexagon::LDrih_indexed_shl_cPt_V4 : 2687 case Hexagon::LDrih_indexed_shl_cNotPt_V4 : 2688 case Hexagon::LDriuh_indexed_cPt_V4 : 2689 case Hexagon::LDriuh_indexed_cNotPt_V4 : 2690 case Hexagon::LDriuh_indexed_shl_cPt_V4 : 2691 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : 2692 case Hexagon::LDriw_indexed_cPt_V4 : 2693 case Hexagon::LDriw_indexed_cNotPt_V4 : 2694 case Hexagon::LDriw_indexed_shl_cPt_V4 : 2695 case Hexagon::LDriw_indexed_shl_cNotPt_V4 : 2696 return QRI.Subtarget.hasV4TOps(); 2697 } 2698 } 2699 2700 // Returns true if an instruction is a conditional store. 2701 // 2702 // Note: It doesn't include conditional new-value stores as they can't be 2703 // converted to .new predicate. 2704 // 2705 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ] 2706 // ^ ^ 2707 // / \ (not OK. it will cause new-value store to be 2708 // / X conditional on p0.new while R2 producer is 2709 // / \ on p0) 2710 // / \. 2711 // p.new store p.old NV store 2712 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new] 2713 // ^ ^ 2714 // \ / 2715 // \ / 2716 // \ / 2717 // p.old store 2718 // [if (p0)memw(R0+#0)=R2] 2719 // 2720 // The above diagram shows the steps involoved in the conversion of a predicated 2721 // store instruction to its .new predicated new-value form. 2722 // 2723 // The following set of instructions further explains the scenario where 2724 // conditional new-value store becomes invalid when promoted to .new predicate 2725 // form. 2726 // 2727 // { 1) if (p0) r0 = add(r1, r2) 2728 // 2) p0 = cmp.eq(r3, #0) } 2729 // 2730 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with 2731 // the first two instructions because in instr 1, r0 is conditional on old value 2732 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which 2733 // is not valid for new-value stores. 2734 bool HexagonInstrInfo:: 2735 isConditionalStore (const MachineInstr* MI) const { 2736 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2737 switch (MI->getOpcode()) 2738 { 2739 default: return false; 2740 case Hexagon::STrib_imm_cPt_V4 : 2741 case Hexagon::STrib_imm_cNotPt_V4 : 2742 case Hexagon::STrib_indexed_shl_cPt_V4 : 2743 case Hexagon::STrib_indexed_shl_cNotPt_V4 : 2744 case Hexagon::STrib_cPt : 2745 case Hexagon::STrib_cNotPt : 2746 case Hexagon::POST_STbri_cPt : 2747 case Hexagon::POST_STbri_cNotPt : 2748 case Hexagon::STrid_indexed_cPt : 2749 case Hexagon::STrid_indexed_cNotPt : 2750 case Hexagon::STrid_indexed_shl_cPt_V4 : 2751 case Hexagon::POST_STdri_cPt : 2752 case Hexagon::POST_STdri_cNotPt : 2753 case Hexagon::STrih_cPt : 2754 case Hexagon::STrih_cNotPt : 2755 case Hexagon::STrih_indexed_cPt : 2756 case Hexagon::STrih_indexed_cNotPt : 2757 case Hexagon::STrih_imm_cPt_V4 : 2758 case Hexagon::STrih_imm_cNotPt_V4 : 2759 case Hexagon::STrih_indexed_shl_cPt_V4 : 2760 case Hexagon::STrih_indexed_shl_cNotPt_V4 : 2761 case Hexagon::POST_SThri_cPt : 2762 case Hexagon::POST_SThri_cNotPt : 2763 case Hexagon::STriw_cPt : 2764 case Hexagon::STriw_cNotPt : 2765 case Hexagon::STriw_indexed_cPt : 2766 case Hexagon::STriw_indexed_cNotPt : 2767 case Hexagon::STriw_imm_cPt_V4 : 2768 case Hexagon::STriw_imm_cNotPt_V4 : 2769 case Hexagon::STriw_indexed_shl_cPt_V4 : 2770 case Hexagon::STriw_indexed_shl_cNotPt_V4 : 2771 case Hexagon::POST_STwri_cPt : 2772 case Hexagon::POST_STwri_cNotPt : 2773 return QRI.Subtarget.hasV4TOps(); 2774 2775 // V4 global address store before promoting to dot new. 2776 case Hexagon::STrid_GP_cPt_V4 : 2777 case Hexagon::STrid_GP_cNotPt_V4 : 2778 case Hexagon::STrib_GP_cPt_V4 : 2779 case Hexagon::STrib_GP_cNotPt_V4 : 2780 case Hexagon::STrih_GP_cPt_V4 : 2781 case Hexagon::STrih_GP_cNotPt_V4 : 2782 case Hexagon::STriw_GP_cPt_V4 : 2783 case Hexagon::STriw_GP_cNotPt_V4 : 2784 case Hexagon::STd_GP_cPt_V4 : 2785 case Hexagon::STd_GP_cNotPt_V4 : 2786 case Hexagon::STb_GP_cPt_V4 : 2787 case Hexagon::STb_GP_cNotPt_V4 : 2788 case Hexagon::STh_GP_cPt_V4 : 2789 case Hexagon::STh_GP_cNotPt_V4 : 2790 case Hexagon::STw_GP_cPt_V4 : 2791 case Hexagon::STw_GP_cNotPt_V4 : 2792 return QRI.Subtarget.hasV4TOps(); 2793 2794 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded 2795 // from the "Conditional Store" list. Because a predicated new value store 2796 // would NOT be promoted to a double dot new store. See diagram below: 2797 // This function returns yes for those stores that are predicated but not 2798 // yet promoted to predicate dot new instructions. 2799 // 2800 // +---------------------+ 2801 // /-----| if (p0) memw(..)=r0 |---------\~ 2802 // || +---------------------+ || 2803 // promote || /\ /\ || promote 2804 // || /||\ /||\ || 2805 // \||/ demote || \||/ 2806 // \/ || || \/ 2807 // +-------------------------+ || +-------------------------+ 2808 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new | 2809 // +-------------------------+ || +-------------------------+ 2810 // || || || 2811 // || demote \||/ 2812 // promote || \/ NOT possible 2813 // || || /\~ 2814 // \||/ || /||\~ 2815 // \/ || || 2816 // +-----------------------------+ 2817 // | if (p0.new) memw(..)=r0.new | 2818 // +-----------------------------+ 2819 // Double Dot New Store 2820 // 2821 } 2822 } 2823 2824 2825 2826 DFAPacketizer *HexagonInstrInfo:: 2827 CreateTargetScheduleState(const TargetMachine *TM, 2828 const ScheduleDAG *DAG) const { 2829 const InstrItineraryData *II = TM->getInstrItineraryData(); 2830 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II); 2831 } 2832 2833 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 2834 const MachineBasicBlock *MBB, 2835 const MachineFunction &MF) const { 2836 // Debug info is never a scheduling boundary. It's necessary to be explicit 2837 // due to the special treatment of IT instructions below, otherwise a 2838 // dbg_value followed by an IT will result in the IT instruction being 2839 // considered a scheduling hazard, which is wrong. It should be the actual 2840 // instruction preceding the dbg_value instruction(s), just like it is 2841 // when debug info is not present. 2842 if (MI->isDebugValue()) 2843 return false; 2844 2845 // Terminators and labels can't be scheduled around. 2846 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm()) 2847 return true; 2848 2849 return false; 2850 } 2851
