1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is responsible for emitting a description of a target 11 // register file for a code generator. It uses instances of the Register, 12 // RegisterAliases, and RegisterClass classes to gather this information. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenRegisters.h" 17 #include "CodeGenTarget.h" 18 #include "SequenceToOffsetTable.h" 19 #include "llvm/ADT/BitVector.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/ADT/Twine.h" 23 #include "llvm/Support/Format.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 #include <set> 29 #include <vector> 30 using namespace llvm; 31 32 namespace { 33 class RegisterInfoEmitter { 34 RecordKeeper &Records; 35 public: 36 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} 37 38 // runEnums - Print out enum values for all of the registers. 39 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 40 41 // runMCDesc - Print out MC register descriptions. 42 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 43 44 // runTargetHeader - Emit a header fragment for the register info emitter. 45 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 46 CodeGenRegBank &Bank); 47 48 // runTargetDesc - Output the target register and register file descriptions. 49 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 50 CodeGenRegBank &Bank); 51 52 // run - Output the register file description. 53 void run(raw_ostream &o); 54 55 private: 56 void EmitRegMapping(raw_ostream &o, 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor); 58 void EmitRegMappingTables(raw_ostream &o, 59 const std::vector<CodeGenRegister*> &Regs, 60 bool isCtor); 61 void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target); 62 63 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 64 const std::string &ClassName); 65 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 66 const std::string &ClassName); 67 }; 68 } // End anonymous namespace 69 70 // runEnums - Print out enum values for all of the registers. 71 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 72 CodeGenTarget &Target, CodeGenRegBank &Bank) { 73 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 74 75 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 77 78 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 79 80 emitSourceFileHeader("Target Register Enum Values", OS); 81 82 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 83 OS << "#undef GET_REGINFO_ENUM\n"; 84 85 OS << "namespace llvm {\n\n"; 86 87 OS << "class MCRegisterClass;\n" 88 << "extern const MCRegisterClass " << Namespace 89 << "MCRegisterClasses[];\n\n"; 90 91 if (!Namespace.empty()) 92 OS << "namespace " << Namespace << " {\n"; 93 OS << "enum {\n NoRegister,\n"; 94 95 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 96 OS << " " << Registers[i]->getName() << " = " << 97 Registers[i]->EnumValue << ",\n"; 98 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 99 "Register enum value mismatch!"); 100 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 101 OS << "};\n"; 102 if (!Namespace.empty()) 103 OS << "}\n"; 104 105 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses(); 106 if (!RegisterClasses.empty()) { 107 108 // RegisterClass enums are stored as uint16_t in the tables. 109 assert(RegisterClasses.size() <= 0xffff && 110 "Too many register classes to fit in tables"); 111 112 OS << "\n// Register classes\n"; 113 if (!Namespace.empty()) 114 OS << "namespace " << Namespace << " {\n"; 115 OS << "enum {\n"; 116 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 117 if (i) OS << ",\n"; 118 OS << " " << RegisterClasses[i]->getName() << "RegClassID"; 119 OS << " = " << i; 120 } 121 OS << "\n };\n"; 122 if (!Namespace.empty()) 123 OS << "}\n"; 124 } 125 126 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); 127 // If the only definition is the default NoRegAltName, we don't need to 128 // emit anything. 129 if (RegAltNameIndices.size() > 1) { 130 OS << "\n// Register alternate name indices\n"; 131 if (!Namespace.empty()) 132 OS << "namespace " << Namespace << " {\n"; 133 OS << "enum {\n"; 134 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 135 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 136 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 137 OS << "};\n"; 138 if (!Namespace.empty()) 139 OS << "}\n"; 140 } 141 142 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices(); 143 if (!SubRegIndices.empty()) { 144 OS << "\n// Subregister indices\n"; 145 std::string Namespace = 146 SubRegIndices[0]->getNamespace(); 147 if (!Namespace.empty()) 148 OS << "namespace " << Namespace << " {\n"; 149 OS << "enum {\n NoSubRegister,\n"; 150 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 151 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 152 OS << " NUM_TARGET_SUBREGS\n};\n"; 153 if (!Namespace.empty()) 154 OS << "}\n"; 155 } 156 157 OS << "} // End llvm namespace \n"; 158 OS << "#endif // GET_REGINFO_ENUM\n\n"; 159 } 160 161 void RegisterInfoEmitter:: 162 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 163 const std::string &ClassName) { 164 unsigned NumRCs = RegBank.getRegClasses().size(); 165 unsigned NumSets = RegBank.getNumRegPressureSets(); 166 167 OS << "/// Get the weight in units of pressure for this register class.\n" 168 << "const RegClassWeight &" << ClassName << "::\n" 169 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 170 << " static const RegClassWeight RCWeightTable[] = {\n"; 171 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 172 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; 173 const CodeGenRegister::Set &Regs = RC.getMembers(); 174 if (Regs.empty()) 175 OS << " {0, 0"; 176 else { 177 std::vector<unsigned> RegUnits; 178 RC.buildRegUnitSet(RegUnits); 179 OS << " {" << (*Regs.begin())->getWeight(RegBank) 180 << ", " << RegBank.getRegUnitSetWeight(RegUnits); 181 } 182 OS << "}, \t// " << RC.getName() << "\n"; 183 } 184 OS << " {0, 0} };\n" 185 << " return RCWeightTable[RC->getID()];\n" 186 << "}\n\n"; 187 188 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 189 // bother generating a table. 190 bool RegUnitsHaveUnitWeight = true; 191 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 192 UnitIdx < UnitEnd; ++UnitIdx) { 193 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 194 RegUnitsHaveUnitWeight = false; 195 } 196 OS << "/// Get the weight in units of pressure for this register unit.\n" 197 << "unsigned " << ClassName << "::\n" 198 << "getRegUnitWeight(unsigned RegUnit) const {\n" 199 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 200 << " && \"invalid register unit\");\n"; 201 if (!RegUnitsHaveUnitWeight) { 202 OS << " static const uint8_t RUWeightTable[] = {\n "; 203 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 204 UnitIdx < UnitEnd; ++UnitIdx) { 205 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 206 assert(RU.Weight < 256 && "RegUnit too heavy"); 207 OS << RU.Weight << ", "; 208 } 209 OS << "0 };\n" 210 << " return RUWeightTable[RegUnit];\n"; 211 } 212 else { 213 OS << " // All register units have unit weight.\n" 214 << " return 1;\n"; 215 } 216 OS << "}\n\n"; 217 218 OS << "\n" 219 << "// Get the number of dimensions of register pressure.\n" 220 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 221 << " return " << NumSets << ";\n}\n\n"; 222 223 OS << "// Get the name of this register unit pressure set.\n" 224 << "const char *" << ClassName << "::\n" 225 << "getRegPressureSetName(unsigned Idx) const {\n" 226 << " static const char *PressureNameTable[] = {\n"; 227 for (unsigned i = 0; i < NumSets; ++i ) { 228 OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n"; 229 } 230 OS << " 0 };\n" 231 << " return PressureNameTable[Idx];\n" 232 << "}\n\n"; 233 234 OS << "// Get the register unit pressure limit for this dimension.\n" 235 << "// This limit must be adjusted dynamically for reserved registers.\n" 236 << "unsigned " << ClassName << "::\n" 237 << "getRegPressureSetLimit(unsigned Idx) const {\n" 238 << " static const unsigned PressureLimitTable[] = {\n"; 239 for (unsigned i = 0; i < NumSets; ++i ) { 240 const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i); 241 OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units) 242 << ", \t// " << i << ": " << RegUnits.Name << "\n"; 243 } 244 OS << " 0 };\n" 245 << " return PressureLimitTable[Idx];\n" 246 << "}\n\n"; 247 248 // This table may be larger than NumRCs if some register units needed a list 249 // of unit sets that did not correspond to a register class. 250 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 251 OS << "/// Table of pressure sets per register class or unit.\n" 252 << "static const int RCSetsTable[] = {\n "; 253 std::vector<unsigned> RCSetStarts(NumRCUnitSets); 254 for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) { 255 RCSetStarts[i] = StartIdx; 256 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 257 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 258 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 259 OS << *PSetI << ", "; 260 ++StartIdx; 261 } 262 OS << "-1, \t// #" << RCSetStarts[i] << " "; 263 if (i < NumRCs) 264 OS << RegBank.getRegClasses()[i]->getName(); 265 else { 266 OS << "inferred"; 267 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 268 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 269 OS << "~" << RegBank.getRegPressureSet(*PSetI).Name; 270 } 271 } 272 OS << "\n "; 273 ++StartIdx; 274 } 275 OS << "-1 };\n\n"; 276 277 OS << "/// Get the dimensions of register pressure impacted by this " 278 << "register class.\n" 279 << "/// Returns a -1 terminated array of pressure set IDs\n" 280 << "const int* " << ClassName << "::\n" 281 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 282 OS << " static const unsigned RCSetStartTable[] = {\n "; 283 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 284 OS << RCSetStarts[i] << ","; 285 } 286 OS << "0 };\n" 287 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n" 288 << " return &RCSetsTable[SetListStart];\n" 289 << "}\n\n"; 290 291 OS << "/// Get the dimensions of register pressure impacted by this " 292 << "register unit.\n" 293 << "/// Returns a -1 terminated array of pressure set IDs\n" 294 << "const int* " << ClassName << "::\n" 295 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 296 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 297 << " && \"invalid register unit\");\n"; 298 OS << " static const unsigned RUSetStartTable[] = {\n "; 299 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 300 UnitIdx < UnitEnd; ++UnitIdx) { 301 OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ","; 302 } 303 OS << "0 };\n" 304 << " unsigned SetListStart = RUSetStartTable[RegUnit];\n" 305 << " return &RCSetsTable[SetListStart];\n" 306 << "}\n\n"; 307 } 308 309 void 310 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS, 311 const std::vector<CodeGenRegister*> &Regs, 312 bool isCtor) { 313 // Collect all information about dwarf register numbers 314 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 315 DwarfRegNumsMapTy DwarfRegNums; 316 317 // First, just pull all provided information to the map 318 unsigned maxLength = 0; 319 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 320 Record *Reg = Regs[i]->TheDef; 321 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 322 maxLength = std::max((size_t)maxLength, RegNums.size()); 323 if (DwarfRegNums.count(Reg)) 324 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 325 getQualifiedName(Reg) + "specified multiple times"); 326 DwarfRegNums[Reg] = RegNums; 327 } 328 329 if (!maxLength) 330 return; 331 332 // Now we know maximal length of number list. Append -1's, where needed 333 for (DwarfRegNumsMapTy::iterator 334 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 335 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 336 I->second.push_back(-1); 337 338 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 339 340 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 341 342 // Emit reverse information about the dwarf register numbers. 343 for (unsigned j = 0; j < 2; ++j) { 344 for (unsigned i = 0, e = maxLength; i != e; ++i) { 345 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 346 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 347 OS << i << "Dwarf2L[]"; 348 349 if (!isCtor) { 350 OS << " = {\n"; 351 352 // Store the mapping sorted by the LLVM reg num so lookup can be done 353 // with a binary search. 354 std::map<uint64_t, Record*> Dwarf2LMap; 355 for (DwarfRegNumsMapTy::iterator 356 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 357 int DwarfRegNo = I->second[i]; 358 if (DwarfRegNo < 0) 359 continue; 360 Dwarf2LMap[DwarfRegNo] = I->first; 361 } 362 363 for (std::map<uint64_t, Record*>::iterator 364 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 365 OS << " { " << I->first << "U, " << getQualifiedName(I->second) 366 << " },\n"; 367 368 OS << "};\n"; 369 } else { 370 OS << ";\n"; 371 } 372 373 // We have to store the size in a const global, it's used in multiple 374 // places. 375 OS << "extern const unsigned " << Namespace 376 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 377 if (!isCtor) 378 OS << " = sizeof(" << Namespace 379 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 380 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 381 else 382 OS << ";\n\n"; 383 } 384 } 385 386 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 387 Record *Reg = Regs[i]->TheDef; 388 const RecordVal *V = Reg->getValue("DwarfAlias"); 389 if (!V || !V->getValue()) 390 continue; 391 392 DefInit *DI = cast<DefInit>(V->getValue()); 393 Record *Alias = DI->getDef(); 394 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 395 } 396 397 // Emit information about the dwarf register numbers. 398 for (unsigned j = 0; j < 2; ++j) { 399 for (unsigned i = 0, e = maxLength; i != e; ++i) { 400 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 401 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 402 OS << i << "L2Dwarf[]"; 403 if (!isCtor) { 404 OS << " = {\n"; 405 // Store the mapping sorted by the Dwarf reg num so lookup can be done 406 // with a binary search. 407 for (DwarfRegNumsMapTy::iterator 408 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 409 int RegNo = I->second[i]; 410 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 411 continue; 412 413 OS << " { " << getQualifiedName(I->first) << ", " << RegNo 414 << "U },\n"; 415 } 416 OS << "};\n"; 417 } else { 418 OS << ";\n"; 419 } 420 421 // We have to store the size in a const global, it's used in multiple 422 // places. 423 OS << "extern const unsigned " << Namespace 424 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 425 if (!isCtor) 426 OS << " = sizeof(" << Namespace 427 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 428 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n"; 429 else 430 OS << ";\n\n"; 431 } 432 } 433 } 434 435 void 436 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 437 const std::vector<CodeGenRegister*> &Regs, 438 bool isCtor) { 439 // Emit the initializer so the tables from EmitRegMappingTables get wired up 440 // to the MCRegisterInfo object. 441 unsigned maxLength = 0; 442 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 443 Record *Reg = Regs[i]->TheDef; 444 maxLength = std::max((size_t)maxLength, 445 Reg->getValueAsListOfInts("DwarfNumbers").size()); 446 } 447 448 if (!maxLength) 449 return; 450 451 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 452 453 // Emit reverse information about the dwarf register numbers. 454 for (unsigned j = 0; j < 2; ++j) { 455 OS << " switch ("; 456 if (j == 0) 457 OS << "DwarfFlavour"; 458 else 459 OS << "EHFlavour"; 460 OS << ") {\n" 461 << " default:\n" 462 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 463 464 for (unsigned i = 0, e = maxLength; i != e; ++i) { 465 OS << " case " << i << ":\n"; 466 OS << " "; 467 if (!isCtor) 468 OS << "RI->"; 469 std::string Tmp; 470 raw_string_ostream(Tmp) << Namespace 471 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 472 << "Dwarf2L"; 473 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 474 if (j == 0) 475 OS << "false"; 476 else 477 OS << "true"; 478 OS << ");\n"; 479 OS << " break;\n"; 480 } 481 OS << " }\n"; 482 } 483 484 // Emit information about the dwarf register numbers. 485 for (unsigned j = 0; j < 2; ++j) { 486 OS << " switch ("; 487 if (j == 0) 488 OS << "DwarfFlavour"; 489 else 490 OS << "EHFlavour"; 491 OS << ") {\n" 492 << " default:\n" 493 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 494 495 for (unsigned i = 0, e = maxLength; i != e; ++i) { 496 OS << " case " << i << ":\n"; 497 OS << " "; 498 if (!isCtor) 499 OS << "RI->"; 500 std::string Tmp; 501 raw_string_ostream(Tmp) << Namespace 502 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 503 << "L2Dwarf"; 504 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 505 if (j == 0) 506 OS << "false"; 507 else 508 OS << "true"; 509 OS << ");\n"; 510 OS << " break;\n"; 511 } 512 OS << " }\n"; 513 } 514 } 515 516 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 517 // Width is the number of bits per hex number. 518 static void printBitVectorAsHex(raw_ostream &OS, 519 const BitVector &Bits, 520 unsigned Width) { 521 assert(Width <= 32 && "Width too large"); 522 unsigned Digits = (Width + 3) / 4; 523 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 524 unsigned Value = 0; 525 for (unsigned j = 0; j != Width && i + j != e; ++j) 526 Value |= Bits.test(i + j) << j; 527 OS << format("0x%0*x, ", Digits, Value); 528 } 529 } 530 531 // Helper to emit a set of bits into a constant byte array. 532 class BitVectorEmitter { 533 BitVector Values; 534 public: 535 void add(unsigned v) { 536 if (v >= Values.size()) 537 Values.resize(((v/8)+1)*8); // Round up to the next byte. 538 Values[v] = true; 539 } 540 541 void print(raw_ostream &OS) { 542 printBitVectorAsHex(OS, Values, 8); 543 } 544 }; 545 546 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 547 OS << getEnumName(VT); 548 } 549 550 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 551 OS << Idx->EnumValue; 552 } 553 554 // Differentially encoded register and regunit lists allow for better 555 // compression on regular register banks. The sequence is computed from the 556 // differential list as: 557 // 558 // out[0] = InitVal; 559 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 560 // 561 // The initial value depends on the specific list. The list is terminated by a 562 // 0 differential which means we can't encode repeated elements. 563 564 typedef SmallVector<uint16_t, 4> DiffVec; 565 566 // Differentially encode a sequence of numbers into V. The starting value and 567 // terminating 0 are not added to V, so it will have the same size as List. 568 static 569 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) { 570 assert(V.empty() && "Clear DiffVec before diffEncode."); 571 uint16_t Val = uint16_t(InitVal); 572 for (unsigned i = 0; i != List.size(); ++i) { 573 uint16_t Cur = List[i]; 574 V.push_back(Cur - Val); 575 Val = Cur; 576 } 577 return V; 578 } 579 580 template<typename Iter> 581 static 582 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 583 assert(V.empty() && "Clear DiffVec before diffEncode."); 584 uint16_t Val = uint16_t(InitVal); 585 for (Iter I = Begin; I != End; ++I) { 586 uint16_t Cur = (*I)->EnumValue; 587 V.push_back(Cur - Val); 588 Val = Cur; 589 } 590 return V; 591 } 592 593 static void printDiff16(raw_ostream &OS, uint16_t Val) { 594 OS << Val; 595 } 596 597 // Try to combine Idx's compose map into Vec if it is compatible. 598 // Return false if it's not possible. 599 static bool combine(const CodeGenSubRegIndex *Idx, 600 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 601 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 602 for (CodeGenSubRegIndex::CompMap::const_iterator 603 I = Map.begin(), E = Map.end(); I != E; ++I) { 604 CodeGenSubRegIndex *&Entry = Vec[I->first->EnumValue - 1]; 605 if (Entry && Entry != I->second) 606 return false; 607 } 608 609 // All entries are compatible. Make it so. 610 for (CodeGenSubRegIndex::CompMap::const_iterator 611 I = Map.begin(), E = Map.end(); I != E; ++I) 612 Vec[I->first->EnumValue - 1] = I->second; 613 return true; 614 } 615 616 static const char *getMinimalTypeForRange(uint64_t Range) { 617 assert(Range < 0xFFFFFFFFULL && "Enum too large"); 618 if (Range > 0xFFFF) 619 return "uint32_t"; 620 if (Range > 0xFF) 621 return "uint16_t"; 622 return "uint8_t"; 623 } 624 625 void 626 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 627 CodeGenRegBank &RegBank, 628 const std::string &ClName) { 629 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 630 OS << "unsigned " << ClName 631 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 632 633 // Many sub-register indexes are composition-compatible, meaning that 634 // 635 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 636 // 637 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 638 // The illegal entries can be use as wildcards to compress the table further. 639 640 // Map each Sub-register index to a compatible table row. 641 SmallVector<unsigned, 4> RowMap; 642 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 643 644 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 645 unsigned Found = ~0u; 646 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 647 if (combine(SubRegIndices[i], Rows[r])) { 648 Found = r; 649 break; 650 } 651 } 652 if (Found == ~0u) { 653 Found = Rows.size(); 654 Rows.resize(Found + 1); 655 Rows.back().resize(SubRegIndices.size()); 656 combine(SubRegIndices[i], Rows.back()); 657 } 658 RowMap.push_back(Found); 659 } 660 661 // Output the row map if there is multiple rows. 662 if (Rows.size() > 1) { 663 OS << " static const " << getMinimalTypeForRange(Rows.size()) 664 << " RowMap[" << SubRegIndices.size() << "] = {\n "; 665 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 666 OS << RowMap[i] << ", "; 667 OS << "\n };\n"; 668 } 669 670 // Output the rows. 671 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1) 672 << " Rows[" << Rows.size() << "][" << SubRegIndices.size() << "] = {\n"; 673 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 674 OS << " { "; 675 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 676 if (Rows[r][i]) 677 OS << Rows[r][i]->EnumValue << ", "; 678 else 679 OS << "0, "; 680 OS << "},\n"; 681 } 682 OS << " };\n\n"; 683 684 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n" 685 << " --IdxB; assert(IdxB < " << SubRegIndices.size() << ");\n"; 686 if (Rows.size() > 1) 687 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 688 else 689 OS << " return Rows[0][IdxB];\n"; 690 OS << "}\n\n"; 691 } 692 693 // 694 // runMCDesc - Print out MC register descriptions. 695 // 696 void 697 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 698 CodeGenRegBank &RegBank) { 699 emitSourceFileHeader("MC Register Information", OS); 700 701 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 702 OS << "#undef GET_REGINFO_MC_DESC\n"; 703 704 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 705 706 // The lists of sub-registers, super-registers, and overlaps all go in the 707 // same array. That allows us to share suffixes. 708 typedef std::vector<const CodeGenRegister*> RegVec; 709 710 // Differentially encoded lists. 711 SequenceToOffsetTable<DiffVec> DiffSeqs; 712 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 713 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 714 SmallVector<DiffVec, 4> OverlapLists(Regs.size()); 715 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 716 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 717 718 // Keep track of sub-register names as well. These are not differentially 719 // encoded. 720 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 721 SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs; 722 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 723 724 SequenceToOffsetTable<std::string> RegStrings; 725 726 // Precompute register lists for the SequenceToOffsetTable. 727 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 728 const CodeGenRegister *Reg = Regs[i]; 729 730 RegStrings.add(Reg->getName()); 731 732 // Compute the ordered sub-register list. 733 SetVector<const CodeGenRegister*> SR; 734 Reg->addSubRegsPreOrder(SR, RegBank); 735 diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end()); 736 DiffSeqs.add(SubRegLists[i]); 737 738 // Compute the corresponding sub-register indexes. 739 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 740 for (unsigned j = 0, je = SR.size(); j != je; ++j) 741 SRIs.push_back(Reg->getSubRegIndex(SR[j])); 742 SubRegIdxSeqs.add(SRIs); 743 744 // Super-registers are already computed. 745 const RegVec &SuperRegList = Reg->getSuperRegs(); 746 diffEncode(SuperRegLists[i], Reg->EnumValue, 747 SuperRegList.begin(), SuperRegList.end()); 748 DiffSeqs.add(SuperRegLists[i]); 749 750 // The list of overlaps doesn't need to have any particular order, and Reg 751 // itself must be omitted. 752 DiffVec &OverlapList = OverlapLists[i]; 753 CodeGenRegister::Set OSet; 754 Reg->computeOverlaps(OSet, RegBank); 755 OSet.erase(Reg); 756 diffEncode(OverlapList, Reg->EnumValue, OSet.begin(), OSet.end()); 757 DiffSeqs.add(OverlapList); 758 759 // Differentially encode the register unit list, seeded by register number. 760 // First compute a scale factor that allows more diff-lists to be reused: 761 // 762 // D0 -> (S0, S1) 763 // D1 -> (S2, S3) 764 // 765 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 766 // value for the differential decoder is the register number multiplied by 767 // the scale. 768 // 769 // Check the neighboring registers for arithmetic progressions. 770 unsigned ScaleA = ~0u, ScaleB = ~0u; 771 ArrayRef<unsigned> RUs = Reg->getNativeRegUnits(); 772 if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size()) 773 ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front(); 774 if (i+1 != Regs.size() && 775 Regs[i+1]->getNativeRegUnits().size() == RUs.size()) 776 ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front(); 777 unsigned Scale = std::min(ScaleB, ScaleA); 778 // Default the scale to 0 if it can't be encoded in 4 bits. 779 if (Scale >= 16) 780 Scale = 0; 781 RegUnitInitScale[i] = Scale; 782 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs)); 783 } 784 785 // Compute the final layout of the sequence table. 786 DiffSeqs.layout(); 787 SubRegIdxSeqs.layout(); 788 789 OS << "namespace llvm {\n\n"; 790 791 const std::string &TargetName = Target.getName(); 792 793 // Emit the shared table of differential lists. 794 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 795 DiffSeqs.emit(OS, printDiff16); 796 OS << "};\n\n"; 797 798 // Emit the table of sub-register indexes. 799 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 800 SubRegIdxSeqs.emit(OS, printSubRegIndex); 801 OS << "};\n\n"; 802 803 // Emit the string table. 804 RegStrings.layout(); 805 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 806 RegStrings.emit(OS, printChar); 807 OS << "};\n\n"; 808 809 OS << "extern const MCRegisterDesc " << TargetName 810 << "RegDesc[] = { // Descriptors\n"; 811 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 812 813 // Emit the register descriptors now. 814 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 815 const CodeGenRegister *Reg = Regs[i]; 816 OS << " { " << RegStrings.get(Reg->getName()) << ", " 817 << DiffSeqs.get(OverlapLists[i]) << ", " 818 << DiffSeqs.get(SubRegLists[i]) << ", " 819 << DiffSeqs.get(SuperRegLists[i]) << ", " 820 << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 821 << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n"; 822 } 823 OS << "};\n\n"; // End of register descriptors... 824 825 // Emit the table of register unit roots. Each regunit has one or two root 826 // registers. 827 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n"; 828 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 829 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 830 assert(!Roots.empty() && "All regunits must have a root register."); 831 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 832 OS << " { " << getQualifiedName(Roots.front()->TheDef); 833 for (unsigned r = 1; r != Roots.size(); ++r) 834 OS << ", " << getQualifiedName(Roots[r]->TheDef); 835 OS << " },\n"; 836 } 837 OS << "};\n\n"; 838 839 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 840 841 // Loop over all of the register classes... emitting each one. 842 OS << "namespace { // Register classes...\n"; 843 844 // Emit the register enum value arrays for each RegisterClass 845 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 846 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 847 ArrayRef<Record*> Order = RC.getOrder(); 848 849 // Give the register class a legal C name if it's anonymous. 850 std::string Name = RC.getName(); 851 852 // Emit the register list now. 853 OS << " // " << Name << " Register Class...\n" 854 << " const uint16_t " << Name 855 << "[] = {\n "; 856 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 857 Record *Reg = Order[i]; 858 OS << getQualifiedName(Reg) << ", "; 859 } 860 OS << "\n };\n\n"; 861 862 OS << " // " << Name << " Bit set.\n" 863 << " const uint8_t " << Name 864 << "Bits[] = {\n "; 865 BitVectorEmitter BVE; 866 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 867 Record *Reg = Order[i]; 868 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 869 } 870 BVE.print(OS); 871 OS << "\n };\n\n"; 872 873 } 874 OS << "}\n\n"; 875 876 OS << "extern const MCRegisterClass " << TargetName 877 << "MCRegisterClasses[] = {\n"; 878 879 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 880 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 881 882 // Asserts to make sure values will fit in table assuming types from 883 // MCRegisterInfo.h 884 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); 885 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); 886 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); 887 888 OS << " { " << '\"' << RC.getName() << "\", " 889 << RC.getName() << ", " << RC.getName() << "Bits, " 890 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 891 << RC.getQualifiedName() + "RegClassID" << ", " 892 << RC.SpillSize/8 << ", " 893 << RC.SpillAlignment/8 << ", " 894 << RC.CopyCost << ", " 895 << RC.Allocatable << " },\n"; 896 } 897 898 OS << "};\n\n"; 899 900 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 901 902 EmitRegMappingTables(OS, Regs, false); 903 904 // Emit Reg encoding table 905 OS << "extern const uint16_t " << TargetName; 906 OS << "RegEncodingTable[] = {\n"; 907 // Add entry for NoRegister 908 OS << " 0,\n"; 909 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 910 Record *Reg = Regs[i]->TheDef; 911 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 912 uint64_t Value = 0; 913 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 914 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 915 Value |= (uint64_t)B->getValue() << b; 916 } 917 OS << " " << Value << ",\n"; 918 } 919 OS << "};\n"; // End of HW encoding table 920 921 // MCRegisterInfo initialization routine. 922 OS << "static inline void Init" << TargetName 923 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 924 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n" 925 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 926 << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 927 << RegisterClasses.size() << ", " 928 << TargetName << "RegUnitRoots, " 929 << RegBank.getNumNativeRegUnits() << ", " 930 << TargetName << "RegDiffLists, " 931 << TargetName << "RegStrings, " 932 << TargetName << "SubRegIdxLists, " 933 << (SubRegIndices.size() + 1) << ",\n" 934 << " " << TargetName << "RegEncodingTable);\n\n"; 935 936 EmitRegMapping(OS, Regs, false); 937 938 OS << "}\n\n"; 939 940 OS << "} // End llvm namespace \n"; 941 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 942 } 943 944 void 945 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 946 CodeGenRegBank &RegBank) { 947 emitSourceFileHeader("Register Information Header Fragment", OS); 948 949 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 950 OS << "#undef GET_REGINFO_HEADER\n"; 951 952 const std::string &TargetName = Target.getName(); 953 std::string ClassName = TargetName + "GenRegisterInfo"; 954 955 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; 956 957 OS << "namespace llvm {\n\n"; 958 959 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 960 << " explicit " << ClassName 961 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n" 962 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 963 << " { return false; }\n"; 964 if (!RegBank.getSubRegIndices().empty()) { 965 OS << " virtual unsigned composeSubRegIndicesImpl" 966 << "(unsigned, unsigned) const;\n" 967 << " virtual const TargetRegisterClass *" 968 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"; 969 } 970 OS << " virtual const RegClassWeight &getRegClassWeight(" 971 << "const TargetRegisterClass *RC) const;\n" 972 << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n" 973 << " virtual unsigned getNumRegPressureSets() const;\n" 974 << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n" 975 << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n" 976 << " virtual const int *getRegClassPressureSets(" 977 << "const TargetRegisterClass *RC) const;\n" 978 << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n" 979 << "};\n\n"; 980 981 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 982 983 if (!RegisterClasses.empty()) { 984 OS << "namespace " << RegisterClasses[0]->Namespace 985 << " { // Register classes\n"; 986 987 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 988 const CodeGenRegisterClass &RC = *RegisterClasses[i]; 989 const std::string &Name = RC.getName(); 990 991 // Output the extern for the instance. 992 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 993 } 994 OS << "} // end of namespace " << TargetName << "\n\n"; 995 } 996 OS << "} // End llvm namespace \n"; 997 OS << "#endif // GET_REGINFO_HEADER\n\n"; 998 } 999 1000 // 1001 // runTargetDesc - Output the target register and register file descriptions. 1002 // 1003 void 1004 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1005 CodeGenRegBank &RegBank){ 1006 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1007 1008 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1009 OS << "#undef GET_REGINFO_TARGET_DESC\n"; 1010 1011 OS << "namespace llvm {\n\n"; 1012 1013 // Get access to MCRegisterClass data. 1014 OS << "extern const MCRegisterClass " << Target.getName() 1015 << "MCRegisterClasses[];\n"; 1016 1017 // Start out by emitting each of the register classes. 1018 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); 1019 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); 1020 1021 // Collect all registers belonging to any allocatable class. 1022 std::set<Record*> AllocatableRegs; 1023 1024 // Collect allocatable registers. 1025 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1026 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1027 ArrayRef<Record*> Order = RC.getOrder(); 1028 1029 if (RC.Allocatable) 1030 AllocatableRegs.insert(Order.begin(), Order.end()); 1031 } 1032 1033 // Build a shared array of value types. 1034 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs; 1035 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) 1036 VTSeqs.add(RegisterClasses[rc]->VTs); 1037 VTSeqs.layout(); 1038 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1039 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1040 OS << "};\n"; 1041 1042 // Emit SubRegIndex names, skipping 0. 1043 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1044 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1045 OS << SubRegIndices[i]->getName(); 1046 if (i + 1 != e) 1047 OS << "\", \""; 1048 } 1049 OS << "\" };\n\n"; 1050 1051 // Emit SubRegIndex lane masks, including 0. 1052 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; 1053 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1054 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask) 1055 << SubRegIndices[i]->getName() << '\n'; 1056 } 1057 OS << " };\n\n"; 1058 1059 OS << "\n"; 1060 1061 // Now that all of the structs have been emitted, emit the instances. 1062 if (!RegisterClasses.empty()) { 1063 OS << "\nstatic const TargetRegisterClass *const " 1064 << "NullRegClasses[] = { NULL };\n\n"; 1065 1066 // Emit register class bit mask tables. The first bit mask emitted for a 1067 // register class, RC, is the set of sub-classes, including RC itself. 1068 // 1069 // If RC has super-registers, also create a list of subreg indices and bit 1070 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1071 // SuperRC, that satisfies: 1072 // 1073 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1074 // 1075 // The 0-terminated list of subreg indices starts at: 1076 // 1077 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1078 // 1079 // The corresponding bitmasks follow the sub-class mask in memory. Each 1080 // mask has RCMaskWords uint32_t entries. 1081 // 1082 // Every bit mask present in the list has at least one bit set. 1083 1084 // Compress the sub-reg index lists. 1085 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1086 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1087 SequenceToOffsetTable<IdxList> SuperRegIdxSeqs; 1088 BitVector MaskBV(RegisterClasses.size()); 1089 1090 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1091 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1092 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; 1093 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1094 1095 // Emit super-reg class masks for any relevant SubRegIndices that can 1096 // project into RC. 1097 IdxList &SRIList = SuperRegIdxLists[rc]; 1098 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1099 CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1100 MaskBV.reset(); 1101 RC.getSuperRegClasses(Idx, MaskBV); 1102 if (MaskBV.none()) 1103 continue; 1104 SRIList.push_back(Idx); 1105 OS << "\n "; 1106 printBitVectorAsHex(OS, MaskBV, 32); 1107 OS << "// " << Idx->getName(); 1108 } 1109 SuperRegIdxSeqs.add(SRIList); 1110 OS << "\n};\n\n"; 1111 } 1112 1113 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1114 SuperRegIdxSeqs.layout(); 1115 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1116 OS << "};\n\n"; 1117 1118 // Emit NULL terminated super-class lists. 1119 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 1120 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; 1121 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1122 1123 // Skip classes without supers. We can reuse NullRegClasses. 1124 if (Supers.empty()) 1125 continue; 1126 1127 OS << "static const TargetRegisterClass *const " 1128 << RC.getName() << "Superclasses[] = {\n"; 1129 for (unsigned i = 0; i != Supers.size(); ++i) 1130 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; 1131 OS << " NULL\n};\n\n"; 1132 } 1133 1134 // Emit methods. 1135 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1136 const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1137 if (!RC.AltOrderSelect.empty()) { 1138 OS << "\nstatic inline unsigned " << RC.getName() 1139 << "AltOrderSelect(const MachineFunction &MF) {" 1140 << RC.AltOrderSelect << "}\n\n" 1141 << "static ArrayRef<MCPhysReg> " << RC.getName() 1142 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1143 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1144 ArrayRef<Record*> Elems = RC.getOrder(oi); 1145 if (!Elems.empty()) { 1146 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1147 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1148 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1149 OS << " };\n"; 1150 } 1151 } 1152 OS << " const MCRegisterClass &MCR = " << Target.getName() 1153 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1154 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1155 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1156 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1157 if (RC.getOrder(oi).empty()) 1158 OS << "),\n ArrayRef<MCPhysReg>("; 1159 else 1160 OS << "),\n makeArrayRef(AltOrder" << oi; 1161 OS << ")\n };\n const unsigned Select = " << RC.getName() 1162 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1163 << ");\n return Order[Select];\n}\n"; 1164 } 1165 } 1166 1167 // Now emit the actual value-initialized register class instances. 1168 OS << "namespace " << RegisterClasses[0]->Namespace 1169 << " { // Register class instances\n"; 1170 1171 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 1172 const CodeGenRegisterClass &RC = *RegisterClasses[i]; 1173 OS << " extern const TargetRegisterClass " 1174 << RegisterClasses[i]->getName() << "RegClass = {\n " 1175 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() 1176 << "RegClassID],\n " 1177 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " 1178 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1179 << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n "; 1180 if (RC.getSuperClasses().empty()) 1181 OS << "NullRegClasses,\n "; 1182 else 1183 OS << RC.getName() << "Superclasses,\n "; 1184 if (RC.AltOrderSelect.empty()) 1185 OS << "0\n"; 1186 else 1187 OS << RC.getName() << "GetRawAllocationOrder\n"; 1188 OS << " };\n\n"; 1189 } 1190 1191 OS << "}\n"; 1192 } 1193 1194 OS << "\nnamespace {\n"; 1195 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1196 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 1197 OS << " &" << RegisterClasses[i]->getQualifiedName() 1198 << "RegClass,\n"; 1199 OS << " };\n"; 1200 OS << "}\n"; // End of anonymous namespace... 1201 1202 // Emit extra information about registers. 1203 const std::string &TargetName = Target.getName(); 1204 OS << "\nstatic const TargetRegisterInfoDesc " 1205 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1206 OS << " { 0, 0 },\n"; 1207 1208 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 1209 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 1210 const CodeGenRegister &Reg = *Regs[i]; 1211 OS << " { "; 1212 OS << Reg.CostPerUse << ", " 1213 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 1214 } 1215 OS << "};\n"; // End of register descriptors... 1216 1217 1218 std::string ClassName = Target.getName() + "GenRegisterInfo"; 1219 1220 if (!SubRegIndices.empty()) 1221 emitComposeSubRegIndices(OS, RegBank, ClassName); 1222 1223 // Emit getSubClassWithSubReg. 1224 if (!SubRegIndices.empty()) { 1225 OS << "const TargetRegisterClass *" << ClassName 1226 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1227 << " const {\n"; 1228 // Use the smallest type that can hold a regclass ID with room for a 1229 // sentinel. 1230 if (RegisterClasses.size() < UINT8_MAX) 1231 OS << " static const uint8_t Table["; 1232 else if (RegisterClasses.size() < UINT16_MAX) 1233 OS << " static const uint16_t Table["; 1234 else 1235 PrintFatalError("Too many register classes."); 1236 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; 1237 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) { 1238 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; 1239 OS << " {\t// " << RC.getName() << "\n"; 1240 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1241 CodeGenSubRegIndex *Idx = SubRegIndices[sri]; 1242 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) 1243 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() 1244 << " -> " << SRC->getName() << "\n"; 1245 else 1246 OS << " 0,\t// " << Idx->getName() << "\n"; 1247 } 1248 OS << " },\n"; 1249 } 1250 OS << " };\n assert(RC && \"Missing regclass\");\n" 1251 << " if (!Idx) return RC;\n --Idx;\n" 1252 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" 1253 << " unsigned TV = Table[RC->getID()][Idx];\n" 1254 << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; 1255 } 1256 1257 EmitRegUnitPressure(OS, RegBank, ClassName); 1258 1259 // Emit the constructor of the class... 1260 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1261 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1262 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1263 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n"; 1264 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1265 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1266 1267 EmitRegMappingTables(OS, Regs, true); 1268 1269 OS << ClassName << "::\n" << ClassName 1270 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" 1271 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1272 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 1273 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable) {\n" 1274 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 1275 << Regs.size()+1 << ", RA, PC,\n " << TargetName 1276 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1277 << " " << TargetName << "RegUnitRoots,\n" 1278 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1279 << " " << TargetName << "RegDiffLists,\n" 1280 << " " << TargetName << "RegStrings,\n" 1281 << " " << TargetName << "SubRegIdxLists,\n" 1282 << " " << SubRegIndices.size() + 1 << ",\n" 1283 << " " << TargetName << "RegEncodingTable);\n\n"; 1284 1285 EmitRegMapping(OS, Regs, true); 1286 1287 OS << "}\n\n"; 1288 1289 1290 // Emit CalleeSavedRegs information. 1291 std::vector<Record*> CSRSets = 1292 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1293 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1294 Record *CSRSet = CSRSets[i]; 1295 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1296 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1297 1298 // Emit the *_SaveList list of callee-saved registers. 1299 OS << "static const MCPhysReg " << CSRSet->getName() 1300 << "_SaveList[] = { "; 1301 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1302 OS << getQualifiedName((*Regs)[r]) << ", "; 1303 OS << "0 };\n"; 1304 1305 // Emit the *_RegMask bit mask of call-preserved registers. 1306 OS << "static const uint32_t " << CSRSet->getName() 1307 << "_RegMask[] = { "; 1308 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32); 1309 OS << "};\n"; 1310 } 1311 OS << "\n\n"; 1312 1313 OS << "} // End llvm namespace \n"; 1314 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1315 } 1316 1317 void RegisterInfoEmitter::run(raw_ostream &OS) { 1318 CodeGenTarget Target(Records); 1319 CodeGenRegBank &RegBank = Target.getRegBank(); 1320 RegBank.computeDerivedInfo(); 1321 1322 runEnums(OS, Target, RegBank); 1323 runMCDesc(OS, Target, RegBank); 1324 runTargetHeader(OS, Target, RegBank); 1325 runTargetDesc(OS, Target, RegBank); 1326 } 1327 1328 namespace llvm { 1329 1330 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1331 RegisterInfoEmitter(RK).run(OS); 1332 } 1333 1334 } // End llvm namespace 1335