1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCTargetAsmParser.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/ADT/BitVector.h" 15 #include "llvm/ADT/OwningPtr.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/MC/MCAsmInfo.h" 21 #include "llvm/MC/MCAssembler.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCELFStreamer.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCInst.h" 26 #include "llvm/MC/MCInstrDesc.h" 27 #include "llvm/MC/MCParser/MCAsmLexer.h" 28 #include "llvm/MC/MCParser/MCAsmParser.h" 29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCStreamer.h" 32 #include "llvm/MC/MCSubtargetInfo.h" 33 #include "llvm/Support/ELF.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Support/SourceMgr.h" 36 #include "llvm/Support/TargetRegistry.h" 37 #include "llvm/Support/raw_ostream.h" 38 39 using namespace llvm; 40 41 namespace { 42 43 class ARMOperand; 44 45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 46 47 class ARMAsmParser : public MCTargetAsmParser { 48 MCSubtargetInfo &STI; 49 MCAsmParser &Parser; 50 const MCRegisterInfo *MRI; 51 52 // Unwind directives state 53 SMLoc FnStartLoc; 54 SMLoc CantUnwindLoc; 55 SMLoc PersonalityLoc; 56 SMLoc HandlerDataLoc; 57 int FPReg; 58 void resetUnwindDirectiveParserState() { 59 FnStartLoc = SMLoc(); 60 CantUnwindLoc = SMLoc(); 61 PersonalityLoc = SMLoc(); 62 HandlerDataLoc = SMLoc(); 63 FPReg = -1; 64 } 65 66 // Map of register aliases registers via the .req directive. 67 StringMap<unsigned> RegisterReqs; 68 69 struct { 70 ARMCC::CondCodes Cond; // Condition for IT block. 71 unsigned Mask:4; // Condition mask for instructions. 72 // Starting at first 1 (from lsb). 73 // '1' condition as indicated in IT. 74 // '0' inverse of condition (else). 75 // Count of instructions in IT block is 76 // 4 - trailingzeroes(mask) 77 78 bool FirstCond; // Explicit flag for when we're parsing the 79 // First instruction in the IT block. It's 80 // implied in the mask, so needs special 81 // handling. 82 83 unsigned CurPosition; // Current position in parsing of IT 84 // block. In range [0,3]. Initialized 85 // according to count of instructions in block. 86 // ~0U if no active IT block. 87 } ITState; 88 bool inITBlock() { return ITState.CurPosition != ~0U;} 89 void forwardITPosition() { 90 if (!inITBlock()) return; 91 // Move to the next instruction in the IT block, if there is one. If not, 92 // mark the block as done. 93 unsigned TZ = countTrailingZeros(ITState.Mask); 94 if (++ITState.CurPosition == 5 - TZ) 95 ITState.CurPosition = ~0U; // Done with the IT block after this. 96 } 97 98 99 MCAsmParser &getParser() const { return Parser; } 100 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 101 102 bool Warning(SMLoc L, const Twine &Msg, 103 ArrayRef<SMRange> Ranges = None) { 104 return Parser.Warning(L, Msg, Ranges); 105 } 106 bool Error(SMLoc L, const Twine &Msg, 107 ArrayRef<SMRange> Ranges = None) { 108 return Parser.Error(L, Msg, Ranges); 109 } 110 111 int tryParseRegister(); 112 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 113 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 114 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 115 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 116 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 117 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 118 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 119 unsigned &ShiftAmount); 120 bool parseDirectiveWord(unsigned Size, SMLoc L); 121 bool parseDirectiveThumb(SMLoc L); 122 bool parseDirectiveARM(SMLoc L); 123 bool parseDirectiveThumbFunc(SMLoc L); 124 bool parseDirectiveCode(SMLoc L); 125 bool parseDirectiveSyntax(SMLoc L); 126 bool parseDirectiveReq(StringRef Name, SMLoc L); 127 bool parseDirectiveUnreq(SMLoc L); 128 bool parseDirectiveArch(SMLoc L); 129 bool parseDirectiveEabiAttr(SMLoc L); 130 bool parseDirectiveFnStart(SMLoc L); 131 bool parseDirectiveFnEnd(SMLoc L); 132 bool parseDirectiveCantUnwind(SMLoc L); 133 bool parseDirectivePersonality(SMLoc L); 134 bool parseDirectiveHandlerData(SMLoc L); 135 bool parseDirectiveSetFP(SMLoc L); 136 bool parseDirectivePad(SMLoc L); 137 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 138 139 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 140 bool &CarrySetting, unsigned &ProcessorIMod, 141 StringRef &ITMask); 142 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 143 bool &CanAcceptPredicationCode); 144 145 bool isThumb() const { 146 // FIXME: Can tablegen auto-generate this? 147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 148 } 149 bool isThumbOne() const { 150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 151 } 152 bool isThumbTwo() const { 153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 154 } 155 bool hasThumb() const { 156 return STI.getFeatureBits() & ARM::HasV4TOps; 157 } 158 bool hasV6Ops() const { 159 return STI.getFeatureBits() & ARM::HasV6Ops; 160 } 161 bool hasV7Ops() const { 162 return STI.getFeatureBits() & ARM::HasV7Ops; 163 } 164 bool hasV8Ops() const { 165 return STI.getFeatureBits() & ARM::HasV8Ops; 166 } 167 bool hasARM() const { 168 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 169 } 170 171 void SwitchMode() { 172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 173 setAvailableFeatures(FB); 174 } 175 bool isMClass() const { 176 return STI.getFeatureBits() & ARM::FeatureMClass; 177 } 178 179 /// @name Auto-generated Match Functions 180 /// { 181 182 #define GET_ASSEMBLER_HEADER 183 #include "ARMGenAsmMatcher.inc" 184 185 /// } 186 187 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 188 OperandMatchResultTy parseCoprocNumOperand( 189 SmallVectorImpl<MCParsedAsmOperand*>&); 190 OperandMatchResultTy parseCoprocRegOperand( 191 SmallVectorImpl<MCParsedAsmOperand*>&); 192 OperandMatchResultTy parseCoprocOptionOperand( 193 SmallVectorImpl<MCParsedAsmOperand*>&); 194 OperandMatchResultTy parseMemBarrierOptOperand( 195 SmallVectorImpl<MCParsedAsmOperand*>&); 196 OperandMatchResultTy parseInstSyncBarrierOptOperand( 197 SmallVectorImpl<MCParsedAsmOperand*>&); 198 OperandMatchResultTy parseProcIFlagsOperand( 199 SmallVectorImpl<MCParsedAsmOperand*>&); 200 OperandMatchResultTy parseMSRMaskOperand( 201 SmallVectorImpl<MCParsedAsmOperand*>&); 202 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 203 StringRef Op, int Low, int High); 204 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 205 return parsePKHImm(O, "lsl", 0, 31); 206 } 207 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 208 return parsePKHImm(O, "asr", 1, 32); 209 } 210 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 211 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 212 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 213 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 214 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 215 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 216 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 217 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 218 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 219 SMLoc &EndLoc); 220 221 // Asm Match Converter Methods 222 void cvtThumbMultiply(MCInst &Inst, 223 const SmallVectorImpl<MCParsedAsmOperand*> &); 224 bool validateInstruction(MCInst &Inst, 225 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 226 bool processInstruction(MCInst &Inst, 227 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 228 bool shouldOmitCCOutOperand(StringRef Mnemonic, 229 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 230 bool shouldOmitPredicateOperand(StringRef Mnemonic, 231 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 232 bool isDeprecated(MCInst &Inst, StringRef &Info); 233 234 public: 235 enum ARMMatchResultTy { 236 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 237 Match_RequiresNotITBlock, 238 Match_RequiresV6, 239 Match_RequiresThumb2, 240 #define GET_OPERAND_DIAGNOSTIC_TYPES 241 #include "ARMGenAsmMatcher.inc" 242 243 }; 244 245 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 246 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) { 247 MCAsmParserExtension::Initialize(_Parser); 248 249 // Cache the MCRegisterInfo. 250 MRI = getContext().getRegisterInfo(); 251 252 // Initialize the set of available features. 253 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 254 255 // Not in an ITBlock to start with. 256 ITState.CurPosition = ~0U; 257 258 // Set ELF header flags. 259 // FIXME: This should eventually end up somewhere else where more 260 // intelligent flag decisions can be made. For now we are just maintaining 261 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default. 262 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer())) 263 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5); 264 } 265 266 // Implementation of the MCTargetAsmParser interface: 267 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 268 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 269 SMLoc NameLoc, 270 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 271 bool ParseDirective(AsmToken DirectiveID); 272 273 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 274 unsigned checkTargetMatchPredicate(MCInst &Inst); 275 276 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 277 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 278 MCStreamer &Out, unsigned &ErrorInfo, 279 bool MatchingInlineAsm); 280 }; 281 } // end anonymous namespace 282 283 namespace { 284 285 /// ARMOperand - Instances of this class represent a parsed ARM machine 286 /// operand. 287 class ARMOperand : public MCParsedAsmOperand { 288 enum KindTy { 289 k_CondCode, 290 k_CCOut, 291 k_ITCondMask, 292 k_CoprocNum, 293 k_CoprocReg, 294 k_CoprocOption, 295 k_Immediate, 296 k_MemBarrierOpt, 297 k_InstSyncBarrierOpt, 298 k_Memory, 299 k_PostIndexRegister, 300 k_MSRMask, 301 k_ProcIFlags, 302 k_VectorIndex, 303 k_Register, 304 k_RegisterList, 305 k_DPRRegisterList, 306 k_SPRRegisterList, 307 k_VectorList, 308 k_VectorListAllLanes, 309 k_VectorListIndexed, 310 k_ShiftedRegister, 311 k_ShiftedImmediate, 312 k_ShifterImmediate, 313 k_RotateImmediate, 314 k_BitfieldDescriptor, 315 k_Token 316 } Kind; 317 318 SMLoc StartLoc, EndLoc; 319 SmallVector<unsigned, 8> Registers; 320 321 struct CCOp { 322 ARMCC::CondCodes Val; 323 }; 324 325 struct CopOp { 326 unsigned Val; 327 }; 328 329 struct CoprocOptionOp { 330 unsigned Val; 331 }; 332 333 struct ITMaskOp { 334 unsigned Mask:4; 335 }; 336 337 struct MBOptOp { 338 ARM_MB::MemBOpt Val; 339 }; 340 341 struct ISBOptOp { 342 ARM_ISB::InstSyncBOpt Val; 343 }; 344 345 struct IFlagsOp { 346 ARM_PROC::IFlags Val; 347 }; 348 349 struct MMaskOp { 350 unsigned Val; 351 }; 352 353 struct TokOp { 354 const char *Data; 355 unsigned Length; 356 }; 357 358 struct RegOp { 359 unsigned RegNum; 360 }; 361 362 // A vector register list is a sequential list of 1 to 4 registers. 363 struct VectorListOp { 364 unsigned RegNum; 365 unsigned Count; 366 unsigned LaneIndex; 367 bool isDoubleSpaced; 368 }; 369 370 struct VectorIndexOp { 371 unsigned Val; 372 }; 373 374 struct ImmOp { 375 const MCExpr *Val; 376 }; 377 378 /// Combined record for all forms of ARM address expressions. 379 struct MemoryOp { 380 unsigned BaseRegNum; 381 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 382 // was specified. 383 const MCConstantExpr *OffsetImm; // Offset immediate value 384 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 385 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 386 unsigned ShiftImm; // shift for OffsetReg. 387 unsigned Alignment; // 0 = no alignment specified 388 // n = alignment in bytes (2, 4, 8, 16, or 32) 389 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 390 }; 391 392 struct PostIdxRegOp { 393 unsigned RegNum; 394 bool isAdd; 395 ARM_AM::ShiftOpc ShiftTy; 396 unsigned ShiftImm; 397 }; 398 399 struct ShifterImmOp { 400 bool isASR; 401 unsigned Imm; 402 }; 403 404 struct RegShiftedRegOp { 405 ARM_AM::ShiftOpc ShiftTy; 406 unsigned SrcReg; 407 unsigned ShiftReg; 408 unsigned ShiftImm; 409 }; 410 411 struct RegShiftedImmOp { 412 ARM_AM::ShiftOpc ShiftTy; 413 unsigned SrcReg; 414 unsigned ShiftImm; 415 }; 416 417 struct RotImmOp { 418 unsigned Imm; 419 }; 420 421 struct BitfieldOp { 422 unsigned LSB; 423 unsigned Width; 424 }; 425 426 union { 427 struct CCOp CC; 428 struct CopOp Cop; 429 struct CoprocOptionOp CoprocOption; 430 struct MBOptOp MBOpt; 431 struct ISBOptOp ISBOpt; 432 struct ITMaskOp ITMask; 433 struct IFlagsOp IFlags; 434 struct MMaskOp MMask; 435 struct TokOp Tok; 436 struct RegOp Reg; 437 struct VectorListOp VectorList; 438 struct VectorIndexOp VectorIndex; 439 struct ImmOp Imm; 440 struct MemoryOp Memory; 441 struct PostIdxRegOp PostIdxReg; 442 struct ShifterImmOp ShifterImm; 443 struct RegShiftedRegOp RegShiftedReg; 444 struct RegShiftedImmOp RegShiftedImm; 445 struct RotImmOp RotImm; 446 struct BitfieldOp Bitfield; 447 }; 448 449 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 450 public: 451 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 452 Kind = o.Kind; 453 StartLoc = o.StartLoc; 454 EndLoc = o.EndLoc; 455 switch (Kind) { 456 case k_CondCode: 457 CC = o.CC; 458 break; 459 case k_ITCondMask: 460 ITMask = o.ITMask; 461 break; 462 case k_Token: 463 Tok = o.Tok; 464 break; 465 case k_CCOut: 466 case k_Register: 467 Reg = o.Reg; 468 break; 469 case k_RegisterList: 470 case k_DPRRegisterList: 471 case k_SPRRegisterList: 472 Registers = o.Registers; 473 break; 474 case k_VectorList: 475 case k_VectorListAllLanes: 476 case k_VectorListIndexed: 477 VectorList = o.VectorList; 478 break; 479 case k_CoprocNum: 480 case k_CoprocReg: 481 Cop = o.Cop; 482 break; 483 case k_CoprocOption: 484 CoprocOption = o.CoprocOption; 485 break; 486 case k_Immediate: 487 Imm = o.Imm; 488 break; 489 case k_MemBarrierOpt: 490 MBOpt = o.MBOpt; 491 break; 492 case k_InstSyncBarrierOpt: 493 ISBOpt = o.ISBOpt; 494 case k_Memory: 495 Memory = o.Memory; 496 break; 497 case k_PostIndexRegister: 498 PostIdxReg = o.PostIdxReg; 499 break; 500 case k_MSRMask: 501 MMask = o.MMask; 502 break; 503 case k_ProcIFlags: 504 IFlags = o.IFlags; 505 break; 506 case k_ShifterImmediate: 507 ShifterImm = o.ShifterImm; 508 break; 509 case k_ShiftedRegister: 510 RegShiftedReg = o.RegShiftedReg; 511 break; 512 case k_ShiftedImmediate: 513 RegShiftedImm = o.RegShiftedImm; 514 break; 515 case k_RotateImmediate: 516 RotImm = o.RotImm; 517 break; 518 case k_BitfieldDescriptor: 519 Bitfield = o.Bitfield; 520 break; 521 case k_VectorIndex: 522 VectorIndex = o.VectorIndex; 523 break; 524 } 525 } 526 527 /// getStartLoc - Get the location of the first token of this operand. 528 SMLoc getStartLoc() const { return StartLoc; } 529 /// getEndLoc - Get the location of the last token of this operand. 530 SMLoc getEndLoc() const { return EndLoc; } 531 /// getLocRange - Get the range between the first and last token of this 532 /// operand. 533 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 534 535 ARMCC::CondCodes getCondCode() const { 536 assert(Kind == k_CondCode && "Invalid access!"); 537 return CC.Val; 538 } 539 540 unsigned getCoproc() const { 541 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 542 return Cop.Val; 543 } 544 545 StringRef getToken() const { 546 assert(Kind == k_Token && "Invalid access!"); 547 return StringRef(Tok.Data, Tok.Length); 548 } 549 550 unsigned getReg() const { 551 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 552 return Reg.RegNum; 553 } 554 555 const SmallVectorImpl<unsigned> &getRegList() const { 556 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 557 Kind == k_SPRRegisterList) && "Invalid access!"); 558 return Registers; 559 } 560 561 const MCExpr *getImm() const { 562 assert(isImm() && "Invalid access!"); 563 return Imm.Val; 564 } 565 566 unsigned getVectorIndex() const { 567 assert(Kind == k_VectorIndex && "Invalid access!"); 568 return VectorIndex.Val; 569 } 570 571 ARM_MB::MemBOpt getMemBarrierOpt() const { 572 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 573 return MBOpt.Val; 574 } 575 576 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 577 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 578 return ISBOpt.Val; 579 } 580 581 ARM_PROC::IFlags getProcIFlags() const { 582 assert(Kind == k_ProcIFlags && "Invalid access!"); 583 return IFlags.Val; 584 } 585 586 unsigned getMSRMask() const { 587 assert(Kind == k_MSRMask && "Invalid access!"); 588 return MMask.Val; 589 } 590 591 bool isCoprocNum() const { return Kind == k_CoprocNum; } 592 bool isCoprocReg() const { return Kind == k_CoprocReg; } 593 bool isCoprocOption() const { return Kind == k_CoprocOption; } 594 bool isCondCode() const { return Kind == k_CondCode; } 595 bool isCCOut() const { return Kind == k_CCOut; } 596 bool isITMask() const { return Kind == k_ITCondMask; } 597 bool isITCondCode() const { return Kind == k_CondCode; } 598 bool isImm() const { return Kind == k_Immediate; } 599 // checks whether this operand is an unsigned offset which fits is a field 600 // of specified width and scaled by a specific number of bits 601 template<unsigned width, unsigned scale> 602 bool isUnsignedOffset() const { 603 if (!isImm()) return false; 604 if (dyn_cast<MCSymbolRefExpr>(Imm.Val)) return true; 605 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 606 int64_t Val = CE->getValue(); 607 int64_t Align = 1LL << scale; 608 int64_t Max = Align * ((1LL << width) - 1); 609 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 610 } 611 return false; 612 } 613 // checks whether this operand is a memory operand computed as an offset 614 // applied to PC. the offset may have 8 bits of magnitude and is represented 615 // with two bits of shift. textually it may be either [pc, #imm], #imm or 616 // relocable expression... 617 bool isThumbMemPC() const { 618 int64_t Val = 0; 619 if (isImm()) { 620 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 621 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 622 if (!CE) return false; 623 Val = CE->getValue(); 624 } 625 else if (isMem()) { 626 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 627 if(Memory.BaseRegNum != ARM::PC) return false; 628 Val = Memory.OffsetImm->getValue(); 629 } 630 else return false; 631 return ((Val % 4) == 0) && (Val >= -1020) && (Val <= 1020); 632 } 633 bool isFPImm() const { 634 if (!isImm()) return false; 635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 636 if (!CE) return false; 637 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 638 return Val != -1; 639 } 640 bool isFBits16() const { 641 if (!isImm()) return false; 642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 643 if (!CE) return false; 644 int64_t Value = CE->getValue(); 645 return Value >= 0 && Value <= 16; 646 } 647 bool isFBits32() const { 648 if (!isImm()) return false; 649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 650 if (!CE) return false; 651 int64_t Value = CE->getValue(); 652 return Value >= 1 && Value <= 32; 653 } 654 bool isImm8s4() const { 655 if (!isImm()) return false; 656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 657 if (!CE) return false; 658 int64_t Value = CE->getValue(); 659 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 660 } 661 bool isImm0_4() const { 662 if (!isImm()) return false; 663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 664 if (!CE) return false; 665 int64_t Value = CE->getValue(); 666 return Value >= 0 && Value < 5; 667 } 668 bool isImm0_1020s4() const { 669 if (!isImm()) return false; 670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 671 if (!CE) return false; 672 int64_t Value = CE->getValue(); 673 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 674 } 675 bool isImm0_508s4() const { 676 if (!isImm()) return false; 677 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 678 if (!CE) return false; 679 int64_t Value = CE->getValue(); 680 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 681 } 682 bool isImm0_508s4Neg() const { 683 if (!isImm()) return false; 684 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 685 if (!CE) return false; 686 int64_t Value = -CE->getValue(); 687 // explicitly exclude zero. we want that to use the normal 0_508 version. 688 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 689 } 690 bool isImm0_255() const { 691 if (!isImm()) return false; 692 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 693 if (!CE) return false; 694 int64_t Value = CE->getValue(); 695 return Value >= 0 && Value < 256; 696 } 697 bool isImm0_4095() const { 698 if (!isImm()) return false; 699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 700 if (!CE) return false; 701 int64_t Value = CE->getValue(); 702 return Value >= 0 && Value < 4096; 703 } 704 bool isImm0_4095Neg() const { 705 if (!isImm()) return false; 706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 707 if (!CE) return false; 708 int64_t Value = -CE->getValue(); 709 return Value > 0 && Value < 4096; 710 } 711 bool isImm0_1() const { 712 if (!isImm()) return false; 713 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 714 if (!CE) return false; 715 int64_t Value = CE->getValue(); 716 return Value >= 0 && Value < 2; 717 } 718 bool isImm0_3() const { 719 if (!isImm()) return false; 720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 721 if (!CE) return false; 722 int64_t Value = CE->getValue(); 723 return Value >= 0 && Value < 4; 724 } 725 bool isImm0_7() const { 726 if (!isImm()) return false; 727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 728 if (!CE) return false; 729 int64_t Value = CE->getValue(); 730 return Value >= 0 && Value < 8; 731 } 732 bool isImm0_15() const { 733 if (!isImm()) return false; 734 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 735 if (!CE) return false; 736 int64_t Value = CE->getValue(); 737 return Value >= 0 && Value < 16; 738 } 739 bool isImm0_31() const { 740 if (!isImm()) return false; 741 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 742 if (!CE) return false; 743 int64_t Value = CE->getValue(); 744 return Value >= 0 && Value < 32; 745 } 746 bool isImm0_63() const { 747 if (!isImm()) return false; 748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 749 if (!CE) return false; 750 int64_t Value = CE->getValue(); 751 return Value >= 0 && Value < 64; 752 } 753 bool isImm8() const { 754 if (!isImm()) return false; 755 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 756 if (!CE) return false; 757 int64_t Value = CE->getValue(); 758 return Value == 8; 759 } 760 bool isImm16() const { 761 if (!isImm()) return false; 762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 763 if (!CE) return false; 764 int64_t Value = CE->getValue(); 765 return Value == 16; 766 } 767 bool isImm32() const { 768 if (!isImm()) return false; 769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 770 if (!CE) return false; 771 int64_t Value = CE->getValue(); 772 return Value == 32; 773 } 774 bool isShrImm8() const { 775 if (!isImm()) return false; 776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 777 if (!CE) return false; 778 int64_t Value = CE->getValue(); 779 return Value > 0 && Value <= 8; 780 } 781 bool isShrImm16() const { 782 if (!isImm()) return false; 783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 784 if (!CE) return false; 785 int64_t Value = CE->getValue(); 786 return Value > 0 && Value <= 16; 787 } 788 bool isShrImm32() const { 789 if (!isImm()) return false; 790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 791 if (!CE) return false; 792 int64_t Value = CE->getValue(); 793 return Value > 0 && Value <= 32; 794 } 795 bool isShrImm64() const { 796 if (!isImm()) return false; 797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 798 if (!CE) return false; 799 int64_t Value = CE->getValue(); 800 return Value > 0 && Value <= 64; 801 } 802 bool isImm1_7() const { 803 if (!isImm()) return false; 804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 805 if (!CE) return false; 806 int64_t Value = CE->getValue(); 807 return Value > 0 && Value < 8; 808 } 809 bool isImm1_15() const { 810 if (!isImm()) return false; 811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 812 if (!CE) return false; 813 int64_t Value = CE->getValue(); 814 return Value > 0 && Value < 16; 815 } 816 bool isImm1_31() const { 817 if (!isImm()) return false; 818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 819 if (!CE) return false; 820 int64_t Value = CE->getValue(); 821 return Value > 0 && Value < 32; 822 } 823 bool isImm1_16() const { 824 if (!isImm()) return false; 825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 826 if (!CE) return false; 827 int64_t Value = CE->getValue(); 828 return Value > 0 && Value < 17; 829 } 830 bool isImm1_32() const { 831 if (!isImm()) return false; 832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 833 if (!CE) return false; 834 int64_t Value = CE->getValue(); 835 return Value > 0 && Value < 33; 836 } 837 bool isImm0_32() const { 838 if (!isImm()) return false; 839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 840 if (!CE) return false; 841 int64_t Value = CE->getValue(); 842 return Value >= 0 && Value < 33; 843 } 844 bool isImm0_65535() const { 845 if (!isImm()) return false; 846 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 847 if (!CE) return false; 848 int64_t Value = CE->getValue(); 849 return Value >= 0 && Value < 65536; 850 } 851 bool isImm0_65535Expr() const { 852 if (!isImm()) return false; 853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 854 // If it's not a constant expression, it'll generate a fixup and be 855 // handled later. 856 if (!CE) return true; 857 int64_t Value = CE->getValue(); 858 return Value >= 0 && Value < 65536; 859 } 860 bool isImm24bit() const { 861 if (!isImm()) return false; 862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 863 if (!CE) return false; 864 int64_t Value = CE->getValue(); 865 return Value >= 0 && Value <= 0xffffff; 866 } 867 bool isImmThumbSR() const { 868 if (!isImm()) return false; 869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 870 if (!CE) return false; 871 int64_t Value = CE->getValue(); 872 return Value > 0 && Value < 33; 873 } 874 bool isPKHLSLImm() const { 875 if (!isImm()) return false; 876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 877 if (!CE) return false; 878 int64_t Value = CE->getValue(); 879 return Value >= 0 && Value < 32; 880 } 881 bool isPKHASRImm() const { 882 if (!isImm()) return false; 883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 884 if (!CE) return false; 885 int64_t Value = CE->getValue(); 886 return Value > 0 && Value <= 32; 887 } 888 bool isAdrLabel() const { 889 // If we have an immediate that's not a constant, treat it as a label 890 // reference needing a fixup. If it is a constant, but it can't fit 891 // into shift immediate encoding, we reject it. 892 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 893 else return (isARMSOImm() || isARMSOImmNeg()); 894 } 895 bool isARMSOImm() const { 896 if (!isImm()) return false; 897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 898 if (!CE) return false; 899 int64_t Value = CE->getValue(); 900 return ARM_AM::getSOImmVal(Value) != -1; 901 } 902 bool isARMSOImmNot() const { 903 if (!isImm()) return false; 904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 905 if (!CE) return false; 906 int64_t Value = CE->getValue(); 907 return ARM_AM::getSOImmVal(~Value) != -1; 908 } 909 bool isARMSOImmNeg() const { 910 if (!isImm()) return false; 911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 912 if (!CE) return false; 913 int64_t Value = CE->getValue(); 914 // Only use this when not representable as a plain so_imm. 915 return ARM_AM::getSOImmVal(Value) == -1 && 916 ARM_AM::getSOImmVal(-Value) != -1; 917 } 918 bool isT2SOImm() const { 919 if (!isImm()) return false; 920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 921 if (!CE) return false; 922 int64_t Value = CE->getValue(); 923 return ARM_AM::getT2SOImmVal(Value) != -1; 924 } 925 bool isT2SOImmNot() const { 926 if (!isImm()) return false; 927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 928 if (!CE) return false; 929 int64_t Value = CE->getValue(); 930 return ARM_AM::getT2SOImmVal(~Value) != -1; 931 } 932 bool isT2SOImmNeg() const { 933 if (!isImm()) return false; 934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 935 if (!CE) return false; 936 int64_t Value = CE->getValue(); 937 // Only use this when not representable as a plain so_imm. 938 return ARM_AM::getT2SOImmVal(Value) == -1 && 939 ARM_AM::getT2SOImmVal(-Value) != -1; 940 } 941 bool isSetEndImm() const { 942 if (!isImm()) return false; 943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 944 if (!CE) return false; 945 int64_t Value = CE->getValue(); 946 return Value == 1 || Value == 0; 947 } 948 bool isReg() const { return Kind == k_Register; } 949 bool isRegList() const { return Kind == k_RegisterList; } 950 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 951 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 952 bool isToken() const { return Kind == k_Token; } 953 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 954 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 955 bool isMem() const { return Kind == k_Memory; } 956 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 957 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 958 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 959 bool isRotImm() const { return Kind == k_RotateImmediate; } 960 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 961 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 962 bool isPostIdxReg() const { 963 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 964 } 965 bool isMemNoOffset(bool alignOK = false) const { 966 if (!isMem()) 967 return false; 968 // No offset of any kind. 969 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 970 (alignOK || Memory.Alignment == 0); 971 } 972 bool isMemPCRelImm12() const { 973 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 974 return false; 975 // Base register must be PC. 976 if (Memory.BaseRegNum != ARM::PC) 977 return false; 978 // Immediate offset in range [-4095, 4095]. 979 if (!Memory.OffsetImm) return true; 980 int64_t Val = Memory.OffsetImm->getValue(); 981 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 982 } 983 bool isAlignedMemory() const { 984 return isMemNoOffset(true); 985 } 986 bool isAddrMode2() const { 987 if (!isMem() || Memory.Alignment != 0) return false; 988 // Check for register offset. 989 if (Memory.OffsetRegNum) return true; 990 // Immediate offset in range [-4095, 4095]. 991 if (!Memory.OffsetImm) return true; 992 int64_t Val = Memory.OffsetImm->getValue(); 993 return Val > -4096 && Val < 4096; 994 } 995 bool isAM2OffsetImm() const { 996 if (!isImm()) return false; 997 // Immediate offset in range [-4095, 4095]. 998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 999 if (!CE) return false; 1000 int64_t Val = CE->getValue(); 1001 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1002 } 1003 bool isAddrMode3() const { 1004 // If we have an immediate that's not a constant, treat it as a label 1005 // reference needing a fixup. If it is a constant, it's something else 1006 // and we reject it. 1007 if (isImm() && !isa<MCConstantExpr>(getImm())) 1008 return true; 1009 if (!isMem() || Memory.Alignment != 0) return false; 1010 // No shifts are legal for AM3. 1011 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1012 // Check for register offset. 1013 if (Memory.OffsetRegNum) return true; 1014 // Immediate offset in range [-255, 255]. 1015 if (!Memory.OffsetImm) return true; 1016 int64_t Val = Memory.OffsetImm->getValue(); 1017 // The #-0 offset is encoded as INT32_MIN, and we have to check 1018 // for this too. 1019 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1020 } 1021 bool isAM3Offset() const { 1022 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1023 return false; 1024 if (Kind == k_PostIndexRegister) 1025 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1026 // Immediate offset in range [-255, 255]. 1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1028 if (!CE) return false; 1029 int64_t Val = CE->getValue(); 1030 // Special case, #-0 is INT32_MIN. 1031 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1032 } 1033 bool isAddrMode5() const { 1034 // If we have an immediate that's not a constant, treat it as a label 1035 // reference needing a fixup. If it is a constant, it's something else 1036 // and we reject it. 1037 if (isImm() && !isa<MCConstantExpr>(getImm())) 1038 return true; 1039 if (!isMem() || Memory.Alignment != 0) return false; 1040 // Check for register offset. 1041 if (Memory.OffsetRegNum) return false; 1042 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1043 if (!Memory.OffsetImm) return true; 1044 int64_t Val = Memory.OffsetImm->getValue(); 1045 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1046 Val == INT32_MIN; 1047 } 1048 bool isMemTBB() const { 1049 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1050 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1051 return false; 1052 return true; 1053 } 1054 bool isMemTBH() const { 1055 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1056 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1057 Memory.Alignment != 0 ) 1058 return false; 1059 return true; 1060 } 1061 bool isMemRegOffset() const { 1062 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1063 return false; 1064 return true; 1065 } 1066 bool isT2MemRegOffset() const { 1067 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1068 Memory.Alignment != 0) 1069 return false; 1070 // Only lsl #{0, 1, 2, 3} allowed. 1071 if (Memory.ShiftType == ARM_AM::no_shift) 1072 return true; 1073 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1074 return false; 1075 return true; 1076 } 1077 bool isMemThumbRR() const { 1078 // Thumb reg+reg addressing is simple. Just two registers, a base and 1079 // an offset. No shifts, negations or any other complicating factors. 1080 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1081 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1082 return false; 1083 return isARMLowRegister(Memory.BaseRegNum) && 1084 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1085 } 1086 bool isMemThumbRIs4() const { 1087 if (!isMem() || Memory.OffsetRegNum != 0 || 1088 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1089 return false; 1090 // Immediate offset, multiple of 4 in range [0, 124]. 1091 if (!Memory.OffsetImm) return true; 1092 int64_t Val = Memory.OffsetImm->getValue(); 1093 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1094 } 1095 bool isMemThumbRIs2() const { 1096 if (!isMem() || Memory.OffsetRegNum != 0 || 1097 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1098 return false; 1099 // Immediate offset, multiple of 4 in range [0, 62]. 1100 if (!Memory.OffsetImm) return true; 1101 int64_t Val = Memory.OffsetImm->getValue(); 1102 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1103 } 1104 bool isMemThumbRIs1() const { 1105 if (!isMem() || Memory.OffsetRegNum != 0 || 1106 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1107 return false; 1108 // Immediate offset in range [0, 31]. 1109 if (!Memory.OffsetImm) return true; 1110 int64_t Val = Memory.OffsetImm->getValue(); 1111 return Val >= 0 && Val <= 31; 1112 } 1113 bool isMemThumbSPI() const { 1114 if (!isMem() || Memory.OffsetRegNum != 0 || 1115 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1116 return false; 1117 // Immediate offset, multiple of 4 in range [0, 1020]. 1118 if (!Memory.OffsetImm) return true; 1119 int64_t Val = Memory.OffsetImm->getValue(); 1120 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1121 } 1122 bool isMemImm8s4Offset() const { 1123 // If we have an immediate that's not a constant, treat it as a label 1124 // reference needing a fixup. If it is a constant, it's something else 1125 // and we reject it. 1126 if (isImm() && !isa<MCConstantExpr>(getImm())) 1127 return true; 1128 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1129 return false; 1130 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1131 if (!Memory.OffsetImm) return true; 1132 int64_t Val = Memory.OffsetImm->getValue(); 1133 // Special case, #-0 is INT32_MIN. 1134 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1135 } 1136 bool isMemImm0_1020s4Offset() const { 1137 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1138 return false; 1139 // Immediate offset a multiple of 4 in range [0, 1020]. 1140 if (!Memory.OffsetImm) return true; 1141 int64_t Val = Memory.OffsetImm->getValue(); 1142 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1143 } 1144 bool isMemImm8Offset() const { 1145 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1146 return false; 1147 // Base reg of PC isn't allowed for these encodings. 1148 if (Memory.BaseRegNum == ARM::PC) return false; 1149 // Immediate offset in range [-255, 255]. 1150 if (!Memory.OffsetImm) return true; 1151 int64_t Val = Memory.OffsetImm->getValue(); 1152 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1153 } 1154 bool isMemPosImm8Offset() const { 1155 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1156 return false; 1157 // Immediate offset in range [0, 255]. 1158 if (!Memory.OffsetImm) return true; 1159 int64_t Val = Memory.OffsetImm->getValue(); 1160 return Val >= 0 && Val < 256; 1161 } 1162 bool isMemNegImm8Offset() const { 1163 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1164 return false; 1165 // Base reg of PC isn't allowed for these encodings. 1166 if (Memory.BaseRegNum == ARM::PC) return false; 1167 // Immediate offset in range [-255, -1]. 1168 if (!Memory.OffsetImm) return false; 1169 int64_t Val = Memory.OffsetImm->getValue(); 1170 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1171 } 1172 bool isMemUImm12Offset() const { 1173 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1174 return false; 1175 // Immediate offset in range [0, 4095]. 1176 if (!Memory.OffsetImm) return true; 1177 int64_t Val = Memory.OffsetImm->getValue(); 1178 return (Val >= 0 && Val < 4096); 1179 } 1180 bool isMemImm12Offset() const { 1181 // If we have an immediate that's not a constant, treat it as a label 1182 // reference needing a fixup. If it is a constant, it's something else 1183 // and we reject it. 1184 if (isImm() && !isa<MCConstantExpr>(getImm())) 1185 return true; 1186 1187 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1188 return false; 1189 // Immediate offset in range [-4095, 4095]. 1190 if (!Memory.OffsetImm) return true; 1191 int64_t Val = Memory.OffsetImm->getValue(); 1192 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1193 } 1194 bool isPostIdxImm8() const { 1195 if (!isImm()) return false; 1196 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1197 if (!CE) return false; 1198 int64_t Val = CE->getValue(); 1199 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1200 } 1201 bool isPostIdxImm8s4() const { 1202 if (!isImm()) return false; 1203 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1204 if (!CE) return false; 1205 int64_t Val = CE->getValue(); 1206 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1207 (Val == INT32_MIN); 1208 } 1209 1210 bool isMSRMask() const { return Kind == k_MSRMask; } 1211 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1212 1213 // NEON operands. 1214 bool isSingleSpacedVectorList() const { 1215 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1216 } 1217 bool isDoubleSpacedVectorList() const { 1218 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1219 } 1220 bool isVecListOneD() const { 1221 if (!isSingleSpacedVectorList()) return false; 1222 return VectorList.Count == 1; 1223 } 1224 1225 bool isVecListDPair() const { 1226 if (!isSingleSpacedVectorList()) return false; 1227 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1228 .contains(VectorList.RegNum)); 1229 } 1230 1231 bool isVecListThreeD() const { 1232 if (!isSingleSpacedVectorList()) return false; 1233 return VectorList.Count == 3; 1234 } 1235 1236 bool isVecListFourD() const { 1237 if (!isSingleSpacedVectorList()) return false; 1238 return VectorList.Count == 4; 1239 } 1240 1241 bool isVecListDPairSpaced() const { 1242 if (isSingleSpacedVectorList()) return false; 1243 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1244 .contains(VectorList.RegNum)); 1245 } 1246 1247 bool isVecListThreeQ() const { 1248 if (!isDoubleSpacedVectorList()) return false; 1249 return VectorList.Count == 3; 1250 } 1251 1252 bool isVecListFourQ() const { 1253 if (!isDoubleSpacedVectorList()) return false; 1254 return VectorList.Count == 4; 1255 } 1256 1257 bool isSingleSpacedVectorAllLanes() const { 1258 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1259 } 1260 bool isDoubleSpacedVectorAllLanes() const { 1261 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1262 } 1263 bool isVecListOneDAllLanes() const { 1264 if (!isSingleSpacedVectorAllLanes()) return false; 1265 return VectorList.Count == 1; 1266 } 1267 1268 bool isVecListDPairAllLanes() const { 1269 if (!isSingleSpacedVectorAllLanes()) return false; 1270 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1271 .contains(VectorList.RegNum)); 1272 } 1273 1274 bool isVecListDPairSpacedAllLanes() const { 1275 if (!isDoubleSpacedVectorAllLanes()) return false; 1276 return VectorList.Count == 2; 1277 } 1278 1279 bool isVecListThreeDAllLanes() const { 1280 if (!isSingleSpacedVectorAllLanes()) return false; 1281 return VectorList.Count == 3; 1282 } 1283 1284 bool isVecListThreeQAllLanes() const { 1285 if (!isDoubleSpacedVectorAllLanes()) return false; 1286 return VectorList.Count == 3; 1287 } 1288 1289 bool isVecListFourDAllLanes() const { 1290 if (!isSingleSpacedVectorAllLanes()) return false; 1291 return VectorList.Count == 4; 1292 } 1293 1294 bool isVecListFourQAllLanes() const { 1295 if (!isDoubleSpacedVectorAllLanes()) return false; 1296 return VectorList.Count == 4; 1297 } 1298 1299 bool isSingleSpacedVectorIndexed() const { 1300 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1301 } 1302 bool isDoubleSpacedVectorIndexed() const { 1303 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1304 } 1305 bool isVecListOneDByteIndexed() const { 1306 if (!isSingleSpacedVectorIndexed()) return false; 1307 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1308 } 1309 1310 bool isVecListOneDHWordIndexed() const { 1311 if (!isSingleSpacedVectorIndexed()) return false; 1312 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1313 } 1314 1315 bool isVecListOneDWordIndexed() const { 1316 if (!isSingleSpacedVectorIndexed()) return false; 1317 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1318 } 1319 1320 bool isVecListTwoDByteIndexed() const { 1321 if (!isSingleSpacedVectorIndexed()) return false; 1322 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1323 } 1324 1325 bool isVecListTwoDHWordIndexed() const { 1326 if (!isSingleSpacedVectorIndexed()) return false; 1327 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1328 } 1329 1330 bool isVecListTwoQWordIndexed() const { 1331 if (!isDoubleSpacedVectorIndexed()) return false; 1332 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1333 } 1334 1335 bool isVecListTwoQHWordIndexed() const { 1336 if (!isDoubleSpacedVectorIndexed()) return false; 1337 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1338 } 1339 1340 bool isVecListTwoDWordIndexed() const { 1341 if (!isSingleSpacedVectorIndexed()) return false; 1342 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1343 } 1344 1345 bool isVecListThreeDByteIndexed() const { 1346 if (!isSingleSpacedVectorIndexed()) return false; 1347 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1348 } 1349 1350 bool isVecListThreeDHWordIndexed() const { 1351 if (!isSingleSpacedVectorIndexed()) return false; 1352 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1353 } 1354 1355 bool isVecListThreeQWordIndexed() const { 1356 if (!isDoubleSpacedVectorIndexed()) return false; 1357 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1358 } 1359 1360 bool isVecListThreeQHWordIndexed() const { 1361 if (!isDoubleSpacedVectorIndexed()) return false; 1362 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1363 } 1364 1365 bool isVecListThreeDWordIndexed() const { 1366 if (!isSingleSpacedVectorIndexed()) return false; 1367 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1368 } 1369 1370 bool isVecListFourDByteIndexed() const { 1371 if (!isSingleSpacedVectorIndexed()) return false; 1372 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1373 } 1374 1375 bool isVecListFourDHWordIndexed() const { 1376 if (!isSingleSpacedVectorIndexed()) return false; 1377 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1378 } 1379 1380 bool isVecListFourQWordIndexed() const { 1381 if (!isDoubleSpacedVectorIndexed()) return false; 1382 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1383 } 1384 1385 bool isVecListFourQHWordIndexed() const { 1386 if (!isDoubleSpacedVectorIndexed()) return false; 1387 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1388 } 1389 1390 bool isVecListFourDWordIndexed() const { 1391 if (!isSingleSpacedVectorIndexed()) return false; 1392 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1393 } 1394 1395 bool isVectorIndex8() const { 1396 if (Kind != k_VectorIndex) return false; 1397 return VectorIndex.Val < 8; 1398 } 1399 bool isVectorIndex16() const { 1400 if (Kind != k_VectorIndex) return false; 1401 return VectorIndex.Val < 4; 1402 } 1403 bool isVectorIndex32() const { 1404 if (Kind != k_VectorIndex) return false; 1405 return VectorIndex.Val < 2; 1406 } 1407 1408 bool isNEONi8splat() const { 1409 if (!isImm()) return false; 1410 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1411 // Must be a constant. 1412 if (!CE) return false; 1413 int64_t Value = CE->getValue(); 1414 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1415 // value. 1416 return Value >= 0 && Value < 256; 1417 } 1418 1419 bool isNEONi16splat() const { 1420 if (!isImm()) return false; 1421 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1422 // Must be a constant. 1423 if (!CE) return false; 1424 int64_t Value = CE->getValue(); 1425 // i16 value in the range [0,255] or [0x0100, 0xff00] 1426 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1427 } 1428 1429 bool isNEONi32splat() const { 1430 if (!isImm()) return false; 1431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1432 // Must be a constant. 1433 if (!CE) return false; 1434 int64_t Value = CE->getValue(); 1435 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1436 return (Value >= 0 && Value < 256) || 1437 (Value >= 0x0100 && Value <= 0xff00) || 1438 (Value >= 0x010000 && Value <= 0xff0000) || 1439 (Value >= 0x01000000 && Value <= 0xff000000); 1440 } 1441 1442 bool isNEONi32vmov() const { 1443 if (!isImm()) return false; 1444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1445 // Must be a constant. 1446 if (!CE) return false; 1447 int64_t Value = CE->getValue(); 1448 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1449 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1450 return (Value >= 0 && Value < 256) || 1451 (Value >= 0x0100 && Value <= 0xff00) || 1452 (Value >= 0x010000 && Value <= 0xff0000) || 1453 (Value >= 0x01000000 && Value <= 0xff000000) || 1454 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1455 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1456 } 1457 bool isNEONi32vmovNeg() const { 1458 if (!isImm()) return false; 1459 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1460 // Must be a constant. 1461 if (!CE) return false; 1462 int64_t Value = ~CE->getValue(); 1463 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1464 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1465 return (Value >= 0 && Value < 256) || 1466 (Value >= 0x0100 && Value <= 0xff00) || 1467 (Value >= 0x010000 && Value <= 0xff0000) || 1468 (Value >= 0x01000000 && Value <= 0xff000000) || 1469 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1470 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1471 } 1472 1473 bool isNEONi64splat() const { 1474 if (!isImm()) return false; 1475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1476 // Must be a constant. 1477 if (!CE) return false; 1478 uint64_t Value = CE->getValue(); 1479 // i64 value with each byte being either 0 or 0xff. 1480 for (unsigned i = 0; i < 8; ++i) 1481 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1482 return true; 1483 } 1484 1485 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1486 // Add as immediates when possible. Null MCExpr = 0. 1487 if (Expr == 0) 1488 Inst.addOperand(MCOperand::CreateImm(0)); 1489 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1490 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1491 else 1492 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1493 } 1494 1495 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1496 assert(N == 2 && "Invalid number of operands!"); 1497 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1498 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1499 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1500 } 1501 1502 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1503 assert(N == 1 && "Invalid number of operands!"); 1504 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1505 } 1506 1507 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1508 assert(N == 1 && "Invalid number of operands!"); 1509 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1510 } 1511 1512 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1513 assert(N == 1 && "Invalid number of operands!"); 1514 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1515 } 1516 1517 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1518 assert(N == 1 && "Invalid number of operands!"); 1519 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1520 } 1521 1522 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1523 assert(N == 1 && "Invalid number of operands!"); 1524 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1525 } 1526 1527 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1528 assert(N == 1 && "Invalid number of operands!"); 1529 Inst.addOperand(MCOperand::CreateReg(getReg())); 1530 } 1531 1532 void addRegOperands(MCInst &Inst, unsigned N) const { 1533 assert(N == 1 && "Invalid number of operands!"); 1534 Inst.addOperand(MCOperand::CreateReg(getReg())); 1535 } 1536 1537 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1538 assert(N == 3 && "Invalid number of operands!"); 1539 assert(isRegShiftedReg() && 1540 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1541 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1542 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1543 Inst.addOperand(MCOperand::CreateImm( 1544 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1545 } 1546 1547 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1548 assert(N == 2 && "Invalid number of operands!"); 1549 assert(isRegShiftedImm() && 1550 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1551 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1552 // Shift of #32 is encoded as 0 where permitted 1553 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1554 Inst.addOperand(MCOperand::CreateImm( 1555 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1556 } 1557 1558 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1559 assert(N == 1 && "Invalid number of operands!"); 1560 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1561 ShifterImm.Imm)); 1562 } 1563 1564 void addRegListOperands(MCInst &Inst, unsigned N) const { 1565 assert(N == 1 && "Invalid number of operands!"); 1566 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1567 for (SmallVectorImpl<unsigned>::const_iterator 1568 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1569 Inst.addOperand(MCOperand::CreateReg(*I)); 1570 } 1571 1572 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1573 addRegListOperands(Inst, N); 1574 } 1575 1576 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1577 addRegListOperands(Inst, N); 1578 } 1579 1580 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1581 assert(N == 1 && "Invalid number of operands!"); 1582 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1583 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1584 } 1585 1586 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1587 assert(N == 1 && "Invalid number of operands!"); 1588 // Munge the lsb/width into a bitfield mask. 1589 unsigned lsb = Bitfield.LSB; 1590 unsigned width = Bitfield.Width; 1591 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1592 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1593 (32 - (lsb + width))); 1594 Inst.addOperand(MCOperand::CreateImm(Mask)); 1595 } 1596 1597 void addImmOperands(MCInst &Inst, unsigned N) const { 1598 assert(N == 1 && "Invalid number of operands!"); 1599 addExpr(Inst, getImm()); 1600 } 1601 1602 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1603 assert(N == 1 && "Invalid number of operands!"); 1604 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1605 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1606 } 1607 1608 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1609 assert(N == 1 && "Invalid number of operands!"); 1610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1611 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1612 } 1613 1614 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1615 assert(N == 1 && "Invalid number of operands!"); 1616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1617 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1618 Inst.addOperand(MCOperand::CreateImm(Val)); 1619 } 1620 1621 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1622 assert(N == 1 && "Invalid number of operands!"); 1623 // FIXME: We really want to scale the value here, but the LDRD/STRD 1624 // instruction don't encode operands that way yet. 1625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1626 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1627 } 1628 1629 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1630 assert(N == 1 && "Invalid number of operands!"); 1631 // The immediate is scaled by four in the encoding and is stored 1632 // in the MCInst as such. Lop off the low two bits here. 1633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1634 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1635 } 1636 1637 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1638 assert(N == 1 && "Invalid number of operands!"); 1639 // The immediate is scaled by four in the encoding and is stored 1640 // in the MCInst as such. Lop off the low two bits here. 1641 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1642 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1643 } 1644 1645 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1646 assert(N == 1 && "Invalid number of operands!"); 1647 // The immediate is scaled by four in the encoding and is stored 1648 // in the MCInst as such. Lop off the low two bits here. 1649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1650 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1651 } 1652 1653 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1654 assert(N == 1 && "Invalid number of operands!"); 1655 // The constant encodes as the immediate-1, and we store in the instruction 1656 // the bits as encoded, so subtract off one here. 1657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1658 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1659 } 1660 1661 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1662 assert(N == 1 && "Invalid number of operands!"); 1663 // The constant encodes as the immediate-1, and we store in the instruction 1664 // the bits as encoded, so subtract off one here. 1665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1666 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1667 } 1668 1669 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1670 assert(N == 1 && "Invalid number of operands!"); 1671 // The constant encodes as the immediate, except for 32, which encodes as 1672 // zero. 1673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1674 unsigned Imm = CE->getValue(); 1675 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1676 } 1677 1678 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1679 assert(N == 1 && "Invalid number of operands!"); 1680 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1681 // the instruction as well. 1682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1683 int Val = CE->getValue(); 1684 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1685 } 1686 1687 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1688 assert(N == 1 && "Invalid number of operands!"); 1689 // The operand is actually a t2_so_imm, but we have its bitwise 1690 // negation in the assembly source, so twiddle it here. 1691 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1692 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1693 } 1694 1695 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1696 assert(N == 1 && "Invalid number of operands!"); 1697 // The operand is actually a t2_so_imm, but we have its 1698 // negation in the assembly source, so twiddle it here. 1699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1700 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1701 } 1702 1703 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1704 assert(N == 1 && "Invalid number of operands!"); 1705 // The operand is actually an imm0_4095, but we have its 1706 // negation in the assembly source, so twiddle it here. 1707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1708 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1709 } 1710 1711 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1712 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1713 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); 1714 return; 1715 } 1716 1717 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1718 assert(SR && "Unknown value type!"); 1719 Inst.addOperand(MCOperand::CreateExpr(SR)); 1720 } 1721 1722 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1723 assert(N == 1 && "Invalid number of operands!"); 1724 if (isImm()) { 1725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1726 if (CE) { 1727 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1728 return; 1729 } 1730 1731 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1732 assert(SR && "Unknown value type!"); 1733 Inst.addOperand(MCOperand::CreateExpr(SR)); 1734 return; 1735 } 1736 1737 assert(isMem() && "Unknown value type!"); 1738 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1739 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); 1740 } 1741 1742 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1743 assert(N == 1 && "Invalid number of operands!"); 1744 // The operand is actually a so_imm, but we have its bitwise 1745 // negation in the assembly source, so twiddle it here. 1746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1747 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1748 } 1749 1750 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1751 assert(N == 1 && "Invalid number of operands!"); 1752 // The operand is actually a so_imm, but we have its 1753 // negation in the assembly source, so twiddle it here. 1754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1755 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1756 } 1757 1758 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1759 assert(N == 1 && "Invalid number of operands!"); 1760 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1761 } 1762 1763 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1764 assert(N == 1 && "Invalid number of operands!"); 1765 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1766 } 1767 1768 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1769 assert(N == 1 && "Invalid number of operands!"); 1770 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1771 } 1772 1773 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1774 assert(N == 1 && "Invalid number of operands!"); 1775 int32_t Imm = Memory.OffsetImm->getValue(); 1776 // FIXME: Handle #-0 1777 if (Imm == INT32_MIN) Imm = 0; 1778 Inst.addOperand(MCOperand::CreateImm(Imm)); 1779 } 1780 1781 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1782 assert(N == 1 && "Invalid number of operands!"); 1783 assert(isImm() && "Not an immediate!"); 1784 1785 // If we have an immediate that's not a constant, treat it as a label 1786 // reference needing a fixup. 1787 if (!isa<MCConstantExpr>(getImm())) { 1788 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1789 return; 1790 } 1791 1792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1793 int Val = CE->getValue(); 1794 Inst.addOperand(MCOperand::CreateImm(Val)); 1795 } 1796 1797 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1798 assert(N == 2 && "Invalid number of operands!"); 1799 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1800 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1801 } 1802 1803 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1804 assert(N == 3 && "Invalid number of operands!"); 1805 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1806 if (!Memory.OffsetRegNum) { 1807 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1808 // Special case for #-0 1809 if (Val == INT32_MIN) Val = 0; 1810 if (Val < 0) Val = -Val; 1811 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1812 } else { 1813 // For register offset, we encode the shift type and negation flag 1814 // here. 1815 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1816 Memory.ShiftImm, Memory.ShiftType); 1817 } 1818 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1819 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1820 Inst.addOperand(MCOperand::CreateImm(Val)); 1821 } 1822 1823 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1824 assert(N == 2 && "Invalid number of operands!"); 1825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1826 assert(CE && "non-constant AM2OffsetImm operand!"); 1827 int32_t Val = CE->getValue(); 1828 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1829 // Special case for #-0 1830 if (Val == INT32_MIN) Val = 0; 1831 if (Val < 0) Val = -Val; 1832 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1833 Inst.addOperand(MCOperand::CreateReg(0)); 1834 Inst.addOperand(MCOperand::CreateImm(Val)); 1835 } 1836 1837 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1838 assert(N == 3 && "Invalid number of operands!"); 1839 // If we have an immediate that's not a constant, treat it as a label 1840 // reference needing a fixup. If it is a constant, it's something else 1841 // and we reject it. 1842 if (isImm()) { 1843 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1844 Inst.addOperand(MCOperand::CreateReg(0)); 1845 Inst.addOperand(MCOperand::CreateImm(0)); 1846 return; 1847 } 1848 1849 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1850 if (!Memory.OffsetRegNum) { 1851 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1852 // Special case for #-0 1853 if (Val == INT32_MIN) Val = 0; 1854 if (Val < 0) Val = -Val; 1855 Val = ARM_AM::getAM3Opc(AddSub, Val); 1856 } else { 1857 // For register offset, we encode the shift type and negation flag 1858 // here. 1859 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1860 } 1861 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1862 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1863 Inst.addOperand(MCOperand::CreateImm(Val)); 1864 } 1865 1866 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1867 assert(N == 2 && "Invalid number of operands!"); 1868 if (Kind == k_PostIndexRegister) { 1869 int32_t Val = 1870 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1871 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1872 Inst.addOperand(MCOperand::CreateImm(Val)); 1873 return; 1874 } 1875 1876 // Constant offset. 1877 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1878 int32_t Val = CE->getValue(); 1879 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1880 // Special case for #-0 1881 if (Val == INT32_MIN) Val = 0; 1882 if (Val < 0) Val = -Val; 1883 Val = ARM_AM::getAM3Opc(AddSub, Val); 1884 Inst.addOperand(MCOperand::CreateReg(0)); 1885 Inst.addOperand(MCOperand::CreateImm(Val)); 1886 } 1887 1888 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1889 assert(N == 2 && "Invalid number of operands!"); 1890 // If we have an immediate that's not a constant, treat it as a label 1891 // reference needing a fixup. If it is a constant, it's something else 1892 // and we reject it. 1893 if (isImm()) { 1894 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1895 Inst.addOperand(MCOperand::CreateImm(0)); 1896 return; 1897 } 1898 1899 // The lower two bits are always zero and as such are not encoded. 1900 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1901 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1902 // Special case for #-0 1903 if (Val == INT32_MIN) Val = 0; 1904 if (Val < 0) Val = -Val; 1905 Val = ARM_AM::getAM5Opc(AddSub, Val); 1906 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1907 Inst.addOperand(MCOperand::CreateImm(Val)); 1908 } 1909 1910 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1911 assert(N == 2 && "Invalid number of operands!"); 1912 // If we have an immediate that's not a constant, treat it as a label 1913 // reference needing a fixup. If it is a constant, it's something else 1914 // and we reject it. 1915 if (isImm()) { 1916 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1917 Inst.addOperand(MCOperand::CreateImm(0)); 1918 return; 1919 } 1920 1921 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1922 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1923 Inst.addOperand(MCOperand::CreateImm(Val)); 1924 } 1925 1926 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1927 assert(N == 2 && "Invalid number of operands!"); 1928 // The lower two bits are always zero and as such are not encoded. 1929 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1930 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1931 Inst.addOperand(MCOperand::CreateImm(Val)); 1932 } 1933 1934 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1935 assert(N == 2 && "Invalid number of operands!"); 1936 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1937 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1938 Inst.addOperand(MCOperand::CreateImm(Val)); 1939 } 1940 1941 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1942 addMemImm8OffsetOperands(Inst, N); 1943 } 1944 1945 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1946 addMemImm8OffsetOperands(Inst, N); 1947 } 1948 1949 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1950 assert(N == 2 && "Invalid number of operands!"); 1951 // If this is an immediate, it's a label reference. 1952 if (isImm()) { 1953 addExpr(Inst, getImm()); 1954 Inst.addOperand(MCOperand::CreateImm(0)); 1955 return; 1956 } 1957 1958 // Otherwise, it's a normal memory reg+offset. 1959 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1960 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1961 Inst.addOperand(MCOperand::CreateImm(Val)); 1962 } 1963 1964 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1965 assert(N == 2 && "Invalid number of operands!"); 1966 // If this is an immediate, it's a label reference. 1967 if (isImm()) { 1968 addExpr(Inst, getImm()); 1969 Inst.addOperand(MCOperand::CreateImm(0)); 1970 return; 1971 } 1972 1973 // Otherwise, it's a normal memory reg+offset. 1974 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1975 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1976 Inst.addOperand(MCOperand::CreateImm(Val)); 1977 } 1978 1979 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1980 assert(N == 2 && "Invalid number of operands!"); 1981 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1982 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1983 } 1984 1985 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1986 assert(N == 2 && "Invalid number of operands!"); 1987 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1988 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1989 } 1990 1991 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1992 assert(N == 3 && "Invalid number of operands!"); 1993 unsigned Val = 1994 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1995 Memory.ShiftImm, Memory.ShiftType); 1996 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1997 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1998 Inst.addOperand(MCOperand::CreateImm(Val)); 1999 } 2000 2001 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2002 assert(N == 3 && "Invalid number of operands!"); 2003 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2004 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2005 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 2006 } 2007 2008 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2009 assert(N == 2 && "Invalid number of operands!"); 2010 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2011 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2012 } 2013 2014 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2015 assert(N == 2 && "Invalid number of operands!"); 2016 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2017 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2018 Inst.addOperand(MCOperand::CreateImm(Val)); 2019 } 2020 2021 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2022 assert(N == 2 && "Invalid number of operands!"); 2023 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2024 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2025 Inst.addOperand(MCOperand::CreateImm(Val)); 2026 } 2027 2028 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2029 assert(N == 2 && "Invalid number of operands!"); 2030 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2031 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2032 Inst.addOperand(MCOperand::CreateImm(Val)); 2033 } 2034 2035 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2036 assert(N == 2 && "Invalid number of operands!"); 2037 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2038 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2039 Inst.addOperand(MCOperand::CreateImm(Val)); 2040 } 2041 2042 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2043 assert(N == 1 && "Invalid number of operands!"); 2044 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2045 assert(CE && "non-constant post-idx-imm8 operand!"); 2046 int Imm = CE->getValue(); 2047 bool isAdd = Imm >= 0; 2048 if (Imm == INT32_MIN) Imm = 0; 2049 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2050 Inst.addOperand(MCOperand::CreateImm(Imm)); 2051 } 2052 2053 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2054 assert(N == 1 && "Invalid number of operands!"); 2055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2056 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2057 int Imm = CE->getValue(); 2058 bool isAdd = Imm >= 0; 2059 if (Imm == INT32_MIN) Imm = 0; 2060 // Immediate is scaled by 4. 2061 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2062 Inst.addOperand(MCOperand::CreateImm(Imm)); 2063 } 2064 2065 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2066 assert(N == 2 && "Invalid number of operands!"); 2067 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2068 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2069 } 2070 2071 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2072 assert(N == 2 && "Invalid number of operands!"); 2073 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2074 // The sign, shift type, and shift amount are encoded in a single operand 2075 // using the AM2 encoding helpers. 2076 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2077 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2078 PostIdxReg.ShiftTy); 2079 Inst.addOperand(MCOperand::CreateImm(Imm)); 2080 } 2081 2082 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2083 assert(N == 1 && "Invalid number of operands!"); 2084 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2085 } 2086 2087 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2088 assert(N == 1 && "Invalid number of operands!"); 2089 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2090 } 2091 2092 void addVecListOperands(MCInst &Inst, unsigned N) const { 2093 assert(N == 1 && "Invalid number of operands!"); 2094 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2095 } 2096 2097 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2098 assert(N == 2 && "Invalid number of operands!"); 2099 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2100 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2101 } 2102 2103 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2104 assert(N == 1 && "Invalid number of operands!"); 2105 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2106 } 2107 2108 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2109 assert(N == 1 && "Invalid number of operands!"); 2110 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2111 } 2112 2113 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2114 assert(N == 1 && "Invalid number of operands!"); 2115 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2116 } 2117 2118 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2119 assert(N == 1 && "Invalid number of operands!"); 2120 // The immediate encodes the type of constant as well as the value. 2121 // Mask in that this is an i8 splat. 2122 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2123 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2124 } 2125 2126 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2127 assert(N == 1 && "Invalid number of operands!"); 2128 // The immediate encodes the type of constant as well as the value. 2129 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2130 unsigned Value = CE->getValue(); 2131 if (Value >= 256) 2132 Value = (Value >> 8) | 0xa00; 2133 else 2134 Value |= 0x800; 2135 Inst.addOperand(MCOperand::CreateImm(Value)); 2136 } 2137 2138 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2139 assert(N == 1 && "Invalid number of operands!"); 2140 // The immediate encodes the type of constant as well as the value. 2141 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2142 unsigned Value = CE->getValue(); 2143 if (Value >= 256 && Value <= 0xff00) 2144 Value = (Value >> 8) | 0x200; 2145 else if (Value > 0xffff && Value <= 0xff0000) 2146 Value = (Value >> 16) | 0x400; 2147 else if (Value > 0xffffff) 2148 Value = (Value >> 24) | 0x600; 2149 Inst.addOperand(MCOperand::CreateImm(Value)); 2150 } 2151 2152 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2153 assert(N == 1 && "Invalid number of operands!"); 2154 // The immediate encodes the type of constant as well as the value. 2155 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2156 unsigned Value = CE->getValue(); 2157 if (Value >= 256 && Value <= 0xffff) 2158 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2159 else if (Value > 0xffff && Value <= 0xffffff) 2160 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2161 else if (Value > 0xffffff) 2162 Value = (Value >> 24) | 0x600; 2163 Inst.addOperand(MCOperand::CreateImm(Value)); 2164 } 2165 2166 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2167 assert(N == 1 && "Invalid number of operands!"); 2168 // The immediate encodes the type of constant as well as the value. 2169 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2170 unsigned Value = ~CE->getValue(); 2171 if (Value >= 256 && Value <= 0xffff) 2172 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2173 else if (Value > 0xffff && Value <= 0xffffff) 2174 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2175 else if (Value > 0xffffff) 2176 Value = (Value >> 24) | 0x600; 2177 Inst.addOperand(MCOperand::CreateImm(Value)); 2178 } 2179 2180 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2181 assert(N == 1 && "Invalid number of operands!"); 2182 // The immediate encodes the type of constant as well as the value. 2183 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2184 uint64_t Value = CE->getValue(); 2185 unsigned Imm = 0; 2186 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2187 Imm |= (Value & 1) << i; 2188 } 2189 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2190 } 2191 2192 virtual void print(raw_ostream &OS) const; 2193 2194 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2195 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2196 Op->ITMask.Mask = Mask; 2197 Op->StartLoc = S; 2198 Op->EndLoc = S; 2199 return Op; 2200 } 2201 2202 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2203 ARMOperand *Op = new ARMOperand(k_CondCode); 2204 Op->CC.Val = CC; 2205 Op->StartLoc = S; 2206 Op->EndLoc = S; 2207 return Op; 2208 } 2209 2210 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2211 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2212 Op->Cop.Val = CopVal; 2213 Op->StartLoc = S; 2214 Op->EndLoc = S; 2215 return Op; 2216 } 2217 2218 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2219 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2220 Op->Cop.Val = CopVal; 2221 Op->StartLoc = S; 2222 Op->EndLoc = S; 2223 return Op; 2224 } 2225 2226 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2227 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2228 Op->Cop.Val = Val; 2229 Op->StartLoc = S; 2230 Op->EndLoc = E; 2231 return Op; 2232 } 2233 2234 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2235 ARMOperand *Op = new ARMOperand(k_CCOut); 2236 Op->Reg.RegNum = RegNum; 2237 Op->StartLoc = S; 2238 Op->EndLoc = S; 2239 return Op; 2240 } 2241 2242 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2243 ARMOperand *Op = new ARMOperand(k_Token); 2244 Op->Tok.Data = Str.data(); 2245 Op->Tok.Length = Str.size(); 2246 Op->StartLoc = S; 2247 Op->EndLoc = S; 2248 return Op; 2249 } 2250 2251 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2252 ARMOperand *Op = new ARMOperand(k_Register); 2253 Op->Reg.RegNum = RegNum; 2254 Op->StartLoc = S; 2255 Op->EndLoc = E; 2256 return Op; 2257 } 2258 2259 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2260 unsigned SrcReg, 2261 unsigned ShiftReg, 2262 unsigned ShiftImm, 2263 SMLoc S, SMLoc E) { 2264 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2265 Op->RegShiftedReg.ShiftTy = ShTy; 2266 Op->RegShiftedReg.SrcReg = SrcReg; 2267 Op->RegShiftedReg.ShiftReg = ShiftReg; 2268 Op->RegShiftedReg.ShiftImm = ShiftImm; 2269 Op->StartLoc = S; 2270 Op->EndLoc = E; 2271 return Op; 2272 } 2273 2274 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2275 unsigned SrcReg, 2276 unsigned ShiftImm, 2277 SMLoc S, SMLoc E) { 2278 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2279 Op->RegShiftedImm.ShiftTy = ShTy; 2280 Op->RegShiftedImm.SrcReg = SrcReg; 2281 Op->RegShiftedImm.ShiftImm = ShiftImm; 2282 Op->StartLoc = S; 2283 Op->EndLoc = E; 2284 return Op; 2285 } 2286 2287 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2288 SMLoc S, SMLoc E) { 2289 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2290 Op->ShifterImm.isASR = isASR; 2291 Op->ShifterImm.Imm = Imm; 2292 Op->StartLoc = S; 2293 Op->EndLoc = E; 2294 return Op; 2295 } 2296 2297 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2298 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2299 Op->RotImm.Imm = Imm; 2300 Op->StartLoc = S; 2301 Op->EndLoc = E; 2302 return Op; 2303 } 2304 2305 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2306 SMLoc S, SMLoc E) { 2307 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2308 Op->Bitfield.LSB = LSB; 2309 Op->Bitfield.Width = Width; 2310 Op->StartLoc = S; 2311 Op->EndLoc = E; 2312 return Op; 2313 } 2314 2315 static ARMOperand * 2316 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs, 2317 SMLoc StartLoc, SMLoc EndLoc) { 2318 assert (Regs.size() > 0 && "RegList contains no registers?"); 2319 KindTy Kind = k_RegisterList; 2320 2321 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2322 Kind = k_DPRRegisterList; 2323 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2324 contains(Regs.front().second)) 2325 Kind = k_SPRRegisterList; 2326 2327 // Sort based on the register encoding values. 2328 array_pod_sort(Regs.begin(), Regs.end()); 2329 2330 ARMOperand *Op = new ARMOperand(Kind); 2331 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2332 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2333 Op->Registers.push_back(I->second); 2334 Op->StartLoc = StartLoc; 2335 Op->EndLoc = EndLoc; 2336 return Op; 2337 } 2338 2339 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2340 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2341 ARMOperand *Op = new ARMOperand(k_VectorList); 2342 Op->VectorList.RegNum = RegNum; 2343 Op->VectorList.Count = Count; 2344 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2345 Op->StartLoc = S; 2346 Op->EndLoc = E; 2347 return Op; 2348 } 2349 2350 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2351 bool isDoubleSpaced, 2352 SMLoc S, SMLoc E) { 2353 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2354 Op->VectorList.RegNum = RegNum; 2355 Op->VectorList.Count = Count; 2356 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2357 Op->StartLoc = S; 2358 Op->EndLoc = E; 2359 return Op; 2360 } 2361 2362 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2363 unsigned Index, 2364 bool isDoubleSpaced, 2365 SMLoc S, SMLoc E) { 2366 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2367 Op->VectorList.RegNum = RegNum; 2368 Op->VectorList.Count = Count; 2369 Op->VectorList.LaneIndex = Index; 2370 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2371 Op->StartLoc = S; 2372 Op->EndLoc = E; 2373 return Op; 2374 } 2375 2376 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2377 MCContext &Ctx) { 2378 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2379 Op->VectorIndex.Val = Idx; 2380 Op->StartLoc = S; 2381 Op->EndLoc = E; 2382 return Op; 2383 } 2384 2385 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2386 ARMOperand *Op = new ARMOperand(k_Immediate); 2387 Op->Imm.Val = Val; 2388 Op->StartLoc = S; 2389 Op->EndLoc = E; 2390 return Op; 2391 } 2392 2393 static ARMOperand *CreateMem(unsigned BaseRegNum, 2394 const MCConstantExpr *OffsetImm, 2395 unsigned OffsetRegNum, 2396 ARM_AM::ShiftOpc ShiftType, 2397 unsigned ShiftImm, 2398 unsigned Alignment, 2399 bool isNegative, 2400 SMLoc S, SMLoc E) { 2401 ARMOperand *Op = new ARMOperand(k_Memory); 2402 Op->Memory.BaseRegNum = BaseRegNum; 2403 Op->Memory.OffsetImm = OffsetImm; 2404 Op->Memory.OffsetRegNum = OffsetRegNum; 2405 Op->Memory.ShiftType = ShiftType; 2406 Op->Memory.ShiftImm = ShiftImm; 2407 Op->Memory.Alignment = Alignment; 2408 Op->Memory.isNegative = isNegative; 2409 Op->StartLoc = S; 2410 Op->EndLoc = E; 2411 return Op; 2412 } 2413 2414 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2415 ARM_AM::ShiftOpc ShiftTy, 2416 unsigned ShiftImm, 2417 SMLoc S, SMLoc E) { 2418 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2419 Op->PostIdxReg.RegNum = RegNum; 2420 Op->PostIdxReg.isAdd = isAdd; 2421 Op->PostIdxReg.ShiftTy = ShiftTy; 2422 Op->PostIdxReg.ShiftImm = ShiftImm; 2423 Op->StartLoc = S; 2424 Op->EndLoc = E; 2425 return Op; 2426 } 2427 2428 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2429 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2430 Op->MBOpt.Val = Opt; 2431 Op->StartLoc = S; 2432 Op->EndLoc = S; 2433 return Op; 2434 } 2435 2436 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, 2437 SMLoc S) { 2438 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt); 2439 Op->ISBOpt.Val = Opt; 2440 Op->StartLoc = S; 2441 Op->EndLoc = S; 2442 return Op; 2443 } 2444 2445 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2446 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2447 Op->IFlags.Val = IFlags; 2448 Op->StartLoc = S; 2449 Op->EndLoc = S; 2450 return Op; 2451 } 2452 2453 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2454 ARMOperand *Op = new ARMOperand(k_MSRMask); 2455 Op->MMask.Val = MMask; 2456 Op->StartLoc = S; 2457 Op->EndLoc = S; 2458 return Op; 2459 } 2460 }; 2461 2462 } // end anonymous namespace. 2463 2464 void ARMOperand::print(raw_ostream &OS) const { 2465 switch (Kind) { 2466 case k_CondCode: 2467 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2468 break; 2469 case k_CCOut: 2470 OS << "<ccout " << getReg() << ">"; 2471 break; 2472 case k_ITCondMask: { 2473 static const char *const MaskStr[] = { 2474 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2475 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2476 }; 2477 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2478 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2479 break; 2480 } 2481 case k_CoprocNum: 2482 OS << "<coprocessor number: " << getCoproc() << ">"; 2483 break; 2484 case k_CoprocReg: 2485 OS << "<coprocessor register: " << getCoproc() << ">"; 2486 break; 2487 case k_CoprocOption: 2488 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2489 break; 2490 case k_MSRMask: 2491 OS << "<mask: " << getMSRMask() << ">"; 2492 break; 2493 case k_Immediate: 2494 getImm()->print(OS); 2495 break; 2496 case k_MemBarrierOpt: 2497 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2498 break; 2499 case k_InstSyncBarrierOpt: 2500 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2501 break; 2502 case k_Memory: 2503 OS << "<memory " 2504 << " base:" << Memory.BaseRegNum; 2505 OS << ">"; 2506 break; 2507 case k_PostIndexRegister: 2508 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2509 << PostIdxReg.RegNum; 2510 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2511 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2512 << PostIdxReg.ShiftImm; 2513 OS << ">"; 2514 break; 2515 case k_ProcIFlags: { 2516 OS << "<ARM_PROC::"; 2517 unsigned IFlags = getProcIFlags(); 2518 for (int i=2; i >= 0; --i) 2519 if (IFlags & (1 << i)) 2520 OS << ARM_PROC::IFlagsToString(1 << i); 2521 OS << ">"; 2522 break; 2523 } 2524 case k_Register: 2525 OS << "<register " << getReg() << ">"; 2526 break; 2527 case k_ShifterImmediate: 2528 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2529 << " #" << ShifterImm.Imm << ">"; 2530 break; 2531 case k_ShiftedRegister: 2532 OS << "<so_reg_reg " 2533 << RegShiftedReg.SrcReg << " " 2534 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2535 << " " << RegShiftedReg.ShiftReg << ">"; 2536 break; 2537 case k_ShiftedImmediate: 2538 OS << "<so_reg_imm " 2539 << RegShiftedImm.SrcReg << " " 2540 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2541 << " #" << RegShiftedImm.ShiftImm << ">"; 2542 break; 2543 case k_RotateImmediate: 2544 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2545 break; 2546 case k_BitfieldDescriptor: 2547 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2548 << ", width: " << Bitfield.Width << ">"; 2549 break; 2550 case k_RegisterList: 2551 case k_DPRRegisterList: 2552 case k_SPRRegisterList: { 2553 OS << "<register_list "; 2554 2555 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2556 for (SmallVectorImpl<unsigned>::const_iterator 2557 I = RegList.begin(), E = RegList.end(); I != E; ) { 2558 OS << *I; 2559 if (++I < E) OS << ", "; 2560 } 2561 2562 OS << ">"; 2563 break; 2564 } 2565 case k_VectorList: 2566 OS << "<vector_list " << VectorList.Count << " * " 2567 << VectorList.RegNum << ">"; 2568 break; 2569 case k_VectorListAllLanes: 2570 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2571 << VectorList.RegNum << ">"; 2572 break; 2573 case k_VectorListIndexed: 2574 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2575 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2576 break; 2577 case k_Token: 2578 OS << "'" << getToken() << "'"; 2579 break; 2580 case k_VectorIndex: 2581 OS << "<vectorindex " << getVectorIndex() << ">"; 2582 break; 2583 } 2584 } 2585 2586 /// @name Auto-generated Match Functions 2587 /// { 2588 2589 static unsigned MatchRegisterName(StringRef Name); 2590 2591 /// } 2592 2593 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2594 SMLoc &StartLoc, SMLoc &EndLoc) { 2595 StartLoc = Parser.getTok().getLoc(); 2596 EndLoc = Parser.getTok().getEndLoc(); 2597 RegNo = tryParseRegister(); 2598 2599 return (RegNo == (unsigned)-1); 2600 } 2601 2602 /// Try to parse a register name. The token must be an Identifier when called, 2603 /// and if it is a register name the token is eaten and the register number is 2604 /// returned. Otherwise return -1. 2605 /// 2606 int ARMAsmParser::tryParseRegister() { 2607 const AsmToken &Tok = Parser.getTok(); 2608 if (Tok.isNot(AsmToken::Identifier)) return -1; 2609 2610 std::string lowerCase = Tok.getString().lower(); 2611 unsigned RegNum = MatchRegisterName(lowerCase); 2612 if (!RegNum) { 2613 RegNum = StringSwitch<unsigned>(lowerCase) 2614 .Case("r13", ARM::SP) 2615 .Case("r14", ARM::LR) 2616 .Case("r15", ARM::PC) 2617 .Case("ip", ARM::R12) 2618 // Additional register name aliases for 'gas' compatibility. 2619 .Case("a1", ARM::R0) 2620 .Case("a2", ARM::R1) 2621 .Case("a3", ARM::R2) 2622 .Case("a4", ARM::R3) 2623 .Case("v1", ARM::R4) 2624 .Case("v2", ARM::R5) 2625 .Case("v3", ARM::R6) 2626 .Case("v4", ARM::R7) 2627 .Case("v5", ARM::R8) 2628 .Case("v6", ARM::R9) 2629 .Case("v7", ARM::R10) 2630 .Case("v8", ARM::R11) 2631 .Case("sb", ARM::R9) 2632 .Case("sl", ARM::R10) 2633 .Case("fp", ARM::R11) 2634 .Default(0); 2635 } 2636 if (!RegNum) { 2637 // Check for aliases registered via .req. Canonicalize to lower case. 2638 // That's more consistent since register names are case insensitive, and 2639 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2640 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2641 // If no match, return failure. 2642 if (Entry == RegisterReqs.end()) 2643 return -1; 2644 Parser.Lex(); // Eat identifier token. 2645 return Entry->getValue(); 2646 } 2647 2648 Parser.Lex(); // Eat identifier token. 2649 2650 return RegNum; 2651 } 2652 2653 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2654 // If a recoverable error occurs, return 1. If an irrecoverable error 2655 // occurs, return -1. An irrecoverable error is one where tokens have been 2656 // consumed in the process of trying to parse the shifter (i.e., when it is 2657 // indeed a shifter operand, but malformed). 2658 int ARMAsmParser::tryParseShiftRegister( 2659 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2660 SMLoc S = Parser.getTok().getLoc(); 2661 const AsmToken &Tok = Parser.getTok(); 2662 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2663 2664 std::string lowerCase = Tok.getString().lower(); 2665 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2666 .Case("asl", ARM_AM::lsl) 2667 .Case("lsl", ARM_AM::lsl) 2668 .Case("lsr", ARM_AM::lsr) 2669 .Case("asr", ARM_AM::asr) 2670 .Case("ror", ARM_AM::ror) 2671 .Case("rrx", ARM_AM::rrx) 2672 .Default(ARM_AM::no_shift); 2673 2674 if (ShiftTy == ARM_AM::no_shift) 2675 return 1; 2676 2677 Parser.Lex(); // Eat the operator. 2678 2679 // The source register for the shift has already been added to the 2680 // operand list, so we need to pop it off and combine it into the shifted 2681 // register operand instead. 2682 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2683 if (!PrevOp->isReg()) 2684 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2685 int SrcReg = PrevOp->getReg(); 2686 2687 SMLoc EndLoc; 2688 int64_t Imm = 0; 2689 int ShiftReg = 0; 2690 if (ShiftTy == ARM_AM::rrx) { 2691 // RRX Doesn't have an explicit shift amount. The encoder expects 2692 // the shift register to be the same as the source register. Seems odd, 2693 // but OK. 2694 ShiftReg = SrcReg; 2695 } else { 2696 // Figure out if this is shifted by a constant or a register (for non-RRX). 2697 if (Parser.getTok().is(AsmToken::Hash) || 2698 Parser.getTok().is(AsmToken::Dollar)) { 2699 Parser.Lex(); // Eat hash. 2700 SMLoc ImmLoc = Parser.getTok().getLoc(); 2701 const MCExpr *ShiftExpr = 0; 2702 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2703 Error(ImmLoc, "invalid immediate shift value"); 2704 return -1; 2705 } 2706 // The expression must be evaluatable as an immediate. 2707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2708 if (!CE) { 2709 Error(ImmLoc, "invalid immediate shift value"); 2710 return -1; 2711 } 2712 // Range check the immediate. 2713 // lsl, ror: 0 <= imm <= 31 2714 // lsr, asr: 0 <= imm <= 32 2715 Imm = CE->getValue(); 2716 if (Imm < 0 || 2717 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2718 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2719 Error(ImmLoc, "immediate shift value out of range"); 2720 return -1; 2721 } 2722 // shift by zero is a nop. Always send it through as lsl. 2723 // ('as' compatibility) 2724 if (Imm == 0) 2725 ShiftTy = ARM_AM::lsl; 2726 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2727 SMLoc L = Parser.getTok().getLoc(); 2728 EndLoc = Parser.getTok().getEndLoc(); 2729 ShiftReg = tryParseRegister(); 2730 if (ShiftReg == -1) { 2731 Error (L, "expected immediate or register in shift operand"); 2732 return -1; 2733 } 2734 } else { 2735 Error (Parser.getTok().getLoc(), 2736 "expected immediate or register in shift operand"); 2737 return -1; 2738 } 2739 } 2740 2741 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2742 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2743 ShiftReg, Imm, 2744 S, EndLoc)); 2745 else 2746 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2747 S, EndLoc)); 2748 2749 return 0; 2750 } 2751 2752 2753 /// Try to parse a register name. The token must be an Identifier when called. 2754 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2755 /// if there is a "writeback". 'true' if it's not a register. 2756 /// 2757 /// TODO this is likely to change to allow different register types and or to 2758 /// parse for a specific register type. 2759 bool ARMAsmParser:: 2760 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2761 const AsmToken &RegTok = Parser.getTok(); 2762 int RegNo = tryParseRegister(); 2763 if (RegNo == -1) 2764 return true; 2765 2766 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2767 RegTok.getEndLoc())); 2768 2769 const AsmToken &ExclaimTok = Parser.getTok(); 2770 if (ExclaimTok.is(AsmToken::Exclaim)) { 2771 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2772 ExclaimTok.getLoc())); 2773 Parser.Lex(); // Eat exclaim token 2774 return false; 2775 } 2776 2777 // Also check for an index operand. This is only legal for vector registers, 2778 // but that'll get caught OK in operand matching, so we don't need to 2779 // explicitly filter everything else out here. 2780 if (Parser.getTok().is(AsmToken::LBrac)) { 2781 SMLoc SIdx = Parser.getTok().getLoc(); 2782 Parser.Lex(); // Eat left bracket token. 2783 2784 const MCExpr *ImmVal; 2785 if (getParser().parseExpression(ImmVal)) 2786 return true; 2787 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2788 if (!MCE) 2789 return TokError("immediate value expected for vector index"); 2790 2791 if (Parser.getTok().isNot(AsmToken::RBrac)) 2792 return Error(Parser.getTok().getLoc(), "']' expected"); 2793 2794 SMLoc E = Parser.getTok().getEndLoc(); 2795 Parser.Lex(); // Eat right bracket token. 2796 2797 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2798 SIdx, E, 2799 getContext())); 2800 } 2801 2802 return false; 2803 } 2804 2805 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2806 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2807 /// "c5", ... 2808 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2809 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2810 // but efficient. 2811 switch (Name.size()) { 2812 default: return -1; 2813 case 2: 2814 if (Name[0] != CoprocOp) 2815 return -1; 2816 switch (Name[1]) { 2817 default: return -1; 2818 case '0': return 0; 2819 case '1': return 1; 2820 case '2': return 2; 2821 case '3': return 3; 2822 case '4': return 4; 2823 case '5': return 5; 2824 case '6': return 6; 2825 case '7': return 7; 2826 case '8': return 8; 2827 case '9': return 9; 2828 } 2829 case 3: 2830 if (Name[0] != CoprocOp || Name[1] != '1') 2831 return -1; 2832 switch (Name[2]) { 2833 default: return -1; 2834 case '0': return 10; 2835 case '1': return 11; 2836 case '2': return 12; 2837 case '3': return 13; 2838 case '4': return 14; 2839 case '5': return 15; 2840 } 2841 } 2842 } 2843 2844 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2845 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2846 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2847 SMLoc S = Parser.getTok().getLoc(); 2848 const AsmToken &Tok = Parser.getTok(); 2849 if (!Tok.is(AsmToken::Identifier)) 2850 return MatchOperand_NoMatch; 2851 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2852 .Case("eq", ARMCC::EQ) 2853 .Case("ne", ARMCC::NE) 2854 .Case("hs", ARMCC::HS) 2855 .Case("cs", ARMCC::HS) 2856 .Case("lo", ARMCC::LO) 2857 .Case("cc", ARMCC::LO) 2858 .Case("mi", ARMCC::MI) 2859 .Case("pl", ARMCC::PL) 2860 .Case("vs", ARMCC::VS) 2861 .Case("vc", ARMCC::VC) 2862 .Case("hi", ARMCC::HI) 2863 .Case("ls", ARMCC::LS) 2864 .Case("ge", ARMCC::GE) 2865 .Case("lt", ARMCC::LT) 2866 .Case("gt", ARMCC::GT) 2867 .Case("le", ARMCC::LE) 2868 .Case("al", ARMCC::AL) 2869 .Default(~0U); 2870 if (CC == ~0U) 2871 return MatchOperand_NoMatch; 2872 Parser.Lex(); // Eat the token. 2873 2874 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2875 2876 return MatchOperand_Success; 2877 } 2878 2879 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2880 /// token must be an Identifier when called, and if it is a coprocessor 2881 /// number, the token is eaten and the operand is added to the operand list. 2882 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2883 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2884 SMLoc S = Parser.getTok().getLoc(); 2885 const AsmToken &Tok = Parser.getTok(); 2886 if (Tok.isNot(AsmToken::Identifier)) 2887 return MatchOperand_NoMatch; 2888 2889 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2890 if (Num == -1) 2891 return MatchOperand_NoMatch; 2892 2893 Parser.Lex(); // Eat identifier token. 2894 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2895 return MatchOperand_Success; 2896 } 2897 2898 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2899 /// token must be an Identifier when called, and if it is a coprocessor 2900 /// number, the token is eaten and the operand is added to the operand list. 2901 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2902 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2903 SMLoc S = Parser.getTok().getLoc(); 2904 const AsmToken &Tok = Parser.getTok(); 2905 if (Tok.isNot(AsmToken::Identifier)) 2906 return MatchOperand_NoMatch; 2907 2908 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2909 if (Reg == -1) 2910 return MatchOperand_NoMatch; 2911 2912 Parser.Lex(); // Eat identifier token. 2913 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2914 return MatchOperand_Success; 2915 } 2916 2917 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2918 /// coproc_option : '{' imm0_255 '}' 2919 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2920 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2921 SMLoc S = Parser.getTok().getLoc(); 2922 2923 // If this isn't a '{', this isn't a coprocessor immediate operand. 2924 if (Parser.getTok().isNot(AsmToken::LCurly)) 2925 return MatchOperand_NoMatch; 2926 Parser.Lex(); // Eat the '{' 2927 2928 const MCExpr *Expr; 2929 SMLoc Loc = Parser.getTok().getLoc(); 2930 if (getParser().parseExpression(Expr)) { 2931 Error(Loc, "illegal expression"); 2932 return MatchOperand_ParseFail; 2933 } 2934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2935 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2936 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2937 return MatchOperand_ParseFail; 2938 } 2939 int Val = CE->getValue(); 2940 2941 // Check for and consume the closing '}' 2942 if (Parser.getTok().isNot(AsmToken::RCurly)) 2943 return MatchOperand_ParseFail; 2944 SMLoc E = Parser.getTok().getEndLoc(); 2945 Parser.Lex(); // Eat the '}' 2946 2947 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2948 return MatchOperand_Success; 2949 } 2950 2951 // For register list parsing, we need to map from raw GPR register numbering 2952 // to the enumeration values. The enumeration values aren't sorted by 2953 // register number due to our using "sp", "lr" and "pc" as canonical names. 2954 static unsigned getNextRegister(unsigned Reg) { 2955 // If this is a GPR, we need to do it manually, otherwise we can rely 2956 // on the sort ordering of the enumeration since the other reg-classes 2957 // are sane. 2958 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2959 return Reg + 1; 2960 switch(Reg) { 2961 default: llvm_unreachable("Invalid GPR number!"); 2962 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2963 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2964 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2965 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2966 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2967 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2968 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2969 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2970 } 2971 } 2972 2973 // Return the low-subreg of a given Q register. 2974 static unsigned getDRegFromQReg(unsigned QReg) { 2975 switch (QReg) { 2976 default: llvm_unreachable("expected a Q register!"); 2977 case ARM::Q0: return ARM::D0; 2978 case ARM::Q1: return ARM::D2; 2979 case ARM::Q2: return ARM::D4; 2980 case ARM::Q3: return ARM::D6; 2981 case ARM::Q4: return ARM::D8; 2982 case ARM::Q5: return ARM::D10; 2983 case ARM::Q6: return ARM::D12; 2984 case ARM::Q7: return ARM::D14; 2985 case ARM::Q8: return ARM::D16; 2986 case ARM::Q9: return ARM::D18; 2987 case ARM::Q10: return ARM::D20; 2988 case ARM::Q11: return ARM::D22; 2989 case ARM::Q12: return ARM::D24; 2990 case ARM::Q13: return ARM::D26; 2991 case ARM::Q14: return ARM::D28; 2992 case ARM::Q15: return ARM::D30; 2993 } 2994 } 2995 2996 /// Parse a register list. 2997 bool ARMAsmParser:: 2998 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2999 assert(Parser.getTok().is(AsmToken::LCurly) && 3000 "Token is not a Left Curly Brace"); 3001 SMLoc S = Parser.getTok().getLoc(); 3002 Parser.Lex(); // Eat '{' token. 3003 SMLoc RegLoc = Parser.getTok().getLoc(); 3004 3005 // Check the first register in the list to see what register class 3006 // this is a list of. 3007 int Reg = tryParseRegister(); 3008 if (Reg == -1) 3009 return Error(RegLoc, "register expected"); 3010 3011 // The reglist instructions have at most 16 registers, so reserve 3012 // space for that many. 3013 int EReg = 0; 3014 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3015 3016 // Allow Q regs and just interpret them as the two D sub-registers. 3017 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3018 Reg = getDRegFromQReg(Reg); 3019 EReg = MRI->getEncodingValue(Reg); 3020 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3021 ++Reg; 3022 } 3023 const MCRegisterClass *RC; 3024 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3025 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3026 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3027 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3028 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3029 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3030 else 3031 return Error(RegLoc, "invalid register in register list"); 3032 3033 // Store the register. 3034 EReg = MRI->getEncodingValue(Reg); 3035 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3036 3037 // This starts immediately after the first register token in the list, 3038 // so we can see either a comma or a minus (range separator) as a legal 3039 // next token. 3040 while (Parser.getTok().is(AsmToken::Comma) || 3041 Parser.getTok().is(AsmToken::Minus)) { 3042 if (Parser.getTok().is(AsmToken::Minus)) { 3043 Parser.Lex(); // Eat the minus. 3044 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3045 int EndReg = tryParseRegister(); 3046 if (EndReg == -1) 3047 return Error(AfterMinusLoc, "register expected"); 3048 // Allow Q regs and just interpret them as the two D sub-registers. 3049 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3050 EndReg = getDRegFromQReg(EndReg) + 1; 3051 // If the register is the same as the start reg, there's nothing 3052 // more to do. 3053 if (Reg == EndReg) 3054 continue; 3055 // The register must be in the same register class as the first. 3056 if (!RC->contains(EndReg)) 3057 return Error(AfterMinusLoc, "invalid register in register list"); 3058 // Ranges must go from low to high. 3059 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3060 return Error(AfterMinusLoc, "bad range in register list"); 3061 3062 // Add all the registers in the range to the register list. 3063 while (Reg != EndReg) { 3064 Reg = getNextRegister(Reg); 3065 EReg = MRI->getEncodingValue(Reg); 3066 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3067 } 3068 continue; 3069 } 3070 Parser.Lex(); // Eat the comma. 3071 RegLoc = Parser.getTok().getLoc(); 3072 int OldReg = Reg; 3073 const AsmToken RegTok = Parser.getTok(); 3074 Reg = tryParseRegister(); 3075 if (Reg == -1) 3076 return Error(RegLoc, "register expected"); 3077 // Allow Q regs and just interpret them as the two D sub-registers. 3078 bool isQReg = false; 3079 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3080 Reg = getDRegFromQReg(Reg); 3081 isQReg = true; 3082 } 3083 // The register must be in the same register class as the first. 3084 if (!RC->contains(Reg)) 3085 return Error(RegLoc, "invalid register in register list"); 3086 // List must be monotonically increasing. 3087 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3088 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3089 Warning(RegLoc, "register list not in ascending order"); 3090 else 3091 return Error(RegLoc, "register list not in ascending order"); 3092 } 3093 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3094 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3095 ") in register list"); 3096 continue; 3097 } 3098 // VFP register lists must also be contiguous. 3099 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3100 Reg != OldReg + 1) 3101 return Error(RegLoc, "non-contiguous register range"); 3102 EReg = MRI->getEncodingValue(Reg); 3103 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3104 if (isQReg) { 3105 EReg = MRI->getEncodingValue(++Reg); 3106 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3107 } 3108 } 3109 3110 if (Parser.getTok().isNot(AsmToken::RCurly)) 3111 return Error(Parser.getTok().getLoc(), "'}' expected"); 3112 SMLoc E = Parser.getTok().getEndLoc(); 3113 Parser.Lex(); // Eat '}' token. 3114 3115 // Push the register list operand. 3116 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3117 3118 // The ARM system instruction variants for LDM/STM have a '^' token here. 3119 if (Parser.getTok().is(AsmToken::Caret)) { 3120 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3121 Parser.Lex(); // Eat '^' token. 3122 } 3123 3124 return false; 3125 } 3126 3127 // Helper function to parse the lane index for vector lists. 3128 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3129 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3130 Index = 0; // Always return a defined index value. 3131 if (Parser.getTok().is(AsmToken::LBrac)) { 3132 Parser.Lex(); // Eat the '['. 3133 if (Parser.getTok().is(AsmToken::RBrac)) { 3134 // "Dn[]" is the 'all lanes' syntax. 3135 LaneKind = AllLanes; 3136 EndLoc = Parser.getTok().getEndLoc(); 3137 Parser.Lex(); // Eat the ']'. 3138 return MatchOperand_Success; 3139 } 3140 3141 // There's an optional '#' token here. Normally there wouldn't be, but 3142 // inline assemble puts one in, and it's friendly to accept that. 3143 if (Parser.getTok().is(AsmToken::Hash)) 3144 Parser.Lex(); // Eat '#' or '$'. 3145 3146 const MCExpr *LaneIndex; 3147 SMLoc Loc = Parser.getTok().getLoc(); 3148 if (getParser().parseExpression(LaneIndex)) { 3149 Error(Loc, "illegal expression"); 3150 return MatchOperand_ParseFail; 3151 } 3152 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3153 if (!CE) { 3154 Error(Loc, "lane index must be empty or an integer"); 3155 return MatchOperand_ParseFail; 3156 } 3157 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3158 Error(Parser.getTok().getLoc(), "']' expected"); 3159 return MatchOperand_ParseFail; 3160 } 3161 EndLoc = Parser.getTok().getEndLoc(); 3162 Parser.Lex(); // Eat the ']'. 3163 int64_t Val = CE->getValue(); 3164 3165 // FIXME: Make this range check context sensitive for .8, .16, .32. 3166 if (Val < 0 || Val > 7) { 3167 Error(Parser.getTok().getLoc(), "lane index out of range"); 3168 return MatchOperand_ParseFail; 3169 } 3170 Index = Val; 3171 LaneKind = IndexedLane; 3172 return MatchOperand_Success; 3173 } 3174 LaneKind = NoLanes; 3175 return MatchOperand_Success; 3176 } 3177 3178 // parse a vector register list 3179 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3180 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3181 VectorLaneTy LaneKind; 3182 unsigned LaneIndex; 3183 SMLoc S = Parser.getTok().getLoc(); 3184 // As an extension (to match gas), support a plain D register or Q register 3185 // (without encosing curly braces) as a single or double entry list, 3186 // respectively. 3187 if (Parser.getTok().is(AsmToken::Identifier)) { 3188 SMLoc E = Parser.getTok().getEndLoc(); 3189 int Reg = tryParseRegister(); 3190 if (Reg == -1) 3191 return MatchOperand_NoMatch; 3192 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3193 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3194 if (Res != MatchOperand_Success) 3195 return Res; 3196 switch (LaneKind) { 3197 case NoLanes: 3198 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3199 break; 3200 case AllLanes: 3201 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3202 S, E)); 3203 break; 3204 case IndexedLane: 3205 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3206 LaneIndex, 3207 false, S, E)); 3208 break; 3209 } 3210 return MatchOperand_Success; 3211 } 3212 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3213 Reg = getDRegFromQReg(Reg); 3214 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3215 if (Res != MatchOperand_Success) 3216 return Res; 3217 switch (LaneKind) { 3218 case NoLanes: 3219 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3220 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3221 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3222 break; 3223 case AllLanes: 3224 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3225 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3226 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3227 S, E)); 3228 break; 3229 case IndexedLane: 3230 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3231 LaneIndex, 3232 false, S, E)); 3233 break; 3234 } 3235 return MatchOperand_Success; 3236 } 3237 Error(S, "vector register expected"); 3238 return MatchOperand_ParseFail; 3239 } 3240 3241 if (Parser.getTok().isNot(AsmToken::LCurly)) 3242 return MatchOperand_NoMatch; 3243 3244 Parser.Lex(); // Eat '{' token. 3245 SMLoc RegLoc = Parser.getTok().getLoc(); 3246 3247 int Reg = tryParseRegister(); 3248 if (Reg == -1) { 3249 Error(RegLoc, "register expected"); 3250 return MatchOperand_ParseFail; 3251 } 3252 unsigned Count = 1; 3253 int Spacing = 0; 3254 unsigned FirstReg = Reg; 3255 // The list is of D registers, but we also allow Q regs and just interpret 3256 // them as the two D sub-registers. 3257 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3258 FirstReg = Reg = getDRegFromQReg(Reg); 3259 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3260 // it's ambiguous with four-register single spaced. 3261 ++Reg; 3262 ++Count; 3263 } 3264 3265 SMLoc E; 3266 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3267 return MatchOperand_ParseFail; 3268 3269 while (Parser.getTok().is(AsmToken::Comma) || 3270 Parser.getTok().is(AsmToken::Minus)) { 3271 if (Parser.getTok().is(AsmToken::Minus)) { 3272 if (!Spacing) 3273 Spacing = 1; // Register range implies a single spaced list. 3274 else if (Spacing == 2) { 3275 Error(Parser.getTok().getLoc(), 3276 "sequential registers in double spaced list"); 3277 return MatchOperand_ParseFail; 3278 } 3279 Parser.Lex(); // Eat the minus. 3280 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3281 int EndReg = tryParseRegister(); 3282 if (EndReg == -1) { 3283 Error(AfterMinusLoc, "register expected"); 3284 return MatchOperand_ParseFail; 3285 } 3286 // Allow Q regs and just interpret them as the two D sub-registers. 3287 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3288 EndReg = getDRegFromQReg(EndReg) + 1; 3289 // If the register is the same as the start reg, there's nothing 3290 // more to do. 3291 if (Reg == EndReg) 3292 continue; 3293 // The register must be in the same register class as the first. 3294 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3295 Error(AfterMinusLoc, "invalid register in register list"); 3296 return MatchOperand_ParseFail; 3297 } 3298 // Ranges must go from low to high. 3299 if (Reg > EndReg) { 3300 Error(AfterMinusLoc, "bad range in register list"); 3301 return MatchOperand_ParseFail; 3302 } 3303 // Parse the lane specifier if present. 3304 VectorLaneTy NextLaneKind; 3305 unsigned NextLaneIndex; 3306 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3307 MatchOperand_Success) 3308 return MatchOperand_ParseFail; 3309 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3310 Error(AfterMinusLoc, "mismatched lane index in register list"); 3311 return MatchOperand_ParseFail; 3312 } 3313 3314 // Add all the registers in the range to the register list. 3315 Count += EndReg - Reg; 3316 Reg = EndReg; 3317 continue; 3318 } 3319 Parser.Lex(); // Eat the comma. 3320 RegLoc = Parser.getTok().getLoc(); 3321 int OldReg = Reg; 3322 Reg = tryParseRegister(); 3323 if (Reg == -1) { 3324 Error(RegLoc, "register expected"); 3325 return MatchOperand_ParseFail; 3326 } 3327 // vector register lists must be contiguous. 3328 // It's OK to use the enumeration values directly here rather, as the 3329 // VFP register classes have the enum sorted properly. 3330 // 3331 // The list is of D registers, but we also allow Q regs and just interpret 3332 // them as the two D sub-registers. 3333 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3334 if (!Spacing) 3335 Spacing = 1; // Register range implies a single spaced list. 3336 else if (Spacing == 2) { 3337 Error(RegLoc, 3338 "invalid register in double-spaced list (must be 'D' register')"); 3339 return MatchOperand_ParseFail; 3340 } 3341 Reg = getDRegFromQReg(Reg); 3342 if (Reg != OldReg + 1) { 3343 Error(RegLoc, "non-contiguous register range"); 3344 return MatchOperand_ParseFail; 3345 } 3346 ++Reg; 3347 Count += 2; 3348 // Parse the lane specifier if present. 3349 VectorLaneTy NextLaneKind; 3350 unsigned NextLaneIndex; 3351 SMLoc LaneLoc = Parser.getTok().getLoc(); 3352 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3353 MatchOperand_Success) 3354 return MatchOperand_ParseFail; 3355 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3356 Error(LaneLoc, "mismatched lane index in register list"); 3357 return MatchOperand_ParseFail; 3358 } 3359 continue; 3360 } 3361 // Normal D register. 3362 // Figure out the register spacing (single or double) of the list if 3363 // we don't know it already. 3364 if (!Spacing) 3365 Spacing = 1 + (Reg == OldReg + 2); 3366 3367 // Just check that it's contiguous and keep going. 3368 if (Reg != OldReg + Spacing) { 3369 Error(RegLoc, "non-contiguous register range"); 3370 return MatchOperand_ParseFail; 3371 } 3372 ++Count; 3373 // Parse the lane specifier if present. 3374 VectorLaneTy NextLaneKind; 3375 unsigned NextLaneIndex; 3376 SMLoc EndLoc = Parser.getTok().getLoc(); 3377 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3378 return MatchOperand_ParseFail; 3379 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3380 Error(EndLoc, "mismatched lane index in register list"); 3381 return MatchOperand_ParseFail; 3382 } 3383 } 3384 3385 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3386 Error(Parser.getTok().getLoc(), "'}' expected"); 3387 return MatchOperand_ParseFail; 3388 } 3389 E = Parser.getTok().getEndLoc(); 3390 Parser.Lex(); // Eat '}' token. 3391 3392 switch (LaneKind) { 3393 case NoLanes: 3394 // Two-register operands have been converted to the 3395 // composite register classes. 3396 if (Count == 2) { 3397 const MCRegisterClass *RC = (Spacing == 1) ? 3398 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3399 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3400 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3401 } 3402 3403 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3404 (Spacing == 2), S, E)); 3405 break; 3406 case AllLanes: 3407 // Two-register operands have been converted to the 3408 // composite register classes. 3409 if (Count == 2) { 3410 const MCRegisterClass *RC = (Spacing == 1) ? 3411 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3412 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3413 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3414 } 3415 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3416 (Spacing == 2), 3417 S, E)); 3418 break; 3419 case IndexedLane: 3420 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3421 LaneIndex, 3422 (Spacing == 2), 3423 S, E)); 3424 break; 3425 } 3426 return MatchOperand_Success; 3427 } 3428 3429 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3430 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3431 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3432 SMLoc S = Parser.getTok().getLoc(); 3433 const AsmToken &Tok = Parser.getTok(); 3434 unsigned Opt; 3435 3436 if (Tok.is(AsmToken::Identifier)) { 3437 StringRef OptStr = Tok.getString(); 3438 3439 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3440 .Case("sy", ARM_MB::SY) 3441 .Case("st", ARM_MB::ST) 3442 .Case("sh", ARM_MB::ISH) 3443 .Case("ish", ARM_MB::ISH) 3444 .Case("shst", ARM_MB::ISHST) 3445 .Case("ishst", ARM_MB::ISHST) 3446 .Case("nsh", ARM_MB::NSH) 3447 .Case("un", ARM_MB::NSH) 3448 .Case("nshst", ARM_MB::NSHST) 3449 .Case("unst", ARM_MB::NSHST) 3450 .Case("osh", ARM_MB::OSH) 3451 .Case("oshst", ARM_MB::OSHST) 3452 .Default(~0U); 3453 3454 if (Opt == ~0U) 3455 return MatchOperand_NoMatch; 3456 3457 Parser.Lex(); // Eat identifier token. 3458 } else if (Tok.is(AsmToken::Hash) || 3459 Tok.is(AsmToken::Dollar) || 3460 Tok.is(AsmToken::Integer)) { 3461 if (Parser.getTok().isNot(AsmToken::Integer)) 3462 Parser.Lex(); // Eat '#' or '$'. 3463 SMLoc Loc = Parser.getTok().getLoc(); 3464 3465 const MCExpr *MemBarrierID; 3466 if (getParser().parseExpression(MemBarrierID)) { 3467 Error(Loc, "illegal expression"); 3468 return MatchOperand_ParseFail; 3469 } 3470 3471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3472 if (!CE) { 3473 Error(Loc, "constant expression expected"); 3474 return MatchOperand_ParseFail; 3475 } 3476 3477 int Val = CE->getValue(); 3478 if (Val & ~0xf) { 3479 Error(Loc, "immediate value out of range"); 3480 return MatchOperand_ParseFail; 3481 } 3482 3483 Opt = ARM_MB::RESERVED_0 + Val; 3484 } else 3485 return MatchOperand_ParseFail; 3486 3487 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3488 return MatchOperand_Success; 3489 } 3490 3491 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3492 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3493 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3494 SMLoc S = Parser.getTok().getLoc(); 3495 const AsmToken &Tok = Parser.getTok(); 3496 unsigned Opt; 3497 3498 if (Tok.is(AsmToken::Identifier)) { 3499 StringRef OptStr = Tok.getString(); 3500 3501 if (OptStr.lower() == "sy") 3502 Opt = ARM_ISB::SY; 3503 else 3504 return MatchOperand_NoMatch; 3505 3506 Parser.Lex(); // Eat identifier token. 3507 } else if (Tok.is(AsmToken::Hash) || 3508 Tok.is(AsmToken::Dollar) || 3509 Tok.is(AsmToken::Integer)) { 3510 if (Parser.getTok().isNot(AsmToken::Integer)) 3511 Parser.Lex(); // Eat '#' or '$'. 3512 SMLoc Loc = Parser.getTok().getLoc(); 3513 3514 const MCExpr *ISBarrierID; 3515 if (getParser().parseExpression(ISBarrierID)) { 3516 Error(Loc, "illegal expression"); 3517 return MatchOperand_ParseFail; 3518 } 3519 3520 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3521 if (!CE) { 3522 Error(Loc, "constant expression expected"); 3523 return MatchOperand_ParseFail; 3524 } 3525 3526 int Val = CE->getValue(); 3527 if (Val & ~0xf) { 3528 Error(Loc, "immediate value out of range"); 3529 return MatchOperand_ParseFail; 3530 } 3531 3532 Opt = ARM_ISB::RESERVED_0 + Val; 3533 } else 3534 return MatchOperand_ParseFail; 3535 3536 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3537 (ARM_ISB::InstSyncBOpt)Opt, S)); 3538 return MatchOperand_Success; 3539 } 3540 3541 3542 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3543 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3544 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3545 SMLoc S = Parser.getTok().getLoc(); 3546 const AsmToken &Tok = Parser.getTok(); 3547 if (!Tok.is(AsmToken::Identifier)) 3548 return MatchOperand_NoMatch; 3549 StringRef IFlagsStr = Tok.getString(); 3550 3551 // An iflags string of "none" is interpreted to mean that none of the AIF 3552 // bits are set. Not a terribly useful instruction, but a valid encoding. 3553 unsigned IFlags = 0; 3554 if (IFlagsStr != "none") { 3555 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3556 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3557 .Case("a", ARM_PROC::A) 3558 .Case("i", ARM_PROC::I) 3559 .Case("f", ARM_PROC::F) 3560 .Default(~0U); 3561 3562 // If some specific iflag is already set, it means that some letter is 3563 // present more than once, this is not acceptable. 3564 if (Flag == ~0U || (IFlags & Flag)) 3565 return MatchOperand_NoMatch; 3566 3567 IFlags |= Flag; 3568 } 3569 } 3570 3571 Parser.Lex(); // Eat identifier token. 3572 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3573 return MatchOperand_Success; 3574 } 3575 3576 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3577 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3578 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3579 SMLoc S = Parser.getTok().getLoc(); 3580 const AsmToken &Tok = Parser.getTok(); 3581 if (!Tok.is(AsmToken::Identifier)) 3582 return MatchOperand_NoMatch; 3583 StringRef Mask = Tok.getString(); 3584 3585 if (isMClass()) { 3586 // See ARMv6-M 10.1.1 3587 std::string Name = Mask.lower(); 3588 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3589 // Note: in the documentation: 3590 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3591 // for MSR APSR_nzcvq. 3592 // but we do make it an alias here. This is so to get the "mask encoding" 3593 // bits correct on MSR APSR writes. 3594 // 3595 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3596 // should really only be allowed when writing a special register. Note 3597 // they get dropped in the MRS instruction reading a special register as 3598 // the SYSm field is only 8 bits. 3599 // 3600 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3601 // includes the DSP extension but that is not checked. 3602 .Case("apsr", 0x800) 3603 .Case("apsr_nzcvq", 0x800) 3604 .Case("apsr_g", 0x400) 3605 .Case("apsr_nzcvqg", 0xc00) 3606 .Case("iapsr", 0x801) 3607 .Case("iapsr_nzcvq", 0x801) 3608 .Case("iapsr_g", 0x401) 3609 .Case("iapsr_nzcvqg", 0xc01) 3610 .Case("eapsr", 0x802) 3611 .Case("eapsr_nzcvq", 0x802) 3612 .Case("eapsr_g", 0x402) 3613 .Case("eapsr_nzcvqg", 0xc02) 3614 .Case("xpsr", 0x803) 3615 .Case("xpsr_nzcvq", 0x803) 3616 .Case("xpsr_g", 0x403) 3617 .Case("xpsr_nzcvqg", 0xc03) 3618 .Case("ipsr", 0x805) 3619 .Case("epsr", 0x806) 3620 .Case("iepsr", 0x807) 3621 .Case("msp", 0x808) 3622 .Case("psp", 0x809) 3623 .Case("primask", 0x810) 3624 .Case("basepri", 0x811) 3625 .Case("basepri_max", 0x812) 3626 .Case("faultmask", 0x813) 3627 .Case("control", 0x814) 3628 .Default(~0U); 3629 3630 if (FlagsVal == ~0U) 3631 return MatchOperand_NoMatch; 3632 3633 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3634 // basepri, basepri_max and faultmask only valid for V7m. 3635 return MatchOperand_NoMatch; 3636 3637 Parser.Lex(); // Eat identifier token. 3638 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3639 return MatchOperand_Success; 3640 } 3641 3642 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3643 size_t Start = 0, Next = Mask.find('_'); 3644 StringRef Flags = ""; 3645 std::string SpecReg = Mask.slice(Start, Next).lower(); 3646 if (Next != StringRef::npos) 3647 Flags = Mask.slice(Next+1, Mask.size()); 3648 3649 // FlagsVal contains the complete mask: 3650 // 3-0: Mask 3651 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3652 unsigned FlagsVal = 0; 3653 3654 if (SpecReg == "apsr") { 3655 FlagsVal = StringSwitch<unsigned>(Flags) 3656 .Case("nzcvq", 0x8) // same as CPSR_f 3657 .Case("g", 0x4) // same as CPSR_s 3658 .Case("nzcvqg", 0xc) // same as CPSR_fs 3659 .Default(~0U); 3660 3661 if (FlagsVal == ~0U) { 3662 if (!Flags.empty()) 3663 return MatchOperand_NoMatch; 3664 else 3665 FlagsVal = 8; // No flag 3666 } 3667 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3668 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3669 if (Flags == "all" || Flags == "") 3670 Flags = "fc"; 3671 for (int i = 0, e = Flags.size(); i != e; ++i) { 3672 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3673 .Case("c", 1) 3674 .Case("x", 2) 3675 .Case("s", 4) 3676 .Case("f", 8) 3677 .Default(~0U); 3678 3679 // If some specific flag is already set, it means that some letter is 3680 // present more than once, this is not acceptable. 3681 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3682 return MatchOperand_NoMatch; 3683 FlagsVal |= Flag; 3684 } 3685 } else // No match for special register. 3686 return MatchOperand_NoMatch; 3687 3688 // Special register without flags is NOT equivalent to "fc" flags. 3689 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3690 // two lines would enable gas compatibility at the expense of breaking 3691 // round-tripping. 3692 // 3693 // if (!FlagsVal) 3694 // FlagsVal = 0x9; 3695 3696 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3697 if (SpecReg == "spsr") 3698 FlagsVal |= 16; 3699 3700 Parser.Lex(); // Eat identifier token. 3701 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3702 return MatchOperand_Success; 3703 } 3704 3705 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3706 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3707 int Low, int High) { 3708 const AsmToken &Tok = Parser.getTok(); 3709 if (Tok.isNot(AsmToken::Identifier)) { 3710 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3711 return MatchOperand_ParseFail; 3712 } 3713 StringRef ShiftName = Tok.getString(); 3714 std::string LowerOp = Op.lower(); 3715 std::string UpperOp = Op.upper(); 3716 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3717 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3718 return MatchOperand_ParseFail; 3719 } 3720 Parser.Lex(); // Eat shift type token. 3721 3722 // There must be a '#' and a shift amount. 3723 if (Parser.getTok().isNot(AsmToken::Hash) && 3724 Parser.getTok().isNot(AsmToken::Dollar)) { 3725 Error(Parser.getTok().getLoc(), "'#' expected"); 3726 return MatchOperand_ParseFail; 3727 } 3728 Parser.Lex(); // Eat hash token. 3729 3730 const MCExpr *ShiftAmount; 3731 SMLoc Loc = Parser.getTok().getLoc(); 3732 SMLoc EndLoc; 3733 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3734 Error(Loc, "illegal expression"); 3735 return MatchOperand_ParseFail; 3736 } 3737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3738 if (!CE) { 3739 Error(Loc, "constant expression expected"); 3740 return MatchOperand_ParseFail; 3741 } 3742 int Val = CE->getValue(); 3743 if (Val < Low || Val > High) { 3744 Error(Loc, "immediate value out of range"); 3745 return MatchOperand_ParseFail; 3746 } 3747 3748 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 3749 3750 return MatchOperand_Success; 3751 } 3752 3753 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3754 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3755 const AsmToken &Tok = Parser.getTok(); 3756 SMLoc S = Tok.getLoc(); 3757 if (Tok.isNot(AsmToken::Identifier)) { 3758 Error(S, "'be' or 'le' operand expected"); 3759 return MatchOperand_ParseFail; 3760 } 3761 int Val = StringSwitch<int>(Tok.getString().lower()) 3762 .Case("be", 1) 3763 .Case("le", 0) 3764 .Default(-1); 3765 Parser.Lex(); // Eat the token. 3766 3767 if (Val == -1) { 3768 Error(S, "'be' or 'le' operand expected"); 3769 return MatchOperand_ParseFail; 3770 } 3771 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3772 getContext()), 3773 S, Tok.getEndLoc())); 3774 return MatchOperand_Success; 3775 } 3776 3777 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3778 /// instructions. Legal values are: 3779 /// lsl #n 'n' in [0,31] 3780 /// asr #n 'n' in [1,32] 3781 /// n == 32 encoded as n == 0. 3782 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3783 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3784 const AsmToken &Tok = Parser.getTok(); 3785 SMLoc S = Tok.getLoc(); 3786 if (Tok.isNot(AsmToken::Identifier)) { 3787 Error(S, "shift operator 'asr' or 'lsl' expected"); 3788 return MatchOperand_ParseFail; 3789 } 3790 StringRef ShiftName = Tok.getString(); 3791 bool isASR; 3792 if (ShiftName == "lsl" || ShiftName == "LSL") 3793 isASR = false; 3794 else if (ShiftName == "asr" || ShiftName == "ASR") 3795 isASR = true; 3796 else { 3797 Error(S, "shift operator 'asr' or 'lsl' expected"); 3798 return MatchOperand_ParseFail; 3799 } 3800 Parser.Lex(); // Eat the operator. 3801 3802 // A '#' and a shift amount. 3803 if (Parser.getTok().isNot(AsmToken::Hash) && 3804 Parser.getTok().isNot(AsmToken::Dollar)) { 3805 Error(Parser.getTok().getLoc(), "'#' expected"); 3806 return MatchOperand_ParseFail; 3807 } 3808 Parser.Lex(); // Eat hash token. 3809 SMLoc ExLoc = Parser.getTok().getLoc(); 3810 3811 const MCExpr *ShiftAmount; 3812 SMLoc EndLoc; 3813 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3814 Error(ExLoc, "malformed shift expression"); 3815 return MatchOperand_ParseFail; 3816 } 3817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3818 if (!CE) { 3819 Error(ExLoc, "shift amount must be an immediate"); 3820 return MatchOperand_ParseFail; 3821 } 3822 3823 int64_t Val = CE->getValue(); 3824 if (isASR) { 3825 // Shift amount must be in [1,32] 3826 if (Val < 1 || Val > 32) { 3827 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 3828 return MatchOperand_ParseFail; 3829 } 3830 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3831 if (isThumb() && Val == 32) { 3832 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 3833 return MatchOperand_ParseFail; 3834 } 3835 if (Val == 32) Val = 0; 3836 } else { 3837 // Shift amount must be in [1,32] 3838 if (Val < 0 || Val > 31) { 3839 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 3840 return MatchOperand_ParseFail; 3841 } 3842 } 3843 3844 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 3845 3846 return MatchOperand_Success; 3847 } 3848 3849 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3850 /// of instructions. Legal values are: 3851 /// ror #n 'n' in {0, 8, 16, 24} 3852 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3853 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3854 const AsmToken &Tok = Parser.getTok(); 3855 SMLoc S = Tok.getLoc(); 3856 if (Tok.isNot(AsmToken::Identifier)) 3857 return MatchOperand_NoMatch; 3858 StringRef ShiftName = Tok.getString(); 3859 if (ShiftName != "ror" && ShiftName != "ROR") 3860 return MatchOperand_NoMatch; 3861 Parser.Lex(); // Eat the operator. 3862 3863 // A '#' and a rotate amount. 3864 if (Parser.getTok().isNot(AsmToken::Hash) && 3865 Parser.getTok().isNot(AsmToken::Dollar)) { 3866 Error(Parser.getTok().getLoc(), "'#' expected"); 3867 return MatchOperand_ParseFail; 3868 } 3869 Parser.Lex(); // Eat hash token. 3870 SMLoc ExLoc = Parser.getTok().getLoc(); 3871 3872 const MCExpr *ShiftAmount; 3873 SMLoc EndLoc; 3874 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3875 Error(ExLoc, "malformed rotate expression"); 3876 return MatchOperand_ParseFail; 3877 } 3878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3879 if (!CE) { 3880 Error(ExLoc, "rotate amount must be an immediate"); 3881 return MatchOperand_ParseFail; 3882 } 3883 3884 int64_t Val = CE->getValue(); 3885 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3886 // normally, zero is represented in asm by omitting the rotate operand 3887 // entirely. 3888 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3889 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 3890 return MatchOperand_ParseFail; 3891 } 3892 3893 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 3894 3895 return MatchOperand_Success; 3896 } 3897 3898 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3899 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3900 SMLoc S = Parser.getTok().getLoc(); 3901 // The bitfield descriptor is really two operands, the LSB and the width. 3902 if (Parser.getTok().isNot(AsmToken::Hash) && 3903 Parser.getTok().isNot(AsmToken::Dollar)) { 3904 Error(Parser.getTok().getLoc(), "'#' expected"); 3905 return MatchOperand_ParseFail; 3906 } 3907 Parser.Lex(); // Eat hash token. 3908 3909 const MCExpr *LSBExpr; 3910 SMLoc E = Parser.getTok().getLoc(); 3911 if (getParser().parseExpression(LSBExpr)) { 3912 Error(E, "malformed immediate expression"); 3913 return MatchOperand_ParseFail; 3914 } 3915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3916 if (!CE) { 3917 Error(E, "'lsb' operand must be an immediate"); 3918 return MatchOperand_ParseFail; 3919 } 3920 3921 int64_t LSB = CE->getValue(); 3922 // The LSB must be in the range [0,31] 3923 if (LSB < 0 || LSB > 31) { 3924 Error(E, "'lsb' operand must be in the range [0,31]"); 3925 return MatchOperand_ParseFail; 3926 } 3927 E = Parser.getTok().getLoc(); 3928 3929 // Expect another immediate operand. 3930 if (Parser.getTok().isNot(AsmToken::Comma)) { 3931 Error(Parser.getTok().getLoc(), "too few operands"); 3932 return MatchOperand_ParseFail; 3933 } 3934 Parser.Lex(); // Eat hash token. 3935 if (Parser.getTok().isNot(AsmToken::Hash) && 3936 Parser.getTok().isNot(AsmToken::Dollar)) { 3937 Error(Parser.getTok().getLoc(), "'#' expected"); 3938 return MatchOperand_ParseFail; 3939 } 3940 Parser.Lex(); // Eat hash token. 3941 3942 const MCExpr *WidthExpr; 3943 SMLoc EndLoc; 3944 if (getParser().parseExpression(WidthExpr, EndLoc)) { 3945 Error(E, "malformed immediate expression"); 3946 return MatchOperand_ParseFail; 3947 } 3948 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3949 if (!CE) { 3950 Error(E, "'width' operand must be an immediate"); 3951 return MatchOperand_ParseFail; 3952 } 3953 3954 int64_t Width = CE->getValue(); 3955 // The LSB must be in the range [1,32-lsb] 3956 if (Width < 1 || Width > 32 - LSB) { 3957 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3958 return MatchOperand_ParseFail; 3959 } 3960 3961 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 3962 3963 return MatchOperand_Success; 3964 } 3965 3966 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3967 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3968 // Check for a post-index addressing register operand. Specifically: 3969 // postidx_reg := '+' register {, shift} 3970 // | '-' register {, shift} 3971 // | register {, shift} 3972 3973 // This method must return MatchOperand_NoMatch without consuming any tokens 3974 // in the case where there is no match, as other alternatives take other 3975 // parse methods. 3976 AsmToken Tok = Parser.getTok(); 3977 SMLoc S = Tok.getLoc(); 3978 bool haveEaten = false; 3979 bool isAdd = true; 3980 if (Tok.is(AsmToken::Plus)) { 3981 Parser.Lex(); // Eat the '+' token. 3982 haveEaten = true; 3983 } else if (Tok.is(AsmToken::Minus)) { 3984 Parser.Lex(); // Eat the '-' token. 3985 isAdd = false; 3986 haveEaten = true; 3987 } 3988 3989 SMLoc E = Parser.getTok().getEndLoc(); 3990 int Reg = tryParseRegister(); 3991 if (Reg == -1) { 3992 if (!haveEaten) 3993 return MatchOperand_NoMatch; 3994 Error(Parser.getTok().getLoc(), "register expected"); 3995 return MatchOperand_ParseFail; 3996 } 3997 3998 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3999 unsigned ShiftImm = 0; 4000 if (Parser.getTok().is(AsmToken::Comma)) { 4001 Parser.Lex(); // Eat the ','. 4002 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4003 return MatchOperand_ParseFail; 4004 4005 // FIXME: Only approximates end...may include intervening whitespace. 4006 E = Parser.getTok().getLoc(); 4007 } 4008 4009 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4010 ShiftImm, S, E)); 4011 4012 return MatchOperand_Success; 4013 } 4014 4015 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4016 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4017 // Check for a post-index addressing register operand. Specifically: 4018 // am3offset := '+' register 4019 // | '-' register 4020 // | register 4021 // | # imm 4022 // | # + imm 4023 // | # - imm 4024 4025 // This method must return MatchOperand_NoMatch without consuming any tokens 4026 // in the case where there is no match, as other alternatives take other 4027 // parse methods. 4028 AsmToken Tok = Parser.getTok(); 4029 SMLoc S = Tok.getLoc(); 4030 4031 // Do immediates first, as we always parse those if we have a '#'. 4032 if (Parser.getTok().is(AsmToken::Hash) || 4033 Parser.getTok().is(AsmToken::Dollar)) { 4034 Parser.Lex(); // Eat '#' or '$'. 4035 // Explicitly look for a '-', as we need to encode negative zero 4036 // differently. 4037 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4038 const MCExpr *Offset; 4039 SMLoc E; 4040 if (getParser().parseExpression(Offset, E)) 4041 return MatchOperand_ParseFail; 4042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4043 if (!CE) { 4044 Error(S, "constant expression expected"); 4045 return MatchOperand_ParseFail; 4046 } 4047 // Negative zero is encoded as the flag value INT32_MIN. 4048 int32_t Val = CE->getValue(); 4049 if (isNegative && Val == 0) 4050 Val = INT32_MIN; 4051 4052 Operands.push_back( 4053 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4054 4055 return MatchOperand_Success; 4056 } 4057 4058 4059 bool haveEaten = false; 4060 bool isAdd = true; 4061 if (Tok.is(AsmToken::Plus)) { 4062 Parser.Lex(); // Eat the '+' token. 4063 haveEaten = true; 4064 } else if (Tok.is(AsmToken::Minus)) { 4065 Parser.Lex(); // Eat the '-' token. 4066 isAdd = false; 4067 haveEaten = true; 4068 } 4069 4070 Tok = Parser.getTok(); 4071 int Reg = tryParseRegister(); 4072 if (Reg == -1) { 4073 if (!haveEaten) 4074 return MatchOperand_NoMatch; 4075 Error(Tok.getLoc(), "register expected"); 4076 return MatchOperand_ParseFail; 4077 } 4078 4079 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4080 0, S, Tok.getEndLoc())); 4081 4082 return MatchOperand_Success; 4083 } 4084 4085 /// Convert parsed operands to MCInst. Needed here because this instruction 4086 /// only has two register operands, but multiplication is commutative so 4087 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4088 void ARMAsmParser:: 4089 cvtThumbMultiply(MCInst &Inst, 4090 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4091 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4092 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4093 // If we have a three-operand form, make sure to set Rn to be the operand 4094 // that isn't the same as Rd. 4095 unsigned RegOp = 4; 4096 if (Operands.size() == 6 && 4097 ((ARMOperand*)Operands[4])->getReg() == 4098 ((ARMOperand*)Operands[3])->getReg()) 4099 RegOp = 5; 4100 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4101 Inst.addOperand(Inst.getOperand(0)); 4102 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4103 } 4104 4105 /// Parse an ARM memory expression, return false if successful else return true 4106 /// or an error. The first token must be a '[' when called. 4107 bool ARMAsmParser:: 4108 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4109 SMLoc S, E; 4110 assert(Parser.getTok().is(AsmToken::LBrac) && 4111 "Token is not a Left Bracket"); 4112 S = Parser.getTok().getLoc(); 4113 Parser.Lex(); // Eat left bracket token. 4114 4115 const AsmToken &BaseRegTok = Parser.getTok(); 4116 int BaseRegNum = tryParseRegister(); 4117 if (BaseRegNum == -1) 4118 return Error(BaseRegTok.getLoc(), "register expected"); 4119 4120 // The next token must either be a comma, a colon or a closing bracket. 4121 const AsmToken &Tok = Parser.getTok(); 4122 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4123 !Tok.is(AsmToken::RBrac)) 4124 return Error(Tok.getLoc(), "malformed memory operand"); 4125 4126 if (Tok.is(AsmToken::RBrac)) { 4127 E = Tok.getEndLoc(); 4128 Parser.Lex(); // Eat right bracket token. 4129 4130 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4131 0, 0, false, S, E)); 4132 4133 // If there's a pre-indexing writeback marker, '!', just add it as a token 4134 // operand. It's rather odd, but syntactically valid. 4135 if (Parser.getTok().is(AsmToken::Exclaim)) { 4136 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4137 Parser.Lex(); // Eat the '!'. 4138 } 4139 4140 return false; 4141 } 4142 4143 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4144 "Lost colon or comma in memory operand?!"); 4145 if (Tok.is(AsmToken::Comma)) { 4146 Parser.Lex(); // Eat the comma. 4147 } 4148 4149 // If we have a ':', it's an alignment specifier. 4150 if (Parser.getTok().is(AsmToken::Colon)) { 4151 Parser.Lex(); // Eat the ':'. 4152 E = Parser.getTok().getLoc(); 4153 4154 const MCExpr *Expr; 4155 if (getParser().parseExpression(Expr)) 4156 return true; 4157 4158 // The expression has to be a constant. Memory references with relocations 4159 // don't come through here, as they use the <label> forms of the relevant 4160 // instructions. 4161 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4162 if (!CE) 4163 return Error (E, "constant expression expected"); 4164 4165 unsigned Align = 0; 4166 switch (CE->getValue()) { 4167 default: 4168 return Error(E, 4169 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4170 case 16: Align = 2; break; 4171 case 32: Align = 4; break; 4172 case 64: Align = 8; break; 4173 case 128: Align = 16; break; 4174 case 256: Align = 32; break; 4175 } 4176 4177 // Now we should have the closing ']' 4178 if (Parser.getTok().isNot(AsmToken::RBrac)) 4179 return Error(Parser.getTok().getLoc(), "']' expected"); 4180 E = Parser.getTok().getEndLoc(); 4181 Parser.Lex(); // Eat right bracket token. 4182 4183 // Don't worry about range checking the value here. That's handled by 4184 // the is*() predicates. 4185 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4186 ARM_AM::no_shift, 0, Align, 4187 false, S, E)); 4188 4189 // If there's a pre-indexing writeback marker, '!', just add it as a token 4190 // operand. 4191 if (Parser.getTok().is(AsmToken::Exclaim)) { 4192 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4193 Parser.Lex(); // Eat the '!'. 4194 } 4195 4196 return false; 4197 } 4198 4199 // If we have a '#', it's an immediate offset, else assume it's a register 4200 // offset. Be friendly and also accept a plain integer (without a leading 4201 // hash) for gas compatibility. 4202 if (Parser.getTok().is(AsmToken::Hash) || 4203 Parser.getTok().is(AsmToken::Dollar) || 4204 Parser.getTok().is(AsmToken::Integer)) { 4205 if (Parser.getTok().isNot(AsmToken::Integer)) 4206 Parser.Lex(); // Eat '#' or '$'. 4207 E = Parser.getTok().getLoc(); 4208 4209 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4210 const MCExpr *Offset; 4211 if (getParser().parseExpression(Offset)) 4212 return true; 4213 4214 // The expression has to be a constant. Memory references with relocations 4215 // don't come through here, as they use the <label> forms of the relevant 4216 // instructions. 4217 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4218 if (!CE) 4219 return Error (E, "constant expression expected"); 4220 4221 // If the constant was #-0, represent it as INT32_MIN. 4222 int32_t Val = CE->getValue(); 4223 if (isNegative && Val == 0) 4224 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4225 4226 // Now we should have the closing ']' 4227 if (Parser.getTok().isNot(AsmToken::RBrac)) 4228 return Error(Parser.getTok().getLoc(), "']' expected"); 4229 E = Parser.getTok().getEndLoc(); 4230 Parser.Lex(); // Eat right bracket token. 4231 4232 // Don't worry about range checking the value here. That's handled by 4233 // the is*() predicates. 4234 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4235 ARM_AM::no_shift, 0, 0, 4236 false, S, E)); 4237 4238 // If there's a pre-indexing writeback marker, '!', just add it as a token 4239 // operand. 4240 if (Parser.getTok().is(AsmToken::Exclaim)) { 4241 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4242 Parser.Lex(); // Eat the '!'. 4243 } 4244 4245 return false; 4246 } 4247 4248 // The register offset is optionally preceded by a '+' or '-' 4249 bool isNegative = false; 4250 if (Parser.getTok().is(AsmToken::Minus)) { 4251 isNegative = true; 4252 Parser.Lex(); // Eat the '-'. 4253 } else if (Parser.getTok().is(AsmToken::Plus)) { 4254 // Nothing to do. 4255 Parser.Lex(); // Eat the '+'. 4256 } 4257 4258 E = Parser.getTok().getLoc(); 4259 int OffsetRegNum = tryParseRegister(); 4260 if (OffsetRegNum == -1) 4261 return Error(E, "register expected"); 4262 4263 // If there's a shift operator, handle it. 4264 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4265 unsigned ShiftImm = 0; 4266 if (Parser.getTok().is(AsmToken::Comma)) { 4267 Parser.Lex(); // Eat the ','. 4268 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4269 return true; 4270 } 4271 4272 // Now we should have the closing ']' 4273 if (Parser.getTok().isNot(AsmToken::RBrac)) 4274 return Error(Parser.getTok().getLoc(), "']' expected"); 4275 E = Parser.getTok().getEndLoc(); 4276 Parser.Lex(); // Eat right bracket token. 4277 4278 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4279 ShiftType, ShiftImm, 0, isNegative, 4280 S, E)); 4281 4282 // If there's a pre-indexing writeback marker, '!', just add it as a token 4283 // operand. 4284 if (Parser.getTok().is(AsmToken::Exclaim)) { 4285 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4286 Parser.Lex(); // Eat the '!'. 4287 } 4288 4289 return false; 4290 } 4291 4292 /// parseMemRegOffsetShift - one of these two: 4293 /// ( lsl | lsr | asr | ror ) , # shift_amount 4294 /// rrx 4295 /// return true if it parses a shift otherwise it returns false. 4296 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4297 unsigned &Amount) { 4298 SMLoc Loc = Parser.getTok().getLoc(); 4299 const AsmToken &Tok = Parser.getTok(); 4300 if (Tok.isNot(AsmToken::Identifier)) 4301 return true; 4302 StringRef ShiftName = Tok.getString(); 4303 if (ShiftName == "lsl" || ShiftName == "LSL" || 4304 ShiftName == "asl" || ShiftName == "ASL") 4305 St = ARM_AM::lsl; 4306 else if (ShiftName == "lsr" || ShiftName == "LSR") 4307 St = ARM_AM::lsr; 4308 else if (ShiftName == "asr" || ShiftName == "ASR") 4309 St = ARM_AM::asr; 4310 else if (ShiftName == "ror" || ShiftName == "ROR") 4311 St = ARM_AM::ror; 4312 else if (ShiftName == "rrx" || ShiftName == "RRX") 4313 St = ARM_AM::rrx; 4314 else 4315 return Error(Loc, "illegal shift operator"); 4316 Parser.Lex(); // Eat shift type token. 4317 4318 // rrx stands alone. 4319 Amount = 0; 4320 if (St != ARM_AM::rrx) { 4321 Loc = Parser.getTok().getLoc(); 4322 // A '#' and a shift amount. 4323 const AsmToken &HashTok = Parser.getTok(); 4324 if (HashTok.isNot(AsmToken::Hash) && 4325 HashTok.isNot(AsmToken::Dollar)) 4326 return Error(HashTok.getLoc(), "'#' expected"); 4327 Parser.Lex(); // Eat hash token. 4328 4329 const MCExpr *Expr; 4330 if (getParser().parseExpression(Expr)) 4331 return true; 4332 // Range check the immediate. 4333 // lsl, ror: 0 <= imm <= 31 4334 // lsr, asr: 0 <= imm <= 32 4335 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4336 if (!CE) 4337 return Error(Loc, "shift amount must be an immediate"); 4338 int64_t Imm = CE->getValue(); 4339 if (Imm < 0 || 4340 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4341 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4342 return Error(Loc, "immediate shift value out of range"); 4343 // If <ShiftTy> #0, turn it into a no_shift. 4344 if (Imm == 0) 4345 St = ARM_AM::lsl; 4346 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4347 if (Imm == 32) 4348 Imm = 0; 4349 Amount = Imm; 4350 } 4351 4352 return false; 4353 } 4354 4355 /// parseFPImm - A floating point immediate expression operand. 4356 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4357 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4358 // Anything that can accept a floating point constant as an operand 4359 // needs to go through here, as the regular parseExpression is 4360 // integer only. 4361 // 4362 // This routine still creates a generic Immediate operand, containing 4363 // a bitcast of the 64-bit floating point value. The various operands 4364 // that accept floats can check whether the value is valid for them 4365 // via the standard is*() predicates. 4366 4367 SMLoc S = Parser.getTok().getLoc(); 4368 4369 if (Parser.getTok().isNot(AsmToken::Hash) && 4370 Parser.getTok().isNot(AsmToken::Dollar)) 4371 return MatchOperand_NoMatch; 4372 4373 // Disambiguate the VMOV forms that can accept an FP immediate. 4374 // vmov.f32 <sreg>, #imm 4375 // vmov.f64 <dreg>, #imm 4376 // vmov.f32 <dreg>, #imm @ vector f32x2 4377 // vmov.f32 <qreg>, #imm @ vector f32x4 4378 // 4379 // There are also the NEON VMOV instructions which expect an 4380 // integer constant. Make sure we don't try to parse an FPImm 4381 // for these: 4382 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4383 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4384 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4385 TyOp->getToken() != ".f64")) 4386 return MatchOperand_NoMatch; 4387 4388 Parser.Lex(); // Eat '#' or '$'. 4389 4390 // Handle negation, as that still comes through as a separate token. 4391 bool isNegative = false; 4392 if (Parser.getTok().is(AsmToken::Minus)) { 4393 isNegative = true; 4394 Parser.Lex(); 4395 } 4396 const AsmToken &Tok = Parser.getTok(); 4397 SMLoc Loc = Tok.getLoc(); 4398 if (Tok.is(AsmToken::Real)) { 4399 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4400 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4401 // If we had a '-' in front, toggle the sign bit. 4402 IntVal ^= (uint64_t)isNegative << 31; 4403 Parser.Lex(); // Eat the token. 4404 Operands.push_back(ARMOperand::CreateImm( 4405 MCConstantExpr::Create(IntVal, getContext()), 4406 S, Parser.getTok().getLoc())); 4407 return MatchOperand_Success; 4408 } 4409 // Also handle plain integers. Instructions which allow floating point 4410 // immediates also allow a raw encoded 8-bit value. 4411 if (Tok.is(AsmToken::Integer)) { 4412 int64_t Val = Tok.getIntVal(); 4413 Parser.Lex(); // Eat the token. 4414 if (Val > 255 || Val < 0) { 4415 Error(Loc, "encoded floating point value out of range"); 4416 return MatchOperand_ParseFail; 4417 } 4418 double RealVal = ARM_AM::getFPImmFloat(Val); 4419 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4420 Operands.push_back(ARMOperand::CreateImm( 4421 MCConstantExpr::Create(Val, getContext()), S, 4422 Parser.getTok().getLoc())); 4423 return MatchOperand_Success; 4424 } 4425 4426 Error(Loc, "invalid floating point immediate"); 4427 return MatchOperand_ParseFail; 4428 } 4429 4430 /// Parse a arm instruction operand. For now this parses the operand regardless 4431 /// of the mnemonic. 4432 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4433 StringRef Mnemonic) { 4434 SMLoc S, E; 4435 4436 // Check if the current operand has a custom associated parser, if so, try to 4437 // custom parse the operand, or fallback to the general approach. 4438 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4439 if (ResTy == MatchOperand_Success) 4440 return false; 4441 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4442 // there was a match, but an error occurred, in which case, just return that 4443 // the operand parsing failed. 4444 if (ResTy == MatchOperand_ParseFail) 4445 return true; 4446 4447 switch (getLexer().getKind()) { 4448 default: 4449 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4450 return true; 4451 case AsmToken::Identifier: { 4452 // If we've seen a branch mnemonic, the next operand must be a label. This 4453 // is true even if the label is a register name. So "br r1" means branch to 4454 // label "r1". 4455 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4456 if (!ExpectLabel) { 4457 if (!tryParseRegisterWithWriteBack(Operands)) 4458 return false; 4459 int Res = tryParseShiftRegister(Operands); 4460 if (Res == 0) // success 4461 return false; 4462 else if (Res == -1) // irrecoverable error 4463 return true; 4464 // If this is VMRS, check for the apsr_nzcv operand. 4465 if (Mnemonic == "vmrs" && 4466 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4467 S = Parser.getTok().getLoc(); 4468 Parser.Lex(); 4469 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4470 return false; 4471 } 4472 } 4473 4474 // Fall though for the Identifier case that is not a register or a 4475 // special name. 4476 } 4477 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4478 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4479 case AsmToken::String: // quoted label names. 4480 case AsmToken::Dot: { // . as a branch target 4481 // This was not a register so parse other operands that start with an 4482 // identifier (like labels) as expressions and create them as immediates. 4483 const MCExpr *IdVal; 4484 S = Parser.getTok().getLoc(); 4485 if (getParser().parseExpression(IdVal)) 4486 return true; 4487 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4488 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4489 return false; 4490 } 4491 case AsmToken::LBrac: 4492 return parseMemory(Operands); 4493 case AsmToken::LCurly: 4494 return parseRegisterList(Operands); 4495 case AsmToken::Dollar: 4496 case AsmToken::Hash: { 4497 // #42 -> immediate. 4498 S = Parser.getTok().getLoc(); 4499 Parser.Lex(); 4500 4501 if (Parser.getTok().isNot(AsmToken::Colon)) { 4502 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4503 const MCExpr *ImmVal; 4504 if (getParser().parseExpression(ImmVal)) 4505 return true; 4506 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4507 if (CE) { 4508 int32_t Val = CE->getValue(); 4509 if (isNegative && Val == 0) 4510 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4511 } 4512 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4513 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4514 4515 // There can be a trailing '!' on operands that we want as a separate 4516 // '!' Token operand. Handle that here. For example, the compatibilty 4517 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 4518 if (Parser.getTok().is(AsmToken::Exclaim)) { 4519 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 4520 Parser.getTok().getLoc())); 4521 Parser.Lex(); // Eat exclaim token 4522 } 4523 return false; 4524 } 4525 // w/ a ':' after the '#', it's just like a plain ':'. 4526 // FALLTHROUGH 4527 } 4528 case AsmToken::Colon: { 4529 // ":lower16:" and ":upper16:" expression prefixes 4530 // FIXME: Check it's an expression prefix, 4531 // e.g. (FOO - :lower16:BAR) isn't legal. 4532 ARMMCExpr::VariantKind RefKind; 4533 if (parsePrefix(RefKind)) 4534 return true; 4535 4536 const MCExpr *SubExprVal; 4537 if (getParser().parseExpression(SubExprVal)) 4538 return true; 4539 4540 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4541 getContext()); 4542 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4543 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4544 return false; 4545 } 4546 } 4547 } 4548 4549 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4550 // :lower16: and :upper16:. 4551 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4552 RefKind = ARMMCExpr::VK_ARM_None; 4553 4554 // :lower16: and :upper16: modifiers 4555 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4556 Parser.Lex(); // Eat ':' 4557 4558 if (getLexer().isNot(AsmToken::Identifier)) { 4559 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4560 return true; 4561 } 4562 4563 StringRef IDVal = Parser.getTok().getIdentifier(); 4564 if (IDVal == "lower16") { 4565 RefKind = ARMMCExpr::VK_ARM_LO16; 4566 } else if (IDVal == "upper16") { 4567 RefKind = ARMMCExpr::VK_ARM_HI16; 4568 } else { 4569 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4570 return true; 4571 } 4572 Parser.Lex(); 4573 4574 if (getLexer().isNot(AsmToken::Colon)) { 4575 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4576 return true; 4577 } 4578 Parser.Lex(); // Eat the last ':' 4579 return false; 4580 } 4581 4582 /// \brief Given a mnemonic, split out possible predication code and carry 4583 /// setting letters to form a canonical mnemonic and flags. 4584 // 4585 // FIXME: Would be nice to autogen this. 4586 // FIXME: This is a bit of a maze of special cases. 4587 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4588 unsigned &PredicationCode, 4589 bool &CarrySetting, 4590 unsigned &ProcessorIMod, 4591 StringRef &ITMask) { 4592 PredicationCode = ARMCC::AL; 4593 CarrySetting = false; 4594 ProcessorIMod = 0; 4595 4596 // Ignore some mnemonics we know aren't predicated forms. 4597 // 4598 // FIXME: Would be nice to autogen this. 4599 if ((Mnemonic == "movs" && isThumb()) || 4600 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4601 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4602 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4603 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4604 Mnemonic == "vaclt" || Mnemonic == "vacle" || 4605 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4606 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4607 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4608 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 4609 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 4610 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 4611 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel")) 4612 return Mnemonic; 4613 4614 // First, split out any predication code. Ignore mnemonics we know aren't 4615 // predicated but do have a carry-set and so weren't caught above. 4616 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4617 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4618 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4619 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4620 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4621 .Case("eq", ARMCC::EQ) 4622 .Case("ne", ARMCC::NE) 4623 .Case("hs", ARMCC::HS) 4624 .Case("cs", ARMCC::HS) 4625 .Case("lo", ARMCC::LO) 4626 .Case("cc", ARMCC::LO) 4627 .Case("mi", ARMCC::MI) 4628 .Case("pl", ARMCC::PL) 4629 .Case("vs", ARMCC::VS) 4630 .Case("vc", ARMCC::VC) 4631 .Case("hi", ARMCC::HI) 4632 .Case("ls", ARMCC::LS) 4633 .Case("ge", ARMCC::GE) 4634 .Case("lt", ARMCC::LT) 4635 .Case("gt", ARMCC::GT) 4636 .Case("le", ARMCC::LE) 4637 .Case("al", ARMCC::AL) 4638 .Default(~0U); 4639 if (CC != ~0U) { 4640 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4641 PredicationCode = CC; 4642 } 4643 } 4644 4645 // Next, determine if we have a carry setting bit. We explicitly ignore all 4646 // the instructions we know end in 's'. 4647 if (Mnemonic.endswith("s") && 4648 !(Mnemonic == "cps" || Mnemonic == "mls" || 4649 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4650 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4651 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4652 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4653 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4654 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4655 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4656 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4657 (Mnemonic == "movs" && isThumb()))) { 4658 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4659 CarrySetting = true; 4660 } 4661 4662 // The "cps" instruction can have a interrupt mode operand which is glued into 4663 // the mnemonic. Check if this is the case, split it and parse the imod op 4664 if (Mnemonic.startswith("cps")) { 4665 // Split out any imod code. 4666 unsigned IMod = 4667 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4668 .Case("ie", ARM_PROC::IE) 4669 .Case("id", ARM_PROC::ID) 4670 .Default(~0U); 4671 if (IMod != ~0U) { 4672 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4673 ProcessorIMod = IMod; 4674 } 4675 } 4676 4677 // The "it" instruction has the condition mask on the end of the mnemonic. 4678 if (Mnemonic.startswith("it")) { 4679 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4680 Mnemonic = Mnemonic.slice(0, 2); 4681 } 4682 4683 return Mnemonic; 4684 } 4685 4686 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4687 /// inclusion of carry set or predication code operands. 4688 // 4689 // FIXME: It would be nice to autogen this. 4690 void ARMAsmParser:: 4691 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4692 bool &CanAcceptPredicationCode) { 4693 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4694 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4695 Mnemonic == "add" || Mnemonic == "adc" || 4696 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4697 Mnemonic == "orr" || Mnemonic == "mvn" || 4698 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4699 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4700 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4701 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4702 Mnemonic == "mla" || Mnemonic == "smlal" || 4703 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4704 CanAcceptCarrySet = true; 4705 } else 4706 CanAcceptCarrySet = false; 4707 4708 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 4709 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 4710 Mnemonic == "trap" || Mnemonic == "setend" || 4711 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") || 4712 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" || 4713 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || 4714 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" || 4715 Mnemonic == "vrintm") { 4716 // These mnemonics are never predicable 4717 CanAcceptPredicationCode = false; 4718 } else if (!isThumb()) { 4719 // Some instructions are only predicable in Thumb mode 4720 CanAcceptPredicationCode 4721 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 4722 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 4723 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 4724 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 4725 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 4726 Mnemonic != "stc2" && Mnemonic != "stc2l" && 4727 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 4728 } else if (isThumbOne()) { 4729 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 4730 } else 4731 CanAcceptPredicationCode = true; 4732 } 4733 4734 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4735 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4736 // FIXME: This is all horribly hacky. We really need a better way to deal 4737 // with optional operands like this in the matcher table. 4738 4739 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4740 // another does not. Specifically, the MOVW instruction does not. So we 4741 // special case it here and remove the defaulted (non-setting) cc_out 4742 // operand if that's the instruction we're trying to match. 4743 // 4744 // We do this as post-processing of the explicit operands rather than just 4745 // conditionally adding the cc_out in the first place because we need 4746 // to check the type of the parsed immediate operand. 4747 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4748 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4749 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4750 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4751 return true; 4752 4753 // Register-register 'add' for thumb does not have a cc_out operand 4754 // when there are only two register operands. 4755 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4756 static_cast<ARMOperand*>(Operands[3])->isReg() && 4757 static_cast<ARMOperand*>(Operands[4])->isReg() && 4758 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4759 return true; 4760 // Register-register 'add' for thumb does not have a cc_out operand 4761 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4762 // have to check the immediate range here since Thumb2 has a variant 4763 // that can handle a different range and has a cc_out operand. 4764 if (((isThumb() && Mnemonic == "add") || 4765 (isThumbTwo() && Mnemonic == "sub")) && 4766 Operands.size() == 6 && 4767 static_cast<ARMOperand*>(Operands[3])->isReg() && 4768 static_cast<ARMOperand*>(Operands[4])->isReg() && 4769 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4770 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4771 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4772 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4773 return true; 4774 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4775 // imm0_4095 variant. That's the least-preferred variant when 4776 // selecting via the generic "add" mnemonic, so to know that we 4777 // should remove the cc_out operand, we have to explicitly check that 4778 // it's not one of the other variants. Ugh. 4779 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4780 Operands.size() == 6 && 4781 static_cast<ARMOperand*>(Operands[3])->isReg() && 4782 static_cast<ARMOperand*>(Operands[4])->isReg() && 4783 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4784 // Nest conditions rather than one big 'if' statement for readability. 4785 // 4786 // If both registers are low, we're in an IT block, and the immediate is 4787 // in range, we should use encoding T1 instead, which has a cc_out. 4788 if (inITBlock() && 4789 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4790 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4791 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4792 return false; 4793 // Check against T3. If the second register is the PC, this is an 4794 // alternate form of ADR, which uses encoding T4, so check for that too. 4795 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 4796 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4797 return false; 4798 4799 // Otherwise, we use encoding T4, which does not have a cc_out 4800 // operand. 4801 return true; 4802 } 4803 4804 // The thumb2 multiply instruction doesn't have a CCOut register, so 4805 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4806 // use the 16-bit encoding or not. 4807 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4808 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4809 static_cast<ARMOperand*>(Operands[3])->isReg() && 4810 static_cast<ARMOperand*>(Operands[4])->isReg() && 4811 static_cast<ARMOperand*>(Operands[5])->isReg() && 4812 // If the registers aren't low regs, the destination reg isn't the 4813 // same as one of the source regs, or the cc_out operand is zero 4814 // outside of an IT block, we have to use the 32-bit encoding, so 4815 // remove the cc_out operand. 4816 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4817 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4818 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4819 !inITBlock() || 4820 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4821 static_cast<ARMOperand*>(Operands[5])->getReg() && 4822 static_cast<ARMOperand*>(Operands[3])->getReg() != 4823 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4824 return true; 4825 4826 // Also check the 'mul' syntax variant that doesn't specify an explicit 4827 // destination register. 4828 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4829 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4830 static_cast<ARMOperand*>(Operands[3])->isReg() && 4831 static_cast<ARMOperand*>(Operands[4])->isReg() && 4832 // If the registers aren't low regs or the cc_out operand is zero 4833 // outside of an IT block, we have to use the 32-bit encoding, so 4834 // remove the cc_out operand. 4835 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4836 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4837 !inITBlock())) 4838 return true; 4839 4840 4841 4842 // Register-register 'add/sub' for thumb does not have a cc_out operand 4843 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4844 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4845 // right, this will result in better diagnostics (which operand is off) 4846 // anyway. 4847 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4848 (Operands.size() == 5 || Operands.size() == 6) && 4849 static_cast<ARMOperand*>(Operands[3])->isReg() && 4850 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4851 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4852 (static_cast<ARMOperand*>(Operands[4])->isImm() || 4853 (Operands.size() == 6 && 4854 static_cast<ARMOperand*>(Operands[5])->isImm()))) 4855 return true; 4856 4857 return false; 4858 } 4859 4860 bool ARMAsmParser::shouldOmitPredicateOperand( 4861 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) { 4862 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 4863 unsigned RegIdx = 3; 4864 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 4865 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") { 4866 if (static_cast<ARMOperand *>(Operands[3])->isToken() && 4867 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32") 4868 RegIdx = 4; 4869 4870 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() && 4871 (ARMMCRegisterClasses[ARM::DPRRegClassID] 4872 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) || 4873 ARMMCRegisterClasses[ARM::QPRRegClassID] 4874 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()))) 4875 return true; 4876 } 4877 return false; 4878 } 4879 4880 bool ARMAsmParser::isDeprecated(MCInst &Inst, StringRef &Info) { 4881 if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) { 4882 Info = "armv8"; 4883 return true; 4884 } 4885 return false; 4886 } 4887 4888 static bool isDataTypeToken(StringRef Tok) { 4889 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4890 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4891 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4892 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4893 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 4894 Tok == ".f" || Tok == ".d"; 4895 } 4896 4897 // FIXME: This bit should probably be handled via an explicit match class 4898 // in the .td files that matches the suffix instead of having it be 4899 // a literal string token the way it is now. 4900 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 4901 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 4902 } 4903 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, 4904 unsigned VariantID); 4905 /// Parse an arm instruction mnemonic followed by its operands. 4906 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 4907 SMLoc NameLoc, 4908 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4909 // Apply mnemonic aliases before doing anything else, as the destination 4910 // mnemnonic may include suffices and we want to handle them normally. 4911 // The generic tblgen'erated code does this later, at the start of 4912 // MatchInstructionImpl(), but that's too late for aliases that include 4913 // any sort of suffix. 4914 unsigned AvailableFeatures = getAvailableFeatures(); 4915 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 4916 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 4917 4918 // First check for the ARM-specific .req directive. 4919 if (Parser.getTok().is(AsmToken::Identifier) && 4920 Parser.getTok().getIdentifier() == ".req") { 4921 parseDirectiveReq(Name, NameLoc); 4922 // We always return 'error' for this, as we're done with this 4923 // statement and don't need to match the 'instruction." 4924 return true; 4925 } 4926 4927 // Create the leading tokens for the mnemonic, split by '.' characters. 4928 size_t Start = 0, Next = Name.find('.'); 4929 StringRef Mnemonic = Name.slice(Start, Next); 4930 4931 // Split out the predication code and carry setting flag from the mnemonic. 4932 unsigned PredicationCode; 4933 unsigned ProcessorIMod; 4934 bool CarrySetting; 4935 StringRef ITMask; 4936 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 4937 ProcessorIMod, ITMask); 4938 4939 // In Thumb1, only the branch (B) instruction can be predicated. 4940 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 4941 Parser.eatToEndOfStatement(); 4942 return Error(NameLoc, "conditional execution not supported in Thumb1"); 4943 } 4944 4945 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4946 4947 // Handle the IT instruction ITMask. Convert it to a bitmask. This 4948 // is the mask as it will be for the IT encoding if the conditional 4949 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 4950 // where the conditional bit0 is zero, the instruction post-processing 4951 // will adjust the mask accordingly. 4952 if (Mnemonic == "it") { 4953 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4954 if (ITMask.size() > 3) { 4955 Parser.eatToEndOfStatement(); 4956 return Error(Loc, "too many conditions on IT instruction"); 4957 } 4958 unsigned Mask = 8; 4959 for (unsigned i = ITMask.size(); i != 0; --i) { 4960 char pos = ITMask[i - 1]; 4961 if (pos != 't' && pos != 'e') { 4962 Parser.eatToEndOfStatement(); 4963 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 4964 } 4965 Mask >>= 1; 4966 if (ITMask[i - 1] == 't') 4967 Mask |= 8; 4968 } 4969 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 4970 } 4971 4972 // FIXME: This is all a pretty gross hack. We should automatically handle 4973 // optional operands like this via tblgen. 4974 4975 // Next, add the CCOut and ConditionCode operands, if needed. 4976 // 4977 // For mnemonics which can ever incorporate a carry setting bit or predication 4978 // code, our matching model involves us always generating CCOut and 4979 // ConditionCode operands to match the mnemonic "as written" and then we let 4980 // the matcher deal with finding the right instruction or generating an 4981 // appropriate error. 4982 bool CanAcceptCarrySet, CanAcceptPredicationCode; 4983 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 4984 4985 // If we had a carry-set on an instruction that can't do that, issue an 4986 // error. 4987 if (!CanAcceptCarrySet && CarrySetting) { 4988 Parser.eatToEndOfStatement(); 4989 return Error(NameLoc, "instruction '" + Mnemonic + 4990 "' can not set flags, but 's' suffix specified"); 4991 } 4992 // If we had a predication code on an instruction that can't do that, issue an 4993 // error. 4994 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 4995 Parser.eatToEndOfStatement(); 4996 return Error(NameLoc, "instruction '" + Mnemonic + 4997 "' is not predicable, but condition code specified"); 4998 } 4999 5000 // Add the carry setting operand, if necessary. 5001 if (CanAcceptCarrySet) { 5002 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5003 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5004 Loc)); 5005 } 5006 5007 // Add the predication code operand, if necessary. 5008 if (CanAcceptPredicationCode) { 5009 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5010 CarrySetting); 5011 Operands.push_back(ARMOperand::CreateCondCode( 5012 ARMCC::CondCodes(PredicationCode), Loc)); 5013 } 5014 5015 // Add the processor imod operand, if necessary. 5016 if (ProcessorIMod) { 5017 Operands.push_back(ARMOperand::CreateImm( 5018 MCConstantExpr::Create(ProcessorIMod, getContext()), 5019 NameLoc, NameLoc)); 5020 } 5021 5022 // Add the remaining tokens in the mnemonic. 5023 while (Next != StringRef::npos) { 5024 Start = Next; 5025 Next = Name.find('.', Start + 1); 5026 StringRef ExtraToken = Name.slice(Start, Next); 5027 5028 // Some NEON instructions have an optional datatype suffix that is 5029 // completely ignored. Check for that. 5030 if (isDataTypeToken(ExtraToken) && 5031 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5032 continue; 5033 5034 // For for ARM mode generate an error if the .n qualifier is used. 5035 if (ExtraToken == ".n" && !isThumb()) { 5036 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5037 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5038 "arm mode"); 5039 } 5040 5041 // The .n qualifier is always discarded as that is what the tables 5042 // and matcher expect. In ARM mode the .w qualifier has no effect, 5043 // so discard it to avoid errors that can be caused by the matcher. 5044 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5045 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5046 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5047 } 5048 } 5049 5050 // Read the remaining operands. 5051 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5052 // Read the first operand. 5053 if (parseOperand(Operands, Mnemonic)) { 5054 Parser.eatToEndOfStatement(); 5055 return true; 5056 } 5057 5058 while (getLexer().is(AsmToken::Comma)) { 5059 Parser.Lex(); // Eat the comma. 5060 5061 // Parse and remember the operand. 5062 if (parseOperand(Operands, Mnemonic)) { 5063 Parser.eatToEndOfStatement(); 5064 return true; 5065 } 5066 } 5067 } 5068 5069 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5070 SMLoc Loc = getLexer().getLoc(); 5071 Parser.eatToEndOfStatement(); 5072 return Error(Loc, "unexpected token in argument list"); 5073 } 5074 5075 Parser.Lex(); // Consume the EndOfStatement 5076 5077 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5078 // do and don't have a cc_out optional-def operand. With some spot-checks 5079 // of the operand list, we can figure out which variant we're trying to 5080 // parse and adjust accordingly before actually matching. We shouldn't ever 5081 // try to remove a cc_out operand that was explicitly set on the the 5082 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5083 // table driven matcher doesn't fit well with the ARM instruction set. 5084 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5085 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5086 Operands.erase(Operands.begin() + 1); 5087 delete Op; 5088 } 5089 5090 // Some instructions have the same mnemonic, but don't always 5091 // have a predicate. Distinguish them here and delete the 5092 // predicate if needed. 5093 if (shouldOmitPredicateOperand(Mnemonic, Operands)) { 5094 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5095 Operands.erase(Operands.begin() + 1); 5096 delete Op; 5097 } 5098 5099 // ARM mode 'blx' need special handling, as the register operand version 5100 // is predicable, but the label operand version is not. So, we can't rely 5101 // on the Mnemonic based checking to correctly figure out when to put 5102 // a k_CondCode operand in the list. If we're trying to match the label 5103 // version, remove the k_CondCode operand here. 5104 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5105 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5106 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5107 Operands.erase(Operands.begin() + 1); 5108 delete Op; 5109 } 5110 5111 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5112 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5113 // a single GPRPair reg operand is used in the .td file to replace the two 5114 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5115 // expressed as a GPRPair, so we have to manually merge them. 5116 // FIXME: We would really like to be able to tablegen'erate this. 5117 if (!isThumb() && Operands.size() > 4 && 5118 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) { 5119 bool isLoad = (Mnemonic == "ldrexd"); 5120 unsigned Idx = isLoad ? 2 : 3; 5121 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); 5122 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); 5123 5124 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5125 // Adjust only if Op1 and Op2 are GPRs. 5126 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5127 MRC.contains(Op2->getReg())) { 5128 unsigned Reg1 = Op1->getReg(); 5129 unsigned Reg2 = Op2->getReg(); 5130 unsigned Rt = MRI->getEncodingValue(Reg1); 5131 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5132 5133 // Rt2 must be Rt + 1 and Rt must be even. 5134 if (Rt + 1 != Rt2 || (Rt & 1)) { 5135 Error(Op2->getStartLoc(), isLoad ? 5136 "destination operands must be sequential" : 5137 "source operands must be sequential"); 5138 return true; 5139 } 5140 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5141 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5142 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2); 5143 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg( 5144 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5145 delete Op1; 5146 delete Op2; 5147 } 5148 } 5149 5150 // FIXME: As said above, this is all a pretty gross hack. This instruction 5151 // does not fit with other "subs" and tblgen. 5152 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 5153 // so the Mnemonic is the original name "subs" and delete the predicate 5154 // operand so it will match the table entry. 5155 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 5156 static_cast<ARMOperand*>(Operands[3])->isReg() && 5157 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC && 5158 static_cast<ARMOperand*>(Operands[4])->isReg() && 5159 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR && 5160 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5161 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]); 5162 Operands.erase(Operands.begin()); 5163 delete Op0; 5164 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc)); 5165 5166 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]); 5167 Operands.erase(Operands.begin() + 1); 5168 delete Op1; 5169 } 5170 return false; 5171 } 5172 5173 // Validate context-sensitive operand constraints. 5174 5175 // return 'true' if register list contains non-low GPR registers, 5176 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5177 // 'containsReg' to true. 5178 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5179 unsigned HiReg, bool &containsReg) { 5180 containsReg = false; 5181 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5182 unsigned OpReg = Inst.getOperand(i).getReg(); 5183 if (OpReg == Reg) 5184 containsReg = true; 5185 // Anything other than a low register isn't legal here. 5186 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5187 return true; 5188 } 5189 return false; 5190 } 5191 5192 // Check if the specified regisgter is in the register list of the inst, 5193 // starting at the indicated operand number. 5194 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5195 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5196 unsigned OpReg = Inst.getOperand(i).getReg(); 5197 if (OpReg == Reg) 5198 return true; 5199 } 5200 return false; 5201 } 5202 5203 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5204 // the ARMInsts array) instead. Getting that here requires awkward 5205 // API changes, though. Better way? 5206 namespace llvm { 5207 extern const MCInstrDesc ARMInsts[]; 5208 } 5209 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5210 return ARMInsts[Opcode]; 5211 } 5212 5213 // FIXME: We would really like to be able to tablegen'erate this. 5214 bool ARMAsmParser:: 5215 validateInstruction(MCInst &Inst, 5216 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5217 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5218 SMLoc Loc = Operands[0]->getStartLoc(); 5219 // Check the IT block state first. 5220 // NOTE: BKPT instruction has the interesting property of being 5221 // allowed in IT blocks, but not being predicable. It just always 5222 // executes. 5223 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5224 Inst.getOpcode() != ARM::BKPT) { 5225 unsigned bit = 1; 5226 if (ITState.FirstCond) 5227 ITState.FirstCond = false; 5228 else 5229 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5230 // The instruction must be predicable. 5231 if (!MCID.isPredicable()) 5232 return Error(Loc, "instructions in IT block must be predicable"); 5233 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5234 unsigned ITCond = bit ? ITState.Cond : 5235 ARMCC::getOppositeCondition(ITState.Cond); 5236 if (Cond != ITCond) { 5237 // Find the condition code Operand to get its SMLoc information. 5238 SMLoc CondLoc; 5239 for (unsigned i = 1; i < Operands.size(); ++i) 5240 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5241 CondLoc = Operands[i]->getStartLoc(); 5242 return Error(CondLoc, "incorrect condition in IT block; got '" + 5243 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5244 "', but expected '" + 5245 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5246 } 5247 // Check for non-'al' condition codes outside of the IT block. 5248 } else if (isThumbTwo() && MCID.isPredicable() && 5249 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5250 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5251 Inst.getOpcode() != ARM::t2B) 5252 return Error(Loc, "predicated instructions must be in IT block"); 5253 5254 switch (Inst.getOpcode()) { 5255 case ARM::LDRD: 5256 case ARM::LDRD_PRE: 5257 case ARM::LDRD_POST: { 5258 // Rt2 must be Rt + 1. 5259 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5260 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5261 if (Rt2 != Rt + 1) 5262 return Error(Operands[3]->getStartLoc(), 5263 "destination operands must be sequential"); 5264 return false; 5265 } 5266 case ARM::STRD: { 5267 // Rt2 must be Rt + 1. 5268 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5269 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5270 if (Rt2 != Rt + 1) 5271 return Error(Operands[3]->getStartLoc(), 5272 "source operands must be sequential"); 5273 return false; 5274 } 5275 case ARM::STRD_PRE: 5276 case ARM::STRD_POST: { 5277 // Rt2 must be Rt + 1. 5278 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5279 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5280 if (Rt2 != Rt + 1) 5281 return Error(Operands[3]->getStartLoc(), 5282 "source operands must be sequential"); 5283 return false; 5284 } 5285 case ARM::SBFX: 5286 case ARM::UBFX: { 5287 // width must be in range [1, 32-lsb] 5288 unsigned lsb = Inst.getOperand(2).getImm(); 5289 unsigned widthm1 = Inst.getOperand(3).getImm(); 5290 if (widthm1 >= 32 - lsb) 5291 return Error(Operands[5]->getStartLoc(), 5292 "bitfield width must be in range [1,32-lsb]"); 5293 return false; 5294 } 5295 case ARM::tLDMIA: { 5296 // If we're parsing Thumb2, the .w variant is available and handles 5297 // most cases that are normally illegal for a Thumb1 LDM 5298 // instruction. We'll make the transformation in processInstruction() 5299 // if necessary. 5300 // 5301 // Thumb LDM instructions are writeback iff the base register is not 5302 // in the register list. 5303 unsigned Rn = Inst.getOperand(0).getReg(); 5304 bool hasWritebackToken = 5305 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5306 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5307 bool listContainsBase; 5308 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5309 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5310 "registers must be in range r0-r7"); 5311 // If we should have writeback, then there should be a '!' token. 5312 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5313 return Error(Operands[2]->getStartLoc(), 5314 "writeback operator '!' expected"); 5315 // If we should not have writeback, there must not be a '!'. This is 5316 // true even for the 32-bit wide encodings. 5317 if (listContainsBase && hasWritebackToken) 5318 return Error(Operands[3]->getStartLoc(), 5319 "writeback operator '!' not allowed when base register " 5320 "in register list"); 5321 5322 break; 5323 } 5324 case ARM::t2LDMIA_UPD: { 5325 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5326 return Error(Operands[4]->getStartLoc(), 5327 "writeback operator '!' not allowed when base register " 5328 "in register list"); 5329 break; 5330 } 5331 case ARM::tMUL: { 5332 // The second source operand must be the same register as the destination 5333 // operand. 5334 // 5335 // In this case, we must directly check the parsed operands because the 5336 // cvtThumbMultiply() function is written in such a way that it guarantees 5337 // this first statement is always true for the new Inst. Essentially, the 5338 // destination is unconditionally copied into the second source operand 5339 // without checking to see if it matches what we actually parsed. 5340 if (Operands.size() == 6 && 5341 (((ARMOperand*)Operands[3])->getReg() != 5342 ((ARMOperand*)Operands[5])->getReg()) && 5343 (((ARMOperand*)Operands[3])->getReg() != 5344 ((ARMOperand*)Operands[4])->getReg())) { 5345 return Error(Operands[3]->getStartLoc(), 5346 "destination register must match source register"); 5347 } 5348 break; 5349 } 5350 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5351 // so only issue a diagnostic for thumb1. The instructions will be 5352 // switched to the t2 encodings in processInstruction() if necessary. 5353 case ARM::tPOP: { 5354 bool listContainsBase; 5355 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5356 !isThumbTwo()) 5357 return Error(Operands[2]->getStartLoc(), 5358 "registers must be in range r0-r7 or pc"); 5359 break; 5360 } 5361 case ARM::tPUSH: { 5362 bool listContainsBase; 5363 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5364 !isThumbTwo()) 5365 return Error(Operands[2]->getStartLoc(), 5366 "registers must be in range r0-r7 or lr"); 5367 break; 5368 } 5369 case ARM::tSTMIA_UPD: { 5370 bool listContainsBase; 5371 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5372 return Error(Operands[4]->getStartLoc(), 5373 "registers must be in range r0-r7"); 5374 break; 5375 } 5376 case ARM::tADDrSP: { 5377 // If the non-SP source operand and the destination operand are not the 5378 // same, we need thumb2 (for the wide encoding), or we have an error. 5379 if (!isThumbTwo() && 5380 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5381 return Error(Operands[4]->getStartLoc(), 5382 "source register must be the same as destination"); 5383 } 5384 break; 5385 } 5386 } 5387 5388 StringRef DepInfo; 5389 if (isDeprecated(Inst, DepInfo)) 5390 Warning(Loc, "deprecated on " + DepInfo); 5391 5392 return false; 5393 } 5394 5395 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5396 switch(Opc) { 5397 default: llvm_unreachable("unexpected opcode!"); 5398 // VST1LN 5399 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5400 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5401 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5402 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5403 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5404 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5405 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5406 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5407 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5408 5409 // VST2LN 5410 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5411 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5412 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5413 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5414 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5415 5416 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5417 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5418 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5419 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5420 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5421 5422 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5423 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5424 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5425 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5426 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5427 5428 // VST3LN 5429 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5430 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5431 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5432 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5433 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5434 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5435 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5436 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5437 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5438 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5439 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5440 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5441 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5442 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5443 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5444 5445 // VST3 5446 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5447 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5448 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5449 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5450 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5451 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5452 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5453 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5454 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5455 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5456 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5457 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5458 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5459 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5460 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5461 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5462 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5463 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5464 5465 // VST4LN 5466 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5467 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5468 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5469 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5470 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5471 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5472 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5473 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5474 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5475 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5476 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5477 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5478 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5479 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5480 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5481 5482 // VST4 5483 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5484 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5485 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5486 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5487 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5488 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5489 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5490 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5491 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5492 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5493 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5494 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5495 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5496 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5497 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5498 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5499 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5500 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5501 } 5502 } 5503 5504 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5505 switch(Opc) { 5506 default: llvm_unreachable("unexpected opcode!"); 5507 // VLD1LN 5508 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5509 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5510 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5511 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5512 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5513 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5514 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5515 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5516 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5517 5518 // VLD2LN 5519 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5520 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5521 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5522 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5523 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5524 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5525 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5526 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5527 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5528 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5529 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5530 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5531 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5532 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5533 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5534 5535 // VLD3DUP 5536 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5537 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5538 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5539 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5540 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5541 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5542 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5543 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5544 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5545 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5546 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5547 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5548 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5549 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5550 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5551 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5552 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5553 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5554 5555 // VLD3LN 5556 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5557 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5558 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5559 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5560 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5561 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5562 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5563 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5564 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5565 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5566 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5567 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5568 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5569 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5570 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5571 5572 // VLD3 5573 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5574 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5575 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5576 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5577 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5578 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5579 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5580 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5581 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5582 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5583 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5584 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5585 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5586 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5587 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5588 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5589 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5590 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5591 5592 // VLD4LN 5593 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5594 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5595 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5596 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5597 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5598 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5599 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5600 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5601 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5602 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5603 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5604 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5605 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5606 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5607 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5608 5609 // VLD4DUP 5610 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5611 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5612 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5613 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5614 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5615 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5616 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5617 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5618 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5619 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5620 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5621 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5622 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5623 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5624 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5625 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5626 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5627 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5628 5629 // VLD4 5630 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5631 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5632 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5633 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5634 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5635 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5636 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5637 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5638 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5639 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5640 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5641 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5642 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5643 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5644 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5645 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5646 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5647 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5648 } 5649 } 5650 5651 bool ARMAsmParser:: 5652 processInstruction(MCInst &Inst, 5653 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5654 switch (Inst.getOpcode()) { 5655 // Alias for alternate form of 'ADR Rd, #imm' instruction. 5656 case ARM::ADDri: { 5657 if (Inst.getOperand(1).getReg() != ARM::PC || 5658 Inst.getOperand(5).getReg() != 0) 5659 return false; 5660 MCInst TmpInst; 5661 TmpInst.setOpcode(ARM::ADR); 5662 TmpInst.addOperand(Inst.getOperand(0)); 5663 TmpInst.addOperand(Inst.getOperand(2)); 5664 TmpInst.addOperand(Inst.getOperand(3)); 5665 TmpInst.addOperand(Inst.getOperand(4)); 5666 Inst = TmpInst; 5667 return true; 5668 } 5669 // Aliases for alternate PC+imm syntax of LDR instructions. 5670 case ARM::t2LDRpcrel: 5671 // Select the narrow version if the immediate will fit. 5672 if (Inst.getOperand(1).getImm() > 0 && 5673 Inst.getOperand(1).getImm() <= 0xff && 5674 !(static_cast<ARMOperand*>(Operands[2])->isToken() && 5675 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w")) 5676 Inst.setOpcode(ARM::tLDRpci); 5677 else 5678 Inst.setOpcode(ARM::t2LDRpci); 5679 return true; 5680 case ARM::t2LDRBpcrel: 5681 Inst.setOpcode(ARM::t2LDRBpci); 5682 return true; 5683 case ARM::t2LDRHpcrel: 5684 Inst.setOpcode(ARM::t2LDRHpci); 5685 return true; 5686 case ARM::t2LDRSBpcrel: 5687 Inst.setOpcode(ARM::t2LDRSBpci); 5688 return true; 5689 case ARM::t2LDRSHpcrel: 5690 Inst.setOpcode(ARM::t2LDRSHpci); 5691 return true; 5692 // Handle NEON VST complex aliases. 5693 case ARM::VST1LNdWB_register_Asm_8: 5694 case ARM::VST1LNdWB_register_Asm_16: 5695 case ARM::VST1LNdWB_register_Asm_32: { 5696 MCInst TmpInst; 5697 // Shuffle the operands around so the lane index operand is in the 5698 // right place. 5699 unsigned Spacing; 5700 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5701 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5702 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5703 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5704 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5705 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5706 TmpInst.addOperand(Inst.getOperand(1)); // lane 5707 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5708 TmpInst.addOperand(Inst.getOperand(6)); 5709 Inst = TmpInst; 5710 return true; 5711 } 5712 5713 case ARM::VST2LNdWB_register_Asm_8: 5714 case ARM::VST2LNdWB_register_Asm_16: 5715 case ARM::VST2LNdWB_register_Asm_32: 5716 case ARM::VST2LNqWB_register_Asm_16: 5717 case ARM::VST2LNqWB_register_Asm_32: { 5718 MCInst TmpInst; 5719 // Shuffle the operands around so the lane index operand is in the 5720 // right place. 5721 unsigned Spacing; 5722 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5723 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5724 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5725 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5726 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5727 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5729 Spacing)); 5730 TmpInst.addOperand(Inst.getOperand(1)); // lane 5731 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5732 TmpInst.addOperand(Inst.getOperand(6)); 5733 Inst = TmpInst; 5734 return true; 5735 } 5736 5737 case ARM::VST3LNdWB_register_Asm_8: 5738 case ARM::VST3LNdWB_register_Asm_16: 5739 case ARM::VST3LNdWB_register_Asm_32: 5740 case ARM::VST3LNqWB_register_Asm_16: 5741 case ARM::VST3LNqWB_register_Asm_32: { 5742 MCInst TmpInst; 5743 // Shuffle the operands around so the lane index operand is in the 5744 // right place. 5745 unsigned Spacing; 5746 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5747 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5748 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5749 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5750 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5751 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5752 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5753 Spacing)); 5754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5755 Spacing * 2)); 5756 TmpInst.addOperand(Inst.getOperand(1)); // lane 5757 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5758 TmpInst.addOperand(Inst.getOperand(6)); 5759 Inst = TmpInst; 5760 return true; 5761 } 5762 5763 case ARM::VST4LNdWB_register_Asm_8: 5764 case ARM::VST4LNdWB_register_Asm_16: 5765 case ARM::VST4LNdWB_register_Asm_32: 5766 case ARM::VST4LNqWB_register_Asm_16: 5767 case ARM::VST4LNqWB_register_Asm_32: { 5768 MCInst TmpInst; 5769 // Shuffle the operands around so the lane index operand is in the 5770 // right place. 5771 unsigned Spacing; 5772 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5773 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5774 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5775 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5776 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5777 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5778 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5779 Spacing)); 5780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5781 Spacing * 2)); 5782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5783 Spacing * 3)); 5784 TmpInst.addOperand(Inst.getOperand(1)); // lane 5785 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5786 TmpInst.addOperand(Inst.getOperand(6)); 5787 Inst = TmpInst; 5788 return true; 5789 } 5790 5791 case ARM::VST1LNdWB_fixed_Asm_8: 5792 case ARM::VST1LNdWB_fixed_Asm_16: 5793 case ARM::VST1LNdWB_fixed_Asm_32: { 5794 MCInst TmpInst; 5795 // Shuffle the operands around so the lane index operand is in the 5796 // right place. 5797 unsigned Spacing; 5798 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5799 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5800 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5801 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5802 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5803 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5804 TmpInst.addOperand(Inst.getOperand(1)); // lane 5805 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5806 TmpInst.addOperand(Inst.getOperand(5)); 5807 Inst = TmpInst; 5808 return true; 5809 } 5810 5811 case ARM::VST2LNdWB_fixed_Asm_8: 5812 case ARM::VST2LNdWB_fixed_Asm_16: 5813 case ARM::VST2LNdWB_fixed_Asm_32: 5814 case ARM::VST2LNqWB_fixed_Asm_16: 5815 case ARM::VST2LNqWB_fixed_Asm_32: { 5816 MCInst TmpInst; 5817 // Shuffle the operands around so the lane index operand is in the 5818 // right place. 5819 unsigned Spacing; 5820 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5821 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5822 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5823 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5824 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5825 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5827 Spacing)); 5828 TmpInst.addOperand(Inst.getOperand(1)); // lane 5829 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5830 TmpInst.addOperand(Inst.getOperand(5)); 5831 Inst = TmpInst; 5832 return true; 5833 } 5834 5835 case ARM::VST3LNdWB_fixed_Asm_8: 5836 case ARM::VST3LNdWB_fixed_Asm_16: 5837 case ARM::VST3LNdWB_fixed_Asm_32: 5838 case ARM::VST3LNqWB_fixed_Asm_16: 5839 case ARM::VST3LNqWB_fixed_Asm_32: { 5840 MCInst TmpInst; 5841 // Shuffle the operands around so the lane index operand is in the 5842 // right place. 5843 unsigned Spacing; 5844 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5845 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5846 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5847 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5848 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5849 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5851 Spacing)); 5852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5853 Spacing * 2)); 5854 TmpInst.addOperand(Inst.getOperand(1)); // lane 5855 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5856 TmpInst.addOperand(Inst.getOperand(5)); 5857 Inst = TmpInst; 5858 return true; 5859 } 5860 5861 case ARM::VST4LNdWB_fixed_Asm_8: 5862 case ARM::VST4LNdWB_fixed_Asm_16: 5863 case ARM::VST4LNdWB_fixed_Asm_32: 5864 case ARM::VST4LNqWB_fixed_Asm_16: 5865 case ARM::VST4LNqWB_fixed_Asm_32: { 5866 MCInst TmpInst; 5867 // Shuffle the operands around so the lane index operand is in the 5868 // right place. 5869 unsigned Spacing; 5870 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5871 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5872 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5873 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5874 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5875 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5877 Spacing)); 5878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5879 Spacing * 2)); 5880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5881 Spacing * 3)); 5882 TmpInst.addOperand(Inst.getOperand(1)); // lane 5883 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5884 TmpInst.addOperand(Inst.getOperand(5)); 5885 Inst = TmpInst; 5886 return true; 5887 } 5888 5889 case ARM::VST1LNdAsm_8: 5890 case ARM::VST1LNdAsm_16: 5891 case ARM::VST1LNdAsm_32: { 5892 MCInst TmpInst; 5893 // Shuffle the operands around so the lane index operand is in the 5894 // right place. 5895 unsigned Spacing; 5896 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5897 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5898 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5899 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5900 TmpInst.addOperand(Inst.getOperand(1)); // lane 5901 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5902 TmpInst.addOperand(Inst.getOperand(5)); 5903 Inst = TmpInst; 5904 return true; 5905 } 5906 5907 case ARM::VST2LNdAsm_8: 5908 case ARM::VST2LNdAsm_16: 5909 case ARM::VST2LNdAsm_32: 5910 case ARM::VST2LNqAsm_16: 5911 case ARM::VST2LNqAsm_32: { 5912 MCInst TmpInst; 5913 // Shuffle the operands around so the lane index operand is in the 5914 // right place. 5915 unsigned Spacing; 5916 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5917 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5918 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5919 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5920 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5921 Spacing)); 5922 TmpInst.addOperand(Inst.getOperand(1)); // lane 5923 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5924 TmpInst.addOperand(Inst.getOperand(5)); 5925 Inst = TmpInst; 5926 return true; 5927 } 5928 5929 case ARM::VST3LNdAsm_8: 5930 case ARM::VST3LNdAsm_16: 5931 case ARM::VST3LNdAsm_32: 5932 case ARM::VST3LNqAsm_16: 5933 case ARM::VST3LNqAsm_32: { 5934 MCInst TmpInst; 5935 // Shuffle the operands around so the lane index operand is in the 5936 // right place. 5937 unsigned Spacing; 5938 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5939 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5940 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5941 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5942 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5943 Spacing)); 5944 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5945 Spacing * 2)); 5946 TmpInst.addOperand(Inst.getOperand(1)); // lane 5947 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5948 TmpInst.addOperand(Inst.getOperand(5)); 5949 Inst = TmpInst; 5950 return true; 5951 } 5952 5953 case ARM::VST4LNdAsm_8: 5954 case ARM::VST4LNdAsm_16: 5955 case ARM::VST4LNdAsm_32: 5956 case ARM::VST4LNqAsm_16: 5957 case ARM::VST4LNqAsm_32: { 5958 MCInst TmpInst; 5959 // Shuffle the operands around so the lane index operand is in the 5960 // right place. 5961 unsigned Spacing; 5962 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5963 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5964 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5965 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5966 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5967 Spacing)); 5968 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5969 Spacing * 2)); 5970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5971 Spacing * 3)); 5972 TmpInst.addOperand(Inst.getOperand(1)); // lane 5973 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5974 TmpInst.addOperand(Inst.getOperand(5)); 5975 Inst = TmpInst; 5976 return true; 5977 } 5978 5979 // Handle NEON VLD complex aliases. 5980 case ARM::VLD1LNdWB_register_Asm_8: 5981 case ARM::VLD1LNdWB_register_Asm_16: 5982 case ARM::VLD1LNdWB_register_Asm_32: { 5983 MCInst TmpInst; 5984 // Shuffle the operands around so the lane index operand is in the 5985 // right place. 5986 unsigned Spacing; 5987 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5988 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5989 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5990 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5991 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5992 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5993 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5994 TmpInst.addOperand(Inst.getOperand(1)); // lane 5995 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5996 TmpInst.addOperand(Inst.getOperand(6)); 5997 Inst = TmpInst; 5998 return true; 5999 } 6000 6001 case ARM::VLD2LNdWB_register_Asm_8: 6002 case ARM::VLD2LNdWB_register_Asm_16: 6003 case ARM::VLD2LNdWB_register_Asm_32: 6004