| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
128 MIB.addReg(AM.Base.Reg)
[all...] |
| X86FrameLowering.cpp | 276 .addReg(StackPtr)
277 .addReg(Reg);
295 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
357 .addReg(StackPtr)
583 .addReg(X86::RCX);
586 .addReg(X86::RDX);
589 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
595 .addReg(ZeroReg, RegState::Undef)
596 .addReg(ZeroReg, RegState::Undef);
597 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
61 .addReg(MI->getOperand(0).getReg())
62 .addReg(MI->getOperand(1).getReg())
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 163 .addReg(ThumbIndirectPads[i].first)
166 .addReg(0));
[all...] |
| ARMFrameLowering.cpp | 259 .addReg(Reg, RegState::Kill)
264 .addReg(Reg, RegState::Kill)
273 .addReg(Reg, RegState::Kill)
277 .addReg(Reg, RegState::Kill)
285 .addReg(Reg, RegState::Kill)
467 .addImm((unsigned)ARMCC::AL).addReg(0)
469 .addReg(ARM::R4, RegState::Implicit)
479 .addImm((unsigned)ARMCC::AL).addReg(0)
480 .addReg(ARM::R12, RegState::Kill)
481 .addReg(ARM::R4, RegState::Implicit
[all...] |
| ARMLoadStoreOptimizer.cpp | 512 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
530 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
645 LiveRegs.addReg(R.first);
690 .addReg(Base, getKillRegState(KillOldBase));
693 .addReg(Base, getKillRegState(KillOldBase))
694 .addImm(Pred).addReg(PredReg);
703 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
704 .addImm(Pred).addReg(PredReg)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 174 .addReg(AMDGPU::VGPR0)
175 .addReg(AMDGPU::VGPR0)
176 .addReg(AMDGPU::VGPR0)
177 .addReg(AMDGPU::VGPR0);
190 .addReg(Vcc);
193 .addReg(AMDGPU::EXEC)
194 .addReg(Reg);
209 .addReg(Src); // Saved EXEC
212 .addReg(AMDGPU::EXEC)
213 .addReg(Dst)
[all...] |
| SIFrameLowering.cpp | 168 .addReg(PreloadedScratchWaveOffsetReg, RegState::Kill);
186 .addReg(Lo, RegState::Kill);
188 .addReg(Hi, RegState::Kill);
199 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
203 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
207 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
211 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 259 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
261 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
264 .addReg(HEXAGON_RESERVED_REG_1)
265 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
268 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
270 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
273 .addReg(HEXAGON_RESERVED_REG_1)
275 .addReg(HEXAGON_RESERVED_REG_2);
279 HEXAGON_RESERVED_REG_2).addReg(SrcReg)
[all...] |
| HexagonSplitDouble.cpp | 621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
624 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
630 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
632 .addReg(P.first);
634 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
636 .addReg(P.second);
648 .addReg(AdrOp.getReg(), RSA)
715 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
724 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
744 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg())
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 514 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg));
519 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg));
550 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
604 .addReg(X86::ESP)
605 .addReg(X86::ESP)
608 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32)));
631 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
634 .addReg(ShadowRegI32
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 72 .addReg(FrameReg)
78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
79 .addReg(FrameReg)
85 .addReg(FrameReg)
108 .addReg(FrameReg)
109 .addReg(ScratchOffset, RegState::Kill)
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
115 .addReg(FrameReg)
116 .addReg(ScratchOffset, RegState::Kill)
121 .addReg(FrameReg
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
269 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
309 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
312 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
344 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1)
[all...] |
| MipsLongBranch.cpp | 232 MIB.addReg(MO.getReg());
296 .addReg(Mips::SP).addImm(-8);
297 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
298 .addReg(Mips::SP).addImm(0);
321 .addReg(Mips::AT)
328 .addReg(Mips::RA).addReg(Mips::AT);
330 .addReg(Mips::SP).addImm(0);
334 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
336 .addReg(Mips::SP).addImm(8))
[all...] |
| MipsSEInstrInfo.cpp | 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130 .addReg(DestReg, RegState::ImplicitDefine);
170 MIB.addReg(DestReg, RegState::Define);
173 MIB.addReg(SrcReg, getKillRegState(KillSrc));
176 MIB.addReg(ZeroReg);
244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
324 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
439 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
442 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 354 .addReg(SrcReg)
358 .addReg(SrcReg, RegState::Kill)
363 .addReg(SrcReg)
367 .addReg(SrcReg, RegState::Kill)
372 .addReg(SrcReg)
376 .addReg(SrcReg, RegState::Kill)
380 .addReg(DstReg, RegState::Kill)
764 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
770 .addReg(FPReg)
772 .addReg(SPReg)
[all...] |
| PPCAsmPrinter.cpp | 375 .addReg(ScratchReg)
379 .addReg(ScratchReg)
380 .addReg(ScratchReg)
384 .addReg(ScratchReg)
385 .addReg(ScratchReg)
389 .addReg(ScratchReg)
390 .addReg(ScratchReg)
396 .addReg(PPC::X2)
398 .addReg(PPC::X1));
408 .addReg(PPC::X2
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 86 .addReg(SPReg)
95 .addReg(SPReg)
96 .addReg(OffsetReg);
104 .addReg(OffsetReg)
105 .addReg(WebAssembly::SP32)
163 .addReg(WebAssembly::SP32)
164 .addReg(OffsetReg);
172 .addReg(OffsetReg)
173 .addReg(WebAssembly::SP32)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
139 .addReg(FramePtr);
154 .addReg(SP::G1).addImm(LOX10(Offset));
156 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
157 .addReg(FramePtr);
191 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
203 .addReg(FrameReg).addImm(0);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc));
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
|
| R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
62 .addReg(0) // PREDICATE_BIT
63 .addReg(DestReg, RegState::Define | RegState::Implicit);
72 .addReg(SrcReg, getKillRegState(KillSrc))
74 .addReg(0); // PREDICATE_BIT
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0)
[all...] |
| R600ISelLowering.cpp | 69 .addReg(AMDGPU::PRED_SEL_OFF);
80 .addReg(AMDGPU::PRED_SEL_OFF);
92 .addReg(AMDGPU::PRED_SEL_OFF);
103 .addReg(ConstantReg);
131 .addReg(AMDGPU::ALU_LITERAL_X)
132 .addReg(AMDGPU::PRED_SEL_OFF)
136 .addReg(ShiftValue)
137 .addReg(AMDGPU::PRED_SEL_OFF);
140 .addReg(NewAddr)
173 .addReg(t0, RegState::Implicit
[all...] |
| /external/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 65 addReg(Reg);
100 addReg(Reg.first);
132 LiveRegs.addReg(LI.PhysReg);
144 LiveRegs.addReg(*CSR);
158 addReg(*I);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 69 .addReg(MSP430::FP, RegState::Kill);
73 .addReg(MSP430::SP);
101 .addReg(MSP430::SP).addImm(NumBytes);
159 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
164 .addReg(MSP430::SP).addImm(CSSize);
173 .addReg(MSP430::SP).addImm(NumBytes);
202 .addReg(Reg, RegState::Kill);
251 .addReg(MSP430::SP).addImm(Amount);
260 .addReg(MSP430::SP).addImm(Amount);
278 MSP430::SP).addReg(MSP430::SP).addImm(CalleeAmt)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 70 .addReg(reg)
88 .addReg(FrameReg);
90 .addReg(reg)
|
