| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
426 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
552 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
554 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
556 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
558 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead))
[all...] |
| ARMBaseInstrInfo.h | 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
|
| MLxExpansionPass.cpp | 233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 409 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
411 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
413 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
415 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
542 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
544 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
546 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
548 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead))
[all...] |
| ARMBaseInstrInfo.h | 411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
|
| MLxExpansionPass.cpp | 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 131 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
209 RegState::Define | getDeadRegState(DstIsDead && CountThree))
233 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
383 RegState::Define | getDeadRegState(DstIsDead && SingleMovk))
399 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
556 getDeadRegState(DstIsDead && Shift == LastShift))
581 getDeadRegState(DstIsDead && Shift == LastShift))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 381 inline unsigned getDeadRegState(bool B) {
400 getDeadRegState(RegOp.isDead()) |
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 255 inline unsigned getDeadRegState(bool B) {
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| TargetInstrInfoImpl.cpp | 100 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 142 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 381 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
