1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the ARM-specific support for the FastISel class. Some 11 // of the target-specific code is generated by tablegen in the file 12 // ARMGenFastISel.inc, which is #included here. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMCallingConv.h" 19 #include "ARMRegisterInfo.h" 20 #include "ARMTargetMachine.h" 21 #include "ARMSubtarget.h" 22 #include "ARMConstantPoolValue.h" 23 #include "MCTargetDesc/ARMAddressingModes.h" 24 #include "llvm/CallingConv.h" 25 #include "llvm/DerivedTypes.h" 26 #include "llvm/GlobalVariable.h" 27 #include "llvm/Instructions.h" 28 #include "llvm/IntrinsicInst.h" 29 #include "llvm/Module.h" 30 #include "llvm/Operator.h" 31 #include "llvm/CodeGen/Analysis.h" 32 #include "llvm/CodeGen/FastISel.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/MachineInstrBuilder.h" 35 #include "llvm/CodeGen/MachineModuleInfo.h" 36 #include "llvm/CodeGen/MachineConstantPool.h" 37 #include "llvm/CodeGen/MachineFrameInfo.h" 38 #include "llvm/CodeGen/MachineMemOperand.h" 39 #include "llvm/CodeGen/MachineRegisterInfo.h" 40 #include "llvm/CodeGen/PseudoSourceValue.h" 41 #include "llvm/Support/CallSite.h" 42 #include "llvm/Support/CommandLine.h" 43 #include "llvm/Support/ErrorHandling.h" 44 #include "llvm/Support/GetElementPtrTypeIterator.h" 45 #include "llvm/Target/TargetData.h" 46 #include "llvm/Target/TargetInstrInfo.h" 47 #include "llvm/Target/TargetLowering.h" 48 #include "llvm/Target/TargetMachine.h" 49 #include "llvm/Target/TargetOptions.h" 50 using namespace llvm; 51 52 static cl::opt<bool> 53 DisableARMFastISel("disable-arm-fast-isel", 54 cl::desc("Turn off experimental ARM fast-isel support"), 55 cl::init(false), cl::Hidden); 56 57 extern cl::opt<bool> EnableARMLongCalls; 58 59 namespace { 60 61 // All possible address modes, plus some. 62 typedef struct Address { 63 enum { 64 RegBase, 65 FrameIndexBase 66 } BaseType; 67 68 union { 69 unsigned Reg; 70 int FI; 71 } Base; 72 73 int Offset; 74 75 // Innocuous defaults for our address. 76 Address() 77 : BaseType(RegBase), Offset(0) { 78 Base.Reg = 0; 79 } 80 } Address; 81 82 class ARMFastISel : public FastISel { 83 84 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 85 /// make the right decision when generating code for different targets. 86 const ARMSubtarget *Subtarget; 87 const TargetMachine &TM; 88 const TargetInstrInfo &TII; 89 const TargetLowering &TLI; 90 ARMFunctionInfo *AFI; 91 92 // Convenience variables to avoid some queries. 93 bool isThumb; 94 LLVMContext *Context; 95 96 public: 97 explicit ARMFastISel(FunctionLoweringInfo &funcInfo) 98 : FastISel(funcInfo), 99 TM(funcInfo.MF->getTarget()), 100 TII(*TM.getInstrInfo()), 101 TLI(*TM.getTargetLowering()) { 102 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 103 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); 104 isThumb = AFI->isThumbFunction(); 105 Context = &funcInfo.Fn->getContext(); 106 } 107 108 // Code from FastISel.cpp. 109 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode, 110 const TargetRegisterClass *RC); 111 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode, 112 const TargetRegisterClass *RC, 113 unsigned Op0, bool Op0IsKill); 114 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 115 const TargetRegisterClass *RC, 116 unsigned Op0, bool Op0IsKill, 117 unsigned Op1, bool Op1IsKill); 118 virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, 119 const TargetRegisterClass *RC, 120 unsigned Op0, bool Op0IsKill, 121 unsigned Op1, bool Op1IsKill, 122 unsigned Op2, bool Op2IsKill); 123 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 124 const TargetRegisterClass *RC, 125 unsigned Op0, bool Op0IsKill, 126 uint64_t Imm); 127 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 128 const TargetRegisterClass *RC, 129 unsigned Op0, bool Op0IsKill, 130 const ConstantFP *FPImm); 131 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 132 const TargetRegisterClass *RC, 133 unsigned Op0, bool Op0IsKill, 134 unsigned Op1, bool Op1IsKill, 135 uint64_t Imm); 136 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode, 137 const TargetRegisterClass *RC, 138 uint64_t Imm); 139 virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode, 140 const TargetRegisterClass *RC, 141 uint64_t Imm1, uint64_t Imm2); 142 143 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT, 144 unsigned Op0, bool Op0IsKill, 145 uint32_t Idx); 146 147 // Backend specific FastISel code. 148 virtual bool TargetSelectInstruction(const Instruction *I); 149 virtual unsigned TargetMaterializeConstant(const Constant *C); 150 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI); 151 152 #include "ARMGenFastISel.inc" 153 154 // Instruction selection routines. 155 private: 156 bool SelectLoad(const Instruction *I); 157 bool SelectStore(const Instruction *I); 158 bool SelectBranch(const Instruction *I); 159 bool SelectCmp(const Instruction *I); 160 bool SelectFPExt(const Instruction *I); 161 bool SelectFPTrunc(const Instruction *I); 162 bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode); 163 bool SelectSIToFP(const Instruction *I); 164 bool SelectFPToSI(const Instruction *I); 165 bool SelectSDiv(const Instruction *I); 166 bool SelectSRem(const Instruction *I); 167 bool SelectCall(const Instruction *I); 168 bool SelectSelect(const Instruction *I); 169 bool SelectRet(const Instruction *I); 170 bool SelectIntCast(const Instruction *I); 171 172 // Utility routines. 173 private: 174 bool isTypeLegal(Type *Ty, MVT &VT); 175 bool isLoadTypeLegal(Type *Ty, MVT &VT); 176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr); 177 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr); 178 bool ARMComputeAddress(const Value *Obj, Address &Addr); 179 void ARMSimplifyAddress(Address &Addr, EVT VT); 180 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT); 181 unsigned ARMMaterializeInt(const Constant *C, EVT VT); 182 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT); 183 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg); 184 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg); 185 unsigned ARMSelectCallOp(const GlobalValue *GV); 186 187 // Call handling routines. 188 private: 189 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 190 unsigned &ResultReg); 191 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return); 192 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args, 193 SmallVectorImpl<unsigned> &ArgRegs, 194 SmallVectorImpl<MVT> &ArgVTs, 195 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 196 SmallVectorImpl<unsigned> &RegArgs, 197 CallingConv::ID CC, 198 unsigned &NumBytes); 199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 200 const Instruction *I, CallingConv::ID CC, 201 unsigned &NumBytes); 202 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call); 203 204 // OptionalDef handling routines. 205 private: 206 bool isARMNEONPred(const MachineInstr *MI); 207 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); 208 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 209 void AddLoadStoreOperands(EVT VT, Address &Addr, 210 const MachineInstrBuilder &MIB, 211 unsigned Flags); 212 }; 213 214 } // end anonymous namespace 215 216 #include "ARMGenCallingConv.inc" 217 218 // DefinesOptionalPredicate - This is different from DefinesPredicate in that 219 // we don't care about implicit defs here, just places we'll need to add a 220 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. 221 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { 222 const MCInstrDesc &MCID = MI->getDesc(); 223 if (!MCID.hasOptionalDef()) 224 return false; 225 226 // Look to see if our OptionalDef is defining CPSR or CCR. 227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 228 const MachineOperand &MO = MI->getOperand(i); 229 if (!MO.isReg() || !MO.isDef()) continue; 230 if (MO.getReg() == ARM::CPSR) 231 *CPSR = true; 232 } 233 return true; 234 } 235 236 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { 237 const MCInstrDesc &MCID = MI->getDesc(); 238 239 // If we're a thumb2 or not NEON function we were handled via isPredicable. 240 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON || 241 AFI->isThumb2Function()) 242 return false; 243 244 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) 245 if (MCID.OpInfo[i].isPredicate()) 246 return true; 247 248 return false; 249 } 250 251 // If the machine is predicable go ahead and add the predicate operands, if 252 // it needs default CC operands add those. 253 // TODO: If we want to support thumb1 then we'll need to deal with optional 254 // CPSR defs that need to be added before the remaining operands. See s_cc_out 255 // for descriptions why. 256 const MachineInstrBuilder & 257 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { 258 MachineInstr *MI = &*MIB; 259 260 // Do we use a predicate? or... 261 // Are we NEON in ARM mode and have a predicate operand? If so, I know 262 // we're not predicable but add it anyways. 263 if (TII.isPredicable(MI) || isARMNEONPred(MI)) 264 AddDefaultPred(MIB); 265 266 // Do we optionally set a predicate? Preds is size > 0 iff the predicate 267 // defines CPSR. All other OptionalDefines in ARM are the CCR register. 268 bool CPSR = false; 269 if (DefinesOptionalPredicate(MI, &CPSR)) { 270 if (CPSR) 271 AddDefaultT1CC(MIB); 272 else 273 AddDefaultCC(MIB); 274 } 275 return MIB; 276 } 277 278 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode, 279 const TargetRegisterClass* RC) { 280 unsigned ResultReg = createResultReg(RC); 281 const MCInstrDesc &II = TII.get(MachineInstOpcode); 282 283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); 284 return ResultReg; 285 } 286 287 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode, 288 const TargetRegisterClass *RC, 289 unsigned Op0, bool Op0IsKill) { 290 unsigned ResultReg = createResultReg(RC); 291 const MCInstrDesc &II = TII.get(MachineInstOpcode); 292 293 if (II.getNumDefs() >= 1) 294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 295 .addReg(Op0, Op0IsKill * RegState::Kill)); 296 else { 297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 298 .addReg(Op0, Op0IsKill * RegState::Kill)); 299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 300 TII.get(TargetOpcode::COPY), ResultReg) 301 .addReg(II.ImplicitDefs[0])); 302 } 303 return ResultReg; 304 } 305 306 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 307 const TargetRegisterClass *RC, 308 unsigned Op0, bool Op0IsKill, 309 unsigned Op1, bool Op1IsKill) { 310 unsigned ResultReg = createResultReg(RC); 311 const MCInstrDesc &II = TII.get(MachineInstOpcode); 312 313 if (II.getNumDefs() >= 1) 314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 315 .addReg(Op0, Op0IsKill * RegState::Kill) 316 .addReg(Op1, Op1IsKill * RegState::Kill)); 317 else { 318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 319 .addReg(Op0, Op0IsKill * RegState::Kill) 320 .addReg(Op1, Op1IsKill * RegState::Kill)); 321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 322 TII.get(TargetOpcode::COPY), ResultReg) 323 .addReg(II.ImplicitDefs[0])); 324 } 325 return ResultReg; 326 } 327 328 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, 329 const TargetRegisterClass *RC, 330 unsigned Op0, bool Op0IsKill, 331 unsigned Op1, bool Op1IsKill, 332 unsigned Op2, bool Op2IsKill) { 333 unsigned ResultReg = createResultReg(RC); 334 const MCInstrDesc &II = TII.get(MachineInstOpcode); 335 336 if (II.getNumDefs() >= 1) 337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 338 .addReg(Op0, Op0IsKill * RegState::Kill) 339 .addReg(Op1, Op1IsKill * RegState::Kill) 340 .addReg(Op2, Op2IsKill * RegState::Kill)); 341 else { 342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 343 .addReg(Op0, Op0IsKill * RegState::Kill) 344 .addReg(Op1, Op1IsKill * RegState::Kill) 345 .addReg(Op2, Op2IsKill * RegState::Kill)); 346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 347 TII.get(TargetOpcode::COPY), ResultReg) 348 .addReg(II.ImplicitDefs[0])); 349 } 350 return ResultReg; 351 } 352 353 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 354 const TargetRegisterClass *RC, 355 unsigned Op0, bool Op0IsKill, 356 uint64_t Imm) { 357 unsigned ResultReg = createResultReg(RC); 358 const MCInstrDesc &II = TII.get(MachineInstOpcode); 359 360 if (II.getNumDefs() >= 1) 361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 362 .addReg(Op0, Op0IsKill * RegState::Kill) 363 .addImm(Imm)); 364 else { 365 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 366 .addReg(Op0, Op0IsKill * RegState::Kill) 367 .addImm(Imm)); 368 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 369 TII.get(TargetOpcode::COPY), ResultReg) 370 .addReg(II.ImplicitDefs[0])); 371 } 372 return ResultReg; 373 } 374 375 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 376 const TargetRegisterClass *RC, 377 unsigned Op0, bool Op0IsKill, 378 const ConstantFP *FPImm) { 379 unsigned ResultReg = createResultReg(RC); 380 const MCInstrDesc &II = TII.get(MachineInstOpcode); 381 382 if (II.getNumDefs() >= 1) 383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 384 .addReg(Op0, Op0IsKill * RegState::Kill) 385 .addFPImm(FPImm)); 386 else { 387 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 388 .addReg(Op0, Op0IsKill * RegState::Kill) 389 .addFPImm(FPImm)); 390 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 391 TII.get(TargetOpcode::COPY), ResultReg) 392 .addReg(II.ImplicitDefs[0])); 393 } 394 return ResultReg; 395 } 396 397 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 398 const TargetRegisterClass *RC, 399 unsigned Op0, bool Op0IsKill, 400 unsigned Op1, bool Op1IsKill, 401 uint64_t Imm) { 402 unsigned ResultReg = createResultReg(RC); 403 const MCInstrDesc &II = TII.get(MachineInstOpcode); 404 405 if (II.getNumDefs() >= 1) 406 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 407 .addReg(Op0, Op0IsKill * RegState::Kill) 408 .addReg(Op1, Op1IsKill * RegState::Kill) 409 .addImm(Imm)); 410 else { 411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 412 .addReg(Op0, Op0IsKill * RegState::Kill) 413 .addReg(Op1, Op1IsKill * RegState::Kill) 414 .addImm(Imm)); 415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 416 TII.get(TargetOpcode::COPY), ResultReg) 417 .addReg(II.ImplicitDefs[0])); 418 } 419 return ResultReg; 420 } 421 422 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode, 423 const TargetRegisterClass *RC, 424 uint64_t Imm) { 425 unsigned ResultReg = createResultReg(RC); 426 const MCInstrDesc &II = TII.get(MachineInstOpcode); 427 428 if (II.getNumDefs() >= 1) 429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 430 .addImm(Imm)); 431 else { 432 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 433 .addImm(Imm)); 434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 435 TII.get(TargetOpcode::COPY), ResultReg) 436 .addReg(II.ImplicitDefs[0])); 437 } 438 return ResultReg; 439 } 440 441 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode, 442 const TargetRegisterClass *RC, 443 uint64_t Imm1, uint64_t Imm2) { 444 unsigned ResultReg = createResultReg(RC); 445 const MCInstrDesc &II = TII.get(MachineInstOpcode); 446 447 if (II.getNumDefs() >= 1) 448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 449 .addImm(Imm1).addImm(Imm2)); 450 else { 451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 452 .addImm(Imm1).addImm(Imm2)); 453 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 454 TII.get(TargetOpcode::COPY), 455 ResultReg) 456 .addReg(II.ImplicitDefs[0])); 457 } 458 return ResultReg; 459 } 460 461 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT, 462 unsigned Op0, bool Op0IsKill, 463 uint32_t Idx) { 464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 465 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 466 "Cannot yet extract from physregs"); 467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 468 DL, TII.get(TargetOpcode::COPY), ResultReg) 469 .addReg(Op0, getKillRegState(Op0IsKill), Idx)); 470 return ResultReg; 471 } 472 473 // TODO: Don't worry about 64-bit now, but when this is fixed remove the 474 // checks from the various callers. 475 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { 476 if (VT == MVT::f64) return 0; 477 478 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 479 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 480 TII.get(ARM::VMOVRS), MoveReg) 481 .addReg(SrcReg)); 482 return MoveReg; 483 } 484 485 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { 486 if (VT == MVT::i64) return 0; 487 488 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 489 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 490 TII.get(ARM::VMOVSR), MoveReg) 491 .addReg(SrcReg)); 492 return MoveReg; 493 } 494 495 // For double width floating point we need to materialize two constants 496 // (the high and the low) into integer registers then use a move to get 497 // the combined constant into an FP reg. 498 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) { 499 const APFloat Val = CFP->getValueAPF(); 500 bool is64bit = VT == MVT::f64; 501 502 // This checks to see if we can use VFP3 instructions to materialize 503 // a constant, otherwise we have to go through the constant pool. 504 if (TLI.isFPImmLegal(Val, VT)) { 505 int Imm; 506 unsigned Opc; 507 if (is64bit) { 508 Imm = ARM_AM::getFP64Imm(Val); 509 Opc = ARM::FCONSTD; 510 } else { 511 Imm = ARM_AM::getFP32Imm(Val); 512 Opc = ARM::FCONSTS; 513 } 514 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 515 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 516 DestReg) 517 .addImm(Imm)); 518 return DestReg; 519 } 520 521 // Require VFP2 for loading fp constants. 522 if (!Subtarget->hasVFP2()) return false; 523 524 // MachineConstantPool wants an explicit alignment. 525 unsigned Align = TD.getPrefTypeAlignment(CFP->getType()); 526 if (Align == 0) { 527 // TODO: Figure out if this is correct. 528 Align = TD.getTypeAllocSize(CFP->getType()); 529 } 530 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); 531 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 532 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; 533 534 // The extra reg is for addrmode5. 535 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 536 DestReg) 537 .addConstantPoolIndex(Idx) 538 .addReg(0)); 539 return DestReg; 540 } 541 542 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { 543 544 // For now 32-bit only. 545 if (VT != MVT::i32) return false; 546 547 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 548 549 // If we can do this in a single instruction without a constant pool entry 550 // do so now. 551 const ConstantInt *CI = cast<ConstantInt>(C); 552 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) { 553 unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16; 554 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 555 TII.get(Opc), DestReg) 556 .addImm(CI->getSExtValue())); 557 return DestReg; 558 } 559 560 // MachineConstantPool wants an explicit alignment. 561 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 562 if (Align == 0) { 563 // TODO: Figure out if this is correct. 564 Align = TD.getTypeAllocSize(C->getType()); 565 } 566 unsigned Idx = MCP.getConstantPoolIndex(C, Align); 567 568 if (isThumb) 569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 570 TII.get(ARM::t2LDRpci), DestReg) 571 .addConstantPoolIndex(Idx)); 572 else 573 // The extra immediate is for addrmode2. 574 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 575 TII.get(ARM::LDRcp), DestReg) 576 .addConstantPoolIndex(Idx) 577 .addImm(0)); 578 579 return DestReg; 580 } 581 582 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) { 583 // For now 32-bit only. 584 if (VT != MVT::i32) return 0; 585 586 Reloc::Model RelocM = TM.getRelocationModel(); 587 588 // TODO: Need more magic for ARM PIC. 589 if (!isThumb && (RelocM == Reloc::PIC_)) return 0; 590 591 // MachineConstantPool wants an explicit alignment. 592 unsigned Align = TD.getPrefTypeAlignment(GV->getType()); 593 if (Align == 0) { 594 // TODO: Figure out if this is correct. 595 Align = TD.getTypeAllocSize(GV->getType()); 596 } 597 598 // Grab index. 599 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8); 600 unsigned Id = AFI->createPICLabelUId(); 601 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id, 602 ARMCP::CPValue, 603 PCAdj); 604 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align); 605 606 // Load value. 607 MachineInstrBuilder MIB; 608 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 609 if (isThumb) { 610 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; 611 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 612 .addConstantPoolIndex(Idx); 613 if (RelocM == Reloc::PIC_) 614 MIB.addImm(Id); 615 } else { 616 // The extra immediate is for addrmode2. 617 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), 618 DestReg) 619 .addConstantPoolIndex(Idx) 620 .addImm(0); 621 } 622 AddOptionalDefs(MIB); 623 624 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) { 625 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 626 if (isThumb) 627 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 628 TII.get(ARM::t2LDRi12), NewDestReg) 629 .addReg(DestReg) 630 .addImm(0); 631 else 632 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12), 633 NewDestReg) 634 .addReg(DestReg) 635 .addImm(0); 636 DestReg = NewDestReg; 637 AddOptionalDefs(MIB); 638 } 639 640 return DestReg; 641 } 642 643 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { 644 EVT VT = TLI.getValueType(C->getType(), true); 645 646 // Only handle simple types. 647 if (!VT.isSimple()) return 0; 648 649 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 650 return ARMMaterializeFP(CFP, VT); 651 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 652 return ARMMaterializeGV(GV, VT); 653 else if (isa<ConstantInt>(C)) 654 return ARMMaterializeInt(C, VT); 655 656 return 0; 657 } 658 659 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { 660 // Don't handle dynamic allocas. 661 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; 662 663 MVT VT; 664 if (!isLoadTypeLegal(AI->getType(), VT)) return false; 665 666 DenseMap<const AllocaInst*, int>::iterator SI = 667 FuncInfo.StaticAllocaMap.find(AI); 668 669 // This will get lowered later into the correct offsets and registers 670 // via rewriteXFrameIndex. 671 if (SI != FuncInfo.StaticAllocaMap.end()) { 672 TargetRegisterClass* RC = TLI.getRegClassFor(VT); 673 unsigned ResultReg = createResultReg(RC); 674 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 675 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL, 676 TII.get(Opc), ResultReg) 677 .addFrameIndex(SI->second) 678 .addImm(0)); 679 return ResultReg; 680 } 681 682 return 0; 683 } 684 685 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { 686 EVT evt = TLI.getValueType(Ty, true); 687 688 // Only handle simple types. 689 if (evt == MVT::Other || !evt.isSimple()) return false; 690 VT = evt.getSimpleVT(); 691 692 // Handle all legal types, i.e. a register that will directly hold this 693 // value. 694 return TLI.isTypeLegal(VT); 695 } 696 697 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { 698 if (isTypeLegal(Ty, VT)) return true; 699 700 // If this is a type than can be sign or zero-extended to a basic operation 701 // go ahead and accept it now. 702 if (VT == MVT::i8 || VT == MVT::i16) 703 return true; 704 705 return false; 706 } 707 708 // Computes the address to get to an object. 709 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) { 710 // Some boilerplate from the X86 FastISel. 711 const User *U = NULL; 712 unsigned Opcode = Instruction::UserOp1; 713 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 714 // Don't walk into other basic blocks unless the object is an alloca from 715 // another block, otherwise it may not have a virtual register assigned. 716 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) || 717 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 718 Opcode = I->getOpcode(); 719 U = I; 720 } 721 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 722 Opcode = C->getOpcode(); 723 U = C; 724 } 725 726 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType())) 727 if (Ty->getAddressSpace() > 255) 728 // Fast instruction selection doesn't support the special 729 // address spaces. 730 return false; 731 732 switch (Opcode) { 733 default: 734 break; 735 case Instruction::BitCast: { 736 // Look through bitcasts. 737 return ARMComputeAddress(U->getOperand(0), Addr); 738 } 739 case Instruction::IntToPtr: { 740 // Look past no-op inttoptrs. 741 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 742 return ARMComputeAddress(U->getOperand(0), Addr); 743 break; 744 } 745 case Instruction::PtrToInt: { 746 // Look past no-op ptrtoints. 747 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 748 return ARMComputeAddress(U->getOperand(0), Addr); 749 break; 750 } 751 case Instruction::GetElementPtr: { 752 Address SavedAddr = Addr; 753 int TmpOffset = Addr.Offset; 754 755 // Iterate through the GEP folding the constants into offsets where 756 // we can. 757 gep_type_iterator GTI = gep_type_begin(U); 758 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 759 i != e; ++i, ++GTI) { 760 const Value *Op = *i; 761 if (StructType *STy = dyn_cast<StructType>(*GTI)) { 762 const StructLayout *SL = TD.getStructLayout(STy); 763 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 764 TmpOffset += SL->getElementOffset(Idx); 765 } else { 766 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 767 for (;;) { 768 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 769 // Constant-offset addressing. 770 TmpOffset += CI->getSExtValue() * S; 771 break; 772 } 773 if (isa<AddOperator>(Op) && 774 (!isa<Instruction>(Op) || 775 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()] 776 == FuncInfo.MBB) && 777 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) { 778 // An add (in the same block) with a constant operand. Fold the 779 // constant. 780 ConstantInt *CI = 781 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 782 TmpOffset += CI->getSExtValue() * S; 783 // Iterate on the other operand. 784 Op = cast<AddOperator>(Op)->getOperand(0); 785 continue; 786 } 787 // Unsupported 788 goto unsupported_gep; 789 } 790 } 791 } 792 793 // Try to grab the base operand now. 794 Addr.Offset = TmpOffset; 795 if (ARMComputeAddress(U->getOperand(0), Addr)) return true; 796 797 // We failed, restore everything and try the other options. 798 Addr = SavedAddr; 799 800 unsupported_gep: 801 break; 802 } 803 case Instruction::Alloca: { 804 const AllocaInst *AI = cast<AllocaInst>(Obj); 805 DenseMap<const AllocaInst*, int>::iterator SI = 806 FuncInfo.StaticAllocaMap.find(AI); 807 if (SI != FuncInfo.StaticAllocaMap.end()) { 808 Addr.BaseType = Address::FrameIndexBase; 809 Addr.Base.FI = SI->second; 810 return true; 811 } 812 break; 813 } 814 } 815 816 // Materialize the global variable's address into a reg which can 817 // then be used later to load the variable. 818 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) { 819 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType())); 820 if (Tmp == 0) return false; 821 822 Addr.Base.Reg = Tmp; 823 return true; 824 } 825 826 // Try to get this in a register if nothing else has worked. 827 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj); 828 return Addr.Base.Reg != 0; 829 } 830 831 void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) { 832 833 assert(VT.isSimple() && "Non-simple types are invalid here!"); 834 835 bool needsLowering = false; 836 switch (VT.getSimpleVT().SimpleTy) { 837 default: 838 assert(false && "Unhandled load/store type!"); 839 case MVT::i1: 840 case MVT::i8: 841 case MVT::i16: 842 case MVT::i32: 843 // Integer loads/stores handle 12-bit offsets. 844 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset); 845 break; 846 case MVT::f32: 847 case MVT::f64: 848 // Floating point operands handle 8-bit offsets. 849 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset); 850 break; 851 } 852 853 // If this is a stack pointer and the offset needs to be simplified then 854 // put the alloca address into a register, set the base type back to 855 // register and continue. This should almost never happen. 856 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) { 857 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass : 858 ARM::GPRRegisterClass; 859 unsigned ResultReg = createResultReg(RC); 860 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 861 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL, 862 TII.get(Opc), ResultReg) 863 .addFrameIndex(Addr.Base.FI) 864 .addImm(0)); 865 Addr.Base.Reg = ResultReg; 866 Addr.BaseType = Address::RegBase; 867 } 868 869 // Since the offset is too large for the load/store instruction 870 // get the reg+offset into a register. 871 if (needsLowering) { 872 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, 873 /*Op0IsKill*/false, Addr.Offset, MVT::i32); 874 Addr.Offset = 0; 875 } 876 } 877 878 void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr, 879 const MachineInstrBuilder &MIB, 880 unsigned Flags) { 881 // addrmode5 output depends on the selection dag addressing dividing the 882 // offset by 4 that it then later multiplies. Do this here as well. 883 if (VT.getSimpleVT().SimpleTy == MVT::f32 || 884 VT.getSimpleVT().SimpleTy == MVT::f64) 885 Addr.Offset /= 4; 886 887 // Frame base works a bit differently. Handle it separately. 888 if (Addr.BaseType == Address::FrameIndexBase) { 889 int FI = Addr.Base.FI; 890 int Offset = Addr.Offset; 891 MachineMemOperand *MMO = 892 FuncInfo.MF->getMachineMemOperand( 893 MachinePointerInfo::getFixedStack(FI, Offset), 894 Flags, 895 MFI.getObjectSize(FI), 896 MFI.getObjectAlignment(FI)); 897 // Now add the rest of the operands. 898 MIB.addFrameIndex(FI); 899 900 // ARM halfword load/stores need an additional operand. 901 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); 902 903 MIB.addImm(Addr.Offset); 904 MIB.addMemOperand(MMO); 905 } else { 906 // Now add the rest of the operands. 907 MIB.addReg(Addr.Base.Reg); 908 909 // ARM halfword load/stores need an additional operand. 910 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); 911 912 MIB.addImm(Addr.Offset); 913 } 914 AddOptionalDefs(MIB); 915 } 916 917 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) { 918 919 assert(VT.isSimple() && "Non-simple types are invalid here!"); 920 unsigned Opc; 921 TargetRegisterClass *RC; 922 switch (VT.getSimpleVT().SimpleTy) { 923 // This is mostly going to be Neon/vector support. 924 default: return false; 925 case MVT::i16: 926 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH; 927 RC = ARM::GPRRegisterClass; 928 break; 929 case MVT::i8: 930 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12; 931 RC = ARM::GPRRegisterClass; 932 break; 933 case MVT::i32: 934 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12; 935 RC = ARM::GPRRegisterClass; 936 break; 937 case MVT::f32: 938 Opc = ARM::VLDRS; 939 RC = TLI.getRegClassFor(VT); 940 break; 941 case MVT::f64: 942 Opc = ARM::VLDRD; 943 RC = TLI.getRegClassFor(VT); 944 break; 945 } 946 // Simplify this down to something we can handle. 947 ARMSimplifyAddress(Addr, VT); 948 949 // Create the base instruction, then add the operands. 950 ResultReg = createResultReg(RC); 951 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 952 TII.get(Opc), ResultReg); 953 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad); 954 return true; 955 } 956 957 bool ARMFastISel::SelectLoad(const Instruction *I) { 958 // Atomic loads need special handling. 959 if (cast<LoadInst>(I)->isAtomic()) 960 return false; 961 962 // Verify we have a legal type before going any further. 963 MVT VT; 964 if (!isLoadTypeLegal(I->getType(), VT)) 965 return false; 966 967 // See if we can handle this address. 968 Address Addr; 969 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false; 970 971 unsigned ResultReg; 972 if (!ARMEmitLoad(VT, ResultReg, Addr)) return false; 973 UpdateValueMap(I, ResultReg); 974 return true; 975 } 976 977 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) { 978 unsigned StrOpc; 979 switch (VT.getSimpleVT().SimpleTy) { 980 // This is mostly going to be Neon/vector support. 981 default: return false; 982 case MVT::i1: { 983 unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass : 984 ARM::GPRRegisterClass); 985 unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; 986 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 987 TII.get(Opc), Res) 988 .addReg(SrcReg).addImm(1)); 989 SrcReg = Res; 990 } // Fallthrough here. 991 case MVT::i8: 992 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12; 993 break; 994 case MVT::i16: 995 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH; 996 break; 997 case MVT::i32: 998 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12; 999 break; 1000 case MVT::f32: 1001 if (!Subtarget->hasVFP2()) return false; 1002 StrOpc = ARM::VSTRS; 1003 break; 1004 case MVT::f64: 1005 if (!Subtarget->hasVFP2()) return false; 1006 StrOpc = ARM::VSTRD; 1007 break; 1008 } 1009 // Simplify this down to something we can handle. 1010 ARMSimplifyAddress(Addr, VT); 1011 1012 // Create the base instruction, then add the operands. 1013 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1014 TII.get(StrOpc)) 1015 .addReg(SrcReg, getKillRegState(true)); 1016 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore); 1017 return true; 1018 } 1019 1020 bool ARMFastISel::SelectStore(const Instruction *I) { 1021 Value *Op0 = I->getOperand(0); 1022 unsigned SrcReg = 0; 1023 1024 // Atomic stores need special handling. 1025 if (cast<StoreInst>(I)->isAtomic()) 1026 return false; 1027 1028 // Verify we have a legal type before going any further. 1029 MVT VT; 1030 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) 1031 return false; 1032 1033 // Get the value to be stored into a register. 1034 SrcReg = getRegForValue(Op0); 1035 if (SrcReg == 0) return false; 1036 1037 // See if we can handle this address. 1038 Address Addr; 1039 if (!ARMComputeAddress(I->getOperand(1), Addr)) 1040 return false; 1041 1042 if (!ARMEmitStore(VT, SrcReg, Addr)) return false; 1043 return true; 1044 } 1045 1046 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) { 1047 switch (Pred) { 1048 // Needs two compares... 1049 case CmpInst::FCMP_ONE: 1050 case CmpInst::FCMP_UEQ: 1051 default: 1052 // AL is our "false" for now. The other two need more compares. 1053 return ARMCC::AL; 1054 case CmpInst::ICMP_EQ: 1055 case CmpInst::FCMP_OEQ: 1056 return ARMCC::EQ; 1057 case CmpInst::ICMP_SGT: 1058 case CmpInst::FCMP_OGT: 1059 return ARMCC::GT; 1060 case CmpInst::ICMP_SGE: 1061 case CmpInst::FCMP_OGE: 1062 return ARMCC::GE; 1063 case CmpInst::ICMP_UGT: 1064 case CmpInst::FCMP_UGT: 1065 return ARMCC::HI; 1066 case CmpInst::FCMP_OLT: 1067 return ARMCC::MI; 1068 case CmpInst::ICMP_ULE: 1069 case CmpInst::FCMP_OLE: 1070 return ARMCC::LS; 1071 case CmpInst::FCMP_ORD: 1072 return ARMCC::VC; 1073 case CmpInst::FCMP_UNO: 1074 return ARMCC::VS; 1075 case CmpInst::FCMP_UGE: 1076 return ARMCC::PL; 1077 case CmpInst::ICMP_SLT: 1078 case CmpInst::FCMP_ULT: 1079 return ARMCC::LT; 1080 case CmpInst::ICMP_SLE: 1081 case CmpInst::FCMP_ULE: 1082 return ARMCC::LE; 1083 case CmpInst::FCMP_UNE: 1084 case CmpInst::ICMP_NE: 1085 return ARMCC::NE; 1086 case CmpInst::ICMP_UGE: 1087 return ARMCC::HS; 1088 case CmpInst::ICMP_ULT: 1089 return ARMCC::LO; 1090 } 1091 } 1092 1093 bool ARMFastISel::SelectBranch(const Instruction *I) { 1094 const BranchInst *BI = cast<BranchInst>(I); 1095 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 1096 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 1097 1098 // Simple branch support. 1099 1100 // If we can, avoid recomputing the compare - redoing it could lead to wonky 1101 // behavior. 1102 // TODO: Factor this out. 1103 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 1104 MVT SourceVT; 1105 Type *Ty = CI->getOperand(0)->getType(); 1106 if (CI->hasOneUse() && (CI->getParent() == I->getParent()) 1107 && isTypeLegal(Ty, SourceVT)) { 1108 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); 1109 if (isFloat && !Subtarget->hasVFP2()) 1110 return false; 1111 1112 unsigned CmpOpc; 1113 switch (SourceVT.SimpleTy) { 1114 default: return false; 1115 // TODO: Verify compares. 1116 case MVT::f32: 1117 CmpOpc = ARM::VCMPES; 1118 break; 1119 case MVT::f64: 1120 CmpOpc = ARM::VCMPED; 1121 break; 1122 case MVT::i32: 1123 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; 1124 break; 1125 } 1126 1127 // Get the compare predicate. 1128 // Try to take advantage of fallthrough opportunities. 1129 CmpInst::Predicate Predicate = CI->getPredicate(); 1130 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1131 std::swap(TBB, FBB); 1132 Predicate = CmpInst::getInversePredicate(Predicate); 1133 } 1134 1135 ARMCC::CondCodes ARMPred = getComparePred(Predicate); 1136 1137 // We may not handle every CC for now. 1138 if (ARMPred == ARMCC::AL) return false; 1139 1140 unsigned Arg1 = getRegForValue(CI->getOperand(0)); 1141 if (Arg1 == 0) return false; 1142 1143 unsigned Arg2 = getRegForValue(CI->getOperand(1)); 1144 if (Arg2 == 0) return false; 1145 1146 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1147 TII.get(CmpOpc)) 1148 .addReg(Arg1).addReg(Arg2)); 1149 1150 // For floating point we need to move the result to a comparison register 1151 // that we can then use for branches. 1152 if (isFloat) 1153 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1154 TII.get(ARM::FMSTAT))); 1155 1156 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; 1157 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 1158 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); 1159 FastEmitBranch(FBB, DL); 1160 FuncInfo.MBB->addSuccessor(TBB); 1161 return true; 1162 } 1163 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { 1164 MVT SourceVT; 1165 if (TI->hasOneUse() && TI->getParent() == I->getParent() && 1166 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) { 1167 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; 1168 unsigned OpReg = getRegForValue(TI->getOperand(0)); 1169 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1170 TII.get(TstOpc)) 1171 .addReg(OpReg).addImm(1)); 1172 1173 unsigned CCMode = ARMCC::NE; 1174 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1175 std::swap(TBB, FBB); 1176 CCMode = ARMCC::EQ; 1177 } 1178 1179 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; 1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 1181 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1182 1183 FastEmitBranch(FBB, DL); 1184 FuncInfo.MBB->addSuccessor(TBB); 1185 return true; 1186 } 1187 } 1188 1189 unsigned CmpReg = getRegForValue(BI->getCondition()); 1190 if (CmpReg == 0) return false; 1191 1192 // We've been divorced from our compare! Our block was split, and 1193 // now our compare lives in a predecessor block. We musn't 1194 // re-compare here, as the children of the compare aren't guaranteed 1195 // live across the block boundary (we *could* check for this). 1196 // Regardless, the compare has been done in the predecessor block, 1197 // and it left a value for us in a virtual register. Ergo, we test 1198 // the one-bit value left in the virtual register. 1199 unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; 1200 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc)) 1201 .addReg(CmpReg).addImm(1)); 1202 1203 unsigned CCMode = ARMCC::NE; 1204 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1205 std::swap(TBB, FBB); 1206 CCMode = ARMCC::EQ; 1207 } 1208 1209 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; 1210 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 1211 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1212 FastEmitBranch(FBB, DL); 1213 FuncInfo.MBB->addSuccessor(TBB); 1214 return true; 1215 } 1216 1217 bool ARMFastISel::SelectCmp(const Instruction *I) { 1218 const CmpInst *CI = cast<CmpInst>(I); 1219 1220 MVT VT; 1221 Type *Ty = CI->getOperand(0)->getType(); 1222 if (!isTypeLegal(Ty, VT)) 1223 return false; 1224 1225 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); 1226 if (isFloat && !Subtarget->hasVFP2()) 1227 return false; 1228 1229 unsigned CmpOpc; 1230 unsigned CondReg; 1231 switch (VT.SimpleTy) { 1232 default: return false; 1233 // TODO: Verify compares. 1234 case MVT::f32: 1235 CmpOpc = ARM::VCMPES; 1236 CondReg = ARM::FPSCR; 1237 break; 1238 case MVT::f64: 1239 CmpOpc = ARM::VCMPED; 1240 CondReg = ARM::FPSCR; 1241 break; 1242 case MVT::i32: 1243 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; 1244 CondReg = ARM::CPSR; 1245 break; 1246 } 1247 1248 // Get the compare predicate. 1249 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate()); 1250 1251 // We may not handle every CC for now. 1252 if (ARMPred == ARMCC::AL) return false; 1253 1254 unsigned Arg1 = getRegForValue(CI->getOperand(0)); 1255 if (Arg1 == 0) return false; 1256 1257 unsigned Arg2 = getRegForValue(CI->getOperand(1)); 1258 if (Arg2 == 0) return false; 1259 1260 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 1261 .addReg(Arg1).addReg(Arg2)); 1262 1263 // For floating point we need to move the result to a comparison register 1264 // that we can then use for branches. 1265 if (isFloat) 1266 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1267 TII.get(ARM::FMSTAT))); 1268 1269 // Now set a register based on the comparison. Explicitly set the predicates 1270 // here. 1271 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi; 1272 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass 1273 : ARM::GPRRegisterClass; 1274 unsigned DestReg = createResultReg(RC); 1275 Constant *Zero 1276 = ConstantInt::get(Type::getInt32Ty(*Context), 0); 1277 unsigned ZeroReg = TargetMaterializeConstant(Zero); 1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg) 1279 .addReg(ZeroReg).addImm(1) 1280 .addImm(ARMPred).addReg(CondReg); 1281 1282 UpdateValueMap(I, DestReg); 1283 return true; 1284 } 1285 1286 bool ARMFastISel::SelectFPExt(const Instruction *I) { 1287 // Make sure we have VFP and that we're extending float to double. 1288 if (!Subtarget->hasVFP2()) return false; 1289 1290 Value *V = I->getOperand(0); 1291 if (!I->getType()->isDoubleTy() || 1292 !V->getType()->isFloatTy()) return false; 1293 1294 unsigned Op = getRegForValue(V); 1295 if (Op == 0) return false; 1296 1297 unsigned Result = createResultReg(ARM::DPRRegisterClass); 1298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1299 TII.get(ARM::VCVTDS), Result) 1300 .addReg(Op)); 1301 UpdateValueMap(I, Result); 1302 return true; 1303 } 1304 1305 bool ARMFastISel::SelectFPTrunc(const Instruction *I) { 1306 // Make sure we have VFP and that we're truncating double to float. 1307 if (!Subtarget->hasVFP2()) return false; 1308 1309 Value *V = I->getOperand(0); 1310 if (!(I->getType()->isFloatTy() && 1311 V->getType()->isDoubleTy())) return false; 1312 1313 unsigned Op = getRegForValue(V); 1314 if (Op == 0) return false; 1315 1316 unsigned Result = createResultReg(ARM::SPRRegisterClass); 1317 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1318 TII.get(ARM::VCVTSD), Result) 1319 .addReg(Op)); 1320 UpdateValueMap(I, Result); 1321 return true; 1322 } 1323 1324 bool ARMFastISel::SelectSIToFP(const Instruction *I) { 1325 // Make sure we have VFP. 1326 if (!Subtarget->hasVFP2()) return false; 1327 1328 MVT DstVT; 1329 Type *Ty = I->getType(); 1330 if (!isTypeLegal(Ty, DstVT)) 1331 return false; 1332 1333 // FIXME: Handle sign-extension where necessary. 1334 if (!I->getOperand(0)->getType()->isIntegerTy(32)) 1335 return false; 1336 1337 unsigned Op = getRegForValue(I->getOperand(0)); 1338 if (Op == 0) return false; 1339 1340 // The conversion routine works on fp-reg to fp-reg and the operand above 1341 // was an integer, move it to the fp registers if possible. 1342 unsigned FP = ARMMoveToFPReg(MVT::f32, Op); 1343 if (FP == 0) return false; 1344 1345 unsigned Opc; 1346 if (Ty->isFloatTy()) Opc = ARM::VSITOS; 1347 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD; 1348 else return false; 1349 1350 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); 1351 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 1352 ResultReg) 1353 .addReg(FP)); 1354 UpdateValueMap(I, ResultReg); 1355 return true; 1356 } 1357 1358 bool ARMFastISel::SelectFPToSI(const Instruction *I) { 1359 // Make sure we have VFP. 1360 if (!Subtarget->hasVFP2()) return false; 1361 1362 MVT DstVT; 1363 Type *RetTy = I->getType(); 1364 if (!isTypeLegal(RetTy, DstVT)) 1365 return false; 1366 1367 unsigned Op = getRegForValue(I->getOperand(0)); 1368 if (Op == 0) return false; 1369 1370 unsigned Opc; 1371 Type *OpTy = I->getOperand(0)->getType(); 1372 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS; 1373 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD; 1374 else return false; 1375 1376 // f64->s32 or f32->s32 both need an intermediate f32 reg. 1377 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); 1378 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 1379 ResultReg) 1380 .addReg(Op)); 1381 1382 // This result needs to be in an integer register, but the conversion only 1383 // takes place in fp-regs. 1384 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); 1385 if (IntReg == 0) return false; 1386 1387 UpdateValueMap(I, IntReg); 1388 return true; 1389 } 1390 1391 bool ARMFastISel::SelectSelect(const Instruction *I) { 1392 MVT VT; 1393 if (!isTypeLegal(I->getType(), VT)) 1394 return false; 1395 1396 // Things need to be register sized for register moves. 1397 if (VT != MVT::i32) return false; 1398 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 1399 1400 unsigned CondReg = getRegForValue(I->getOperand(0)); 1401 if (CondReg == 0) return false; 1402 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1403 if (Op1Reg == 0) return false; 1404 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1405 if (Op2Reg == 0) return false; 1406 1407 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri; 1408 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 1409 .addReg(CondReg).addImm(1)); 1410 unsigned ResultReg = createResultReg(RC); 1411 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr; 1412 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg) 1413 .addReg(Op1Reg).addReg(Op2Reg) 1414 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 1415 UpdateValueMap(I, ResultReg); 1416 return true; 1417 } 1418 1419 bool ARMFastISel::SelectSDiv(const Instruction *I) { 1420 MVT VT; 1421 Type *Ty = I->getType(); 1422 if (!isTypeLegal(Ty, VT)) 1423 return false; 1424 1425 // If we have integer div support we should have selected this automagically. 1426 // In case we have a real miss go ahead and return false and we'll pick 1427 // it up later. 1428 if (Subtarget->hasDivide()) return false; 1429 1430 // Otherwise emit a libcall. 1431 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1432 if (VT == MVT::i8) 1433 LC = RTLIB::SDIV_I8; 1434 else if (VT == MVT::i16) 1435 LC = RTLIB::SDIV_I16; 1436 else if (VT == MVT::i32) 1437 LC = RTLIB::SDIV_I32; 1438 else if (VT == MVT::i64) 1439 LC = RTLIB::SDIV_I64; 1440 else if (VT == MVT::i128) 1441 LC = RTLIB::SDIV_I128; 1442 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1443 1444 return ARMEmitLibcall(I, LC); 1445 } 1446 1447 bool ARMFastISel::SelectSRem(const Instruction *I) { 1448 MVT VT; 1449 Type *Ty = I->getType(); 1450 if (!isTypeLegal(Ty, VT)) 1451 return false; 1452 1453 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1454 if (VT == MVT::i8) 1455 LC = RTLIB::SREM_I8; 1456 else if (VT == MVT::i16) 1457 LC = RTLIB::SREM_I16; 1458 else if (VT == MVT::i32) 1459 LC = RTLIB::SREM_I32; 1460 else if (VT == MVT::i64) 1461 LC = RTLIB::SREM_I64; 1462 else if (VT == MVT::i128) 1463 LC = RTLIB::SREM_I128; 1464 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1465 1466 return ARMEmitLibcall(I, LC); 1467 } 1468 1469 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { 1470 EVT VT = TLI.getValueType(I->getType(), true); 1471 1472 // We can get here in the case when we want to use NEON for our fp 1473 // operations, but can't figure out how to. Just use the vfp instructions 1474 // if we have them. 1475 // FIXME: It'd be nice to use NEON instructions. 1476 Type *Ty = I->getType(); 1477 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); 1478 if (isFloat && !Subtarget->hasVFP2()) 1479 return false; 1480 1481 unsigned Op1 = getRegForValue(I->getOperand(0)); 1482 if (Op1 == 0) return false; 1483 1484 unsigned Op2 = getRegForValue(I->getOperand(1)); 1485 if (Op2 == 0) return false; 1486 1487 unsigned Opc; 1488 bool is64bit = VT == MVT::f64 || VT == MVT::i64; 1489 switch (ISDOpcode) { 1490 default: return false; 1491 case ISD::FADD: 1492 Opc = is64bit ? ARM::VADDD : ARM::VADDS; 1493 break; 1494 case ISD::FSUB: 1495 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; 1496 break; 1497 case ISD::FMUL: 1498 Opc = is64bit ? ARM::VMULD : ARM::VMULS; 1499 break; 1500 } 1501 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1502 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1503 TII.get(Opc), ResultReg) 1504 .addReg(Op1).addReg(Op2)); 1505 UpdateValueMap(I, ResultReg); 1506 return true; 1507 } 1508 1509 // Call Handling Code 1510 1511 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, 1512 EVT SrcVT, unsigned &ResultReg) { 1513 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 1514 Src, /*TODO: Kill=*/false); 1515 1516 if (RR != 0) { 1517 ResultReg = RR; 1518 return true; 1519 } else 1520 return false; 1521 } 1522 1523 // This is largely taken directly from CCAssignFnForNode - we don't support 1524 // varargs in FastISel so that part has been removed. 1525 // TODO: We may not support all of this. 1526 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) { 1527 switch (CC) { 1528 default: 1529 llvm_unreachable("Unsupported calling convention"); 1530 case CallingConv::Fast: 1531 // Ignore fastcc. Silence compiler warnings. 1532 (void)RetFastCC_ARM_APCS; 1533 (void)FastCC_ARM_APCS; 1534 // Fallthrough 1535 case CallingConv::C: 1536 // Use target triple & subtarget features to do actual dispatch. 1537 if (Subtarget->isAAPCS_ABI()) { 1538 if (Subtarget->hasVFP2() && 1539 FloatABIType == FloatABI::Hard) 1540 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1541 else 1542 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1543 } else 1544 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1545 case CallingConv::ARM_AAPCS_VFP: 1546 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1547 case CallingConv::ARM_AAPCS: 1548 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1549 case CallingConv::ARM_APCS: 1550 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1551 } 1552 } 1553 1554 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, 1555 SmallVectorImpl<unsigned> &ArgRegs, 1556 SmallVectorImpl<MVT> &ArgVTs, 1557 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 1558 SmallVectorImpl<unsigned> &RegArgs, 1559 CallingConv::ID CC, 1560 unsigned &NumBytes) { 1561 SmallVector<CCValAssign, 16> ArgLocs; 1562 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context); 1563 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false)); 1564 1565 // Get a count of how many bytes are to be pushed on the stack. 1566 NumBytes = CCInfo.getNextStackOffset(); 1567 1568 // Issue CALLSEQ_START 1569 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 1570 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1571 TII.get(AdjStackDown)) 1572 .addImm(NumBytes)); 1573 1574 // Process the args. 1575 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1576 CCValAssign &VA = ArgLocs[i]; 1577 unsigned Arg = ArgRegs[VA.getValNo()]; 1578 MVT ArgVT = ArgVTs[VA.getValNo()]; 1579 1580 // We don't handle NEON/vector parameters yet. 1581 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64) 1582 return false; 1583 1584 // Handle arg promotion, etc. 1585 switch (VA.getLocInfo()) { 1586 case CCValAssign::Full: break; 1587 case CCValAssign::SExt: { 1588 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1589 Arg, ArgVT, Arg); 1590 assert(Emitted && "Failed to emit a sext!"); (void)Emitted; 1591 Emitted = true; 1592 ArgVT = VA.getLocVT(); 1593 break; 1594 } 1595 case CCValAssign::ZExt: { 1596 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1597 Arg, ArgVT, Arg); 1598 assert(Emitted && "Failed to emit a zext!"); (void)Emitted; 1599 Emitted = true; 1600 ArgVT = VA.getLocVT(); 1601 break; 1602 } 1603 case CCValAssign::AExt: { 1604 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1605 Arg, ArgVT, Arg); 1606 if (!Emitted) 1607 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1608 Arg, ArgVT, Arg); 1609 if (!Emitted) 1610 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1611 Arg, ArgVT, Arg); 1612 1613 assert(Emitted && "Failed to emit a aext!"); (void)Emitted; 1614 ArgVT = VA.getLocVT(); 1615 break; 1616 } 1617 case CCValAssign::BCvt: { 1618 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, 1619 /*TODO: Kill=*/false); 1620 assert(BC != 0 && "Failed to emit a bitcast!"); 1621 Arg = BC; 1622 ArgVT = VA.getLocVT(); 1623 break; 1624 } 1625 default: llvm_unreachable("Unknown arg promotion!"); 1626 } 1627 1628 // Now copy/store arg to correct locations. 1629 if (VA.isRegLoc() && !VA.needsCustom()) { 1630 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1631 VA.getLocReg()) 1632 .addReg(Arg); 1633 RegArgs.push_back(VA.getLocReg()); 1634 } else if (VA.needsCustom()) { 1635 // TODO: We need custom lowering for vector (v2f64) args. 1636 if (VA.getLocVT() != MVT::f64) return false; 1637 1638 CCValAssign &NextVA = ArgLocs[++i]; 1639 1640 // TODO: Only handle register args for now. 1641 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false; 1642 1643 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1644 TII.get(ARM::VMOVRRD), VA.getLocReg()) 1645 .addReg(NextVA.getLocReg(), RegState::Define) 1646 .addReg(Arg)); 1647 RegArgs.push_back(VA.getLocReg()); 1648 RegArgs.push_back(NextVA.getLocReg()); 1649 } else { 1650 assert(VA.isMemLoc()); 1651 // Need to store on the stack. 1652 Address Addr; 1653 Addr.BaseType = Address::RegBase; 1654 Addr.Base.Reg = ARM::SP; 1655 Addr.Offset = VA.getLocMemOffset(); 1656 1657 if (!ARMEmitStore(ArgVT, Arg, Addr)) return false; 1658 } 1659 } 1660 return true; 1661 } 1662 1663 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 1664 const Instruction *I, CallingConv::ID CC, 1665 unsigned &NumBytes) { 1666 // Issue CALLSEQ_END 1667 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 1668 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1669 TII.get(AdjStackUp)) 1670 .addImm(NumBytes).addImm(0)); 1671 1672 // Now the return value. 1673 if (RetVT != MVT::isVoid) { 1674 SmallVector<CCValAssign, 16> RVLocs; 1675 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); 1676 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true)); 1677 1678 // Copy all of the result registers out of their specified physreg. 1679 if (RVLocs.size() == 2 && RetVT == MVT::f64) { 1680 // For this move we copy into two registers and then move into the 1681 // double fp reg we want. 1682 EVT DestVT = RVLocs[0].getValVT(); 1683 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); 1684 unsigned ResultReg = createResultReg(DstRC); 1685 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1686 TII.get(ARM::VMOVDRR), ResultReg) 1687 .addReg(RVLocs[0].getLocReg()) 1688 .addReg(RVLocs[1].getLocReg())); 1689 1690 UsedRegs.push_back(RVLocs[0].getLocReg()); 1691 UsedRegs.push_back(RVLocs[1].getLocReg()); 1692 1693 // Finally update the result. 1694 UpdateValueMap(I, ResultReg); 1695 } else { 1696 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); 1697 EVT CopyVT = RVLocs[0].getValVT(); 1698 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1699 1700 unsigned ResultReg = createResultReg(DstRC); 1701 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1702 ResultReg).addReg(RVLocs[0].getLocReg()); 1703 UsedRegs.push_back(RVLocs[0].getLocReg()); 1704 1705 // Finally update the result. 1706 UpdateValueMap(I, ResultReg); 1707 } 1708 } 1709 1710 return true; 1711 } 1712 1713 bool ARMFastISel::SelectRet(const Instruction *I) { 1714 const ReturnInst *Ret = cast<ReturnInst>(I); 1715 const Function &F = *I->getParent()->getParent(); 1716 1717 if (!FuncInfo.CanLowerReturn) 1718 return false; 1719 1720 if (F.isVarArg()) 1721 return false; 1722 1723 CallingConv::ID CC = F.getCallingConv(); 1724 if (Ret->getNumOperands() > 0) { 1725 SmallVector<ISD::OutputArg, 4> Outs; 1726 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 1727 Outs, TLI); 1728 1729 // Analyze operands of the call, assigning locations to each operand. 1730 SmallVector<CCValAssign, 16> ValLocs; 1731 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext()); 1732 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */)); 1733 1734 const Value *RV = Ret->getOperand(0); 1735 unsigned Reg = getRegForValue(RV); 1736 if (Reg == 0) 1737 return false; 1738 1739 // Only handle a single return value for now. 1740 if (ValLocs.size() != 1) 1741 return false; 1742 1743 CCValAssign &VA = ValLocs[0]; 1744 1745 // Don't bother handling odd stuff for now. 1746 // FIXME: Should be able to handle i1, i8, and/or i16 return types. 1747 if (VA.getLocInfo() != CCValAssign::Full) 1748 return false; 1749 // Only handle register returns for now. 1750 if (!VA.isRegLoc()) 1751 return false; 1752 // TODO: For now, don't try to handle cases where getLocInfo() 1753 // says Full but the types don't match. 1754 if (TLI.getValueType(RV->getType()) != VA.getValVT()) 1755 return false; 1756 1757 // Make the copy. 1758 unsigned SrcReg = Reg + VA.getValNo(); 1759 unsigned DstReg = VA.getLocReg(); 1760 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); 1761 // Avoid a cross-class copy. This is very unlikely. 1762 if (!SrcRC->contains(DstReg)) 1763 return false; 1764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1765 DstReg).addReg(SrcReg); 1766 1767 // Mark the register as live out of the function. 1768 MRI.addLiveOut(VA.getLocReg()); 1769 } 1770 1771 unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET; 1772 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1773 TII.get(RetOpc))); 1774 return true; 1775 } 1776 1777 unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) { 1778 1779 // Darwin needs the r9 versions of the opcodes. 1780 bool isDarwin = Subtarget->isTargetDarwin(); 1781 if (isThumb) { 1782 return isDarwin ? ARM::tBLr9 : ARM::tBL; 1783 } else { 1784 return isDarwin ? ARM::BLr9 : ARM::BL; 1785 } 1786 } 1787 1788 // A quick function that will emit a call for a named libcall in F with the 1789 // vector of passed arguments for the Instruction in I. We can assume that we 1790 // can emit a call for any libcall we can produce. This is an abridged version 1791 // of the full call infrastructure since we won't need to worry about things 1792 // like computed function pointers or strange arguments at call sites. 1793 // TODO: Try to unify this and the normal call bits for ARM, then try to unify 1794 // with X86. 1795 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { 1796 CallingConv::ID CC = TLI.getLibcallCallingConv(Call); 1797 1798 // Handle *simple* calls for now. 1799 Type *RetTy = I->getType(); 1800 MVT RetVT; 1801 if (RetTy->isVoidTy()) 1802 RetVT = MVT::isVoid; 1803 else if (!isTypeLegal(RetTy, RetVT)) 1804 return false; 1805 1806 // TODO: For now if we have long calls specified we don't handle the call. 1807 if (EnableARMLongCalls) return false; 1808 1809 // Set up the argument vectors. 1810 SmallVector<Value*, 8> Args; 1811 SmallVector<unsigned, 8> ArgRegs; 1812 SmallVector<MVT, 8> ArgVTs; 1813 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1814 Args.reserve(I->getNumOperands()); 1815 ArgRegs.reserve(I->getNumOperands()); 1816 ArgVTs.reserve(I->getNumOperands()); 1817 ArgFlags.reserve(I->getNumOperands()); 1818 for (unsigned i = 0; i < I->getNumOperands(); ++i) { 1819 Value *Op = I->getOperand(i); 1820 unsigned Arg = getRegForValue(Op); 1821 if (Arg == 0) return false; 1822 1823 Type *ArgTy = Op->getType(); 1824 MVT ArgVT; 1825 if (!isTypeLegal(ArgTy, ArgVT)) return false; 1826 1827 ISD::ArgFlagsTy Flags; 1828 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1829 Flags.setOrigAlign(OriginalAlignment); 1830 1831 Args.push_back(Op); 1832 ArgRegs.push_back(Arg); 1833 ArgVTs.push_back(ArgVT); 1834 ArgFlags.push_back(Flags); 1835 } 1836 1837 // Handle the arguments now that we've gotten them. 1838 SmallVector<unsigned, 4> RegArgs; 1839 unsigned NumBytes; 1840 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) 1841 return false; 1842 1843 // Issue the call, BLr9 for darwin, BL otherwise. 1844 // TODO: Turn this into the table of arm call ops. 1845 MachineInstrBuilder MIB; 1846 unsigned CallOpc = ARMSelectCallOp(NULL); 1847 if(isThumb) 1848 // Explicitly adding the predicate here. 1849 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1850 TII.get(CallOpc))) 1851 .addExternalSymbol(TLI.getLibcallName(Call)); 1852 else 1853 // Explicitly adding the predicate here. 1854 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1855 TII.get(CallOpc)) 1856 .addExternalSymbol(TLI.getLibcallName(Call))); 1857 1858 // Add implicit physical register uses to the call. 1859 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1860 MIB.addReg(RegArgs[i]); 1861 1862 // Finish off the call including any return values. 1863 SmallVector<unsigned, 4> UsedRegs; 1864 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false; 1865 1866 // Set all unused physreg defs as dead. 1867 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1868 1869 return true; 1870 } 1871 1872 bool ARMFastISel::SelectCall(const Instruction *I) { 1873 const CallInst *CI = cast<CallInst>(I); 1874 const Value *Callee = CI->getCalledValue(); 1875 1876 // Can't handle inline asm or worry about intrinsics yet. 1877 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false; 1878 1879 // Only handle global variable Callees. 1880 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); 1881 if (!GV) 1882 return false; 1883 1884 // Check the calling convention. 1885 ImmutableCallSite CS(CI); 1886 CallingConv::ID CC = CS.getCallingConv(); 1887 1888 // TODO: Avoid some calling conventions? 1889 1890 // Let SDISel handle vararg functions. 1891 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1892 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1893 if (FTy->isVarArg()) 1894 return false; 1895 1896 // Handle *simple* calls for now. 1897 Type *RetTy = I->getType(); 1898 MVT RetVT; 1899 if (RetTy->isVoidTy()) 1900 RetVT = MVT::isVoid; 1901 else if (!isTypeLegal(RetTy, RetVT)) 1902 return false; 1903 1904 // TODO: For now if we have long calls specified we don't handle the call. 1905 if (EnableARMLongCalls) return false; 1906 1907 // Set up the argument vectors. 1908 SmallVector<Value*, 8> Args; 1909 SmallVector<unsigned, 8> ArgRegs; 1910 SmallVector<MVT, 8> ArgVTs; 1911 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1912 Args.reserve(CS.arg_size()); 1913 ArgRegs.reserve(CS.arg_size()); 1914 ArgVTs.reserve(CS.arg_size()); 1915 ArgFlags.reserve(CS.arg_size()); 1916 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1917 i != e; ++i) { 1918 unsigned Arg = getRegForValue(*i); 1919 1920 if (Arg == 0) 1921 return false; 1922 ISD::ArgFlagsTy Flags; 1923 unsigned AttrInd = i - CS.arg_begin() + 1; 1924 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1925 Flags.setSExt(); 1926 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1927 Flags.setZExt(); 1928 1929 // FIXME: Only handle *easy* calls for now. 1930 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1931 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1932 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1933 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1934 return false; 1935 1936 Type *ArgTy = (*i)->getType(); 1937 MVT ArgVT; 1938 // FIXME: Should be able to handle i1, i8, and/or i16 parameters. 1939 if (!isTypeLegal(ArgTy, ArgVT)) 1940 return false; 1941 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1942 Flags.setOrigAlign(OriginalAlignment); 1943 1944 Args.push_back(*i); 1945 ArgRegs.push_back(Arg); 1946 ArgVTs.push_back(ArgVT); 1947 ArgFlags.push_back(Flags); 1948 } 1949 1950 // Handle the arguments now that we've gotten them. 1951 SmallVector<unsigned, 4> RegArgs; 1952 unsigned NumBytes; 1953 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) 1954 return false; 1955 1956 // Issue the call, BLr9 for darwin, BL otherwise. 1957 // TODO: Turn this into the table of arm call ops. 1958 MachineInstrBuilder MIB; 1959 unsigned CallOpc = ARMSelectCallOp(GV); 1960 // Explicitly adding the predicate here. 1961 if(isThumb) 1962 // Explicitly adding the predicate here. 1963 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1964 TII.get(CallOpc))) 1965 .addGlobalAddress(GV, 0, 0); 1966 else 1967 // Explicitly adding the predicate here. 1968 MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1969 TII.get(CallOpc)) 1970 .addGlobalAddress(GV, 0, 0)); 1971 1972 // Add implicit physical register uses to the call. 1973 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1974 MIB.addReg(RegArgs[i]); 1975 1976 // Finish off the call including any return values. 1977 SmallVector<unsigned, 4> UsedRegs; 1978 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false; 1979 1980 // Set all unused physreg defs as dead. 1981 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1982 1983 return true; 1984 1985 } 1986 1987 bool ARMFastISel::SelectIntCast(const Instruction *I) { 1988 // On ARM, in general, integer casts don't involve legal types; this code 1989 // handles promotable integers. The high bits for a type smaller than 1990 // the register size are assumed to be undefined. 1991 Type *DestTy = I->getType(); 1992 Value *Op = I->getOperand(0); 1993 Type *SrcTy = Op->getType(); 1994 1995 EVT SrcVT, DestVT; 1996 SrcVT = TLI.getValueType(SrcTy, true); 1997 DestVT = TLI.getValueType(DestTy, true); 1998 1999 if (isa<TruncInst>(I)) { 2000 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) 2001 return false; 2002 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) 2003 return false; 2004 2005 unsigned SrcReg = getRegForValue(Op); 2006 if (!SrcReg) return false; 2007 2008 // Because the high bits are undefined, a truncate doesn't generate 2009 // any code. 2010 UpdateValueMap(I, SrcReg); 2011 return true; 2012 } 2013 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) 2014 return false; 2015 2016 unsigned Opc; 2017 bool isZext = isa<ZExtInst>(I); 2018 bool isBoolZext = false; 2019 if (!SrcVT.isSimple()) 2020 return false; 2021 switch (SrcVT.getSimpleVT().SimpleTy) { 2022 default: return false; 2023 case MVT::i16: 2024 if (!Subtarget->hasV6Ops()) return false; 2025 if (isZext) 2026 Opc = isThumb ? ARM::t2UXTH : ARM::UXTH; 2027 else 2028 Opc = isThumb ? ARM::t2SXTH : ARM::SXTH; 2029 break; 2030 case MVT::i8: 2031 if (!Subtarget->hasV6Ops()) return false; 2032 if (isZext) 2033 Opc = isThumb ? ARM::t2UXTB : ARM::UXTB; 2034 else 2035 Opc = isThumb ? ARM::t2SXTB : ARM::SXTB; 2036 break; 2037 case MVT::i1: 2038 if (isZext) { 2039 Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; 2040 isBoolZext = true; 2041 break; 2042 } 2043 return false; 2044 } 2045 2046 // FIXME: We could save an instruction in many cases by special-casing 2047 // load instructions. 2048 unsigned SrcReg = getRegForValue(Op); 2049 if (!SrcReg) return false; 2050 2051 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32)); 2052 MachineInstrBuilder MIB; 2053 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 2054 .addReg(SrcReg); 2055 if (isBoolZext) 2056 MIB.addImm(1); 2057 else 2058 MIB.addImm(0); 2059 AddOptionalDefs(MIB); 2060 UpdateValueMap(I, DestReg); 2061 return true; 2062 } 2063 2064 // TODO: SoftFP support. 2065 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { 2066 2067 switch (I->getOpcode()) { 2068 case Instruction::Load: 2069 return SelectLoad(I); 2070 case Instruction::Store: 2071 return SelectStore(I); 2072 case Instruction::Br: 2073 return SelectBranch(I); 2074 case Instruction::ICmp: 2075 case Instruction::FCmp: 2076 return SelectCmp(I); 2077 case Instruction::FPExt: 2078 return SelectFPExt(I); 2079 case Instruction::FPTrunc: 2080 return SelectFPTrunc(I); 2081 case Instruction::SIToFP: 2082 return SelectSIToFP(I); 2083 case Instruction::FPToSI: 2084 return SelectFPToSI(I); 2085 case Instruction::FAdd: 2086 return SelectBinaryOp(I, ISD::FADD); 2087 case Instruction::FSub: 2088 return SelectBinaryOp(I, ISD::FSUB); 2089 case Instruction::FMul: 2090 return SelectBinaryOp(I, ISD::FMUL); 2091 case Instruction::SDiv: 2092 return SelectSDiv(I); 2093 case Instruction::SRem: 2094 return SelectSRem(I); 2095 case Instruction::Call: 2096 return SelectCall(I); 2097 case Instruction::Select: 2098 return SelectSelect(I); 2099 case Instruction::Ret: 2100 return SelectRet(I); 2101 case Instruction::Trunc: 2102 case Instruction::ZExt: 2103 case Instruction::SExt: 2104 return SelectIntCast(I); 2105 default: break; 2106 } 2107 return false; 2108 } 2109 2110 namespace llvm { 2111 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { 2112 // Completely untested on non-darwin. 2113 const TargetMachine &TM = funcInfo.MF->getTarget(); 2114 2115 // Darwin and thumb1 only for now. 2116 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>(); 2117 if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && 2118 !DisableARMFastISel) 2119 return new ARMFastISel(funcInfo); 2120 return 0; 2121 } 2122 } 2123