| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 166 unsigned getInvertedPredicatedOpcode(const int Opc) const;
169 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
|
| /external/llvm/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 479 vspltisw(const char *N, unsigned Opc)
480 : Operator(MakeMask(Elt, Elt, Elt, Elt), N, Opc) {}
490 vsldoi(const char *Name, unsigned Opc)
491 : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), Name, Opc) {
528 vdup(const char *N, unsigned Opc)
529 : Operator(MakeMask(Elt, Elt, Elt, Elt), N, Opc) {}
539 vext(const char *Name, unsigned Opc)
540 : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), Name, Opc) {
|
| /external/qemu/ |
| translate-all.c | 77 #include "tcg-opc.h"
197 /* find opc index corresponding to search_pc */
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 432 unsigned Opc = Node->getMachineOpcode();
449 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
486 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
487 Opc == TargetOpcode::SUBREG_TO_REG) {
515 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
520 if (Opc == TargetOpcode::SUBREG_TO_REG) {
666 unsigned Opc = Node->getMachineOpcode();
669 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
670 Opc == TargetOpcode::INSERT_SUBREG ||
671 Opc == TargetOpcode::SUBREG_TO_REG)
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.h | 344 bool ParseCmpPredicate(unsigned &Pred, unsigned Opc);
353 bool ParseArithmetic(Instruction *&I, PerFunctionState &PFS, unsigned Opc,
355 bool ParseLogical(Instruction *&I, PerFunctionState &PFS, unsigned Opc);
356 bool ParseCompare(Instruction *&I, PerFunctionState &PFS, unsigned Opc);
357 bool ParseCast(Instruction *&I, PerFunctionState &PFS, unsigned Opc);
|
| LLParser.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode();
102 if (Opc != ISD::Constant)
213 unsigned Opc = MBlaze::ADDIK;
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| MBlazeInstrInfo.cpp | 196 unsigned Opc = MBlaze::BRID;
198 Opc = (unsigned)Cond[0].getImm();
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 495 unsigned OpC = MI.getOpcode();
499 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
506 if (OpC == PPC::SPILL_CR) {
509 } else if (OpC == PPC::RESTORE_CR) {
527 switch (OpC) {
557 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
589 if (OpC != TargetOpcode::INLINEASM) {
590 assert(ImmToIdxMap.count(OpC) &&
592 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second
[all...] |
| PPCInstrInfo.cpp | 325 unsigned Opc;
327 Opc = PPC::OR;
329 Opc = PPC::OR8;
331 Opc = PPC::FMR;
333 Opc = PPC::MCRF;
335 Opc = PPC::VOR;
337 Opc = PPC::CROR;
341 const MCInstrDesc &MCID = get(Opc);
|
| PPCISelLowering.h | 122 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
124 /// encoding for the OPC field to identify the compare. For example, 838
128 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
130 /// opcode number encoding for the OPC field to identify the compare. For
134 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
136 /// condition register to branch on, OPC is the branch opcode to use (e.g.
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
560 unsigned Opc = MI->getOpcode();
561 switch (Opc) {
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)
[all...] |
| ARMInstrThumb.td | 250 class T1SystemEncoding<bits<8> opc>
253 let Inst{7-0} = opc;
759 string opc, string asm, list<dag> pattern>
760 : T1pI<oops, iops, itin, opc, asm, pattern>,
768 string opc, string asm, list<dag> pattern>
769 : T1pI<oops, iops, itin, opc, asm, pattern>,
779 string opc, string asm, list<dag> pattern>
780 : T1sI<oops, iops, itin, opc, asm, pattern>,
788 string opc, string asm, list<dag> pattern>
789 : T1sI<oops, iops, itin, opc, asm, pattern>
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 834 UnaryOp Opc;
837 UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type)
838 : OpInit(Type), Opc(opc), LHS(lhs) {}
844 static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type);
859 UnaryOp getOpcode() const { return Opc; }
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/base/core/jni/ |
| AndroidRuntime.cpp | 568 const char* opc; local
571 opc = strstr(dexoptFlagsBuf, "v="); /* verification */
572 if (opc != NULL) {
573 switch (*(opc+2)) {
586 opc = strstr(dexoptFlagsBuf, "o="); /* optimization */
587 if (opc != NULL) {
588 switch (*(opc+2)) {
602 opc = strstr(dexoptFlagsBuf, "m=y"); /* register map */
603 if (opc != NULL) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 240 if (Inst->Opc == LUi)
244 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
249 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
|
| MipsInstrInfo.h | 30 unsigned GetOppositeBranchOpc(unsigned Opc);
|
| MipsMCInstLower.cpp | 110 static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0,
113 Inst.setOpcode(Opc);
211 unsigned Opc = MI->getOpcode();
233 switch (Opc) {
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
|
| /external/qemu/hw/ |
| bt-hci-csr.c | 184 int opc; local
188 opc = le16_to_cpu(((struct hci_command_hdr *) pkt)->opcode);
189 if (cmd_opcode_ogf(opc) == OGF_VENDOR_CMD) {
190 csrhci_in_packet_vendor(s, cmd_opcode_ocf(opc),
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 142 unsigned Opc = PI->getOpcode();
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 343 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 local
346 opc = 2; // 0b0010
351 return ARM_AM::getSOImmVal(Value) | (opc << 21);
356 unsigned opc = 0; local
359 opc = 5;
362 uint32_t out = (opc << 21);
|
