1 //===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the execution dependency fix pass. 11 // 12 // Some X86 SSE instructions like mov, and, or, xor are available in different 13 // variants for different operand types. These variant instructions are 14 // equivalent, but on Nehalem and newer cpus there is extra latency 15 // transferring data between integer and floating point domains. ARM cores 16 // have similar issues when they are configured with both VFP and NEON 17 // pipelines. 18 // 19 // This pass changes the variant instructions to minimize domain crossings. 20 // 21 //===----------------------------------------------------------------------===// 22 23 #include "llvm/CodeGen/Passes.h" 24 #include "llvm/ADT/PostOrderIterator.h" 25 #include "llvm/ADT/iterator_range.h" 26 #include "llvm/CodeGen/LivePhysRegs.h" 27 #include "llvm/CodeGen/MachineFunctionPass.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/Support/Allocator.h" 30 #include "llvm/Support/Debug.h" 31 #include "llvm/Support/raw_ostream.h" 32 #include "llvm/Target/TargetInstrInfo.h" 33 #include "llvm/Target/TargetSubtargetInfo.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "execution-fix" 38 39 /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track 40 /// of execution domains. 41 /// 42 /// An open DomainValue represents a set of instructions that can still switch 43 /// execution domain. Multiple registers may refer to the same open 44 /// DomainValue - they will eventually be collapsed to the same execution 45 /// domain. 46 /// 47 /// A collapsed DomainValue represents a single register that has been forced 48 /// into one of more execution domains. There is a separate collapsed 49 /// DomainValue for each register, but it may contain multiple execution 50 /// domains. A register value is initially created in a single execution 51 /// domain, but if we were forced to pay the penalty of a domain crossing, we 52 /// keep track of the fact that the register is now available in multiple 53 /// domains. 54 namespace { 55 struct DomainValue { 56 // Basic reference counting. 57 unsigned Refs; 58 59 // Bitmask of available domains. For an open DomainValue, it is the still 60 // possible domains for collapsing. For a collapsed DomainValue it is the 61 // domains where the register is available for free. 62 unsigned AvailableDomains; 63 64 // Pointer to the next DomainValue in a chain. When two DomainValues are 65 // merged, Victim.Next is set to point to Victor, so old DomainValue 66 // references can be updated by following the chain. 67 DomainValue *Next; 68 69 // Twiddleable instructions using or defining these registers. 70 SmallVector<MachineInstr*, 8> Instrs; 71 72 // A collapsed DomainValue has no instructions to twiddle - it simply keeps 73 // track of the domains where the registers are already available. 74 bool isCollapsed() const { return Instrs.empty(); } 75 76 // Is domain available? 77 bool hasDomain(unsigned domain) const { 78 assert(domain < 79 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) && 80 "undefined behavior"); 81 return AvailableDomains & (1u << domain); 82 } 83 84 // Mark domain as available. 85 void addDomain(unsigned domain) { 86 AvailableDomains |= 1u << domain; 87 } 88 89 // Restrict to a single domain available. 90 void setSingleDomain(unsigned domain) { 91 AvailableDomains = 1u << domain; 92 } 93 94 // Return bitmask of domains that are available and in mask. 95 unsigned getCommonDomains(unsigned mask) const { 96 return AvailableDomains & mask; 97 } 98 99 // First domain available. 100 unsigned getFirstDomain() const { 101 return countTrailingZeros(AvailableDomains); 102 } 103 104 DomainValue() : Refs(0) { clear(); } 105 106 // Clear this DomainValue and point to next which has all its data. 107 void clear() { 108 AvailableDomains = 0; 109 Next = nullptr; 110 Instrs.clear(); 111 } 112 }; 113 } 114 115 namespace { 116 /// Information about a live register. 117 struct LiveReg { 118 /// Value currently in this register, or NULL when no value is being tracked. 119 /// This counts as a DomainValue reference. 120 DomainValue *Value; 121 122 /// Instruction that defined this register, relative to the beginning of the 123 /// current basic block. When a LiveReg is used to represent a live-out 124 /// register, this value is relative to the end of the basic block, so it 125 /// will be a negative number. 126 int Def; 127 }; 128 } // anonymous namespace 129 130 namespace { 131 class ExeDepsFix : public MachineFunctionPass { 132 static char ID; 133 SpecificBumpPtrAllocator<DomainValue> Allocator; 134 SmallVector<DomainValue*,16> Avail; 135 136 const TargetRegisterClass *const RC; 137 MachineFunction *MF; 138 const TargetInstrInfo *TII; 139 const TargetRegisterInfo *TRI; 140 std::vector<SmallVector<int, 1>> AliasMap; 141 const unsigned NumRegs; 142 LiveReg *LiveRegs; 143 typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap; 144 LiveOutMap LiveOuts; 145 146 /// List of undefined register reads in this block in forward order. 147 std::vector<std::pair<MachineInstr*, unsigned> > UndefReads; 148 149 /// Storage for register unit liveness. 150 LivePhysRegs LiveRegSet; 151 152 /// Current instruction number. 153 /// The first instruction in each basic block is 0. 154 int CurInstr; 155 156 /// True when the current block has a predecessor that hasn't been visited 157 /// yet. 158 bool SeenUnknownBackEdge; 159 160 public: 161 ExeDepsFix(const TargetRegisterClass *rc) 162 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 163 164 void getAnalysisUsage(AnalysisUsage &AU) const override { 165 AU.setPreservesAll(); 166 MachineFunctionPass::getAnalysisUsage(AU); 167 } 168 169 bool runOnMachineFunction(MachineFunction &MF) override; 170 171 const char *getPassName() const override { 172 return "Execution dependency fix"; 173 } 174 175 private: 176 iterator_range<SmallVectorImpl<int>::const_iterator> 177 regIndices(unsigned Reg) const; 178 179 // DomainValue allocation. 180 DomainValue *alloc(int domain = -1); 181 DomainValue *retain(DomainValue *DV) { 182 if (DV) ++DV->Refs; 183 return DV; 184 } 185 void release(DomainValue*); 186 DomainValue *resolve(DomainValue*&); 187 188 // LiveRegs manipulations. 189 void setLiveReg(int rx, DomainValue *DV); 190 void kill(int rx); 191 void force(int rx, unsigned domain); 192 void collapse(DomainValue *dv, unsigned domain); 193 bool merge(DomainValue *A, DomainValue *B); 194 195 void enterBasicBlock(MachineBasicBlock*); 196 void leaveBasicBlock(MachineBasicBlock*); 197 void visitInstr(MachineInstr*); 198 void processDefs(MachineInstr*, bool Kill); 199 void visitSoftInstr(MachineInstr*, unsigned mask); 200 void visitHardInstr(MachineInstr*, unsigned domain); 201 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref); 202 void processUndefReads(MachineBasicBlock*); 203 }; 204 } 205 206 char ExeDepsFix::ID = 0; 207 208 /// Translate TRI register number to a list of indices into our smaller tables 209 /// of interesting registers. 210 iterator_range<SmallVectorImpl<int>::const_iterator> 211 ExeDepsFix::regIndices(unsigned Reg) const { 212 assert(Reg < AliasMap.size() && "Invalid register"); 213 const auto &Entry = AliasMap[Reg]; 214 return make_range(Entry.begin(), Entry.end()); 215 } 216 217 DomainValue *ExeDepsFix::alloc(int domain) { 218 DomainValue *dv = Avail.empty() ? 219 new(Allocator.Allocate()) DomainValue : 220 Avail.pop_back_val(); 221 if (domain >= 0) 222 dv->addDomain(domain); 223 assert(dv->Refs == 0 && "Reference count wasn't cleared"); 224 assert(!dv->Next && "Chained DomainValue shouldn't have been recycled"); 225 return dv; 226 } 227 228 /// Release a reference to DV. When the last reference is released, 229 /// collapse if needed. 230 void ExeDepsFix::release(DomainValue *DV) { 231 while (DV) { 232 assert(DV->Refs && "Bad DomainValue"); 233 if (--DV->Refs) 234 return; 235 236 // There are no more DV references. Collapse any contained instructions. 237 if (DV->AvailableDomains && !DV->isCollapsed()) 238 collapse(DV, DV->getFirstDomain()); 239 240 DomainValue *Next = DV->Next; 241 DV->clear(); 242 Avail.push_back(DV); 243 // Also release the next DomainValue in the chain. 244 DV = Next; 245 } 246 } 247 248 /// Follow the chain of dead DomainValues until a live DomainValue is reached. 249 /// Update the referenced pointer when necessary. 250 DomainValue *ExeDepsFix::resolve(DomainValue *&DVRef) { 251 DomainValue *DV = DVRef; 252 if (!DV || !DV->Next) 253 return DV; 254 255 // DV has a chain. Find the end. 256 do DV = DV->Next; 257 while (DV->Next); 258 259 // Update DVRef to point to DV. 260 retain(DV); 261 release(DVRef); 262 DVRef = DV; 263 return DV; 264 } 265 266 /// Set LiveRegs[rx] = dv, updating reference counts. 267 void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) { 268 assert(unsigned(rx) < NumRegs && "Invalid index"); 269 assert(LiveRegs && "Must enter basic block first."); 270 271 if (LiveRegs[rx].Value == dv) 272 return; 273 if (LiveRegs[rx].Value) 274 release(LiveRegs[rx].Value); 275 LiveRegs[rx].Value = retain(dv); 276 } 277 278 // Kill register rx, recycle or collapse any DomainValue. 279 void ExeDepsFix::kill(int rx) { 280 assert(unsigned(rx) < NumRegs && "Invalid index"); 281 assert(LiveRegs && "Must enter basic block first."); 282 if (!LiveRegs[rx].Value) 283 return; 284 285 release(LiveRegs[rx].Value); 286 LiveRegs[rx].Value = nullptr; 287 } 288 289 /// Force register rx into domain. 290 void ExeDepsFix::force(int rx, unsigned domain) { 291 assert(unsigned(rx) < NumRegs && "Invalid index"); 292 assert(LiveRegs && "Must enter basic block first."); 293 if (DomainValue *dv = LiveRegs[rx].Value) { 294 if (dv->isCollapsed()) 295 dv->addDomain(domain); 296 else if (dv->hasDomain(domain)) 297 collapse(dv, domain); 298 else { 299 // This is an incompatible open DomainValue. Collapse it to whatever and 300 // force the new value into domain. This costs a domain crossing. 301 collapse(dv, dv->getFirstDomain()); 302 assert(LiveRegs[rx].Value && "Not live after collapse?"); 303 LiveRegs[rx].Value->addDomain(domain); 304 } 305 } else { 306 // Set up basic collapsed DomainValue. 307 setLiveReg(rx, alloc(domain)); 308 } 309 } 310 311 /// Collapse open DomainValue into given domain. If there are multiple 312 /// registers using dv, they each get a unique collapsed DomainValue. 313 void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) { 314 assert(dv->hasDomain(domain) && "Cannot collapse"); 315 316 // Collapse all the instructions. 317 while (!dv->Instrs.empty()) 318 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain); 319 dv->setSingleDomain(domain); 320 321 // If there are multiple users, give them new, unique DomainValues. 322 if (LiveRegs && dv->Refs > 1) 323 for (unsigned rx = 0; rx != NumRegs; ++rx) 324 if (LiveRegs[rx].Value == dv) 325 setLiveReg(rx, alloc(domain)); 326 } 327 328 /// All instructions and registers in B are moved to A, and B is released. 329 bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) { 330 assert(!A->isCollapsed() && "Cannot merge into collapsed"); 331 assert(!B->isCollapsed() && "Cannot merge from collapsed"); 332 if (A == B) 333 return true; 334 // Restrict to the domains that A and B have in common. 335 unsigned common = A->getCommonDomains(B->AvailableDomains); 336 if (!common) 337 return false; 338 A->AvailableDomains = common; 339 A->Instrs.append(B->Instrs.begin(), B->Instrs.end()); 340 341 // Clear the old DomainValue so we won't try to swizzle instructions twice. 342 B->clear(); 343 // All uses of B are referred to A. 344 B->Next = retain(A); 345 346 for (unsigned rx = 0; rx != NumRegs; ++rx) { 347 assert(LiveRegs && "no space allocated for live registers"); 348 if (LiveRegs[rx].Value == B) 349 setLiveReg(rx, A); 350 } 351 return true; 352 } 353 354 /// Set up LiveRegs by merging predecessor live-out values. 355 void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { 356 // Detect back-edges from predecessors we haven't processed yet. 357 SeenUnknownBackEdge = false; 358 359 // Reset instruction counter in each basic block. 360 CurInstr = 0; 361 362 // Set up UndefReads to track undefined register reads. 363 UndefReads.clear(); 364 LiveRegSet.clear(); 365 366 // Set up LiveRegs to represent registers entering MBB. 367 if (!LiveRegs) 368 LiveRegs = new LiveReg[NumRegs]; 369 370 // Default values are 'nothing happened a long time ago'. 371 for (unsigned rx = 0; rx != NumRegs; ++rx) { 372 LiveRegs[rx].Value = nullptr; 373 LiveRegs[rx].Def = -(1 << 20); 374 } 375 376 // This is the entry block. 377 if (MBB->pred_empty()) { 378 for (const auto &LI : MBB->liveins()) { 379 for (int rx : regIndices(LI.PhysReg)) { 380 // Treat function live-ins as if they were defined just before the first 381 // instruction. Usually, function arguments are set up immediately 382 // before the call. 383 LiveRegs[rx].Def = -1; 384 } 385 } 386 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n"); 387 return; 388 } 389 390 // Try to coalesce live-out registers from predecessors. 391 for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(), 392 pe = MBB->pred_end(); pi != pe; ++pi) { 393 LiveOutMap::const_iterator fi = LiveOuts.find(*pi); 394 if (fi == LiveOuts.end()) { 395 SeenUnknownBackEdge = true; 396 continue; 397 } 398 assert(fi->second && "Can't have NULL entries"); 399 400 for (unsigned rx = 0; rx != NumRegs; ++rx) { 401 // Use the most recent predecessor def for each register. 402 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def); 403 404 DomainValue *pdv = resolve(fi->second[rx].Value); 405 if (!pdv) 406 continue; 407 if (!LiveRegs[rx].Value) { 408 setLiveReg(rx, pdv); 409 continue; 410 } 411 412 // We have a live DomainValue from more than one predecessor. 413 if (LiveRegs[rx].Value->isCollapsed()) { 414 // We are already collapsed, but predecessor is not. Force it. 415 unsigned Domain = LiveRegs[rx].Value->getFirstDomain(); 416 if (!pdv->isCollapsed() && pdv->hasDomain(Domain)) 417 collapse(pdv, Domain); 418 continue; 419 } 420 421 // Currently open, merge in predecessor. 422 if (!pdv->isCollapsed()) 423 merge(LiveRegs[rx].Value, pdv); 424 else 425 force(rx, pdv->getFirstDomain()); 426 } 427 } 428 DEBUG(dbgs() << "BB#" << MBB->getNumber() 429 << (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n")); 430 } 431 432 void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) { 433 assert(LiveRegs && "Must enter basic block first."); 434 // Save live registers at end of MBB - used by enterBasicBlock(). 435 // Also use LiveOuts as a visited set to detect back-edges. 436 bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second; 437 438 if (First) { 439 // LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to 440 // the end of this block instead of the beginning. 441 for (unsigned i = 0, e = NumRegs; i != e; ++i) 442 LiveRegs[i].Def -= CurInstr; 443 } else { 444 // Insertion failed, this must be the second pass. 445 // Release all the DomainValues instead of keeping them. 446 for (unsigned i = 0, e = NumRegs; i != e; ++i) 447 release(LiveRegs[i].Value); 448 delete[] LiveRegs; 449 } 450 LiveRegs = nullptr; 451 } 452 453 void ExeDepsFix::visitInstr(MachineInstr *MI) { 454 if (MI->isDebugValue()) 455 return; 456 457 // Update instructions with explicit execution domains. 458 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI); 459 if (DomP.first) { 460 if (DomP.second) 461 visitSoftInstr(MI, DomP.second); 462 else 463 visitHardInstr(MI, DomP.first); 464 } 465 466 // Process defs to track register ages, and kill values clobbered by generic 467 // instructions. 468 processDefs(MI, !DomP.first); 469 } 470 471 /// \brief Return true to if it makes sense to break dependence on a partial def 472 /// or undef use. 473 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, 474 unsigned Pref) { 475 unsigned reg = MI->getOperand(OpIdx).getReg(); 476 for (int rx : regIndices(reg)) { 477 unsigned Clearance = CurInstr - LiveRegs[rx].Def; 478 DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref); 479 480 if (Pref > Clearance) { 481 DEBUG(dbgs() << ": Break dependency.\n"); 482 continue; 483 } 484 // The current clearance seems OK, but we may be ignoring a def from a 485 // back-edge. 486 if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) { 487 DEBUG(dbgs() << ": OK .\n"); 488 return false; 489 } 490 // A def from an unprocessed back-edge may make us break this dependency. 491 DEBUG(dbgs() << ": Wait for back-edge to resolve.\n"); 492 return false; 493 } 494 return true; 495 } 496 497 // Update def-ages for registers defined by MI. 498 // If Kill is set, also kill off DomainValues clobbered by the defs. 499 // 500 // Also break dependencies on partial defs and undef uses. 501 void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) { 502 assert(!MI->isDebugValue() && "Won't process debug values"); 503 504 // Break dependence on undef uses. Do this before updating LiveRegs below. 505 unsigned OpNum; 506 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI); 507 if (Pref) { 508 if (shouldBreakDependence(MI, OpNum, Pref)) 509 UndefReads.push_back(std::make_pair(MI, OpNum)); 510 } 511 const MCInstrDesc &MCID = MI->getDesc(); 512 for (unsigned i = 0, 513 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); 514 i != e; ++i) { 515 MachineOperand &MO = MI->getOperand(i); 516 if (!MO.isReg()) 517 continue; 518 if (MO.isImplicit()) 519 break; 520 if (MO.isUse()) 521 continue; 522 for (int rx : regIndices(MO.getReg())) { 523 // This instruction explicitly defines rx. 524 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr 525 << '\t' << *MI); 526 527 // Check clearance before partial register updates. 528 // Call breakDependence before setting LiveRegs[rx].Def. 529 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI); 530 if (Pref && shouldBreakDependence(MI, i, Pref)) 531 TII->breakPartialRegDependency(MI, i, TRI); 532 533 // How many instructions since rx was last written? 534 LiveRegs[rx].Def = CurInstr; 535 536 // Kill off domains redefined by generic instructions. 537 if (Kill) 538 kill(rx); 539 } 540 } 541 ++CurInstr; 542 } 543 544 /// \break Break false dependencies on undefined register reads. 545 /// 546 /// Walk the block backward computing precise liveness. This is expensive, so we 547 /// only do it on demand. Note that the occurrence of undefined register reads 548 /// that should be broken is very rare, but when they occur we may have many in 549 /// a single block. 550 void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) { 551 if (UndefReads.empty()) 552 return; 553 554 // Collect this block's live out register units. 555 LiveRegSet.init(TRI); 556 LiveRegSet.addLiveOuts(MBB); 557 558 MachineInstr *UndefMI = UndefReads.back().first; 559 unsigned OpIdx = UndefReads.back().second; 560 561 for (MachineInstr &I : make_range(MBB->rbegin(), MBB->rend())) { 562 // Update liveness, including the current instruction's defs. 563 LiveRegSet.stepBackward(I); 564 565 if (UndefMI == &I) { 566 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) 567 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI); 568 569 UndefReads.pop_back(); 570 if (UndefReads.empty()) 571 return; 572 573 UndefMI = UndefReads.back().first; 574 OpIdx = UndefReads.back().second; 575 } 576 } 577 } 578 579 // A hard instruction only works in one domain. All input registers will be 580 // forced into that domain. 581 void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) { 582 // Collapse all uses. 583 for (unsigned i = mi->getDesc().getNumDefs(), 584 e = mi->getDesc().getNumOperands(); i != e; ++i) { 585 MachineOperand &mo = mi->getOperand(i); 586 if (!mo.isReg()) continue; 587 for (int rx : regIndices(mo.getReg())) { 588 force(rx, domain); 589 } 590 } 591 592 // Kill all defs and force them. 593 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { 594 MachineOperand &mo = mi->getOperand(i); 595 if (!mo.isReg()) continue; 596 for (int rx : regIndices(mo.getReg())) { 597 kill(rx); 598 force(rx, domain); 599 } 600 } 601 } 602 603 // A soft instruction can be changed to work in other domains given by mask. 604 void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) { 605 // Bitmask of available domains for this instruction after taking collapsed 606 // operands into account. 607 unsigned available = mask; 608 609 // Scan the explicit use operands for incoming domains. 610 SmallVector<int, 4> used; 611 if (LiveRegs) 612 for (unsigned i = mi->getDesc().getNumDefs(), 613 e = mi->getDesc().getNumOperands(); i != e; ++i) { 614 MachineOperand &mo = mi->getOperand(i); 615 if (!mo.isReg()) continue; 616 for (int rx : regIndices(mo.getReg())) { 617 DomainValue *dv = LiveRegs[rx].Value; 618 if (dv == nullptr) 619 continue; 620 // Bitmask of domains that dv and available have in common. 621 unsigned common = dv->getCommonDomains(available); 622 // Is it possible to use this collapsed register for free? 623 if (dv->isCollapsed()) { 624 // Restrict available domains to the ones in common with the operand. 625 // If there are no common domains, we must pay the cross-domain 626 // penalty for this operand. 627 if (common) available = common; 628 } else if (common) 629 // Open DomainValue is compatible, save it for merging. 630 used.push_back(rx); 631 else 632 // Open DomainValue is not compatible with instruction. It is useless 633 // now. 634 kill(rx); 635 } 636 } 637 638 // If the collapsed operands force a single domain, propagate the collapse. 639 if (isPowerOf2_32(available)) { 640 unsigned domain = countTrailingZeros(available); 641 TII->setExecutionDomain(mi, domain); 642 visitHardInstr(mi, domain); 643 return; 644 } 645 646 // Kill off any remaining uses that don't match available, and build a list of 647 // incoming DomainValues that we want to merge. 648 SmallVector<LiveReg, 4> Regs; 649 for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) { 650 int rx = *i; 651 assert(LiveRegs && "no space allocated for live registers"); 652 const LiveReg &LR = LiveRegs[rx]; 653 // This useless DomainValue could have been missed above. 654 if (!LR.Value->getCommonDomains(available)) { 655 kill(rx); 656 continue; 657 } 658 // Sorted insertion. 659 bool Inserted = false; 660 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); 661 i != e && !Inserted; ++i) { 662 if (LR.Def < i->Def) { 663 Inserted = true; 664 Regs.insert(i, LR); 665 } 666 } 667 if (!Inserted) 668 Regs.push_back(LR); 669 } 670 671 // doms are now sorted in order of appearance. Try to merge them all, giving 672 // priority to the latest ones. 673 DomainValue *dv = nullptr; 674 while (!Regs.empty()) { 675 if (!dv) { 676 dv = Regs.pop_back_val().Value; 677 // Force the first dv to match the current instruction. 678 dv->AvailableDomains = dv->getCommonDomains(available); 679 assert(dv->AvailableDomains && "Domain should have been filtered"); 680 continue; 681 } 682 683 DomainValue *Latest = Regs.pop_back_val().Value; 684 // Skip already merged values. 685 if (Latest == dv || Latest->Next) 686 continue; 687 if (merge(dv, Latest)) 688 continue; 689 690 // If latest didn't merge, it is useless now. Kill all registers using it. 691 for (int i : used) { 692 assert(LiveRegs && "no space allocated for live registers"); 693 if (LiveRegs[i].Value == Latest) 694 kill(i); 695 } 696 } 697 698 // dv is the DomainValue we are going to use for this instruction. 699 if (!dv) { 700 dv = alloc(); 701 dv->AvailableDomains = available; 702 } 703 dv->Instrs.push_back(mi); 704 705 // Finally set all defs and non-collapsed uses to dv. We must iterate through 706 // all the operators, including imp-def ones. 707 for (MachineInstr::mop_iterator ii = mi->operands_begin(), 708 ee = mi->operands_end(); 709 ii != ee; ++ii) { 710 MachineOperand &mo = *ii; 711 if (!mo.isReg()) continue; 712 for (int rx : regIndices(mo.getReg())) { 713 if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) { 714 kill(rx); 715 setLiveReg(rx, dv); 716 } 717 } 718 } 719 } 720 721 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) { 722 MF = &mf; 723 TII = MF->getSubtarget().getInstrInfo(); 724 TRI = MF->getSubtarget().getRegisterInfo(); 725 LiveRegs = nullptr; 726 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); 727 728 DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: " 729 << TRI->getRegClassName(RC) << " **********\n"); 730 731 // If no relevant registers are used in the function, we can skip it 732 // completely. 733 bool anyregs = false; 734 const MachineRegisterInfo &MRI = mf.getRegInfo(); 735 for (unsigned Reg : *RC) { 736 if (MRI.isPhysRegUsed(Reg)) { 737 anyregs = true; 738 break; 739 } 740 } 741 if (!anyregs) return false; 742 743 // Initialize the AliasMap on the first use. 744 if (AliasMap.empty()) { 745 // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and 746 // therefore the LiveRegs array. 747 AliasMap.resize(TRI->getNumRegs()); 748 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) 749 for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); 750 AI.isValid(); ++AI) 751 AliasMap[*AI].push_back(i); 752 } 753 754 MachineBasicBlock *Entry = &*MF->begin(); 755 ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry); 756 SmallVector<MachineBasicBlock*, 16> Loops; 757 for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator 758 MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { 759 MachineBasicBlock *MBB = *MBBI; 760 enterBasicBlock(MBB); 761 if (SeenUnknownBackEdge) 762 Loops.push_back(MBB); 763 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; 764 ++I) 765 visitInstr(I); 766 processUndefReads(MBB); 767 leaveBasicBlock(MBB); 768 } 769 770 // Visit all the loop blocks again in order to merge DomainValues from 771 // back-edges. 772 for (unsigned i = 0, e = Loops.size(); i != e; ++i) { 773 MachineBasicBlock *MBB = Loops[i]; 774 enterBasicBlock(MBB); 775 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; 776 ++I) 777 if (!I->isDebugValue()) 778 processDefs(I, false); 779 processUndefReads(MBB); 780 leaveBasicBlock(MBB); 781 } 782 783 // Clear the LiveOuts vectors and collapse any remaining DomainValues. 784 for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator 785 MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) { 786 LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI); 787 if (FI == LiveOuts.end() || !FI->second) 788 continue; 789 for (unsigned i = 0, e = NumRegs; i != e; ++i) 790 if (FI->second[i].Value) 791 release(FI->second[i].Value); 792 delete[] FI->second; 793 } 794 LiveOuts.clear(); 795 UndefReads.clear(); 796 Avail.clear(); 797 Allocator.DestroyAll(); 798 799 return false; 800 } 801 802 FunctionPass * 803 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) { 804 return new ExeDepsFix(RC); 805 } 806