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  /external/ImageMagick/PerlMagick/demo/
single-pixels.pl 9 my $im=Image::Magick->new();
10 $im->Read('logo:');
15 my $skin=$im->Get('pixel[400,200]');
18 $im->Set('pixel[1,1]'=>'0,0,0,0');
19 $im->Set('pixel[2,1]'=>$skin);
20 $im->Set('pixel[3,1]'=>'green');
21 $im->Set('pixel[4,1]'=>'rgb(255,0,255)');
26 my @pixel = $im->GetPixel( x=>400, y=>200 );
36 $im->SetPixel(x=>5,y=>1,color=>\@pixel);
41 $im->Crop(geometry=>'7x3+0+0')
    [all...]
settings.pl 13 my $im = new Image::Magick;
14 my $e = $im->Set(
25 $e = $im->Read("caption:Lorem ipsum etc etc");
28 $e = $im->Trim();
31 $e = $im->Write('settings.png');
lsys.pl 16 $im->Composite(image=>$flower, compose=>'over', geometry=>$geometry);
36 $im->Draw (primitive=>'Polygon', points=>join(' ',@poly),
46 $im = new Image::Magick;
47 $im->Set(size=>$imagesize . 'x' . $imagesize);
48 $im->Read('xc:white');
79 $im->Write($filename);
80 $im->Write('win:');
  /external/u-boot/board/freescale/mpc8315erdb/
sdram.c 43 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
47 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
48 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
49 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
57 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
58 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
61 im->ddr.cs_config[1] = 0;
63 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
64 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
65 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1
96 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/iproute2/lib/
ll_map.c 46 struct ll_cache *im local
48 if (im->index == index)
49 return im;
71 struct ll_cache *im local
74 if (strncmp(im->name, name, IFNAMSIZ) == 0)
75 return im;
87 struct ll_cache *im; local
96 im = ll_get_by_index(ifi->ifi_index);
98 if (im) {
99 hlist_del(&im->name_hash)
142 const struct ll_cache *im; local
166 const struct ll_cache *im; local
177 const struct ll_cache *im; local
188 const struct ll_cache *im; local
    [all...]
  /external/u-boot/board/freescale/mpc8308rdb/
sdram.c 31 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
35 out_be32(&im->sysconf.ddrlaw[0].bar,
37 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
38 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
44 out_be32(&im->ddr.cs_config[1], 0);
46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1)
69 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/board/gdsys/mpc8308/
sdram.c 32 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
36 out_be32(&im->sysconf.ddrlaw[0].bar,
38 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
39 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
41 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
42 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
45 out_be32(&im->ddr.cs_config[1], 0);
47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
48 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1)
70 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/board/mpc8308_p1m/
sdram.c 27 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
31 out_be32(&im->sysconf.ddrlaw[0].bar,
33 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
34 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
36 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
37 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
40 out_be32(&im->ddr.cs_config[1], 0);
42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
43 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1)
65 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/board/freescale/mpc8313erdb/
sdram.c 47 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
50 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
51 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
52 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
63 im->ddr.csbnds[0].csbnds =
67 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
70 im->ddr.cs_config[1] = 0;
72 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
73 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1
101 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/include/
ioports.h 21 * memory map (im) of the set of registers for a port (idx)
27 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
29 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
  /external/u-boot/arch/powerpc/cpu/mpc83xx/
spl_minimal.c 18 void cpu_init_f (volatile immap_t * im)
29 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
35 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
41 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
46 im->sysconf.spcr |= SPCR_TBEN;
50 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
54 im->sysconf.obir = CONFIG_SYS_OBIR
    [all...]
cpu_init.c 48 void cpu_init_f (volatile immap_t * im)
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
218 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
219 __raw_writel(~(RSR_RES), &im->reset.rsr);
222 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
223 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
229 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
234 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val)
    [all...]
  /external/u-boot/drivers/gpio/
mpc83xx_gpio.c 53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
65 clrbits_be32(&im->gpio[ctrlr].dir, line_mask);
73 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
93 setbits_be32(&im->gpio[ctrlr].dir, line_mask);
101 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
114 return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0;
120 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
143 out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]);
151 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
154 out_be32(&im->gpio[0].dir, CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION)
    [all...]
  /external/u-boot/board/freescale/mpc832xemds/
mpc832xemds.c 94 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
97 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
101 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
116 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
128 im->sysconf.ddrlaw[0].ar =
133 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
134 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
135 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
136 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0
    [all...]
  /external/u-boot/board/ve8313/
ve8313.c 37 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
40 out_be32(&im->sysconf.ddrlaw[0].bar,
42 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
43 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
54 out_be32(&im->ddr.csbnds[0].csbnds,
58 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
61 out_be32(&im->ddr.cs_config[1], 0);
63 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
64 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
65 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1)
92 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
118 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
137 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/board/ids/ids8313/
ids8313.c 53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
59 out_be32(&im->sysconf.ddrlaw[0].bar,
61 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
62 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
71 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
72 out_be32(&im->ddr.cs_config[0], config);
75 out_be32(&im->ddr.cs_config[1], 0);
76 out_be32(&im->ddr.cs_config[2], 0);
77 out_be32(&im->ddr.cs_config[3], 0);
79 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3)
123 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/board/freescale/mpc837xerdb/
mpc837xerdb.c 66 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
69 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
94 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
98 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
101 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
104 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
107 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
108 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG
171 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; local
    [all...]
  /device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Demo/classes/
Complex.py 8 # A Complex instance z has two data attribues, z.re (the real part) and z.im
9 # (the imaginary part). In fact, z.re and z.im can have any value -- all
10 # arithmetic operators work regardless of the type of z.re and z.im (as long
14 # Complex([re [,im]) -> creates a complex number from a real and an imaginary part
15 # IsComplex(z) -> true iff z is a complex number (== has .re and .im attributes)
17 # if z is a tuple(re, im) it will also be converted
36 # hash(z) -> a combination of hash(z.re) and hash(z.im) such that if z.im is zero
72 return hasattr(obj, 're') and hasattr(obj, 'im')
91 def Im(obj):
    [all...]
  /external/python/cpython2/Demo/classes/
Complex.py 8 # A Complex instance z has two data attribues, z.re (the real part) and z.im
9 # (the imaginary part). In fact, z.re and z.im can have any value -- all
10 # arithmetic operators work regardless of the type of z.re and z.im (as long
14 # Complex([re [,im]) -> creates a complex number from a real and an imaginary part
15 # IsComplex(z) -> true iff z is a complex number (== has .re and .im attributes)
17 # if z is a tuple(re, im) it will also be converted
36 # hash(z) -> a combination of hash(z.re) and hash(z.im) such that if z.im is zero
72 return hasattr(obj, 're') and hasattr(obj, 'im')
91 def Im(obj)
    [all...]
  /external/u-boot/board/freescale/mpc8349emds/
mpc8349emds.c 52 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
55 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
59 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
89 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
94 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
95 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
101 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
102 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
103 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0
    [all...]
  /external/u-boot/board/freescale/mpc8323erdb/
mpc8323erdb.c 75 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
78 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
82 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
97 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
109 im->sysconf.ddrlaw[0].ar =
111 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
112 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
113 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
114 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0
    [all...]
  /external/u-boot/board/sbc8349/
sbc8349.c 41 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
44 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
48 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
77 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
82 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
83 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
92 im->ddr.csbnds[2].csbnds =
96 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
99 im->ddr.cs_config[0] = 0
    [all...]
  /external/u-boot/board/freescale/mpc8349itx/
mpc8349itx.c 30 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
35 im->sysconf.ddrlaw[0].ar =
37 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
42 im->ddr.csbnds[0].csbnds =
46 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
49 im->ddr.cs_config[1] = 0;
50 im->ddr.cs_config[2] = 0;
51 im->ddr.cs_config[3] = 0;
53 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
54 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0])
122 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
    [all...]
  /external/u-boot/board/freescale/mpc837xemds/
mpc837xemds.c 65 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; local
75 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
76 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
88 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; local
89 u32 rcwh = in_be32(&im->reset.rcwh);
187 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; local
188 u32 rcwh = in_be32(&im->reset.rcwh);
222 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
225 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
251 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
298 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; local
    [all...]
  /external/libaom/libaom/third_party/fastfeat/
fast.c 6 xy* fast9_detect_nonmax(const byte* im, int xsize, int ysize, int stride, int b, int* ret_num_corners)
13 corners = fast9_detect(im, xsize, ysize, stride, b, &num_corners);
14 scores = fast9_score(im, stride, corners, num_corners, b);

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