1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef Hexagon_ISELLOWERING_H 16 #define Hexagon_ISELLOWERING_H 17 18 #include "Hexagon.h" 19 #include "llvm/Target/TargetLowering.h" 20 #include "llvm/CallingConv.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 23 namespace llvm { 24 namespace HexagonISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 CONST32, 29 CONST32_GP, // For marking data present in GP. 30 FCONST32, 31 SETCC, 32 ADJDYNALLOC, 33 ARGEXTEND, 34 35 CMPICC, // Compare two GPR operands, set icc. 36 CMPFCC, // Compare two FP operands, set fcc. 37 BRICC, // Branch to dest on icc condition 38 BRFCC, // Branch to dest on fcc condition 39 SELECT_ICC, // Select between two values using the current ICC flags. 40 SELECT_FCC, // Select between two values using the current FCC flags. 41 42 Hi, Lo, // Hi/Lo operations, typically on a global address. 43 44 FTOI, // FP to Int within a FP register. 45 ITOF, // Int to FP within a FP register. 46 47 CALL, // A call instruction. 48 RET_FLAG, // Return with a flag operand. 49 BR_JT, // Jump table. 50 BARRIER, // Memory barrier. 51 WrapperJT, 52 WrapperCP, 53 TC_RETURN 54 }; 55 } 56 57 class HexagonTargetLowering : public TargetLowering { 58 int VarArgsFrameOffset; // Frame offset to start of varargs area. 59 60 bool CanReturnSmallStruct(const Function* CalleeFn, 61 unsigned& RetSize) const; 62 63 public: 64 HexagonTargetMachine &TM; 65 explicit HexagonTargetLowering(HexagonTargetMachine &targetmachine); 66 67 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 68 /// for tail call optimization. Targets which want to do tail call 69 /// optimization should implement this function. 70 bool 71 IsEligibleForTailCallOptimization(SDValue Callee, 72 CallingConv::ID CalleeCC, 73 bool isVarArg, 74 bool isCalleeStructRet, 75 bool isCallerStructRet, 76 const 77 SmallVectorImpl<ISD::OutputArg> &Outs, 78 const SmallVectorImpl<SDValue> &OutVals, 79 const SmallVectorImpl<ISD::InputArg> &Ins, 80 SelectionDAG& DAG) const; 81 82 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 83 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 84 85 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 86 87 virtual const char *getTargetNodeName(unsigned Opcode) const; 88 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 91 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; 92 SDValue LowerFormalArguments(SDValue Chain, 93 CallingConv::ID CallConv, bool isVarArg, 94 const SmallVectorImpl<ISD::InputArg> &Ins, 95 DebugLoc dl, SelectionDAG &DAG, 96 SmallVectorImpl<SDValue> &InVals) const; 97 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; 98 99 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 100 SmallVectorImpl<SDValue> &InVals) const; 101 102 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 103 CallingConv::ID CallConv, bool isVarArg, 104 const SmallVectorImpl<ISD::InputArg> &Ins, 105 DebugLoc dl, SelectionDAG &DAG, 106 SmallVectorImpl<SDValue> &InVals, 107 const SmallVectorImpl<SDValue> &OutVals, 108 SDValue Callee) const; 109 110 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 112 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const; 113 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 114 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 115 116 SDValue LowerReturn(SDValue Chain, 117 CallingConv::ID CallConv, bool isVarArg, 118 const SmallVectorImpl<ISD::OutputArg> &Outs, 119 const SmallVectorImpl<SDValue> &OutVals, 120 DebugLoc dl, SelectionDAG &DAG) const; 121 122 virtual MachineBasicBlock 123 *EmitInstrWithCustomInserter(MachineInstr *MI, 124 MachineBasicBlock *BB) const; 125 126 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 127 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 128 virtual EVT getSetCCResultType(EVT VT) const { 129 return MVT::i1; 130 } 131 132 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 133 SDValue &Base, SDValue &Offset, 134 ISD::MemIndexedMode &AM, 135 SelectionDAG &DAG) const; 136 137 std::pair<unsigned, const TargetRegisterClass*> 138 getRegForInlineAsmConstraint(const std::string &Constraint, 139 EVT VT) const; 140 141 // Intrinsics 142 virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, 143 SelectionDAG &DAG) const; 144 /// isLegalAddressingMode - Return true if the addressing mode represented 145 /// by AM is legal for this target, for a load/store of the specified type. 146 /// The type may be VoidTy, in which case only return true if the addressing 147 /// mode is legal for a load/store of any legal type. 148 /// TODO: Handle pre/postinc as well. 149 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 150 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 151 152 /// isLegalICmpImmediate - Return true if the specified immediate is legal 153 /// icmp immediate, that is the target has icmp instructions which can 154 /// compare a register against the immediate without having to materialize 155 /// the immediate into a register. 156 virtual bool isLegalICmpImmediate(int64_t Imm) const; 157 }; 158 } // end namespace llvm 159 160 #endif // Hexagon_ISELLOWERING_H 161
