1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "mblaze-lower" 16 #include "MBlazeISelLowering.h" 17 #include "MBlazeMachineFunction.h" 18 #include "MBlazeTargetMachine.h" 19 #include "MBlazeTargetObjectFile.h" 20 #include "MBlazeSubtarget.h" 21 #include "llvm/DerivedTypes.h" 22 #include "llvm/Function.h" 23 #include "llvm/GlobalVariable.h" 24 #include "llvm/Intrinsics.h" 25 #include "llvm/CallingConv.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ErrorHandling.h" 35 #include "llvm/Support/raw_ostream.h" 36 using namespace llvm; 37 38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 39 CCValAssign::LocInfo &LocInfo, 40 ISD::ArgFlagsTy &ArgFlags, 41 CCState &State); 42 43 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const { 44 switch (Opcode) { 45 case MBlazeISD::JmpLink : return "MBlazeISD::JmpLink"; 46 case MBlazeISD::GPRel : return "MBlazeISD::GPRel"; 47 case MBlazeISD::Wrap : return "MBlazeISD::Wrap"; 48 case MBlazeISD::ICmp : return "MBlazeISD::ICmp"; 49 case MBlazeISD::Ret : return "MBlazeISD::Ret"; 50 case MBlazeISD::Select_CC : return "MBlazeISD::Select_CC"; 51 default : return NULL; 52 } 53 } 54 55 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM) 56 : TargetLowering(TM, new MBlazeTargetObjectFile()) { 57 Subtarget = &TM.getSubtarget<MBlazeSubtarget>(); 58 59 // MBlaze does not have i1 type, so use i32 for 60 // setcc operations results (slt, sgt, ...). 61 setBooleanContents(ZeroOrOneBooleanContent); 62 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 63 64 // Set up the register classes 65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass); 66 if (Subtarget->hasFPU()) { 67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass); 68 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 69 } 70 71 // Floating point operations which are not supported 72 setOperationAction(ISD::FREM, MVT::f32, Expand); 73 setOperationAction(ISD::FMA, MVT::f32, Expand); 74 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand); 75 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand); 76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand); 79 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); 80 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 81 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 82 setOperationAction(ISD::FSIN, MVT::f32, Expand); 83 setOperationAction(ISD::FCOS, MVT::f32, Expand); 84 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 85 setOperationAction(ISD::FPOW, MVT::f32, Expand); 86 setOperationAction(ISD::FLOG, MVT::f32, Expand); 87 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 88 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 89 setOperationAction(ISD::FEXP, MVT::f32, Expand); 90 91 // Load extented operations for i1 types must be promoted 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 94 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 95 96 // Sign extended loads must be expanded 97 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 98 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 99 100 // MBlaze has no REM or DIVREM operations. 101 setOperationAction(ISD::UREM, MVT::i32, Expand); 102 setOperationAction(ISD::SREM, MVT::i32, Expand); 103 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 104 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 105 106 // If the processor doesn't support multiply then expand it 107 if (!Subtarget->hasMul()) { 108 setOperationAction(ISD::MUL, MVT::i32, Expand); 109 } 110 111 // If the processor doesn't support 64-bit multiply then expand 112 if (!Subtarget->hasMul() || !Subtarget->hasMul64()) { 113 setOperationAction(ISD::MULHS, MVT::i32, Expand); 114 setOperationAction(ISD::MULHS, MVT::i64, Expand); 115 setOperationAction(ISD::MULHU, MVT::i32, Expand); 116 setOperationAction(ISD::MULHU, MVT::i64, Expand); 117 } 118 119 // If the processor doesn't support division then expand 120 if (!Subtarget->hasDiv()) { 121 setOperationAction(ISD::UDIV, MVT::i32, Expand); 122 setOperationAction(ISD::SDIV, MVT::i32, Expand); 123 } 124 125 // Expand unsupported conversions 126 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 127 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 128 129 // Expand SELECT_CC 130 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 131 132 // MBlaze doesn't have MUL_LOHI 133 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 134 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 135 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 136 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 137 138 // Used by legalize types to correctly generate the setcc result. 139 // Without this, every float setcc comes with a AND/OR with the result, 140 // we don't want this, since the fpcmp result goes to a flag register, 141 // which is used implicitly by brcond and select operations. 142 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 143 AddPromotedToType(ISD::SELECT, MVT::i1, MVT::i32); 144 AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32); 145 146 // MBlaze Custom Operations 147 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 148 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 149 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 150 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 151 152 // Variable Argument support 153 setOperationAction(ISD::VASTART, MVT::Other, Custom); 154 setOperationAction(ISD::VAEND, MVT::Other, Expand); 155 setOperationAction(ISD::VAARG, MVT::Other, Expand); 156 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 157 158 159 // Operations not directly supported by MBlaze. 160 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 161 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 162 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 164 setOperationAction(ISD::ROTL, MVT::i32, Expand); 165 setOperationAction(ISD::ROTR, MVT::i32, Expand); 166 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 169 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 170 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 171 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 172 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 173 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 174 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 175 176 // We don't have line number support yet. 177 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 178 179 // Use the default for now 180 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 181 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 182 183 // MBlaze doesn't have extending float->double load/store 184 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 185 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 186 187 setMinFunctionAlignment(2); 188 189 setStackPointerRegisterToSaveRestore(MBlaze::R1); 190 computeRegisterProperties(); 191 } 192 193 EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const { 194 return MVT::i32; 195 } 196 197 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op, 198 SelectionDAG &DAG) const { 199 switch (Op.getOpcode()) 200 { 201 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 202 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 203 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 204 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 205 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 206 case ISD::VASTART: return LowerVASTART(Op, DAG); 207 } 208 return SDValue(); 209 } 210 211 //===----------------------------------------------------------------------===// 212 // Lower helper functions 213 //===----------------------------------------------------------------------===// 214 MachineBasicBlock* 215 MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 216 MachineBasicBlock *MBB) 217 const { 218 switch (MI->getOpcode()) { 219 default: llvm_unreachable("Unexpected instr type to insert"); 220 221 case MBlaze::ShiftRL: 222 case MBlaze::ShiftRA: 223 case MBlaze::ShiftL: 224 return EmitCustomShift(MI, MBB); 225 226 case MBlaze::Select_FCC: 227 case MBlaze::Select_CC: 228 return EmitCustomSelect(MI, MBB); 229 230 case MBlaze::CAS32: 231 case MBlaze::SWP32: 232 case MBlaze::LAA32: 233 case MBlaze::LAS32: 234 case MBlaze::LAD32: 235 case MBlaze::LAO32: 236 case MBlaze::LAX32: 237 case MBlaze::LAN32: 238 return EmitCustomAtomic(MI, MBB); 239 240 case MBlaze::MEMBARRIER: 241 // The Microblaze does not need memory barriers. Just delete the pseudo 242 // instruction and finish. 243 MI->eraseFromParent(); 244 return MBB; 245 } 246 } 247 248 MachineBasicBlock* 249 MBlazeTargetLowering::EmitCustomShift(MachineInstr *MI, 250 MachineBasicBlock *MBB) const { 251 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 252 DebugLoc dl = MI->getDebugLoc(); 253 254 // To "insert" a shift left instruction, we actually have to insert a 255 // simple loop. The incoming instruction knows the destination vreg to 256 // set, the source vreg to operate over and the shift amount. 257 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 258 MachineFunction::iterator It = MBB; 259 ++It; 260 261 // start: 262 // andi samt, samt, 31 263 // beqid samt, finish 264 // add dst, src, r0 265 // loop: 266 // addik samt, samt, -1 267 // sra dst, dst 268 // bneid samt, loop 269 // nop 270 // finish: 271 MachineFunction *F = MBB->getParent(); 272 MachineRegisterInfo &R = F->getRegInfo(); 273 MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB); 274 MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB); 275 F->insert(It, loop); 276 F->insert(It, finish); 277 278 // Update machine-CFG edges by transferring adding all successors and 279 // remaining instructions from the current block to the new block which 280 // will contain the Phi node for the select. 281 finish->splice(finish->begin(), MBB, 282 llvm::next(MachineBasicBlock::iterator(MI)), 283 MBB->end()); 284 finish->transferSuccessorsAndUpdatePHIs(MBB); 285 286 // Add the true and fallthrough blocks as its successors. 287 MBB->addSuccessor(loop); 288 MBB->addSuccessor(finish); 289 290 // Next, add the finish block as a successor of the loop block 291 loop->addSuccessor(finish); 292 loop->addSuccessor(loop); 293 294 unsigned IAMT = R.createVirtualRegister(&MBlaze::GPRRegClass); 295 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT) 296 .addReg(MI->getOperand(2).getReg()) 297 .addImm(31); 298 299 unsigned IVAL = R.createVirtualRegister(&MBlaze::GPRRegClass); 300 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL) 301 .addReg(MI->getOperand(1).getReg()) 302 .addImm(0); 303 304 BuildMI(MBB, dl, TII->get(MBlaze::BEQID)) 305 .addReg(IAMT) 306 .addMBB(finish); 307 308 unsigned DST = R.createVirtualRegister(&MBlaze::GPRRegClass); 309 unsigned NDST = R.createVirtualRegister(&MBlaze::GPRRegClass); 310 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST) 311 .addReg(IVAL).addMBB(MBB) 312 .addReg(NDST).addMBB(loop); 313 314 unsigned SAMT = R.createVirtualRegister(&MBlaze::GPRRegClass); 315 unsigned NAMT = R.createVirtualRegister(&MBlaze::GPRRegClass); 316 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT) 317 .addReg(IAMT).addMBB(MBB) 318 .addReg(NAMT).addMBB(loop); 319 320 if (MI->getOpcode() == MBlaze::ShiftL) 321 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST); 322 else if (MI->getOpcode() == MBlaze::ShiftRA) 323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST); 324 else if (MI->getOpcode() == MBlaze::ShiftRL) 325 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST); 326 else 327 llvm_unreachable("Cannot lower unknown shift instruction"); 328 329 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT) 330 .addReg(SAMT) 331 .addImm(-1); 332 333 BuildMI(loop, dl, TII->get(MBlaze::BNEID)) 334 .addReg(NAMT) 335 .addMBB(loop); 336 337 BuildMI(*finish, finish->begin(), dl, 338 TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) 339 .addReg(IVAL).addMBB(MBB) 340 .addReg(NDST).addMBB(loop); 341 342 // The pseudo instruction is no longer needed so remove it 343 MI->eraseFromParent(); 344 return finish; 345 } 346 347 MachineBasicBlock* 348 MBlazeTargetLowering::EmitCustomSelect(MachineInstr *MI, 349 MachineBasicBlock *MBB) const { 350 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 351 DebugLoc dl = MI->getDebugLoc(); 352 353 // To "insert" a SELECT_CC instruction, we actually have to insert the 354 // diamond control-flow pattern. The incoming instruction knows the 355 // destination vreg to set, the condition code register to branch on, the 356 // true/false values to select between, and a branch opcode to use. 357 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 358 MachineFunction::iterator It = MBB; 359 ++It; 360 361 // thisMBB: 362 // ... 363 // TrueVal = ... 364 // setcc r1, r2, r3 365 // bNE r1, r0, copy1MBB 366 // fallthrough --> copy0MBB 367 MachineFunction *F = MBB->getParent(); 368 MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB); 369 MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB); 370 371 unsigned Opc; 372 switch (MI->getOperand(4).getImm()) { 373 default: llvm_unreachable("Unknown branch condition"); 374 case MBlazeCC::EQ: Opc = MBlaze::BEQID; break; 375 case MBlazeCC::NE: Opc = MBlaze::BNEID; break; 376 case MBlazeCC::GT: Opc = MBlaze::BGTID; break; 377 case MBlazeCC::LT: Opc = MBlaze::BLTID; break; 378 case MBlazeCC::GE: Opc = MBlaze::BGEID; break; 379 case MBlazeCC::LE: Opc = MBlaze::BLEID; break; 380 } 381 382 F->insert(It, flsBB); 383 F->insert(It, dneBB); 384 385 // Transfer the remainder of MBB and its successor edges to dneBB. 386 dneBB->splice(dneBB->begin(), MBB, 387 llvm::next(MachineBasicBlock::iterator(MI)), 388 MBB->end()); 389 dneBB->transferSuccessorsAndUpdatePHIs(MBB); 390 391 MBB->addSuccessor(flsBB); 392 MBB->addSuccessor(dneBB); 393 flsBB->addSuccessor(dneBB); 394 395 BuildMI(MBB, dl, TII->get(Opc)) 396 .addReg(MI->getOperand(3).getReg()) 397 .addMBB(dneBB); 398 399 // sinkMBB: 400 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 401 // ... 402 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) 403 // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB) 404 // .addReg(MI->getOperand(2).getReg()).addMBB(BB); 405 406 BuildMI(*dneBB, dneBB->begin(), dl, 407 TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) 408 .addReg(MI->getOperand(2).getReg()).addMBB(flsBB) 409 .addReg(MI->getOperand(1).getReg()).addMBB(MBB); 410 411 MI->eraseFromParent(); // The pseudo instruction is gone now. 412 return dneBB; 413 } 414 415 MachineBasicBlock* 416 MBlazeTargetLowering::EmitCustomAtomic(MachineInstr *MI, 417 MachineBasicBlock *MBB) const { 418 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 419 DebugLoc dl = MI->getDebugLoc(); 420 421 // All atomic instructions on the Microblaze are implemented using the 422 // load-linked / store-conditional style atomic instruction sequences. 423 // Thus, all operations will look something like the following: 424 // 425 // start: 426 // lwx RV, RP, 0 427 // <do stuff> 428 // swx RV, RP, 0 429 // addic RC, R0, 0 430 // bneid RC, start 431 // 432 // exit: 433 // 434 // To "insert" a shift left instruction, we actually have to insert a 435 // simple loop. The incoming instruction knows the destination vreg to 436 // set, the source vreg to operate over and the shift amount. 437 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 438 MachineFunction::iterator It = MBB; 439 ++It; 440 441 // start: 442 // andi samt, samt, 31 443 // beqid samt, finish 444 // add dst, src, r0 445 // loop: 446 // addik samt, samt, -1 447 // sra dst, dst 448 // bneid samt, loop 449 // nop 450 // finish: 451 MachineFunction *F = MBB->getParent(); 452 MachineRegisterInfo &R = F->getRegInfo(); 453 454 // Create the start and exit basic blocks for the atomic operation 455 MachineBasicBlock *start = F->CreateMachineBasicBlock(LLVM_BB); 456 MachineBasicBlock *exit = F->CreateMachineBasicBlock(LLVM_BB); 457 F->insert(It, start); 458 F->insert(It, exit); 459 460 // Update machine-CFG edges by transferring adding all successors and 461 // remaining instructions from the current block to the new block which 462 // will contain the Phi node for the select. 463 exit->splice(exit->begin(), MBB, llvm::next(MachineBasicBlock::iterator(MI)), 464 MBB->end()); 465 exit->transferSuccessorsAndUpdatePHIs(MBB); 466 467 // Add the fallthrough block as its successors. 468 MBB->addSuccessor(start); 469 470 BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg()) 471 .addReg(MI->getOperand(1).getReg()) 472 .addReg(MBlaze::R0); 473 474 MachineBasicBlock *final = start; 475 unsigned finalReg = 0; 476 477 switch (MI->getOpcode()) { 478 default: llvm_unreachable("Cannot lower unknown atomic instruction!"); 479 480 case MBlaze::SWP32: 481 finalReg = MI->getOperand(2).getReg(); 482 start->addSuccessor(exit); 483 start->addSuccessor(start); 484 break; 485 486 case MBlaze::LAN32: 487 case MBlaze::LAX32: 488 case MBlaze::LAO32: 489 case MBlaze::LAD32: 490 case MBlaze::LAS32: 491 case MBlaze::LAA32: { 492 unsigned opcode = 0; 493 switch (MI->getOpcode()) { 494 default: llvm_unreachable("Cannot lower unknown atomic load!"); 495 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break; 496 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break; 497 case MBlaze::LAD32: opcode = MBlaze::AND; break; 498 case MBlaze::LAO32: opcode = MBlaze::OR; break; 499 case MBlaze::LAX32: opcode = MBlaze::XOR; break; 500 case MBlaze::LAN32: opcode = MBlaze::AND; break; 501 } 502 503 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass); 504 start->addSuccessor(exit); 505 start->addSuccessor(start); 506 507 BuildMI(start, dl, TII->get(opcode), finalReg) 508 .addReg(MI->getOperand(0).getReg()) 509 .addReg(MI->getOperand(2).getReg()); 510 511 if (MI->getOpcode() == MBlaze::LAN32) { 512 unsigned tmp = finalReg; 513 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass); 514 BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg) 515 .addReg(tmp) 516 .addImm(-1); 517 } 518 break; 519 } 520 521 case MBlaze::CAS32: { 522 finalReg = MI->getOperand(3).getReg(); 523 final = F->CreateMachineBasicBlock(LLVM_BB); 524 525 F->insert(It, final); 526 start->addSuccessor(exit); 527 start->addSuccessor(final); 528 final->addSuccessor(exit); 529 final->addSuccessor(start); 530 531 unsigned CMP = R.createVirtualRegister(&MBlaze::GPRRegClass); 532 BuildMI(start, dl, TII->get(MBlaze::CMP), CMP) 533 .addReg(MI->getOperand(0).getReg()) 534 .addReg(MI->getOperand(2).getReg()); 535 536 BuildMI(start, dl, TII->get(MBlaze::BNEID)) 537 .addReg(CMP) 538 .addMBB(exit); 539 540 final->moveAfter(start); 541 exit->moveAfter(final); 542 break; 543 } 544 } 545 546 unsigned CHK = R.createVirtualRegister(&MBlaze::GPRRegClass); 547 BuildMI(final, dl, TII->get(MBlaze::SWX)) 548 .addReg(finalReg) 549 .addReg(MI->getOperand(1).getReg()) 550 .addReg(MBlaze::R0); 551 552 BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK) 553 .addReg(MBlaze::R0) 554 .addImm(0); 555 556 BuildMI(final, dl, TII->get(MBlaze::BNEID)) 557 .addReg(CHK) 558 .addMBB(start); 559 560 // The pseudo instruction is no longer needed so remove it 561 MI->eraseFromParent(); 562 return exit; 563 } 564 565 //===----------------------------------------------------------------------===// 566 // Misc Lower Operation implementation 567 //===----------------------------------------------------------------------===// 568 // 569 570 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op, 571 SelectionDAG &DAG) const { 572 SDValue LHS = Op.getOperand(0); 573 SDValue RHS = Op.getOperand(1); 574 SDValue TrueVal = Op.getOperand(2); 575 SDValue FalseVal = Op.getOperand(3); 576 DebugLoc dl = Op.getDebugLoc(); 577 unsigned Opc; 578 579 SDValue CompareFlag; 580 if (LHS.getValueType() == MVT::i32) { 581 Opc = MBlazeISD::Select_CC; 582 CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS) 583 .getValue(1); 584 } else { 585 llvm_unreachable("Cannot lower select_cc with unknown type"); 586 } 587 588 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 589 CompareFlag); 590 } 591 592 SDValue MBlazeTargetLowering:: 593 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 594 // FIXME there isn't actually debug info here 595 DebugLoc dl = Op.getDebugLoc(); 596 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 597 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 598 599 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA); 600 } 601 602 SDValue MBlazeTargetLowering:: 603 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 604 llvm_unreachable("TLS not implemented for MicroBlaze."); 605 } 606 607 SDValue MBlazeTargetLowering:: 608 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 609 SDValue ResNode; 610 SDValue HiPart; 611 // FIXME there isn't actually debug info here 612 DebugLoc dl = Op.getDebugLoc(); 613 614 EVT PtrVT = Op.getValueType(); 615 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 616 617 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0); 618 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI); 619 } 620 621 SDValue MBlazeTargetLowering:: 622 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 623 SDValue ResNode; 624 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 625 const Constant *C = N->getConstVal(); 626 DebugLoc dl = Op.getDebugLoc(); 627 628 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 629 N->getOffset(), 0); 630 return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP); 631 } 632 633 SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op, 634 SelectionDAG &DAG) const { 635 MachineFunction &MF = DAG.getMachineFunction(); 636 MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>(); 637 638 DebugLoc dl = Op.getDebugLoc(); 639 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 640 getPointerTy()); 641 642 // vastart just stores the address of the VarArgsFrameIndex slot into the 643 // memory location argument. 644 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 645 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 646 MachinePointerInfo(SV), 647 false, false, 0); 648 } 649 650 //===----------------------------------------------------------------------===// 651 // Calling Convention Implementation 652 //===----------------------------------------------------------------------===// 653 654 #include "MBlazeGenCallingConv.inc" 655 656 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 657 CCValAssign::LocInfo &LocInfo, 658 ISD::ArgFlagsTy &ArgFlags, 659 CCState &State) { 660 static const uint16_t ArgRegs[] = { 661 MBlaze::R5, MBlaze::R6, MBlaze::R7, 662 MBlaze::R8, MBlaze::R9, MBlaze::R10 663 }; 664 665 const unsigned NumArgRegs = array_lengthof(ArgRegs); 666 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); 667 if (!Reg) return false; 668 669 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 670 State.AllocateStack(SizeInBytes, SizeInBytes); 671 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 672 673 return true; 674 } 675 676 //===----------------------------------------------------------------------===// 677 // Call Calling Convention Implementation 678 //===----------------------------------------------------------------------===// 679 680 /// LowerCall - functions arguments are copied from virtual regs to 681 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 682 /// TODO: isVarArg, isTailCall. 683 SDValue MBlazeTargetLowering:: 684 LowerCall(TargetLowering::CallLoweringInfo &CLI, 685 SmallVectorImpl<SDValue> &InVals) const { 686 SelectionDAG &DAG = CLI.DAG; 687 DebugLoc &dl = CLI.DL; 688 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 689 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 690 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 691 SDValue Chain = CLI.Chain; 692 SDValue Callee = CLI.Callee; 693 bool &isTailCall = CLI.IsTailCall; 694 CallingConv::ID CallConv = CLI.CallConv; 695 bool isVarArg = CLI.IsVarArg; 696 697 // MBlaze does not yet support tail call optimization 698 isTailCall = false; 699 700 // The MBlaze requires stack slots for arguments passed to var arg 701 // functions even if they are passed in registers. 702 bool needsRegArgSlots = isVarArg; 703 704 MachineFunction &MF = DAG.getMachineFunction(); 705 MachineFrameInfo *MFI = MF.getFrameInfo(); 706 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); 707 708 // Analyze operands of the call, assigning locations to each operand. 709 SmallVector<CCValAssign, 16> ArgLocs; 710 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 711 getTargetMachine(), ArgLocs, *DAG.getContext()); 712 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze); 713 714 // Get a count of how many bytes are to be pushed on the stack. 715 unsigned NumBytes = CCInfo.getNextStackOffset(); 716 717 // Variable argument function calls require a minimum of 24-bytes of stack 718 if (isVarArg && NumBytes < 24) NumBytes = 24; 719 720 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 721 722 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 723 SmallVector<SDValue, 8> MemOpChains; 724 725 // Walk the register/memloc assignments, inserting copies/loads. 726 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 727 CCValAssign &VA = ArgLocs[i]; 728 MVT RegVT = VA.getLocVT(); 729 SDValue Arg = OutVals[i]; 730 731 // Promote the value if needed. 732 switch (VA.getLocInfo()) { 733 default: llvm_unreachable("Unknown loc info!"); 734 case CCValAssign::Full: break; 735 case CCValAssign::SExt: 736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 737 break; 738 case CCValAssign::ZExt: 739 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 740 break; 741 case CCValAssign::AExt: 742 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 743 break; 744 } 745 746 // Arguments that can be passed on register must be kept at 747 // RegsToPass vector 748 if (VA.isRegLoc()) { 749 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 750 } else { 751 // Register can't get to this point... 752 assert(VA.isMemLoc()); 753 754 // Since we are alread passing values on the stack we don't 755 // need to worry about creating additional slots for the 756 // values passed via registers. 757 needsRegArgSlots = false; 758 759 // Create the frame index object for this incoming parameter 760 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; 761 unsigned StackLoc = VA.getLocMemOffset() + 4; 762 int FI = MFI->CreateFixedObject(ArgSize, StackLoc, true); 763 764 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 765 766 // emit ISD::STORE whichs stores the 767 // parameter value to a stack Location 768 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 769 MachinePointerInfo(), 770 false, false, 0)); 771 } 772 } 773 774 // If we need to reserve stack space for the arguments passed via registers 775 // then create a fixed stack object at the beginning of the stack. 776 if (needsRegArgSlots && TFI.hasReservedCallFrame(MF)) 777 MFI->CreateFixedObject(28,0,true); 778 779 // Transform all store nodes into one single node because all store 780 // nodes are independent of each other. 781 if (!MemOpChains.empty()) 782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 783 &MemOpChains[0], MemOpChains.size()); 784 785 // Build a sequence of copy-to-reg nodes chained together with token 786 // chain and flag operands which copy the outgoing args into registers. 787 // The InFlag in necessary since all emitted instructions must be 788 // stuck together. 789 SDValue InFlag; 790 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 791 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 792 RegsToPass[i].second, InFlag); 793 InFlag = Chain.getValue(1); 794 } 795 796 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 797 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 798 // node so that legalize doesn't hack it. 799 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 800 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 801 getPointerTy(), 0, 0); 802 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 803 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 804 getPointerTy(), 0); 805 806 // MBlazeJmpLink = #chain, #target_address, #opt_in_flags... 807 // = Chain, Callee, Reg#1, Reg#2, ... 808 // 809 // Returns a chain & a flag for retval copy to use. 810 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 811 SmallVector<SDValue, 8> Ops; 812 Ops.push_back(Chain); 813 Ops.push_back(Callee); 814 815 // Add argument registers to the end of the list so that they are 816 // known live into the call. 817 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 818 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 819 RegsToPass[i].second.getValueType())); 820 } 821 822 if (InFlag.getNode()) 823 Ops.push_back(InFlag); 824 825 Chain = DAG.getNode(MBlazeISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 826 InFlag = Chain.getValue(1); 827 828 // Create the CALLSEQ_END node. 829 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 830 DAG.getIntPtrConstant(0, true), InFlag); 831 if (!Ins.empty()) 832 InFlag = Chain.getValue(1); 833 834 // Handle result values, copying them out of physregs into vregs that we 835 // return. 836 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 837 Ins, dl, DAG, InVals); 838 } 839 840 /// LowerCallResult - Lower the result values of a call into the 841 /// appropriate copies out of appropriate physical registers. 842 SDValue MBlazeTargetLowering:: 843 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, 844 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, 845 DebugLoc dl, SelectionDAG &DAG, 846 SmallVectorImpl<SDValue> &InVals) const { 847 // Assign locations to each value returned by this call. 848 SmallVector<CCValAssign, 16> RVLocs; 849 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 850 getTargetMachine(), RVLocs, *DAG.getContext()); 851 852 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze); 853 854 // Copy all of the result registers out of their specified physreg. 855 for (unsigned i = 0; i != RVLocs.size(); ++i) { 856 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 857 RVLocs[i].getValVT(), InFlag).getValue(1); 858 InFlag = Chain.getValue(2); 859 InVals.push_back(Chain.getValue(0)); 860 } 861 862 return Chain; 863 } 864 865 //===----------------------------------------------------------------------===// 866 // Formal Arguments Calling Convention Implementation 867 //===----------------------------------------------------------------------===// 868 869 /// LowerFormalArguments - transform physical registers into 870 /// virtual registers and generate load operations for 871 /// arguments places on the stack. 872 SDValue MBlazeTargetLowering:: 873 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 874 const SmallVectorImpl<ISD::InputArg> &Ins, 875 DebugLoc dl, SelectionDAG &DAG, 876 SmallVectorImpl<SDValue> &InVals) const { 877 MachineFunction &MF = DAG.getMachineFunction(); 878 MachineFrameInfo *MFI = MF.getFrameInfo(); 879 MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>(); 880 881 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 882 MBlazeFI->setVarArgsFrameIndex(0); 883 884 // Used with vargs to acumulate store chains. 885 std::vector<SDValue> OutChains; 886 887 // Keep track of the last register used for arguments 888 unsigned ArgRegEnd = 0; 889 890 // Assign locations to all of the incoming arguments. 891 SmallVector<CCValAssign, 16> ArgLocs; 892 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 893 getTargetMachine(), ArgLocs, *DAG.getContext()); 894 895 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze); 896 SDValue StackPtr; 897 898 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 899 CCValAssign &VA = ArgLocs[i]; 900 901 // Arguments stored on registers 902 if (VA.isRegLoc()) { 903 MVT RegVT = VA.getLocVT(); 904 ArgRegEnd = VA.getLocReg(); 905 const TargetRegisterClass *RC; 906 907 if (RegVT == MVT::i32) 908 RC = &MBlaze::GPRRegClass; 909 else if (RegVT == MVT::f32) 910 RC = &MBlaze::GPRRegClass; 911 else 912 llvm_unreachable("RegVT not supported by LowerFormalArguments"); 913 914 // Transform the arguments stored on 915 // physical registers into virtual ones 916 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC); 917 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 918 919 // If this is an 8 or 16-bit value, it has been passed promoted 920 // to 32 bits. Insert an assert[sz]ext to capture this, then 921 // truncate to the right size. If if is a floating point value 922 // then convert to the correct type. 923 if (VA.getLocInfo() != CCValAssign::Full) { 924 unsigned Opcode = 0; 925 if (VA.getLocInfo() == CCValAssign::SExt) 926 Opcode = ISD::AssertSext; 927 else if (VA.getLocInfo() == CCValAssign::ZExt) 928 Opcode = ISD::AssertZext; 929 if (Opcode) 930 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 931 DAG.getValueType(VA.getValVT())); 932 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 933 } 934 935 InVals.push_back(ArgValue); 936 } else { // VA.isRegLoc() 937 // sanity check 938 assert(VA.isMemLoc()); 939 940 // The last argument is not a register 941 ArgRegEnd = 0; 942 943 // The stack pointer offset is relative to the caller stack frame. 944 // Since the real stack size is unknown here, a negative SPOffset 945 // is used so there's a way to adjust these offsets when the stack 946 // size get known (on EliminateFrameIndex). A dummy SPOffset is 947 // used instead of a direct negative address (which is recorded to 948 // be used on emitPrologue) to avoid mis-calc of the first stack 949 // offset on PEI::calculateFrameObjectOffsets. 950 // Arguments are always 32-bit. 951 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 952 unsigned StackLoc = VA.getLocMemOffset() + 4; 953 int FI = MFI->CreateFixedObject(ArgSize, 0, true); 954 MBlazeFI->recordLoadArgsFI(FI, -StackLoc); 955 MBlazeFI->recordLiveIn(FI); 956 957 // Create load nodes to retrieve arguments from the stack 958 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 959 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 960 MachinePointerInfo::getFixedStack(FI), 961 false, false, false, 0)); 962 } 963 } 964 965 // To meet ABI, when VARARGS are passed on registers, the registers 966 // must have their values written to the caller stack frame. If the last 967 // argument was placed in the stack, there's no need to save any register. 968 if ((isVarArg) && ArgRegEnd) { 969 if (StackPtr.getNode() == 0) 970 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 971 972 // The last register argument that must be saved is MBlaze::R10 973 const TargetRegisterClass *RC = &MBlaze::GPRRegClass; 974 975 unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5); 976 unsigned Start = getMBlazeRegisterNumbering(ArgRegEnd+1); 977 unsigned End = getMBlazeRegisterNumbering(MBlaze::R10); 978 unsigned StackLoc = Start - Begin + 1; 979 980 for (; Start <= End; ++Start, ++StackLoc) { 981 unsigned Reg = getMBlazeRegisterFromNumbering(Start); 982 unsigned LiveReg = MF.addLiveIn(Reg, RC); 983 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32); 984 985 int FI = MFI->CreateFixedObject(4, 0, true); 986 MBlazeFI->recordStoreVarArgsFI(FI, -(StackLoc*4)); 987 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 988 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 989 MachinePointerInfo(), 990 false, false, 0)); 991 992 // Record the frame index of the first variable argument 993 // which is a value necessary to VASTART. 994 if (!MBlazeFI->getVarArgsFrameIndex()) 995 MBlazeFI->setVarArgsFrameIndex(FI); 996 } 997 } 998 999 // All stores are grouped in one node to allow the matching between 1000 // the size of Ins and InVals. This only happens when on varg functions 1001 if (!OutChains.empty()) { 1002 OutChains.push_back(Chain); 1003 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1004 &OutChains[0], OutChains.size()); 1005 } 1006 1007 return Chain; 1008 } 1009 1010 //===----------------------------------------------------------------------===// 1011 // Return Value Calling Convention Implementation 1012 //===----------------------------------------------------------------------===// 1013 1014 SDValue MBlazeTargetLowering:: 1015 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1016 const SmallVectorImpl<ISD::OutputArg> &Outs, 1017 const SmallVectorImpl<SDValue> &OutVals, 1018 DebugLoc dl, SelectionDAG &DAG) const { 1019 // CCValAssign - represent the assignment of 1020 // the return value to a location 1021 SmallVector<CCValAssign, 16> RVLocs; 1022 1023 // CCState - Info about the registers and stack slot. 1024 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1025 getTargetMachine(), RVLocs, *DAG.getContext()); 1026 1027 // Analize return values. 1028 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze); 1029 1030 // If this is the first return lowered for this function, add 1031 // the regs to the liveout set for the function. 1032 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1033 for (unsigned i = 0; i != RVLocs.size(); ++i) 1034 if (RVLocs[i].isRegLoc()) 1035 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1036 } 1037 1038 SDValue Flag; 1039 1040 // Copy the result values into the output registers. 1041 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1042 CCValAssign &VA = RVLocs[i]; 1043 assert(VA.isRegLoc() && "Can only return in registers!"); 1044 1045 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1046 OutVals[i], Flag); 1047 1048 // guarantee that all emitted copies are 1049 // stuck together, avoiding something bad 1050 Flag = Chain.getValue(1); 1051 } 1052 1053 // If this function is using the interrupt_handler calling convention 1054 // then use "rtid r14, 0" otherwise use "rtsd r15, 8" 1055 unsigned Ret = (CallConv == CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet 1056 : MBlazeISD::Ret; 1057 unsigned Reg = (CallConv == CallingConv::MBLAZE_INTR) ? MBlaze::R14 1058 : MBlaze::R15; 1059 SDValue DReg = DAG.getRegister(Reg, MVT::i32); 1060 1061 if (Flag.getNode()) 1062 return DAG.getNode(Ret, dl, MVT::Other, Chain, DReg, Flag); 1063 1064 return DAG.getNode(Ret, dl, MVT::Other, Chain, DReg); 1065 } 1066 1067 //===----------------------------------------------------------------------===// 1068 // MBlaze Inline Assembly Support 1069 //===----------------------------------------------------------------------===// 1070 1071 /// getConstraintType - Given a constraint letter, return the type of 1072 /// constraint it is for this target. 1073 MBlazeTargetLowering::ConstraintType MBlazeTargetLowering:: 1074 getConstraintType(const std::string &Constraint) const 1075 { 1076 // MBlaze specific constrainy 1077 // 1078 // 'd' : An address register. Equivalent to r. 1079 // 'y' : Equivalent to r; retained for 1080 // backwards compatibility. 1081 // 'f' : Floating Point registers. 1082 if (Constraint.size() == 1) { 1083 switch (Constraint[0]) { 1084 default : break; 1085 case 'd': 1086 case 'y': 1087 case 'f': 1088 return C_RegisterClass; 1089 } 1090 } 1091 return TargetLowering::getConstraintType(Constraint); 1092 } 1093 1094 /// Examine constraint type and operand type and determine a weight value. 1095 /// This object must already have been set up with the operand type 1096 /// and the current alternative constraint selected. 1097 TargetLowering::ConstraintWeight 1098 MBlazeTargetLowering::getSingleConstraintMatchWeight( 1099 AsmOperandInfo &info, const char *constraint) const { 1100 ConstraintWeight weight = CW_Invalid; 1101 Value *CallOperandVal = info.CallOperandVal; 1102 // If we don't have a value, we can't do a match, 1103 // but allow it at the lowest weight. 1104 if (CallOperandVal == NULL) 1105 return CW_Default; 1106 Type *type = CallOperandVal->getType(); 1107 // Look at the constraint type. 1108 switch (*constraint) { 1109 default: 1110 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1111 break; 1112 case 'd': 1113 case 'y': 1114 if (type->isIntegerTy()) 1115 weight = CW_Register; 1116 break; 1117 case 'f': 1118 if (type->isFloatTy()) 1119 weight = CW_Register; 1120 break; 1121 } 1122 return weight; 1123 } 1124 1125 /// Given a register class constraint, like 'r', if this corresponds directly 1126 /// to an LLVM register class, return a register of 0 and the register class 1127 /// pointer. 1128 std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering:: 1129 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { 1130 if (Constraint.size() == 1) { 1131 switch (Constraint[0]) { 1132 case 'r': 1133 return std::make_pair(0U, &MBlaze::GPRRegClass); 1134 // TODO: These can't possibly be right, but match what was in 1135 // getRegClassForInlineAsmConstraint. 1136 case 'd': 1137 case 'y': 1138 case 'f': 1139 if (VT == MVT::f32) 1140 return std::make_pair(0U, &MBlaze::GPRRegClass); 1141 } 1142 } 1143 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1144 } 1145 1146 bool MBlazeTargetLowering:: 1147 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1148 // The MBlaze target isn't yet aware of offsets. 1149 return false; 1150 } 1151 1152 bool MBlazeTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1153 return VT != MVT::f32; 1154 } 1155
