| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 46 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
49 setOperationAction(ISD::ADD, VecTys[i], Legal);
50 setOperationAction(ISD::SUB, VecTys[i], Legal);
51 setOperationAction(ISD::LOAD, VecTys[i], Legal);
52 setOperationAction(ISD::STORE, VecTys[i], Legal);
53 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
65 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
66 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
67 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
70 setTargetDAGCombine(ISD::SHL)
[all...] |
| MipsISelLowering.cpp | 107 return DAG.getNode(ISD::ADD, DL, Ty,
124 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
143 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
226 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
241 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom)
[all...] |
| Mips16ISelDAGToDAG.cpp | 130 case ISD::LOAD: {
141 case ISD::STORE: {
180 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
181 Addr.getOpcode() == ISD::TargetGlobalAddress))
203 if (Addr.getOpcode() == ISD::ADD) {
252 case ISD::SUBE:
253 case ISD::ADDE: {
256 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
257 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 591 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
592 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
593 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
594 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
595 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
596 CCs[RTLIB::UNE_F32] = ISD::SETNE;
597 CCs[RTLIB::UNE_F64] = ISD::SETNE;
598 CCs[RTLIB::UNE_F128] = ISD::SETNE;
599 CCs[RTLIB::OGE_F32] = ISD::SETGE
[all...] |
| Analysis.cpp | 146 /// getFCmpCondCode - Return the ISD condition code corresponding to
150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
152 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE;
153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ;
154 case FCmpInst::FCMP_OGT: return ISD::SETOGT;
155 case FCmpInst::FCMP_OGE: return ISD::SETOGE;
156 case FCmpInst::FCMP_OLT: return ISD::SETOLT;
157 case FCmpInst::FCMP_OLE: return ISD::SETOLE;
158 case FCmpInst::FCMP_ONE: return ISD::SETONE;
159 case FCmpInst::FCMP_ORD: return ISD::SETO
[all...] |
| CallingConvLower.cpp | 45 ISD::ArgFlagsTy ArgFlags) {
67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
73 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
123 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
137 SmallVectorImpl<ISD::ArgFlagsTy> &Flags
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 62 namespace ISD {
74 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
79 /// and all operands of the specified node are ISD::UNDEF.
81 } // end llvm:ISD namespace
367 /// are the opcode values in the ISD and <target>ISD namespaces. For
372 /// \<target\>ISD namespace).
373 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
376 /// memory-referencing opcode (in the \<target\>ISD namespace and
379 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 60 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
61 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
62 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
63 case ISD::ConstantFP:
66 case ISD::EXTRACT_VECTOR_ELT:
68 case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
69 case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
70 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
71 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break;
72 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break
[all...] |
| SelectionDAG.cpp | 92 // ISD Namespace
97 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
99 if (N->getOpcode() == ISD::BITCAST)
102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
107 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
137 N->getOperand(i).getOpcode() != ISD::UNDEF)
145 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
147 if (N->getOpcode() == ISD::BITCAST)
150 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
155 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF
[all...] |
| SelectionDAGBuilder.cpp | 98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
104 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
135 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
136 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
157 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
160 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo)
[all...] |
| LegalizeTypesGeneric.cpp | 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
82 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
84 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 38 ISD::ArgFlagsTy ArgFlags, Hexagon_CCState &State,
77 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
79 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
82 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
84 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
87 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
89 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
96 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
99 /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node,
101 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins
[all...] |
| HexagonCallingConvLower.cpp | 43 ISD::ArgFlagsTy ArgFlags) {
63 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
66 Hexagon_CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg>
82 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
91 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
128 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
131 Hexagon_CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg>
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags
[all...] |
| HexagonISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
90 SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
110 const SmallVectorImpl<ISD::InputArg> &Ins,
121 const SmallVectorImpl<ISD::InputArg> &Ins,
134 const SmallVectorImpl<ISD::OutputArg> &Outs,
150 ISD::MemIndexedMode &AM,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal)
[all...] |
| PPCISelLowering.h | 30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
253 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
348 /// getSetCCResultType - Return the ISD::SETCC ValueType
356 ISD::MemIndexedMode &AM,
481 const SmallVectorImpl<ISD::InputArg> &Ins,
527 const SmallVectorImpl<ISD::InputArg> &Ins,
538 const SmallVectorImpl<ISD::InputArg> &Ins,
544 const SmallVectorImpl<ISD::InputArg> &Ins,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
561 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 29 setOperationAction(ISD::MUL, MVT::i64, Expand);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
38 setOperationAction(ISD::FSUB, MVT::f32, Expand);
40 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 29 setOperationAction(ISD::MUL, MVT::i64, Expand);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
38 setOperationAction(ISD::FSUB, MVT::f32, Expand);
40 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
42 setOperationAction(ISD::FADD, MVT::v2f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
44 setOperationAction(ISD::FMUL, MVT::v2f32, Expand);
45 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
46 setOperationAction(ISD::FDIV, MVT::v2f32, Expand);
47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
48 setOperationAction(ISD::FSUB, MVT::v2f32, Expand);
50 setOperationAction(ISD::FCOS, MVT::f32, Custom);
51 setOperationAction(ISD::FSIN, MVT::f32, Custom)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 89 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91 setOperationAction(ISD::ADDC, MVT::i32, Expand);
92 setOperationAction(ISD::ADDE, MVT::i32, Expand);
93 setOperationAction(ISD::SUBC, MVT::i32, Expand);
94 setOperationAction(ISD::SUBE, MVT::i32, Expand);
97 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
100 setOperationAction(ISD::ADD, MVT::i64, Custom);
101 setOperationAction(ISD::SUB, MVT::i64, Custom);
102 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 133 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
134 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
135 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
136 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
137 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
138 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
139 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
140 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 82 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
83 Addr.getOpcode() == ISD::TargetGlobalAddress)
86 if (Addr.getOpcode() == ISD::ADD) {
118 if (Addr.getOpcode() == ISD::FrameIndex) return false;
119 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
120 Addr.getOpcode() == ISD::TargetGlobalAddress)
123 if (Addr.getOpcode() == ISD::ADD) {
150 case ISD::SDIV:
151 case ISD::UDIV: {
161 if (N->getOpcode() == ISD::SDIV)
[all...] |
| SparcISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
80 const SmallVectorImpl<ISD::InputArg> &Ins,
86 const SmallVectorImpl<ISD::InputArg> &Ins,
92 const SmallVectorImpl<ISD::InputArg> &Ins,
107 const SmallVectorImpl<ISD::OutputArg> &Outs,
112 const SmallVectorImpl<ISD::OutputArg> &Outs,
117 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::InputArg> &Ins,
140 const SmallVectorImpl<ISD::InputArg> &Ins,
147 const SmallVectorImpl<ISD::InputArg> &Ins,
154 const SmallVectorImpl<ISD::InputArg> &Ins,
164 const SmallVectorImpl<ISD::OutputArg> &Outs,
171 ISD::MemIndexedMode &AM,
|
