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      1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "ARMFPUName.h"
     11 #include "ARMFeatures.h"
     12 #include "MCTargetDesc/ARMAddressingModes.h"
     13 #include "MCTargetDesc/ARMArchName.h"
     14 #include "MCTargetDesc/ARMBaseInfo.h"
     15 #include "MCTargetDesc/ARMMCExpr.h"
     16 #include "llvm/ADT/STLExtras.h"
     17 #include "llvm/ADT/SmallVector.h"
     18 #include "llvm/ADT/StringExtras.h"
     19 #include "llvm/ADT/StringSwitch.h"
     20 #include "llvm/ADT/Twine.h"
     21 #include "llvm/MC/MCAsmInfo.h"
     22 #include "llvm/MC/MCAssembler.h"
     23 #include "llvm/MC/MCContext.h"
     24 #include "llvm/MC/MCDisassembler.h"
     25 #include "llvm/MC/MCELFStreamer.h"
     26 #include "llvm/MC/MCExpr.h"
     27 #include "llvm/MC/MCInst.h"
     28 #include "llvm/MC/MCInstrDesc.h"
     29 #include "llvm/MC/MCInstrInfo.h"
     30 #include "llvm/MC/MCObjectFileInfo.h"
     31 #include "llvm/MC/MCParser/MCAsmLexer.h"
     32 #include "llvm/MC/MCParser/MCAsmParser.h"
     33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
     34 #include "llvm/MC/MCRegisterInfo.h"
     35 #include "llvm/MC/MCSection.h"
     36 #include "llvm/MC/MCStreamer.h"
     37 #include "llvm/MC/MCSubtargetInfo.h"
     38 #include "llvm/MC/MCSymbol.h"
     39 #include "llvm/MC/MCTargetAsmParser.h"
     40 #include "llvm/Support/ARMBuildAttributes.h"
     41 #include "llvm/Support/ARMEHABI.h"
     42 #include "llvm/Support/COFF.h"
     43 #include "llvm/Support/Debug.h"
     44 #include "llvm/Support/ELF.h"
     45 #include "llvm/Support/MathExtras.h"
     46 #include "llvm/Support/SourceMgr.h"
     47 #include "llvm/Support/TargetRegistry.h"
     48 #include "llvm/Support/raw_ostream.h"
     49 
     50 using namespace llvm;
     51 
     52 namespace {
     53 
     54 class ARMOperand;
     55 
     56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
     57 
     58 class UnwindContext {
     59   MCAsmParser &Parser;
     60 
     61   typedef SmallVector<SMLoc, 4> Locs;
     62 
     63   Locs FnStartLocs;
     64   Locs CantUnwindLocs;
     65   Locs PersonalityLocs;
     66   Locs PersonalityIndexLocs;
     67   Locs HandlerDataLocs;
     68   int FPReg;
     69 
     70 public:
     71   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
     72 
     73   bool hasFnStart() const { return !FnStartLocs.empty(); }
     74   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
     75   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
     76   bool hasPersonality() const {
     77     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
     78   }
     79 
     80   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
     81   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
     82   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
     83   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
     84   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
     85 
     86   void saveFPReg(int Reg) { FPReg = Reg; }
     87   int getFPReg() const { return FPReg; }
     88 
     89   void emitFnStartLocNotes() const {
     90     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
     91          FI != FE; ++FI)
     92       Parser.Note(*FI, ".fnstart was specified here");
     93   }
     94   void emitCantUnwindLocNotes() const {
     95     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
     96                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
     97       Parser.Note(*UI, ".cantunwind was specified here");
     98   }
     99   void emitHandlerDataLocNotes() const {
    100     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
    101                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
    102       Parser.Note(*HI, ".handlerdata was specified here");
    103   }
    104   void emitPersonalityLocNotes() const {
    105     for (Locs::const_iterator PI = PersonalityLocs.begin(),
    106                               PE = PersonalityLocs.end(),
    107                               PII = PersonalityIndexLocs.begin(),
    108                               PIE = PersonalityIndexLocs.end();
    109          PI != PE || PII != PIE;) {
    110       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
    111         Parser.Note(*PI++, ".personality was specified here");
    112       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
    113         Parser.Note(*PII++, ".personalityindex was specified here");
    114       else
    115         llvm_unreachable(".personality and .personalityindex cannot be "
    116                          "at the same location");
    117     }
    118   }
    119 
    120   void reset() {
    121     FnStartLocs = Locs();
    122     CantUnwindLocs = Locs();
    123     PersonalityLocs = Locs();
    124     HandlerDataLocs = Locs();
    125     PersonalityIndexLocs = Locs();
    126     FPReg = ARM::SP;
    127   }
    128 };
    129 
    130 class ARMAsmParser : public MCTargetAsmParser {
    131   MCSubtargetInfo &STI;
    132   MCAsmParser &Parser;
    133   const MCInstrInfo &MII;
    134   const MCRegisterInfo *MRI;
    135   UnwindContext UC;
    136 
    137   ARMTargetStreamer &getTargetStreamer() {
    138     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
    139     return static_cast<ARMTargetStreamer &>(TS);
    140   }
    141 
    142   // Map of register aliases registers via the .req directive.
    143   StringMap<unsigned> RegisterReqs;
    144 
    145   bool NextSymbolIsThumb;
    146 
    147   struct {
    148     ARMCC::CondCodes Cond;    // Condition for IT block.
    149     unsigned Mask:4;          // Condition mask for instructions.
    150                               // Starting at first 1 (from lsb).
    151                               //   '1'  condition as indicated in IT.
    152                               //   '0'  inverse of condition (else).
    153                               // Count of instructions in IT block is
    154                               // 4 - trailingzeroes(mask)
    155 
    156     bool FirstCond;           // Explicit flag for when we're parsing the
    157                               // First instruction in the IT block. It's
    158                               // implied in the mask, so needs special
    159                               // handling.
    160 
    161     unsigned CurPosition;     // Current position in parsing of IT
    162                               // block. In range [0,3]. Initialized
    163                               // according to count of instructions in block.
    164                               // ~0U if no active IT block.
    165   } ITState;
    166   bool inITBlock() { return ITState.CurPosition != ~0U;}
    167   void forwardITPosition() {
    168     if (!inITBlock()) return;
    169     // Move to the next instruction in the IT block, if there is one. If not,
    170     // mark the block as done.
    171     unsigned TZ = countTrailingZeros(ITState.Mask);
    172     if (++ITState.CurPosition == 5 - TZ)
    173       ITState.CurPosition = ~0U; // Done with the IT block after this.
    174   }
    175 
    176 
    177   MCAsmParser &getParser() const { return Parser; }
    178   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
    179 
    180   void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
    181     return Parser.Note(L, Msg, Ranges);
    182   }
    183   bool Warning(SMLoc L, const Twine &Msg,
    184                ArrayRef<SMRange> Ranges = None) {
    185     return Parser.Warning(L, Msg, Ranges);
    186   }
    187   bool Error(SMLoc L, const Twine &Msg,
    188              ArrayRef<SMRange> Ranges = None) {
    189     return Parser.Error(L, Msg, Ranges);
    190   }
    191 
    192   int tryParseRegister();
    193   bool tryParseRegisterWithWriteBack(OperandVector &);
    194   int tryParseShiftRegister(OperandVector &);
    195   bool parseRegisterList(OperandVector &);
    196   bool parseMemory(OperandVector &);
    197   bool parseOperand(OperandVector &, StringRef Mnemonic);
    198   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
    199   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
    200                               unsigned &ShiftAmount);
    201   bool parseLiteralValues(unsigned Size, SMLoc L);
    202   bool parseDirectiveThumb(SMLoc L);
    203   bool parseDirectiveARM(SMLoc L);
    204   bool parseDirectiveThumbFunc(SMLoc L);
    205   bool parseDirectiveCode(SMLoc L);
    206   bool parseDirectiveSyntax(SMLoc L);
    207   bool parseDirectiveReq(StringRef Name, SMLoc L);
    208   bool parseDirectiveUnreq(SMLoc L);
    209   bool parseDirectiveArch(SMLoc L);
    210   bool parseDirectiveEabiAttr(SMLoc L);
    211   bool parseDirectiveCPU(SMLoc L);
    212   bool parseDirectiveFPU(SMLoc L);
    213   bool parseDirectiveFnStart(SMLoc L);
    214   bool parseDirectiveFnEnd(SMLoc L);
    215   bool parseDirectiveCantUnwind(SMLoc L);
    216   bool parseDirectivePersonality(SMLoc L);
    217   bool parseDirectiveHandlerData(SMLoc L);
    218   bool parseDirectiveSetFP(SMLoc L);
    219   bool parseDirectivePad(SMLoc L);
    220   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
    221   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
    222   bool parseDirectiveLtorg(SMLoc L);
    223   bool parseDirectiveEven(SMLoc L);
    224   bool parseDirectivePersonalityIndex(SMLoc L);
    225   bool parseDirectiveUnwindRaw(SMLoc L);
    226   bool parseDirectiveTLSDescSeq(SMLoc L);
    227   bool parseDirectiveMovSP(SMLoc L);
    228   bool parseDirectiveObjectArch(SMLoc L);
    229   bool parseDirectiveArchExtension(SMLoc L);
    230   bool parseDirectiveAlign(SMLoc L);
    231   bool parseDirectiveThumbSet(SMLoc L);
    232 
    233   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
    234                           bool &CarrySetting, unsigned &ProcessorIMod,
    235                           StringRef &ITMask);
    236   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
    237                              bool &CanAcceptCarrySet,
    238                              bool &CanAcceptPredicationCode);
    239 
    240   bool isThumb() const {
    241     // FIXME: Can tablegen auto-generate this?
    242     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
    243   }
    244   bool isThumbOne() const {
    245     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
    246   }
    247   bool isThumbTwo() const {
    248     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
    249   }
    250   bool hasThumb() const {
    251     return STI.getFeatureBits() & ARM::HasV4TOps;
    252   }
    253   bool hasV6Ops() const {
    254     return STI.getFeatureBits() & ARM::HasV6Ops;
    255   }
    256   bool hasV6MOps() const {
    257     return STI.getFeatureBits() & ARM::HasV6MOps;
    258   }
    259   bool hasV7Ops() const {
    260     return STI.getFeatureBits() & ARM::HasV7Ops;
    261   }
    262   bool hasV8Ops() const {
    263     return STI.getFeatureBits() & ARM::HasV8Ops;
    264   }
    265   bool hasARM() const {
    266     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
    267   }
    268 
    269   void SwitchMode() {
    270     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
    271     setAvailableFeatures(FB);
    272   }
    273   bool isMClass() const {
    274     return STI.getFeatureBits() & ARM::FeatureMClass;
    275   }
    276 
    277   /// @name Auto-generated Match Functions
    278   /// {
    279 
    280 #define GET_ASSEMBLER_HEADER
    281 #include "ARMGenAsmMatcher.inc"
    282 
    283   /// }
    284 
    285   OperandMatchResultTy parseITCondCode(OperandVector &);
    286   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
    287   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
    288   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
    289   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
    290   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
    291   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
    292   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
    293   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
    294                                    int High);
    295   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
    296     return parsePKHImm(O, "lsl", 0, 31);
    297   }
    298   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
    299     return parsePKHImm(O, "asr", 1, 32);
    300   }
    301   OperandMatchResultTy parseSetEndImm(OperandVector &);
    302   OperandMatchResultTy parseShifterImm(OperandVector &);
    303   OperandMatchResultTy parseRotImm(OperandVector &);
    304   OperandMatchResultTy parseBitfield(OperandVector &);
    305   OperandMatchResultTy parsePostIdxReg(OperandVector &);
    306   OperandMatchResultTy parseAM3Offset(OperandVector &);
    307   OperandMatchResultTy parseFPImm(OperandVector &);
    308   OperandMatchResultTy parseVectorList(OperandVector &);
    309   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
    310                                        SMLoc &EndLoc);
    311 
    312   // Asm Match Converter Methods
    313   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
    314   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
    315 
    316   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
    317   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
    318   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
    319   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
    320 
    321 public:
    322   enum ARMMatchResultTy {
    323     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
    324     Match_RequiresNotITBlock,
    325     Match_RequiresV6,
    326     Match_RequiresThumb2,
    327 #define GET_OPERAND_DIAGNOSTIC_TYPES
    328 #include "ARMGenAsmMatcher.inc"
    329 
    330   };
    331 
    332   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
    333                const MCInstrInfo &MII,
    334                const MCTargetOptions &Options)
    335       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
    336     MCAsmParserExtension::Initialize(_Parser);
    337 
    338     // Cache the MCRegisterInfo.
    339     MRI = getContext().getRegisterInfo();
    340 
    341     // Initialize the set of available features.
    342     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
    343 
    344     // Not in an ITBlock to start with.
    345     ITState.CurPosition = ~0U;
    346 
    347     NextSymbolIsThumb = false;
    348   }
    349 
    350   // Implementation of the MCTargetAsmParser interface:
    351   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
    352   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
    353                         SMLoc NameLoc, OperandVector &Operands) override;
    354   bool ParseDirective(AsmToken DirectiveID) override;
    355 
    356   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
    357                                       unsigned Kind) override;
    358   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
    359 
    360   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    361                                OperandVector &Operands, MCStreamer &Out,
    362                                unsigned &ErrorInfo,
    363                                bool MatchingInlineAsm) override;
    364   void onLabelParsed(MCSymbol *Symbol) override;
    365 };
    366 } // end anonymous namespace
    367 
    368 namespace {
    369 
    370 /// ARMOperand - Instances of this class represent a parsed ARM machine
    371 /// operand.
    372 class ARMOperand : public MCParsedAsmOperand {
    373   enum KindTy {
    374     k_CondCode,
    375     k_CCOut,
    376     k_ITCondMask,
    377     k_CoprocNum,
    378     k_CoprocReg,
    379     k_CoprocOption,
    380     k_Immediate,
    381     k_MemBarrierOpt,
    382     k_InstSyncBarrierOpt,
    383     k_Memory,
    384     k_PostIndexRegister,
    385     k_MSRMask,
    386     k_ProcIFlags,
    387     k_VectorIndex,
    388     k_Register,
    389     k_RegisterList,
    390     k_DPRRegisterList,
    391     k_SPRRegisterList,
    392     k_VectorList,
    393     k_VectorListAllLanes,
    394     k_VectorListIndexed,
    395     k_ShiftedRegister,
    396     k_ShiftedImmediate,
    397     k_ShifterImmediate,
    398     k_RotateImmediate,
    399     k_BitfieldDescriptor,
    400     k_Token
    401   } Kind;
    402 
    403   SMLoc StartLoc, EndLoc, AlignmentLoc;
    404   SmallVector<unsigned, 8> Registers;
    405 
    406   struct CCOp {
    407     ARMCC::CondCodes Val;
    408   };
    409 
    410   struct CopOp {
    411     unsigned Val;
    412   };
    413 
    414   struct CoprocOptionOp {
    415     unsigned Val;
    416   };
    417 
    418   struct ITMaskOp {
    419     unsigned Mask:4;
    420   };
    421 
    422   struct MBOptOp {
    423     ARM_MB::MemBOpt Val;
    424   };
    425 
    426   struct ISBOptOp {
    427     ARM_ISB::InstSyncBOpt Val;
    428   };
    429 
    430   struct IFlagsOp {
    431     ARM_PROC::IFlags Val;
    432   };
    433 
    434   struct MMaskOp {
    435     unsigned Val;
    436   };
    437 
    438   struct TokOp {
    439     const char *Data;
    440     unsigned Length;
    441   };
    442 
    443   struct RegOp {
    444     unsigned RegNum;
    445   };
    446 
    447   // A vector register list is a sequential list of 1 to 4 registers.
    448   struct VectorListOp {
    449     unsigned RegNum;
    450     unsigned Count;
    451     unsigned LaneIndex;
    452     bool isDoubleSpaced;
    453   };
    454 
    455   struct VectorIndexOp {
    456     unsigned Val;
    457   };
    458 
    459   struct ImmOp {
    460     const MCExpr *Val;
    461   };
    462 
    463   /// Combined record for all forms of ARM address expressions.
    464   struct MemoryOp {
    465     unsigned BaseRegNum;
    466     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
    467     // was specified.
    468     const MCConstantExpr *OffsetImm;  // Offset immediate value
    469     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
    470     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
    471     unsigned ShiftImm;        // shift for OffsetReg.
    472     unsigned Alignment;       // 0 = no alignment specified
    473     // n = alignment in bytes (2, 4, 8, 16, or 32)
    474     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
    475   };
    476 
    477   struct PostIdxRegOp {
    478     unsigned RegNum;
    479     bool isAdd;
    480     ARM_AM::ShiftOpc ShiftTy;
    481     unsigned ShiftImm;
    482   };
    483 
    484   struct ShifterImmOp {
    485     bool isASR;
    486     unsigned Imm;
    487   };
    488 
    489   struct RegShiftedRegOp {
    490     ARM_AM::ShiftOpc ShiftTy;
    491     unsigned SrcReg;
    492     unsigned ShiftReg;
    493     unsigned ShiftImm;
    494   };
    495 
    496   struct RegShiftedImmOp {
    497     ARM_AM::ShiftOpc ShiftTy;
    498     unsigned SrcReg;
    499     unsigned ShiftImm;
    500   };
    501 
    502   struct RotImmOp {
    503     unsigned Imm;
    504   };
    505 
    506   struct BitfieldOp {
    507     unsigned LSB;
    508     unsigned Width;
    509   };
    510 
    511   union {
    512     struct CCOp CC;
    513     struct CopOp Cop;
    514     struct CoprocOptionOp CoprocOption;
    515     struct MBOptOp MBOpt;
    516     struct ISBOptOp ISBOpt;
    517     struct ITMaskOp ITMask;
    518     struct IFlagsOp IFlags;
    519     struct MMaskOp MMask;
    520     struct TokOp Tok;
    521     struct RegOp Reg;
    522     struct VectorListOp VectorList;
    523     struct VectorIndexOp VectorIndex;
    524     struct ImmOp Imm;
    525     struct MemoryOp Memory;
    526     struct PostIdxRegOp PostIdxReg;
    527     struct ShifterImmOp ShifterImm;
    528     struct RegShiftedRegOp RegShiftedReg;
    529     struct RegShiftedImmOp RegShiftedImm;
    530     struct RotImmOp RotImm;
    531     struct BitfieldOp Bitfield;
    532   };
    533 
    534 public:
    535   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
    536   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
    537     Kind = o.Kind;
    538     StartLoc = o.StartLoc;
    539     EndLoc = o.EndLoc;
    540     switch (Kind) {
    541     case k_CondCode:
    542       CC = o.CC;
    543       break;
    544     case k_ITCondMask:
    545       ITMask = o.ITMask;
    546       break;
    547     case k_Token:
    548       Tok = o.Tok;
    549       break;
    550     case k_CCOut:
    551     case k_Register:
    552       Reg = o.Reg;
    553       break;
    554     case k_RegisterList:
    555     case k_DPRRegisterList:
    556     case k_SPRRegisterList:
    557       Registers = o.Registers;
    558       break;
    559     case k_VectorList:
    560     case k_VectorListAllLanes:
    561     case k_VectorListIndexed:
    562       VectorList = o.VectorList;
    563       break;
    564     case k_CoprocNum:
    565     case k_CoprocReg:
    566       Cop = o.Cop;
    567       break;
    568     case k_CoprocOption:
    569       CoprocOption = o.CoprocOption;
    570       break;
    571     case k_Immediate:
    572       Imm = o.Imm;
    573       break;
    574     case k_MemBarrierOpt:
    575       MBOpt = o.MBOpt;
    576       break;
    577     case k_InstSyncBarrierOpt:
    578       ISBOpt = o.ISBOpt;
    579     case k_Memory:
    580       Memory = o.Memory;
    581       break;
    582     case k_PostIndexRegister:
    583       PostIdxReg = o.PostIdxReg;
    584       break;
    585     case k_MSRMask:
    586       MMask = o.MMask;
    587       break;
    588     case k_ProcIFlags:
    589       IFlags = o.IFlags;
    590       break;
    591     case k_ShifterImmediate:
    592       ShifterImm = o.ShifterImm;
    593       break;
    594     case k_ShiftedRegister:
    595       RegShiftedReg = o.RegShiftedReg;
    596       break;
    597     case k_ShiftedImmediate:
    598       RegShiftedImm = o.RegShiftedImm;
    599       break;
    600     case k_RotateImmediate:
    601       RotImm = o.RotImm;
    602       break;
    603     case k_BitfieldDescriptor:
    604       Bitfield = o.Bitfield;
    605       break;
    606     case k_VectorIndex:
    607       VectorIndex = o.VectorIndex;
    608       break;
    609     }
    610   }
    611 
    612   /// getStartLoc - Get the location of the first token of this operand.
    613   SMLoc getStartLoc() const override { return StartLoc; }
    614   /// getEndLoc - Get the location of the last token of this operand.
    615   SMLoc getEndLoc() const override { return EndLoc; }
    616   /// getLocRange - Get the range between the first and last token of this
    617   /// operand.
    618   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
    619 
    620   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
    621   SMLoc getAlignmentLoc() const {
    622     assert(Kind == k_Memory && "Invalid access!");
    623     return AlignmentLoc;
    624   }
    625 
    626   ARMCC::CondCodes getCondCode() const {
    627     assert(Kind == k_CondCode && "Invalid access!");
    628     return CC.Val;
    629   }
    630 
    631   unsigned getCoproc() const {
    632     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
    633     return Cop.Val;
    634   }
    635 
    636   StringRef getToken() const {
    637     assert(Kind == k_Token && "Invalid access!");
    638     return StringRef(Tok.Data, Tok.Length);
    639   }
    640 
    641   unsigned getReg() const override {
    642     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
    643     return Reg.RegNum;
    644   }
    645 
    646   const SmallVectorImpl<unsigned> &getRegList() const {
    647     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
    648             Kind == k_SPRRegisterList) && "Invalid access!");
    649     return Registers;
    650   }
    651 
    652   const MCExpr *getImm() const {
    653     assert(isImm() && "Invalid access!");
    654     return Imm.Val;
    655   }
    656 
    657   unsigned getVectorIndex() const {
    658     assert(Kind == k_VectorIndex && "Invalid access!");
    659     return VectorIndex.Val;
    660   }
    661 
    662   ARM_MB::MemBOpt getMemBarrierOpt() const {
    663     assert(Kind == k_MemBarrierOpt && "Invalid access!");
    664     return MBOpt.Val;
    665   }
    666 
    667   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
    668     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
    669     return ISBOpt.Val;
    670   }
    671 
    672   ARM_PROC::IFlags getProcIFlags() const {
    673     assert(Kind == k_ProcIFlags && "Invalid access!");
    674     return IFlags.Val;
    675   }
    676 
    677   unsigned getMSRMask() const {
    678     assert(Kind == k_MSRMask && "Invalid access!");
    679     return MMask.Val;
    680   }
    681 
    682   bool isCoprocNum() const { return Kind == k_CoprocNum; }
    683   bool isCoprocReg() const { return Kind == k_CoprocReg; }
    684   bool isCoprocOption() const { return Kind == k_CoprocOption; }
    685   bool isCondCode() const { return Kind == k_CondCode; }
    686   bool isCCOut() const { return Kind == k_CCOut; }
    687   bool isITMask() const { return Kind == k_ITCondMask; }
    688   bool isITCondCode() const { return Kind == k_CondCode; }
    689   bool isImm() const override { return Kind == k_Immediate; }
    690   // checks whether this operand is an unsigned offset which fits is a field
    691   // of specified width and scaled by a specific number of bits
    692   template<unsigned width, unsigned scale>
    693   bool isUnsignedOffset() const {
    694     if (!isImm()) return false;
    695     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
    696     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
    697       int64_t Val = CE->getValue();
    698       int64_t Align = 1LL << scale;
    699       int64_t Max = Align * ((1LL << width) - 1);
    700       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
    701     }
    702     return false;
    703   }
    704   // checks whether this operand is an signed offset which fits is a field
    705   // of specified width and scaled by a specific number of bits
    706   template<unsigned width, unsigned scale>
    707   bool isSignedOffset() const {
    708     if (!isImm()) return false;
    709     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
    710     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
    711       int64_t Val = CE->getValue();
    712       int64_t Align = 1LL << scale;
    713       int64_t Max = Align * ((1LL << (width-1)) - 1);
    714       int64_t Min = -Align * (1LL << (width-1));
    715       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
    716     }
    717     return false;
    718   }
    719 
    720   // checks whether this operand is a memory operand computed as an offset
    721   // applied to PC. the offset may have 8 bits of magnitude and is represented
    722   // with two bits of shift. textually it may be either [pc, #imm], #imm or
    723   // relocable expression...
    724   bool isThumbMemPC() const {
    725     int64_t Val = 0;
    726     if (isImm()) {
    727       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
    728       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
    729       if (!CE) return false;
    730       Val = CE->getValue();
    731     }
    732     else if (isMem()) {
    733       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
    734       if(Memory.BaseRegNum != ARM::PC) return false;
    735       Val = Memory.OffsetImm->getValue();
    736     }
    737     else return false;
    738     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
    739   }
    740   bool isFPImm() const {
    741     if (!isImm()) return false;
    742     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    743     if (!CE) return false;
    744     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
    745     return Val != -1;
    746   }
    747   bool isFBits16() const {
    748     if (!isImm()) return false;
    749     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    750     if (!CE) return false;
    751     int64_t Value = CE->getValue();
    752     return Value >= 0 && Value <= 16;
    753   }
    754   bool isFBits32() const {
    755     if (!isImm()) return false;
    756     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    757     if (!CE) return false;
    758     int64_t Value = CE->getValue();
    759     return Value >= 1 && Value <= 32;
    760   }
    761   bool isImm8s4() const {
    762     if (!isImm()) return false;
    763     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    764     if (!CE) return false;
    765     int64_t Value = CE->getValue();
    766     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
    767   }
    768   bool isImm0_1020s4() const {
    769     if (!isImm()) return false;
    770     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    771     if (!CE) return false;
    772     int64_t Value = CE->getValue();
    773     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
    774   }
    775   bool isImm0_508s4() const {
    776     if (!isImm()) return false;
    777     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    778     if (!CE) return false;
    779     int64_t Value = CE->getValue();
    780     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
    781   }
    782   bool isImm0_508s4Neg() const {
    783     if (!isImm()) return false;
    784     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    785     if (!CE) return false;
    786     int64_t Value = -CE->getValue();
    787     // explicitly exclude zero. we want that to use the normal 0_508 version.
    788     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
    789   }
    790   bool isImm0_239() const {
    791     if (!isImm()) return false;
    792     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    793     if (!CE) return false;
    794     int64_t Value = CE->getValue();
    795     return Value >= 0 && Value < 240;
    796   }
    797   bool isImm0_255() const {
    798     if (!isImm()) return false;
    799     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    800     if (!CE) return false;
    801     int64_t Value = CE->getValue();
    802     return Value >= 0 && Value < 256;
    803   }
    804   bool isImm0_4095() const {
    805     if (!isImm()) return false;
    806     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    807     if (!CE) return false;
    808     int64_t Value = CE->getValue();
    809     return Value >= 0 && Value < 4096;
    810   }
    811   bool isImm0_4095Neg() const {
    812     if (!isImm()) return false;
    813     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    814     if (!CE) return false;
    815     int64_t Value = -CE->getValue();
    816     return Value > 0 && Value < 4096;
    817   }
    818   bool isImm0_1() const {
    819     if (!isImm()) return false;
    820     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    821     if (!CE) return false;
    822     int64_t Value = CE->getValue();
    823     return Value >= 0 && Value < 2;
    824   }
    825   bool isImm0_3() const {
    826     if (!isImm()) return false;
    827     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    828     if (!CE) return false;
    829     int64_t Value = CE->getValue();
    830     return Value >= 0 && Value < 4;
    831   }
    832   bool isImm0_7() const {
    833     if (!isImm()) return false;
    834     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    835     if (!CE) return false;
    836     int64_t Value = CE->getValue();
    837     return Value >= 0 && Value < 8;
    838   }
    839   bool isImm0_15() const {
    840     if (!isImm()) return false;
    841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    842     if (!CE) return false;
    843     int64_t Value = CE->getValue();
    844     return Value >= 0 && Value < 16;
    845   }
    846   bool isImm0_31() const {
    847     if (!isImm()) return false;
    848     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    849     if (!CE) return false;
    850     int64_t Value = CE->getValue();
    851     return Value >= 0 && Value < 32;
    852   }
    853   bool isImm0_63() const {
    854     if (!isImm()) return false;
    855     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    856     if (!CE) return false;
    857     int64_t Value = CE->getValue();
    858     return Value >= 0 && Value < 64;
    859   }
    860   bool isImm8() const {
    861     if (!isImm()) return false;
    862     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    863     if (!CE) return false;
    864     int64_t Value = CE->getValue();
    865     return Value == 8;
    866   }
    867   bool isImm16() const {
    868     if (!isImm()) return false;
    869     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    870     if (!CE) return false;
    871     int64_t Value = CE->getValue();
    872     return Value == 16;
    873   }
    874   bool isImm32() const {
    875     if (!isImm()) return false;
    876     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    877     if (!CE) return false;
    878     int64_t Value = CE->getValue();
    879     return Value == 32;
    880   }
    881   bool isShrImm8() const {
    882     if (!isImm()) return false;
    883     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    884     if (!CE) return false;
    885     int64_t Value = CE->getValue();
    886     return Value > 0 && Value <= 8;
    887   }
    888   bool isShrImm16() const {
    889     if (!isImm()) return false;
    890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    891     if (!CE) return false;
    892     int64_t Value = CE->getValue();
    893     return Value > 0 && Value <= 16;
    894   }
    895   bool isShrImm32() const {
    896     if (!isImm()) return false;
    897     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    898     if (!CE) return false;
    899     int64_t Value = CE->getValue();
    900     return Value > 0 && Value <= 32;
    901   }
    902   bool isShrImm64() const {
    903     if (!isImm()) return false;
    904     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    905     if (!CE) return false;
    906     int64_t Value = CE->getValue();
    907     return Value > 0 && Value <= 64;
    908   }
    909   bool isImm1_7() const {
    910     if (!isImm()) return false;
    911     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    912     if (!CE) return false;
    913     int64_t Value = CE->getValue();
    914     return Value > 0 && Value < 8;
    915   }
    916   bool isImm1_15() const {
    917     if (!isImm()) return false;
    918     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    919     if (!CE) return false;
    920     int64_t Value = CE->getValue();
    921     return Value > 0 && Value < 16;
    922   }
    923   bool isImm1_31() const {
    924     if (!isImm()) return false;
    925     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    926     if (!CE) return false;
    927     int64_t Value = CE->getValue();
    928     return Value > 0 && Value < 32;
    929   }
    930   bool isImm1_16() const {
    931     if (!isImm()) return false;
    932     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    933     if (!CE) return false;
    934     int64_t Value = CE->getValue();
    935     return Value > 0 && Value < 17;
    936   }
    937   bool isImm1_32() const {
    938     if (!isImm()) return false;
    939     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    940     if (!CE) return false;
    941     int64_t Value = CE->getValue();
    942     return Value > 0 && Value < 33;
    943   }
    944   bool isImm0_32() const {
    945     if (!isImm()) return false;
    946     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    947     if (!CE) return false;
    948     int64_t Value = CE->getValue();
    949     return Value >= 0 && Value < 33;
    950   }
    951   bool isImm0_65535() const {
    952     if (!isImm()) return false;
    953     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    954     if (!CE) return false;
    955     int64_t Value = CE->getValue();
    956     return Value >= 0 && Value < 65536;
    957   }
    958   bool isImm256_65535Expr() const {
    959     if (!isImm()) return false;
    960     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    961     // If it's not a constant expression, it'll generate a fixup and be
    962     // handled later.
    963     if (!CE) return true;
    964     int64_t Value = CE->getValue();
    965     return Value >= 256 && Value < 65536;
    966   }
    967   bool isImm0_65535Expr() const {
    968     if (!isImm()) return false;
    969     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    970     // If it's not a constant expression, it'll generate a fixup and be
    971     // handled later.
    972     if (!CE) return true;
    973     int64_t Value = CE->getValue();
    974     return Value >= 0 && Value < 65536;
    975   }
    976   bool isImm24bit() const {
    977     if (!isImm()) return false;
    978     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    979     if (!CE) return false;
    980     int64_t Value = CE->getValue();
    981     return Value >= 0 && Value <= 0xffffff;
    982   }
    983   bool isImmThumbSR() const {
    984     if (!isImm()) return false;
    985     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    986     if (!CE) return false;
    987     int64_t Value = CE->getValue();
    988     return Value > 0 && Value < 33;
    989   }
    990   bool isPKHLSLImm() const {
    991     if (!isImm()) return false;
    992     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    993     if (!CE) return false;
    994     int64_t Value = CE->getValue();
    995     return Value >= 0 && Value < 32;
    996   }
    997   bool isPKHASRImm() const {
    998     if (!isImm()) return false;
    999     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1000     if (!CE) return false;
   1001     int64_t Value = CE->getValue();
   1002     return Value > 0 && Value <= 32;
   1003   }
   1004   bool isAdrLabel() const {
   1005     // If we have an immediate that's not a constant, treat it as a label
   1006     // reference needing a fixup. If it is a constant, but it can't fit
   1007     // into shift immediate encoding, we reject it.
   1008     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
   1009     else return (isARMSOImm() || isARMSOImmNeg());
   1010   }
   1011   bool isARMSOImm() const {
   1012     if (!isImm()) return false;
   1013     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1014     if (!CE) return false;
   1015     int64_t Value = CE->getValue();
   1016     return ARM_AM::getSOImmVal(Value) != -1;
   1017   }
   1018   bool isARMSOImmNot() const {
   1019     if (!isImm()) return false;
   1020     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1021     if (!CE) return false;
   1022     int64_t Value = CE->getValue();
   1023     return ARM_AM::getSOImmVal(~Value) != -1;
   1024   }
   1025   bool isARMSOImmNeg() const {
   1026     if (!isImm()) return false;
   1027     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1028     if (!CE) return false;
   1029     int64_t Value = CE->getValue();
   1030     // Only use this when not representable as a plain so_imm.
   1031     return ARM_AM::getSOImmVal(Value) == -1 &&
   1032       ARM_AM::getSOImmVal(-Value) != -1;
   1033   }
   1034   bool isT2SOImm() const {
   1035     if (!isImm()) return false;
   1036     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1037     if (!CE) return false;
   1038     int64_t Value = CE->getValue();
   1039     return ARM_AM::getT2SOImmVal(Value) != -1;
   1040   }
   1041   bool isT2SOImmNot() const {
   1042     if (!isImm()) return false;
   1043     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1044     if (!CE) return false;
   1045     int64_t Value = CE->getValue();
   1046     return ARM_AM::getT2SOImmVal(Value) == -1 &&
   1047       ARM_AM::getT2SOImmVal(~Value) != -1;
   1048   }
   1049   bool isT2SOImmNeg() const {
   1050     if (!isImm()) return false;
   1051     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1052     if (!CE) return false;
   1053     int64_t Value = CE->getValue();
   1054     // Only use this when not representable as a plain so_imm.
   1055     return ARM_AM::getT2SOImmVal(Value) == -1 &&
   1056       ARM_AM::getT2SOImmVal(-Value) != -1;
   1057   }
   1058   bool isSetEndImm() const {
   1059     if (!isImm()) return false;
   1060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1061     if (!CE) return false;
   1062     int64_t Value = CE->getValue();
   1063     return Value == 1 || Value == 0;
   1064   }
   1065   bool isReg() const override { return Kind == k_Register; }
   1066   bool isRegList() const { return Kind == k_RegisterList; }
   1067   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
   1068   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
   1069   bool isToken() const override { return Kind == k_Token; }
   1070   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
   1071   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
   1072   bool isMem() const override { return Kind == k_Memory; }
   1073   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
   1074   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
   1075   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
   1076   bool isRotImm() const { return Kind == k_RotateImmediate; }
   1077   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
   1078   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
   1079   bool isPostIdxReg() const {
   1080     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
   1081   }
   1082   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
   1083     if (!isMem())
   1084       return false;
   1085     // No offset of any kind.
   1086     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
   1087      (alignOK || Memory.Alignment == Alignment);
   1088   }
   1089   bool isMemPCRelImm12() const {
   1090     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1091       return false;
   1092     // Base register must be PC.
   1093     if (Memory.BaseRegNum != ARM::PC)
   1094       return false;
   1095     // Immediate offset in range [-4095, 4095].
   1096     if (!Memory.OffsetImm) return true;
   1097     int64_t Val = Memory.OffsetImm->getValue();
   1098     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
   1099   }
   1100   bool isAlignedMemory() const {
   1101     return isMemNoOffset(true);
   1102   }
   1103   bool isAlignedMemoryNone() const {
   1104     return isMemNoOffset(false, 0);
   1105   }
   1106   bool isDupAlignedMemoryNone() const {
   1107     return isMemNoOffset(false, 0);
   1108   }
   1109   bool isAlignedMemory16() const {
   1110     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
   1111       return true;
   1112     return isMemNoOffset(false, 0);
   1113   }
   1114   bool isDupAlignedMemory16() const {
   1115     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
   1116       return true;
   1117     return isMemNoOffset(false, 0);
   1118   }
   1119   bool isAlignedMemory32() const {
   1120     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
   1121       return true;
   1122     return isMemNoOffset(false, 0);
   1123   }
   1124   bool isDupAlignedMemory32() const {
   1125     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
   1126       return true;
   1127     return isMemNoOffset(false, 0);
   1128   }
   1129   bool isAlignedMemory64() const {
   1130     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
   1131       return true;
   1132     return isMemNoOffset(false, 0);
   1133   }
   1134   bool isDupAlignedMemory64() const {
   1135     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
   1136       return true;
   1137     return isMemNoOffset(false, 0);
   1138   }
   1139   bool isAlignedMemory64or128() const {
   1140     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
   1141       return true;
   1142     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
   1143       return true;
   1144     return isMemNoOffset(false, 0);
   1145   }
   1146   bool isDupAlignedMemory64or128() const {
   1147     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
   1148       return true;
   1149     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
   1150       return true;
   1151     return isMemNoOffset(false, 0);
   1152   }
   1153   bool isAlignedMemory64or128or256() const {
   1154     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
   1155       return true;
   1156     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
   1157       return true;
   1158     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
   1159       return true;
   1160     return isMemNoOffset(false, 0);
   1161   }
   1162   bool isAddrMode2() const {
   1163     if (!isMem() || Memory.Alignment != 0) return false;
   1164     // Check for register offset.
   1165     if (Memory.OffsetRegNum) return true;
   1166     // Immediate offset in range [-4095, 4095].
   1167     if (!Memory.OffsetImm) return true;
   1168     int64_t Val = Memory.OffsetImm->getValue();
   1169     return Val > -4096 && Val < 4096;
   1170   }
   1171   bool isAM2OffsetImm() const {
   1172     if (!isImm()) return false;
   1173     // Immediate offset in range [-4095, 4095].
   1174     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1175     if (!CE) return false;
   1176     int64_t Val = CE->getValue();
   1177     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
   1178   }
   1179   bool isAddrMode3() const {
   1180     // If we have an immediate that's not a constant, treat it as a label
   1181     // reference needing a fixup. If it is a constant, it's something else
   1182     // and we reject it.
   1183     if (isImm() && !isa<MCConstantExpr>(getImm()))
   1184       return true;
   1185     if (!isMem() || Memory.Alignment != 0) return false;
   1186     // No shifts are legal for AM3.
   1187     if (Memory.ShiftType != ARM_AM::no_shift) return false;
   1188     // Check for register offset.
   1189     if (Memory.OffsetRegNum) return true;
   1190     // Immediate offset in range [-255, 255].
   1191     if (!Memory.OffsetImm) return true;
   1192     int64_t Val = Memory.OffsetImm->getValue();
   1193     // The #-0 offset is encoded as INT32_MIN, and we have to check
   1194     // for this too.
   1195     return (Val > -256 && Val < 256) || Val == INT32_MIN;
   1196   }
   1197   bool isAM3Offset() const {
   1198     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
   1199       return false;
   1200     if (Kind == k_PostIndexRegister)
   1201       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
   1202     // Immediate offset in range [-255, 255].
   1203     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1204     if (!CE) return false;
   1205     int64_t Val = CE->getValue();
   1206     // Special case, #-0 is INT32_MIN.
   1207     return (Val > -256 && Val < 256) || Val == INT32_MIN;
   1208   }
   1209   bool isAddrMode5() const {
   1210     // If we have an immediate that's not a constant, treat it as a label
   1211     // reference needing a fixup. If it is a constant, it's something else
   1212     // and we reject it.
   1213     if (isImm() && !isa<MCConstantExpr>(getImm()))
   1214       return true;
   1215     if (!isMem() || Memory.Alignment != 0) return false;
   1216     // Check for register offset.
   1217     if (Memory.OffsetRegNum) return false;
   1218     // Immediate offset in range [-1020, 1020] and a multiple of 4.
   1219     if (!Memory.OffsetImm) return true;
   1220     int64_t Val = Memory.OffsetImm->getValue();
   1221     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
   1222       Val == INT32_MIN;
   1223   }
   1224   bool isMemTBB() const {
   1225     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
   1226         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
   1227       return false;
   1228     return true;
   1229   }
   1230   bool isMemTBH() const {
   1231     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
   1232         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
   1233         Memory.Alignment != 0 )
   1234       return false;
   1235     return true;
   1236   }
   1237   bool isMemRegOffset() const {
   1238     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
   1239       return false;
   1240     return true;
   1241   }
   1242   bool isT2MemRegOffset() const {
   1243     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
   1244         Memory.Alignment != 0)
   1245       return false;
   1246     // Only lsl #{0, 1, 2, 3} allowed.
   1247     if (Memory.ShiftType == ARM_AM::no_shift)
   1248       return true;
   1249     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
   1250       return false;
   1251     return true;
   1252   }
   1253   bool isMemThumbRR() const {
   1254     // Thumb reg+reg addressing is simple. Just two registers, a base and
   1255     // an offset. No shifts, negations or any other complicating factors.
   1256     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
   1257         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
   1258       return false;
   1259     return isARMLowRegister(Memory.BaseRegNum) &&
   1260       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
   1261   }
   1262   bool isMemThumbRIs4() const {
   1263     if (!isMem() || Memory.OffsetRegNum != 0 ||
   1264         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
   1265       return false;
   1266     // Immediate offset, multiple of 4 in range [0, 124].
   1267     if (!Memory.OffsetImm) return true;
   1268     int64_t Val = Memory.OffsetImm->getValue();
   1269     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
   1270   }
   1271   bool isMemThumbRIs2() const {
   1272     if (!isMem() || Memory.OffsetRegNum != 0 ||
   1273         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
   1274       return false;
   1275     // Immediate offset, multiple of 4 in range [0, 62].
   1276     if (!Memory.OffsetImm) return true;
   1277     int64_t Val = Memory.OffsetImm->getValue();
   1278     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
   1279   }
   1280   bool isMemThumbRIs1() const {
   1281     if (!isMem() || Memory.OffsetRegNum != 0 ||
   1282         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
   1283       return false;
   1284     // Immediate offset in range [0, 31].
   1285     if (!Memory.OffsetImm) return true;
   1286     int64_t Val = Memory.OffsetImm->getValue();
   1287     return Val >= 0 && Val <= 31;
   1288   }
   1289   bool isMemThumbSPI() const {
   1290     if (!isMem() || Memory.OffsetRegNum != 0 ||
   1291         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
   1292       return false;
   1293     // Immediate offset, multiple of 4 in range [0, 1020].
   1294     if (!Memory.OffsetImm) return true;
   1295     int64_t Val = Memory.OffsetImm->getValue();
   1296     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
   1297   }
   1298   bool isMemImm8s4Offset() const {
   1299     // If we have an immediate that's not a constant, treat it as a label
   1300     // reference needing a fixup. If it is a constant, it's something else
   1301     // and we reject it.
   1302     if (isImm() && !isa<MCConstantExpr>(getImm()))
   1303       return true;
   1304     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1305       return false;
   1306     // Immediate offset a multiple of 4 in range [-1020, 1020].
   1307     if (!Memory.OffsetImm) return true;
   1308     int64_t Val = Memory.OffsetImm->getValue();
   1309     // Special case, #-0 is INT32_MIN.
   1310     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
   1311   }
   1312   bool isMemImm0_1020s4Offset() const {
   1313     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1314       return false;
   1315     // Immediate offset a multiple of 4 in range [0, 1020].
   1316     if (!Memory.OffsetImm) return true;
   1317     int64_t Val = Memory.OffsetImm->getValue();
   1318     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
   1319   }
   1320   bool isMemImm8Offset() const {
   1321     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1322       return false;
   1323     // Base reg of PC isn't allowed for these encodings.
   1324     if (Memory.BaseRegNum == ARM::PC) return false;
   1325     // Immediate offset in range [-255, 255].
   1326     if (!Memory.OffsetImm) return true;
   1327     int64_t Val = Memory.OffsetImm->getValue();
   1328     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
   1329   }
   1330   bool isMemPosImm8Offset() const {
   1331     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1332       return false;
   1333     // Immediate offset in range [0, 255].
   1334     if (!Memory.OffsetImm) return true;
   1335     int64_t Val = Memory.OffsetImm->getValue();
   1336     return Val >= 0 && Val < 256;
   1337   }
   1338   bool isMemNegImm8Offset() const {
   1339     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1340       return false;
   1341     // Base reg of PC isn't allowed for these encodings.
   1342     if (Memory.BaseRegNum == ARM::PC) return false;
   1343     // Immediate offset in range [-255, -1].
   1344     if (!Memory.OffsetImm) return false;
   1345     int64_t Val = Memory.OffsetImm->getValue();
   1346     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
   1347   }
   1348   bool isMemUImm12Offset() const {
   1349     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1350       return false;
   1351     // Immediate offset in range [0, 4095].
   1352     if (!Memory.OffsetImm) return true;
   1353     int64_t Val = Memory.OffsetImm->getValue();
   1354     return (Val >= 0 && Val < 4096);
   1355   }
   1356   bool isMemImm12Offset() const {
   1357     // If we have an immediate that's not a constant, treat it as a label
   1358     // reference needing a fixup. If it is a constant, it's something else
   1359     // and we reject it.
   1360     if (isImm() && !isa<MCConstantExpr>(getImm()))
   1361       return true;
   1362 
   1363     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
   1364       return false;
   1365     // Immediate offset in range [-4095, 4095].
   1366     if (!Memory.OffsetImm) return true;
   1367     int64_t Val = Memory.OffsetImm->getValue();
   1368     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
   1369   }
   1370   bool isPostIdxImm8() const {
   1371     if (!isImm()) return false;
   1372     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1373     if (!CE) return false;
   1374     int64_t Val = CE->getValue();
   1375     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
   1376   }
   1377   bool isPostIdxImm8s4() const {
   1378     if (!isImm()) return false;
   1379     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1380     if (!CE) return false;
   1381     int64_t Val = CE->getValue();
   1382     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
   1383       (Val == INT32_MIN);
   1384   }
   1385 
   1386   bool isMSRMask() const { return Kind == k_MSRMask; }
   1387   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
   1388 
   1389   // NEON operands.
   1390   bool isSingleSpacedVectorList() const {
   1391     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
   1392   }
   1393   bool isDoubleSpacedVectorList() const {
   1394     return Kind == k_VectorList && VectorList.isDoubleSpaced;
   1395   }
   1396   bool isVecListOneD() const {
   1397     if (!isSingleSpacedVectorList()) return false;
   1398     return VectorList.Count == 1;
   1399   }
   1400 
   1401   bool isVecListDPair() const {
   1402     if (!isSingleSpacedVectorList()) return false;
   1403     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
   1404               .contains(VectorList.RegNum));
   1405   }
   1406 
   1407   bool isVecListThreeD() const {
   1408     if (!isSingleSpacedVectorList()) return false;
   1409     return VectorList.Count == 3;
   1410   }
   1411 
   1412   bool isVecListFourD() const {
   1413     if (!isSingleSpacedVectorList()) return false;
   1414     return VectorList.Count == 4;
   1415   }
   1416 
   1417   bool isVecListDPairSpaced() const {
   1418     if (Kind != k_VectorList) return false;
   1419     if (isSingleSpacedVectorList()) return false;
   1420     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
   1421               .contains(VectorList.RegNum));
   1422   }
   1423 
   1424   bool isVecListThreeQ() const {
   1425     if (!isDoubleSpacedVectorList()) return false;
   1426     return VectorList.Count == 3;
   1427   }
   1428 
   1429   bool isVecListFourQ() const {
   1430     if (!isDoubleSpacedVectorList()) return false;
   1431     return VectorList.Count == 4;
   1432   }
   1433 
   1434   bool isSingleSpacedVectorAllLanes() const {
   1435     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
   1436   }
   1437   bool isDoubleSpacedVectorAllLanes() const {
   1438     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
   1439   }
   1440   bool isVecListOneDAllLanes() const {
   1441     if (!isSingleSpacedVectorAllLanes()) return false;
   1442     return VectorList.Count == 1;
   1443   }
   1444 
   1445   bool isVecListDPairAllLanes() const {
   1446     if (!isSingleSpacedVectorAllLanes()) return false;
   1447     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
   1448               .contains(VectorList.RegNum));
   1449   }
   1450 
   1451   bool isVecListDPairSpacedAllLanes() const {
   1452     if (!isDoubleSpacedVectorAllLanes()) return false;
   1453     return VectorList.Count == 2;
   1454   }
   1455 
   1456   bool isVecListThreeDAllLanes() const {
   1457     if (!isSingleSpacedVectorAllLanes()) return false;
   1458     return VectorList.Count == 3;
   1459   }
   1460 
   1461   bool isVecListThreeQAllLanes() const {
   1462     if (!isDoubleSpacedVectorAllLanes()) return false;
   1463     return VectorList.Count == 3;
   1464   }
   1465 
   1466   bool isVecListFourDAllLanes() const {
   1467     if (!isSingleSpacedVectorAllLanes()) return false;
   1468     return VectorList.Count == 4;
   1469   }
   1470 
   1471   bool isVecListFourQAllLanes() const {
   1472     if (!isDoubleSpacedVectorAllLanes()) return false;
   1473     return VectorList.Count == 4;
   1474   }
   1475 
   1476   bool isSingleSpacedVectorIndexed() const {
   1477     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
   1478   }
   1479   bool isDoubleSpacedVectorIndexed() const {
   1480     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
   1481   }
   1482   bool isVecListOneDByteIndexed() const {
   1483     if (!isSingleSpacedVectorIndexed()) return false;
   1484     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
   1485   }
   1486 
   1487   bool isVecListOneDHWordIndexed() const {
   1488     if (!isSingleSpacedVectorIndexed()) return false;
   1489     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
   1490   }
   1491 
   1492   bool isVecListOneDWordIndexed() const {
   1493     if (!isSingleSpacedVectorIndexed()) return false;
   1494     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
   1495   }
   1496 
   1497   bool isVecListTwoDByteIndexed() const {
   1498     if (!isSingleSpacedVectorIndexed()) return false;
   1499     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
   1500   }
   1501 
   1502   bool isVecListTwoDHWordIndexed() const {
   1503     if (!isSingleSpacedVectorIndexed()) return false;
   1504     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
   1505   }
   1506 
   1507   bool isVecListTwoQWordIndexed() const {
   1508     if (!isDoubleSpacedVectorIndexed()) return false;
   1509     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
   1510   }
   1511 
   1512   bool isVecListTwoQHWordIndexed() const {
   1513     if (!isDoubleSpacedVectorIndexed()) return false;
   1514     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
   1515   }
   1516 
   1517   bool isVecListTwoDWordIndexed() const {
   1518     if (!isSingleSpacedVectorIndexed()) return false;
   1519     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
   1520   }
   1521 
   1522   bool isVecListThreeDByteIndexed() const {
   1523     if (!isSingleSpacedVectorIndexed()) return false;
   1524     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
   1525   }
   1526 
   1527   bool isVecListThreeDHWordIndexed() const {
   1528     if (!isSingleSpacedVectorIndexed()) return false;
   1529     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
   1530   }
   1531 
   1532   bool isVecListThreeQWordIndexed() const {
   1533     if (!isDoubleSpacedVectorIndexed()) return false;
   1534     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
   1535   }
   1536 
   1537   bool isVecListThreeQHWordIndexed() const {
   1538     if (!isDoubleSpacedVectorIndexed()) return false;
   1539     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
   1540   }
   1541 
   1542   bool isVecListThreeDWordIndexed() const {
   1543     if (!isSingleSpacedVectorIndexed()) return false;
   1544     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
   1545   }
   1546 
   1547   bool isVecListFourDByteIndexed() const {
   1548     if (!isSingleSpacedVectorIndexed()) return false;
   1549     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
   1550   }
   1551 
   1552   bool isVecListFourDHWordIndexed() const {
   1553     if (!isSingleSpacedVectorIndexed()) return false;
   1554     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
   1555   }
   1556 
   1557   bool isVecListFourQWordIndexed() const {
   1558     if (!isDoubleSpacedVectorIndexed()) return false;
   1559     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
   1560   }
   1561 
   1562   bool isVecListFourQHWordIndexed() const {
   1563     if (!isDoubleSpacedVectorIndexed()) return false;
   1564     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
   1565   }
   1566 
   1567   bool isVecListFourDWordIndexed() const {
   1568     if (!isSingleSpacedVectorIndexed()) return false;
   1569     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
   1570   }
   1571 
   1572   bool isVectorIndex8() const {
   1573     if (Kind != k_VectorIndex) return false;
   1574     return VectorIndex.Val < 8;
   1575   }
   1576   bool isVectorIndex16() const {
   1577     if (Kind != k_VectorIndex) return false;
   1578     return VectorIndex.Val < 4;
   1579   }
   1580   bool isVectorIndex32() const {
   1581     if (Kind != k_VectorIndex) return false;
   1582     return VectorIndex.Val < 2;
   1583   }
   1584 
   1585   bool isNEONi8splat() const {
   1586     if (!isImm()) return false;
   1587     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1588     // Must be a constant.
   1589     if (!CE) return false;
   1590     int64_t Value = CE->getValue();
   1591     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
   1592     // value.
   1593     return Value >= 0 && Value < 256;
   1594   }
   1595 
   1596   bool isNEONi16splat() const {
   1597     if (isNEONByteReplicate(2))
   1598       return false; // Leave that for bytes replication and forbid by default.
   1599     if (!isImm())
   1600       return false;
   1601     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1602     // Must be a constant.
   1603     if (!CE) return false;
   1604     int64_t Value = CE->getValue();
   1605     // i16 value in the range [0,255] or [0x0100, 0xff00]
   1606     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
   1607   }
   1608 
   1609   bool isNEONi32splat() const {
   1610     if (isNEONByteReplicate(4))
   1611       return false; // Leave that for bytes replication and forbid by default.
   1612     if (!isImm())
   1613       return false;
   1614     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1615     // Must be a constant.
   1616     if (!CE) return false;
   1617     int64_t Value = CE->getValue();
   1618     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
   1619     return (Value >= 0 && Value < 256) ||
   1620       (Value >= 0x0100 && Value <= 0xff00) ||
   1621       (Value >= 0x010000 && Value <= 0xff0000) ||
   1622       (Value >= 0x01000000 && Value <= 0xff000000);
   1623   }
   1624 
   1625   bool isNEONByteReplicate(unsigned NumBytes) const {
   1626     if (!isImm())
   1627       return false;
   1628     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1629     // Must be a constant.
   1630     if (!CE)
   1631       return false;
   1632     int64_t Value = CE->getValue();
   1633     if (!Value)
   1634       return false; // Don't bother with zero.
   1635 
   1636     unsigned char B = Value & 0xff;
   1637     for (unsigned i = 1; i < NumBytes; ++i) {
   1638       Value >>= 8;
   1639       if ((Value & 0xff) != B)
   1640         return false;
   1641     }
   1642     return true;
   1643   }
   1644   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
   1645   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
   1646   bool isNEONi32vmov() const {
   1647     if (isNEONByteReplicate(4))
   1648       return false; // Let it to be classified as byte-replicate case.
   1649     if (!isImm())
   1650       return false;
   1651     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1652     // Must be a constant.
   1653     if (!CE)
   1654       return false;
   1655     int64_t Value = CE->getValue();
   1656     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
   1657     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
   1658     return (Value >= 0 && Value < 256) ||
   1659       (Value >= 0x0100 && Value <= 0xff00) ||
   1660       (Value >= 0x010000 && Value <= 0xff0000) ||
   1661       (Value >= 0x01000000 && Value <= 0xff000000) ||
   1662       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
   1663       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
   1664   }
   1665   bool isNEONi32vmovNeg() const {
   1666     if (!isImm()) return false;
   1667     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1668     // Must be a constant.
   1669     if (!CE) return false;
   1670     int64_t Value = ~CE->getValue();
   1671     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
   1672     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
   1673     return (Value >= 0 && Value < 256) ||
   1674       (Value >= 0x0100 && Value <= 0xff00) ||
   1675       (Value >= 0x010000 && Value <= 0xff0000) ||
   1676       (Value >= 0x01000000 && Value <= 0xff000000) ||
   1677       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
   1678       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
   1679   }
   1680 
   1681   bool isNEONi64splat() const {
   1682     if (!isImm()) return false;
   1683     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1684     // Must be a constant.
   1685     if (!CE) return false;
   1686     uint64_t Value = CE->getValue();
   1687     // i64 value with each byte being either 0 or 0xff.
   1688     for (unsigned i = 0; i < 8; ++i)
   1689       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
   1690     return true;
   1691   }
   1692 
   1693   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
   1694     // Add as immediates when possible.  Null MCExpr = 0.
   1695     if (!Expr)
   1696       Inst.addOperand(MCOperand::CreateImm(0));
   1697     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
   1698       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
   1699     else
   1700       Inst.addOperand(MCOperand::CreateExpr(Expr));
   1701   }
   1702 
   1703   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
   1704     assert(N == 2 && "Invalid number of operands!");
   1705     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
   1706     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
   1707     Inst.addOperand(MCOperand::CreateReg(RegNum));
   1708   }
   1709 
   1710   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
   1711     assert(N == 1 && "Invalid number of operands!");
   1712     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
   1713   }
   1714 
   1715   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
   1716     assert(N == 1 && "Invalid number of operands!");
   1717     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
   1718   }
   1719 
   1720   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
   1721     assert(N == 1 && "Invalid number of operands!");
   1722     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
   1723   }
   1724 
   1725   void addITMaskOperands(MCInst &Inst, unsigned N) const {
   1726     assert(N == 1 && "Invalid number of operands!");
   1727     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
   1728   }
   1729 
   1730   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
   1731     assert(N == 1 && "Invalid number of operands!");
   1732     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
   1733   }
   1734 
   1735   void addCCOutOperands(MCInst &Inst, unsigned N) const {
   1736     assert(N == 1 && "Invalid number of operands!");
   1737     Inst.addOperand(MCOperand::CreateReg(getReg()));
   1738   }
   1739 
   1740   void addRegOperands(MCInst &Inst, unsigned N) const {
   1741     assert(N == 1 && "Invalid number of operands!");
   1742     Inst.addOperand(MCOperand::CreateReg(getReg()));
   1743   }
   1744 
   1745   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
   1746     assert(N == 3 && "Invalid number of operands!");
   1747     assert(isRegShiftedReg() &&
   1748            "addRegShiftedRegOperands() on non-RegShiftedReg!");
   1749     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
   1750     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
   1751     Inst.addOperand(MCOperand::CreateImm(
   1752       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
   1753   }
   1754 
   1755   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
   1756     assert(N == 2 && "Invalid number of operands!");
   1757     assert(isRegShiftedImm() &&
   1758            "addRegShiftedImmOperands() on non-RegShiftedImm!");
   1759     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
   1760     // Shift of #32 is encoded as 0 where permitted
   1761     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
   1762     Inst.addOperand(MCOperand::CreateImm(
   1763       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
   1764   }
   1765 
   1766   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
   1767     assert(N == 1 && "Invalid number of operands!");
   1768     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
   1769                                          ShifterImm.Imm));
   1770   }
   1771 
   1772   void addRegListOperands(MCInst &Inst, unsigned N) const {
   1773     assert(N == 1 && "Invalid number of operands!");
   1774     const SmallVectorImpl<unsigned> &RegList = getRegList();
   1775     for (SmallVectorImpl<unsigned>::const_iterator
   1776            I = RegList.begin(), E = RegList.end(); I != E; ++I)
   1777       Inst.addOperand(MCOperand::CreateReg(*I));
   1778   }
   1779 
   1780   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
   1781     addRegListOperands(Inst, N);
   1782   }
   1783 
   1784   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
   1785     addRegListOperands(Inst, N);
   1786   }
   1787 
   1788   void addRotImmOperands(MCInst &Inst, unsigned N) const {
   1789     assert(N == 1 && "Invalid number of operands!");
   1790     // Encoded as val>>3. The printer handles display as 8, 16, 24.
   1791     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
   1792   }
   1793 
   1794   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
   1795     assert(N == 1 && "Invalid number of operands!");
   1796     // Munge the lsb/width into a bitfield mask.
   1797     unsigned lsb = Bitfield.LSB;
   1798     unsigned width = Bitfield.Width;
   1799     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
   1800     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
   1801                       (32 - (lsb + width)));
   1802     Inst.addOperand(MCOperand::CreateImm(Mask));
   1803   }
   1804 
   1805   void addImmOperands(MCInst &Inst, unsigned N) const {
   1806     assert(N == 1 && "Invalid number of operands!");
   1807     addExpr(Inst, getImm());
   1808   }
   1809 
   1810   void addFBits16Operands(MCInst &Inst, unsigned N) const {
   1811     assert(N == 1 && "Invalid number of operands!");
   1812     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1813     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
   1814   }
   1815 
   1816   void addFBits32Operands(MCInst &Inst, unsigned N) const {
   1817     assert(N == 1 && "Invalid number of operands!");
   1818     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1819     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
   1820   }
   1821 
   1822   void addFPImmOperands(MCInst &Inst, unsigned N) const {
   1823     assert(N == 1 && "Invalid number of operands!");
   1824     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1825     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
   1826     Inst.addOperand(MCOperand::CreateImm(Val));
   1827   }
   1828 
   1829   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
   1830     assert(N == 1 && "Invalid number of operands!");
   1831     // FIXME: We really want to scale the value here, but the LDRD/STRD
   1832     // instruction don't encode operands that way yet.
   1833     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1834     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
   1835   }
   1836 
   1837   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
   1838     assert(N == 1 && "Invalid number of operands!");
   1839     // The immediate is scaled by four in the encoding and is stored
   1840     // in the MCInst as such. Lop off the low two bits here.
   1841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1842     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
   1843   }
   1844 
   1845   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
   1846     assert(N == 1 && "Invalid number of operands!");
   1847     // The immediate is scaled by four in the encoding and is stored
   1848     // in the MCInst as such. Lop off the low two bits here.
   1849     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1850     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
   1851   }
   1852 
   1853   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
   1854     assert(N == 1 && "Invalid number of operands!");
   1855     // The immediate is scaled by four in the encoding and is stored
   1856     // in the MCInst as such. Lop off the low two bits here.
   1857     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1858     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
   1859   }
   1860 
   1861   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
   1862     assert(N == 1 && "Invalid number of operands!");
   1863     // The constant encodes as the immediate-1, and we store in the instruction
   1864     // the bits as encoded, so subtract off one here.
   1865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1866     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
   1867   }
   1868 
   1869   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
   1870     assert(N == 1 && "Invalid number of operands!");
   1871     // The constant encodes as the immediate-1, and we store in the instruction
   1872     // the bits as encoded, so subtract off one here.
   1873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1874     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
   1875   }
   1876 
   1877   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
   1878     assert(N == 1 && "Invalid number of operands!");
   1879     // The constant encodes as the immediate, except for 32, which encodes as
   1880     // zero.
   1881     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1882     unsigned Imm = CE->getValue();
   1883     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
   1884   }
   1885 
   1886   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
   1887     assert(N == 1 && "Invalid number of operands!");
   1888     // An ASR value of 32 encodes as 0, so that's how we want to add it to
   1889     // the instruction as well.
   1890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1891     int Val = CE->getValue();
   1892     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
   1893   }
   1894 
   1895   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
   1896     assert(N == 1 && "Invalid number of operands!");
   1897     // The operand is actually a t2_so_imm, but we have its bitwise
   1898     // negation in the assembly source, so twiddle it here.
   1899     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1900     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
   1901   }
   1902 
   1903   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
   1904     assert(N == 1 && "Invalid number of operands!");
   1905     // The operand is actually a t2_so_imm, but we have its
   1906     // negation in the assembly source, so twiddle it here.
   1907     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1908     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
   1909   }
   1910 
   1911   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
   1912     assert(N == 1 && "Invalid number of operands!");
   1913     // The operand is actually an imm0_4095, but we have its
   1914     // negation in the assembly source, so twiddle it here.
   1915     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1916     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
   1917   }
   1918 
   1919   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
   1920     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
   1921       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
   1922       return;
   1923     }
   1924 
   1925     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
   1926     assert(SR && "Unknown value type!");
   1927     Inst.addOperand(MCOperand::CreateExpr(SR));
   1928   }
   1929 
   1930   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
   1931     assert(N == 1 && "Invalid number of operands!");
   1932     if (isImm()) {
   1933       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1934       if (CE) {
   1935         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
   1936         return;
   1937       }
   1938 
   1939       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
   1940       assert(SR && "Unknown value type!");
   1941       Inst.addOperand(MCOperand::CreateExpr(SR));
   1942       return;
   1943     }
   1944 
   1945     assert(isMem()  && "Unknown value type!");
   1946     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
   1947     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
   1948   }
   1949 
   1950   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
   1951     assert(N == 1 && "Invalid number of operands!");
   1952     // The operand is actually a so_imm, but we have its bitwise
   1953     // negation in the assembly source, so twiddle it here.
   1954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1955     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
   1956   }
   1957 
   1958   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
   1959     assert(N == 1 && "Invalid number of operands!");
   1960     // The operand is actually a so_imm, but we have its
   1961     // negation in the assembly source, so twiddle it here.
   1962     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1963     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
   1964   }
   1965 
   1966   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
   1967     assert(N == 1 && "Invalid number of operands!");
   1968     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
   1969   }
   1970 
   1971   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
   1972     assert(N == 1 && "Invalid number of operands!");
   1973     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
   1974   }
   1975 
   1976   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
   1977     assert(N == 1 && "Invalid number of operands!");
   1978     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   1979   }
   1980 
   1981   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
   1982     assert(N == 1 && "Invalid number of operands!");
   1983     int32_t Imm = Memory.OffsetImm->getValue();
   1984     Inst.addOperand(MCOperand::CreateImm(Imm));
   1985   }
   1986 
   1987   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
   1988     assert(N == 1 && "Invalid number of operands!");
   1989     assert(isImm() && "Not an immediate!");
   1990 
   1991     // If we have an immediate that's not a constant, treat it as a label
   1992     // reference needing a fixup.
   1993     if (!isa<MCConstantExpr>(getImm())) {
   1994       Inst.addOperand(MCOperand::CreateExpr(getImm()));
   1995       return;
   1996     }
   1997 
   1998     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   1999     int Val = CE->getValue();
   2000     Inst.addOperand(MCOperand::CreateImm(Val));
   2001   }
   2002 
   2003   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
   2004     assert(N == 2 && "Invalid number of operands!");
   2005     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2006     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
   2007   }
   2008 
   2009   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
   2010     addAlignedMemoryOperands(Inst, N);
   2011   }
   2012 
   2013   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
   2014     addAlignedMemoryOperands(Inst, N);
   2015   }
   2016 
   2017   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
   2018     addAlignedMemoryOperands(Inst, N);
   2019   }
   2020 
   2021   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
   2022     addAlignedMemoryOperands(Inst, N);
   2023   }
   2024 
   2025   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
   2026     addAlignedMemoryOperands(Inst, N);
   2027   }
   2028 
   2029   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
   2030     addAlignedMemoryOperands(Inst, N);
   2031   }
   2032 
   2033   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
   2034     addAlignedMemoryOperands(Inst, N);
   2035   }
   2036 
   2037   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
   2038     addAlignedMemoryOperands(Inst, N);
   2039   }
   2040 
   2041   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
   2042     addAlignedMemoryOperands(Inst, N);
   2043   }
   2044 
   2045   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
   2046     addAlignedMemoryOperands(Inst, N);
   2047   }
   2048 
   2049   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
   2050     addAlignedMemoryOperands(Inst, N);
   2051   }
   2052 
   2053   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
   2054     assert(N == 3 && "Invalid number of operands!");
   2055     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
   2056     if (!Memory.OffsetRegNum) {
   2057       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
   2058       // Special case for #-0
   2059       if (Val == INT32_MIN) Val = 0;
   2060       if (Val < 0) Val = -Val;
   2061       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
   2062     } else {
   2063       // For register offset, we encode the shift type and negation flag
   2064       // here.
   2065       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
   2066                               Memory.ShiftImm, Memory.ShiftType);
   2067     }
   2068     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2069     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2070     Inst.addOperand(MCOperand::CreateImm(Val));
   2071   }
   2072 
   2073   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
   2074     assert(N == 2 && "Invalid number of operands!");
   2075     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2076     assert(CE && "non-constant AM2OffsetImm operand!");
   2077     int32_t Val = CE->getValue();
   2078     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
   2079     // Special case for #-0
   2080     if (Val == INT32_MIN) Val = 0;
   2081     if (Val < 0) Val = -Val;
   2082     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
   2083     Inst.addOperand(MCOperand::CreateReg(0));
   2084     Inst.addOperand(MCOperand::CreateImm(Val));
   2085   }
   2086 
   2087   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
   2088     assert(N == 3 && "Invalid number of operands!");
   2089     // If we have an immediate that's not a constant, treat it as a label
   2090     // reference needing a fixup. If it is a constant, it's something else
   2091     // and we reject it.
   2092     if (isImm()) {
   2093       Inst.addOperand(MCOperand::CreateExpr(getImm()));
   2094       Inst.addOperand(MCOperand::CreateReg(0));
   2095       Inst.addOperand(MCOperand::CreateImm(0));
   2096       return;
   2097     }
   2098 
   2099     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
   2100     if (!Memory.OffsetRegNum) {
   2101       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
   2102       // Special case for #-0
   2103       if (Val == INT32_MIN) Val = 0;
   2104       if (Val < 0) Val = -Val;
   2105       Val = ARM_AM::getAM3Opc(AddSub, Val);
   2106     } else {
   2107       // For register offset, we encode the shift type and negation flag
   2108       // here.
   2109       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
   2110     }
   2111     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2112     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2113     Inst.addOperand(MCOperand::CreateImm(Val));
   2114   }
   2115 
   2116   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
   2117     assert(N == 2 && "Invalid number of operands!");
   2118     if (Kind == k_PostIndexRegister) {
   2119       int32_t Val =
   2120         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
   2121       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
   2122       Inst.addOperand(MCOperand::CreateImm(Val));
   2123       return;
   2124     }
   2125 
   2126     // Constant offset.
   2127     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
   2128     int32_t Val = CE->getValue();
   2129     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
   2130     // Special case for #-0
   2131     if (Val == INT32_MIN) Val = 0;
   2132     if (Val < 0) Val = -Val;
   2133     Val = ARM_AM::getAM3Opc(AddSub, Val);
   2134     Inst.addOperand(MCOperand::CreateReg(0));
   2135     Inst.addOperand(MCOperand::CreateImm(Val));
   2136   }
   2137 
   2138   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
   2139     assert(N == 2 && "Invalid number of operands!");
   2140     // If we have an immediate that's not a constant, treat it as a label
   2141     // reference needing a fixup. If it is a constant, it's something else
   2142     // and we reject it.
   2143     if (isImm()) {
   2144       Inst.addOperand(MCOperand::CreateExpr(getImm()));
   2145       Inst.addOperand(MCOperand::CreateImm(0));
   2146       return;
   2147     }
   2148 
   2149     // The lower two bits are always zero and as such are not encoded.
   2150     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
   2151     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
   2152     // Special case for #-0
   2153     if (Val == INT32_MIN) Val = 0;
   2154     if (Val < 0) Val = -Val;
   2155     Val = ARM_AM::getAM5Opc(AddSub, Val);
   2156     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2157     Inst.addOperand(MCOperand::CreateImm(Val));
   2158   }
   2159 
   2160   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
   2161     assert(N == 2 && "Invalid number of operands!");
   2162     // If we have an immediate that's not a constant, treat it as a label
   2163     // reference needing a fixup. If it is a constant, it's something else
   2164     // and we reject it.
   2165     if (isImm()) {
   2166       Inst.addOperand(MCOperand::CreateExpr(getImm()));
   2167       Inst.addOperand(MCOperand::CreateImm(0));
   2168       return;
   2169     }
   2170 
   2171     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
   2172     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2173     Inst.addOperand(MCOperand::CreateImm(Val));
   2174   }
   2175 
   2176   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
   2177     assert(N == 2 && "Invalid number of operands!");
   2178     // The lower two bits are always zero and as such are not encoded.
   2179     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
   2180     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2181     Inst.addOperand(MCOperand::CreateImm(Val));
   2182   }
   2183 
   2184   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
   2185     assert(N == 2 && "Invalid number of operands!");
   2186     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
   2187     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2188     Inst.addOperand(MCOperand::CreateImm(Val));
   2189   }
   2190 
   2191   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
   2192     addMemImm8OffsetOperands(Inst, N);
   2193   }
   2194 
   2195   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
   2196     addMemImm8OffsetOperands(Inst, N);
   2197   }
   2198 
   2199   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
   2200     assert(N == 2 && "Invalid number of operands!");
   2201     // If this is an immediate, it's a label reference.
   2202     if (isImm()) {
   2203       addExpr(Inst, getImm());
   2204       Inst.addOperand(MCOperand::CreateImm(0));
   2205       return;
   2206     }
   2207 
   2208     // Otherwise, it's a normal memory reg+offset.
   2209     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
   2210     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2211     Inst.addOperand(MCOperand::CreateImm(Val));
   2212   }
   2213 
   2214   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
   2215     assert(N == 2 && "Invalid number of operands!");
   2216     // If this is an immediate, it's a label reference.
   2217     if (isImm()) {
   2218       addExpr(Inst, getImm());
   2219       Inst.addOperand(MCOperand::CreateImm(0));
   2220       return;
   2221     }
   2222 
   2223     // Otherwise, it's a normal memory reg+offset.
   2224     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
   2225     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2226     Inst.addOperand(MCOperand::CreateImm(Val));
   2227   }
   2228 
   2229   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
   2230     assert(N == 2 && "Invalid number of operands!");
   2231     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2232     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2233   }
   2234 
   2235   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
   2236     assert(N == 2 && "Invalid number of operands!");
   2237     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2238     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2239   }
   2240 
   2241   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
   2242     assert(N == 3 && "Invalid number of operands!");
   2243     unsigned Val =
   2244       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
   2245                         Memory.ShiftImm, Memory.ShiftType);
   2246     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2247     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2248     Inst.addOperand(MCOperand::CreateImm(Val));
   2249   }
   2250 
   2251   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
   2252     assert(N == 3 && "Invalid number of operands!");
   2253     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2254     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2255     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
   2256   }
   2257 
   2258   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
   2259     assert(N == 2 && "Invalid number of operands!");
   2260     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2261     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
   2262   }
   2263 
   2264   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
   2265     assert(N == 2 && "Invalid number of operands!");
   2266     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
   2267     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2268     Inst.addOperand(MCOperand::CreateImm(Val));
   2269   }
   2270 
   2271   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
   2272     assert(N == 2 && "Invalid number of operands!");
   2273     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
   2274     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2275     Inst.addOperand(MCOperand::CreateImm(Val));
   2276   }
   2277 
   2278   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
   2279     assert(N == 2 && "Invalid number of operands!");
   2280     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
   2281     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2282     Inst.addOperand(MCOperand::CreateImm(Val));
   2283   }
   2284 
   2285   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
   2286     assert(N == 2 && "Invalid number of operands!");
   2287     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
   2288     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
   2289     Inst.addOperand(MCOperand::CreateImm(Val));
   2290   }
   2291 
   2292   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
   2293     assert(N == 1 && "Invalid number of operands!");
   2294     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2295     assert(CE && "non-constant post-idx-imm8 operand!");
   2296     int Imm = CE->getValue();
   2297     bool isAdd = Imm >= 0;
   2298     if (Imm == INT32_MIN) Imm = 0;
   2299     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
   2300     Inst.addOperand(MCOperand::CreateImm(Imm));
   2301   }
   2302 
   2303   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
   2304     assert(N == 1 && "Invalid number of operands!");
   2305     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2306     assert(CE && "non-constant post-idx-imm8s4 operand!");
   2307     int Imm = CE->getValue();
   2308     bool isAdd = Imm >= 0;
   2309     if (Imm == INT32_MIN) Imm = 0;
   2310     // Immediate is scaled by 4.
   2311     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
   2312     Inst.addOperand(MCOperand::CreateImm(Imm));
   2313   }
   2314 
   2315   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
   2316     assert(N == 2 && "Invalid number of operands!");
   2317     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
   2318     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
   2319   }
   2320 
   2321   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
   2322     assert(N == 2 && "Invalid number of operands!");
   2323     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
   2324     // The sign, shift type, and shift amount are encoded in a single operand
   2325     // using the AM2 encoding helpers.
   2326     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
   2327     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
   2328                                      PostIdxReg.ShiftTy);
   2329     Inst.addOperand(MCOperand::CreateImm(Imm));
   2330   }
   2331 
   2332   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
   2333     assert(N == 1 && "Invalid number of operands!");
   2334     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
   2335   }
   2336 
   2337   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
   2338     assert(N == 1 && "Invalid number of operands!");
   2339     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
   2340   }
   2341 
   2342   void addVecListOperands(MCInst &Inst, unsigned N) const {
   2343     assert(N == 1 && "Invalid number of operands!");
   2344     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
   2345   }
   2346 
   2347   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
   2348     assert(N == 2 && "Invalid number of operands!");
   2349     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
   2350     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
   2351   }
   2352 
   2353   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
   2354     assert(N == 1 && "Invalid number of operands!");
   2355     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
   2356   }
   2357 
   2358   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
   2359     assert(N == 1 && "Invalid number of operands!");
   2360     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
   2361   }
   2362 
   2363   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
   2364     assert(N == 1 && "Invalid number of operands!");
   2365     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
   2366   }
   2367 
   2368   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
   2369     assert(N == 1 && "Invalid number of operands!");
   2370     // The immediate encodes the type of constant as well as the value.
   2371     // Mask in that this is an i8 splat.
   2372     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2373     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
   2374   }
   2375 
   2376   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
   2377     assert(N == 1 && "Invalid number of operands!");
   2378     // The immediate encodes the type of constant as well as the value.
   2379     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2380     unsigned Value = CE->getValue();
   2381     if (Value >= 256)
   2382       Value = (Value >> 8) | 0xa00;
   2383     else
   2384       Value |= 0x800;
   2385     Inst.addOperand(MCOperand::CreateImm(Value));
   2386   }
   2387 
   2388   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
   2389     assert(N == 1 && "Invalid number of operands!");
   2390     // The immediate encodes the type of constant as well as the value.
   2391     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2392     unsigned Value = CE->getValue();
   2393     if (Value >= 256 && Value <= 0xff00)
   2394       Value = (Value >> 8) | 0x200;
   2395     else if (Value > 0xffff && Value <= 0xff0000)
   2396       Value = (Value >> 16) | 0x400;
   2397     else if (Value > 0xffffff)
   2398       Value = (Value >> 24) | 0x600;
   2399     Inst.addOperand(MCOperand::CreateImm(Value));
   2400   }
   2401 
   2402   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
   2403     assert(N == 1 && "Invalid number of operands!");
   2404     // The immediate encodes the type of constant as well as the value.
   2405     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2406     unsigned Value = CE->getValue();
   2407     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
   2408             Inst.getOpcode() == ARM::VMOVv16i8) &&
   2409            "All vmvn instructions that wants to replicate non-zero byte "
   2410            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
   2411     unsigned B = ((~Value) & 0xff);
   2412     B |= 0xe00; // cmode = 0b1110
   2413     Inst.addOperand(MCOperand::CreateImm(B));
   2414   }
   2415   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
   2416     assert(N == 1 && "Invalid number of operands!");
   2417     // The immediate encodes the type of constant as well as the value.
   2418     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2419     unsigned Value = CE->getValue();
   2420     if (Value >= 256 && Value <= 0xffff)
   2421       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
   2422     else if (Value > 0xffff && Value <= 0xffffff)
   2423       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
   2424     else if (Value > 0xffffff)
   2425       Value = (Value >> 24) | 0x600;
   2426     Inst.addOperand(MCOperand::CreateImm(Value));
   2427   }
   2428 
   2429   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
   2430     assert(N == 1 && "Invalid number of operands!");
   2431     // The immediate encodes the type of constant as well as the value.
   2432     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2433     unsigned Value = CE->getValue();
   2434     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
   2435             Inst.getOpcode() == ARM::VMOVv16i8) &&
   2436            "All instructions that wants to replicate non-zero byte "
   2437            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
   2438     unsigned B = Value & 0xff;
   2439     B |= 0xe00; // cmode = 0b1110
   2440     Inst.addOperand(MCOperand::CreateImm(B));
   2441   }
   2442   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
   2443     assert(N == 1 && "Invalid number of operands!");
   2444     // The immediate encodes the type of constant as well as the value.
   2445     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2446     unsigned Value = ~CE->getValue();
   2447     if (Value >= 256 && Value <= 0xffff)
   2448       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
   2449     else if (Value > 0xffff && Value <= 0xffffff)
   2450       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
   2451     else if (Value > 0xffffff)
   2452       Value = (Value >> 24) | 0x600;
   2453     Inst.addOperand(MCOperand::CreateImm(Value));
   2454   }
   2455 
   2456   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
   2457     assert(N == 1 && "Invalid number of operands!");
   2458     // The immediate encodes the type of constant as well as the value.
   2459     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
   2460     uint64_t Value = CE->getValue();
   2461     unsigned Imm = 0;
   2462     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
   2463       Imm |= (Value & 1) << i;
   2464     }
   2465     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
   2466   }
   2467 
   2468   void print(raw_ostream &OS) const override;
   2469 
   2470   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
   2471     auto Op = make_unique<ARMOperand>(k_ITCondMask);
   2472     Op->ITMask.Mask = Mask;
   2473     Op->StartLoc = S;
   2474     Op->EndLoc = S;
   2475     return Op;
   2476   }
   2477 
   2478   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
   2479                                                     SMLoc S) {
   2480     auto Op = make_unique<ARMOperand>(k_CondCode);
   2481     Op->CC.Val = CC;
   2482     Op->StartLoc = S;
   2483     Op->EndLoc = S;
   2484     return Op;
   2485   }
   2486 
   2487   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
   2488     auto Op = make_unique<ARMOperand>(k_CoprocNum);
   2489     Op->Cop.Val = CopVal;
   2490     Op->StartLoc = S;
   2491     Op->EndLoc = S;
   2492     return Op;
   2493   }
   2494 
   2495   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
   2496     auto Op = make_unique<ARMOperand>(k_CoprocReg);
   2497     Op->Cop.Val = CopVal;
   2498     Op->StartLoc = S;
   2499     Op->EndLoc = S;
   2500     return Op;
   2501   }
   2502 
   2503   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
   2504                                                         SMLoc E) {
   2505     auto Op = make_unique<ARMOperand>(k_CoprocOption);
   2506     Op->Cop.Val = Val;
   2507     Op->StartLoc = S;
   2508     Op->EndLoc = E;
   2509     return Op;
   2510   }
   2511 
   2512   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
   2513     auto Op = make_unique<ARMOperand>(k_CCOut);
   2514     Op->Reg.RegNum = RegNum;
   2515     Op->StartLoc = S;
   2516     Op->EndLoc = S;
   2517     return Op;
   2518   }
   2519 
   2520   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
   2521     auto Op = make_unique<ARMOperand>(k_Token);
   2522     Op->Tok.Data = Str.data();
   2523     Op->Tok.Length = Str.size();
   2524     Op->StartLoc = S;
   2525     Op->EndLoc = S;
   2526     return Op;
   2527   }
   2528 
   2529   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
   2530                                                SMLoc E) {
   2531     auto Op = make_unique<ARMOperand>(k_Register);
   2532     Op->Reg.RegNum = RegNum;
   2533     Op->StartLoc = S;
   2534     Op->EndLoc = E;
   2535     return Op;
   2536   }
   2537 
   2538   static std::unique_ptr<ARMOperand>
   2539   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
   2540                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
   2541                         SMLoc E) {
   2542     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
   2543     Op->RegShiftedReg.ShiftTy = ShTy;
   2544     Op->RegShiftedReg.SrcReg = SrcReg;
   2545     Op->RegShiftedReg.ShiftReg = ShiftReg;
   2546     Op->RegShiftedReg.ShiftImm = ShiftImm;
   2547     Op->StartLoc = S;
   2548     Op->EndLoc = E;
   2549     return Op;
   2550   }
   2551 
   2552   static std::unique_ptr<ARMOperand>
   2553   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
   2554                          unsigned ShiftImm, SMLoc S, SMLoc E) {
   2555     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
   2556     Op->RegShiftedImm.ShiftTy = ShTy;
   2557     Op->RegShiftedImm.SrcReg = SrcReg;
   2558     Op->RegShiftedImm.ShiftImm = ShiftImm;
   2559     Op->StartLoc = S;
   2560     Op->EndLoc = E;
   2561     return Op;
   2562   }
   2563 
   2564   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
   2565                                                       SMLoc S, SMLoc E) {
   2566     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
   2567     Op->ShifterImm.isASR = isASR;
   2568     Op->ShifterImm.Imm = Imm;
   2569     Op->StartLoc = S;
   2570     Op->EndLoc = E;
   2571     return Op;
   2572   }
   2573 
   2574   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
   2575                                                   SMLoc E) {
   2576     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
   2577     Op->RotImm.Imm = Imm;
   2578     Op->StartLoc = S;
   2579     Op->EndLoc = E;
   2580     return Op;
   2581   }
   2582 
   2583   static std::unique_ptr<ARMOperand>
   2584   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
   2585     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
   2586     Op->Bitfield.LSB = LSB;
   2587     Op->Bitfield.Width = Width;
   2588     Op->StartLoc = S;
   2589     Op->EndLoc = E;
   2590     return Op;
   2591   }
   2592 
   2593   static std::unique_ptr<ARMOperand>
   2594   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
   2595                 SMLoc StartLoc, SMLoc EndLoc) {
   2596     assert (Regs.size() > 0 && "RegList contains no registers?");
   2597     KindTy Kind = k_RegisterList;
   2598 
   2599     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
   2600       Kind = k_DPRRegisterList;
   2601     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
   2602              contains(Regs.front().second))
   2603       Kind = k_SPRRegisterList;
   2604 
   2605     // Sort based on the register encoding values.
   2606     array_pod_sort(Regs.begin(), Regs.end());
   2607 
   2608     auto Op = make_unique<ARMOperand>(Kind);
   2609     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
   2610            I = Regs.begin(), E = Regs.end(); I != E; ++I)
   2611       Op->Registers.push_back(I->second);
   2612     Op->StartLoc = StartLoc;
   2613     Op->EndLoc = EndLoc;
   2614     return Op;
   2615   }
   2616 
   2617   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
   2618                                                       unsigned Count,
   2619                                                       bool isDoubleSpaced,
   2620                                                       SMLoc S, SMLoc E) {
   2621     auto Op = make_unique<ARMOperand>(k_VectorList);
   2622     Op->VectorList.RegNum = RegNum;
   2623     Op->VectorList.Count = Count;
   2624     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
   2625     Op->StartLoc = S;
   2626     Op->EndLoc = E;
   2627     return Op;
   2628   }
   2629 
   2630   static std::unique_ptr<ARMOperand>
   2631   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
   2632                            SMLoc S, SMLoc E) {
   2633     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
   2634     Op->VectorList.RegNum = RegNum;
   2635     Op->VectorList.Count = Count;
   2636     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
   2637     Op->StartLoc = S;
   2638     Op->EndLoc = E;
   2639     return Op;
   2640   }
   2641 
   2642   static std::unique_ptr<ARMOperand>
   2643   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
   2644                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
   2645     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
   2646     Op->VectorList.RegNum = RegNum;
   2647     Op->VectorList.Count = Count;
   2648     Op->VectorList.LaneIndex = Index;
   2649     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
   2650     Op->StartLoc = S;
   2651     Op->EndLoc = E;
   2652     return Op;
   2653   }
   2654 
   2655   static std::unique_ptr<ARMOperand>
   2656   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
   2657     auto Op = make_unique<ARMOperand>(k_VectorIndex);
   2658     Op->VectorIndex.Val = Idx;
   2659     Op->StartLoc = S;
   2660     Op->EndLoc = E;
   2661     return Op;
   2662   }
   2663 
   2664   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
   2665                                                SMLoc E) {
   2666     auto Op = make_unique<ARMOperand>(k_Immediate);
   2667     Op->Imm.Val = Val;
   2668     Op->StartLoc = S;
   2669     Op->EndLoc = E;
   2670     return Op;
   2671   }
   2672 
   2673   static std::unique_ptr<ARMOperand>
   2674   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
   2675             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
   2676             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
   2677             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
   2678     auto Op = make_unique<ARMOperand>(k_Memory);
   2679     Op->Memory.BaseRegNum = BaseRegNum;
   2680     Op->Memory.OffsetImm = OffsetImm;
   2681     Op->Memory.OffsetRegNum = OffsetRegNum;
   2682     Op->Memory.ShiftType = ShiftType;
   2683     Op->Memory.ShiftImm = ShiftImm;
   2684     Op->Memory.Alignment = Alignment;
   2685     Op->Memory.isNegative = isNegative;
   2686     Op->StartLoc = S;
   2687     Op->EndLoc = E;
   2688     Op->AlignmentLoc = AlignmentLoc;
   2689     return Op;
   2690   }
   2691 
   2692   static std::unique_ptr<ARMOperand>
   2693   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
   2694                    unsigned ShiftImm, SMLoc S, SMLoc E) {
   2695     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
   2696     Op->PostIdxReg.RegNum = RegNum;
   2697     Op->PostIdxReg.isAdd = isAdd;
   2698     Op->PostIdxReg.ShiftTy = ShiftTy;
   2699     Op->PostIdxReg.ShiftImm = ShiftImm;
   2700     Op->StartLoc = S;
   2701     Op->EndLoc = E;
   2702     return Op;
   2703   }
   2704 
   2705   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
   2706                                                          SMLoc S) {
   2707     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
   2708     Op->MBOpt.Val = Opt;
   2709     Op->StartLoc = S;
   2710     Op->EndLoc = S;
   2711     return Op;
   2712   }
   2713 
   2714   static std::unique_ptr<ARMOperand>
   2715   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
   2716     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
   2717     Op->ISBOpt.Val = Opt;
   2718     Op->StartLoc = S;
   2719     Op->EndLoc = S;
   2720     return Op;
   2721   }
   2722 
   2723   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
   2724                                                       SMLoc S) {
   2725     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
   2726     Op->IFlags.Val = IFlags;
   2727     Op->StartLoc = S;
   2728     Op->EndLoc = S;
   2729     return Op;
   2730   }
   2731 
   2732   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
   2733     auto Op = make_unique<ARMOperand>(k_MSRMask);
   2734     Op->MMask.Val = MMask;
   2735     Op->StartLoc = S;
   2736     Op->EndLoc = S;
   2737     return Op;
   2738   }
   2739 };
   2740 
   2741 } // end anonymous namespace.
   2742 
   2743 void ARMOperand::print(raw_ostream &OS) const {
   2744   switch (Kind) {
   2745   case k_CondCode:
   2746     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
   2747     break;
   2748   case k_CCOut:
   2749     OS << "<ccout " << getReg() << ">";
   2750     break;
   2751   case k_ITCondMask: {
   2752     static const char *const MaskStr[] = {
   2753       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
   2754       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
   2755     };
   2756     assert((ITMask.Mask & 0xf) == ITMask.Mask);
   2757     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
   2758     break;
   2759   }
   2760   case k_CoprocNum:
   2761     OS << "<coprocessor number: " << getCoproc() << ">";
   2762     break;
   2763   case k_CoprocReg:
   2764     OS << "<coprocessor register: " << getCoproc() << ">";
   2765     break;
   2766   case k_CoprocOption:
   2767     OS << "<coprocessor option: " << CoprocOption.Val << ">";
   2768     break;
   2769   case k_MSRMask:
   2770     OS << "<mask: " << getMSRMask() << ">";
   2771     break;
   2772   case k_Immediate:
   2773     getImm()->print(OS);
   2774     break;
   2775   case k_MemBarrierOpt:
   2776     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
   2777     break;
   2778   case k_InstSyncBarrierOpt:
   2779     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
   2780     break;
   2781   case k_Memory:
   2782     OS << "<memory "
   2783        << " base:" << Memory.BaseRegNum;
   2784     OS << ">";
   2785     break;
   2786   case k_PostIndexRegister:
   2787     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
   2788        << PostIdxReg.RegNum;
   2789     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
   2790       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
   2791          << PostIdxReg.ShiftImm;
   2792     OS << ">";
   2793     break;
   2794   case k_ProcIFlags: {
   2795     OS << "<ARM_PROC::";
   2796     unsigned IFlags = getProcIFlags();
   2797     for (int i=2; i >= 0; --i)
   2798       if (IFlags & (1 << i))
   2799         OS << ARM_PROC::IFlagsToString(1 << i);
   2800     OS << ">";
   2801     break;
   2802   }
   2803   case k_Register:
   2804     OS << "<register " << getReg() << ">";
   2805     break;
   2806   case k_ShifterImmediate:
   2807     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
   2808        << " #" << ShifterImm.Imm << ">";
   2809     break;
   2810   case k_ShiftedRegister:
   2811     OS << "<so_reg_reg "
   2812        << RegShiftedReg.SrcReg << " "
   2813        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
   2814        << " " << RegShiftedReg.ShiftReg << ">";
   2815     break;
   2816   case k_ShiftedImmediate:
   2817     OS << "<so_reg_imm "
   2818        << RegShiftedImm.SrcReg << " "
   2819        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
   2820        << " #" << RegShiftedImm.ShiftImm << ">";
   2821     break;
   2822   case k_RotateImmediate:
   2823     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
   2824     break;
   2825   case k_BitfieldDescriptor:
   2826     OS << "<bitfield " << "lsb: " << Bitfield.LSB
   2827        << ", width: " << Bitfield.Width << ">";
   2828     break;
   2829   case k_RegisterList:
   2830   case k_DPRRegisterList:
   2831   case k_SPRRegisterList: {
   2832     OS << "<register_list ";
   2833 
   2834     const SmallVectorImpl<unsigned> &RegList = getRegList();
   2835     for (SmallVectorImpl<unsigned>::const_iterator
   2836            I = RegList.begin(), E = RegList.end(); I != E; ) {
   2837       OS << *I;
   2838       if (++I < E) OS << ", ";
   2839     }
   2840 
   2841     OS << ">";
   2842     break;
   2843   }
   2844   case k_VectorList:
   2845     OS << "<vector_list " << VectorList.Count << " * "
   2846        << VectorList.RegNum << ">";
   2847     break;
   2848   case k_VectorListAllLanes:
   2849     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
   2850        << VectorList.RegNum << ">";
   2851     break;
   2852   case k_VectorListIndexed:
   2853     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
   2854        << VectorList.Count << " * " << VectorList.RegNum << ">";
   2855     break;
   2856   case k_Token:
   2857     OS << "'" << getToken() << "'";
   2858     break;
   2859   case k_VectorIndex:
   2860     OS << "<vectorindex " << getVectorIndex() << ">";
   2861     break;
   2862   }
   2863 }
   2864 
   2865 /// @name Auto-generated Match Functions
   2866 /// {
   2867 
   2868 static unsigned MatchRegisterName(StringRef Name);
   2869 
   2870 /// }
   2871 
   2872 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
   2873                                  SMLoc &StartLoc, SMLoc &EndLoc) {
   2874   StartLoc = Parser.getTok().getLoc();
   2875   EndLoc = Parser.getTok().getEndLoc();
   2876   RegNo = tryParseRegister();
   2877 
   2878   return (RegNo == (unsigned)-1);
   2879 }
   2880 
   2881 /// Try to parse a register name.  The token must be an Identifier when called,
   2882 /// and if it is a register name the token is eaten and the register number is
   2883 /// returned.  Otherwise return -1.
   2884 ///
   2885 int ARMAsmParser::tryParseRegister() {
   2886   const AsmToken &Tok = Parser.getTok();
   2887   if (Tok.isNot(AsmToken::Identifier)) return -1;
   2888 
   2889   std::string lowerCase = Tok.getString().lower();
   2890   unsigned RegNum = MatchRegisterName(lowerCase);
   2891   if (!RegNum) {
   2892     RegNum = StringSwitch<unsigned>(lowerCase)
   2893       .Case("r13", ARM::SP)
   2894       .Case("r14", ARM::LR)
   2895       .Case("r15", ARM::PC)
   2896       .Case("ip", ARM::R12)
   2897       // Additional register name aliases for 'gas' compatibility.
   2898       .Case("a1", ARM::R0)
   2899       .Case("a2", ARM::R1)
   2900       .Case("a3", ARM::R2)
   2901       .Case("a4", ARM::R3)
   2902       .Case("v1", ARM::R4)
   2903       .Case("v2", ARM::R5)
   2904       .Case("v3", ARM::R6)
   2905       .Case("v4", ARM::R7)
   2906       .Case("v5", ARM::R8)
   2907       .Case("v6", ARM::R9)
   2908       .Case("v7", ARM::R10)
   2909       .Case("v8", ARM::R11)
   2910       .Case("sb", ARM::R9)
   2911       .Case("sl", ARM::R10)
   2912       .Case("fp", ARM::R11)
   2913       .Default(0);
   2914   }
   2915   if (!RegNum) {
   2916     // Check for aliases registered via .req. Canonicalize to lower case.
   2917     // That's more consistent since register names are case insensitive, and
   2918     // it's how the original entry was passed in from MC/MCParser/AsmParser.
   2919     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
   2920     // If no match, return failure.
   2921     if (Entry == RegisterReqs.end())
   2922       return -1;
   2923     Parser.Lex(); // Eat identifier token.
   2924     return Entry->getValue();
   2925   }
   2926 
   2927   Parser.Lex(); // Eat identifier token.
   2928 
   2929   return RegNum;
   2930 }
   2931 
   2932 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
   2933 // If a recoverable error occurs, return 1. If an irrecoverable error
   2934 // occurs, return -1. An irrecoverable error is one where tokens have been
   2935 // consumed in the process of trying to parse the shifter (i.e., when it is
   2936 // indeed a shifter operand, but malformed).
   2937 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
   2938   SMLoc S = Parser.getTok().getLoc();
   2939   const AsmToken &Tok = Parser.getTok();
   2940   if (Tok.isNot(AsmToken::Identifier))
   2941     return -1;
   2942 
   2943   std::string lowerCase = Tok.getString().lower();
   2944   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
   2945       .Case("asl", ARM_AM::lsl)
   2946       .Case("lsl", ARM_AM::lsl)
   2947       .Case("lsr", ARM_AM::lsr)
   2948       .Case("asr", ARM_AM::asr)
   2949       .Case("ror", ARM_AM::ror)
   2950       .Case("rrx", ARM_AM::rrx)
   2951       .Default(ARM_AM::no_shift);
   2952 
   2953   if (ShiftTy == ARM_AM::no_shift)
   2954     return 1;
   2955 
   2956   Parser.Lex(); // Eat the operator.
   2957 
   2958   // The source register for the shift has already been added to the
   2959   // operand list, so we need to pop it off and combine it into the shifted
   2960   // register operand instead.
   2961   std::unique_ptr<ARMOperand> PrevOp(
   2962       (ARMOperand *)Operands.pop_back_val().release());
   2963   if (!PrevOp->isReg())
   2964     return Error(PrevOp->getStartLoc(), "shift must be of a register");
   2965   int SrcReg = PrevOp->getReg();
   2966 
   2967   SMLoc EndLoc;
   2968   int64_t Imm = 0;
   2969   int ShiftReg = 0;
   2970   if (ShiftTy == ARM_AM::rrx) {
   2971     // RRX Doesn't have an explicit shift amount. The encoder expects
   2972     // the shift register to be the same as the source register. Seems odd,
   2973     // but OK.
   2974     ShiftReg = SrcReg;
   2975   } else {
   2976     // Figure out if this is shifted by a constant or a register (for non-RRX).
   2977     if (Parser.getTok().is(AsmToken::Hash) ||
   2978         Parser.getTok().is(AsmToken::Dollar)) {
   2979       Parser.Lex(); // Eat hash.
   2980       SMLoc ImmLoc = Parser.getTok().getLoc();
   2981       const MCExpr *ShiftExpr = nullptr;
   2982       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
   2983         Error(ImmLoc, "invalid immediate shift value");
   2984         return -1;
   2985       }
   2986       // The expression must be evaluatable as an immediate.
   2987       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
   2988       if (!CE) {
   2989         Error(ImmLoc, "invalid immediate shift value");
   2990         return -1;
   2991       }
   2992       // Range check the immediate.
   2993       // lsl, ror: 0 <= imm <= 31
   2994       // lsr, asr: 0 <= imm <= 32
   2995       Imm = CE->getValue();
   2996       if (Imm < 0 ||
   2997           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
   2998           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
   2999         Error(ImmLoc, "immediate shift value out of range");
   3000         return -1;
   3001       }
   3002       // shift by zero is a nop. Always send it through as lsl.
   3003       // ('as' compatibility)
   3004       if (Imm == 0)
   3005         ShiftTy = ARM_AM::lsl;
   3006     } else if (Parser.getTok().is(AsmToken::Identifier)) {
   3007       SMLoc L = Parser.getTok().getLoc();
   3008       EndLoc = Parser.getTok().getEndLoc();
   3009       ShiftReg = tryParseRegister();
   3010       if (ShiftReg == -1) {
   3011         Error(L, "expected immediate or register in shift operand");
   3012         return -1;
   3013       }
   3014     } else {
   3015       Error(Parser.getTok().getLoc(),
   3016             "expected immediate or register in shift operand");
   3017       return -1;
   3018     }
   3019   }
   3020 
   3021   if (ShiftReg && ShiftTy != ARM_AM::rrx)
   3022     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
   3023                                                          ShiftReg, Imm,
   3024                                                          S, EndLoc));
   3025   else
   3026     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
   3027                                                           S, EndLoc));
   3028 
   3029   return 0;
   3030 }
   3031 
   3032 
   3033 /// Try to parse a register name.  The token must be an Identifier when called.
   3034 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
   3035 /// if there is a "writeback". 'true' if it's not a register.
   3036 ///
   3037 /// TODO this is likely to change to allow different register types and or to
   3038 /// parse for a specific register type.
   3039 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
   3040   const AsmToken &RegTok = Parser.getTok();
   3041   int RegNo = tryParseRegister();
   3042   if (RegNo == -1)
   3043     return true;
   3044 
   3045   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
   3046                                            RegTok.getEndLoc()));
   3047 
   3048   const AsmToken &ExclaimTok = Parser.getTok();
   3049   if (ExclaimTok.is(AsmToken::Exclaim)) {
   3050     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
   3051                                                ExclaimTok.getLoc()));
   3052     Parser.Lex(); // Eat exclaim token
   3053     return false;
   3054   }
   3055 
   3056   // Also check for an index operand. This is only legal for vector registers,
   3057   // but that'll get caught OK in operand matching, so we don't need to
   3058   // explicitly filter everything else out here.
   3059   if (Parser.getTok().is(AsmToken::LBrac)) {
   3060     SMLoc SIdx = Parser.getTok().getLoc();
   3061     Parser.Lex(); // Eat left bracket token.
   3062 
   3063     const MCExpr *ImmVal;
   3064     if (getParser().parseExpression(ImmVal))
   3065       return true;
   3066     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
   3067     if (!MCE)
   3068       return TokError("immediate value expected for vector index");
   3069 
   3070     if (Parser.getTok().isNot(AsmToken::RBrac))
   3071       return Error(Parser.getTok().getLoc(), "']' expected");
   3072 
   3073     SMLoc E = Parser.getTok().getEndLoc();
   3074     Parser.Lex(); // Eat right bracket token.
   3075 
   3076     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
   3077                                                      SIdx, E,
   3078                                                      getContext()));
   3079   }
   3080 
   3081   return false;
   3082 }
   3083 
   3084 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
   3085 /// instruction with a symbolic operand name.
   3086 /// We accept "crN" syntax for GAS compatibility.
   3087 /// <operand-name> ::= <prefix><number>
   3088 /// If CoprocOp is 'c', then:
   3089 ///   <prefix> ::= c | cr
   3090 /// If CoprocOp is 'p', then :
   3091 ///   <prefix> ::= p
   3092 /// <number> ::= integer in range [0, 15]
   3093 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
   3094   // Use the same layout as the tablegen'erated register name matcher. Ugly,
   3095   // but efficient.
   3096   if (Name.size() < 2 || Name[0] != CoprocOp)
   3097     return -1;
   3098   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
   3099 
   3100   switch (Name.size()) {
   3101   default: return -1;
   3102   case 1:
   3103     switch (Name[0]) {
   3104     default:  return -1;
   3105     case '0': return 0;
   3106     case '1': return 1;
   3107     case '2': return 2;
   3108     case '3': return 3;
   3109     case '4': return 4;
   3110     case '5': return 5;
   3111     case '6': return 6;
   3112     case '7': return 7;
   3113     case '8': return 8;
   3114     case '9': return 9;
   3115     }
   3116   case 2:
   3117     if (Name[0] != '1')
   3118       return -1;
   3119     switch (Name[1]) {
   3120     default:  return -1;
   3121     // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
   3122     case '0': return CoprocOp == 'p'? -1: 10;
   3123     case '1': return CoprocOp == 'p'? -1: 11;
   3124     case '2': return 12;
   3125     case '3': return 13;
   3126     case '4': return 14;
   3127     case '5': return 15;
   3128     }
   3129   }
   3130 }
   3131 
   3132 /// parseITCondCode - Try to parse a condition code for an IT instruction.
   3133 ARMAsmParser::OperandMatchResultTy
   3134 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
   3135   SMLoc S = Parser.getTok().getLoc();
   3136   const AsmToken &Tok = Parser.getTok();
   3137   if (!Tok.is(AsmToken::Identifier))
   3138     return MatchOperand_NoMatch;
   3139   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
   3140     .Case("eq", ARMCC::EQ)
   3141     .Case("ne", ARMCC::NE)
   3142     .Case("hs", ARMCC::HS)
   3143     .Case("cs", ARMCC::HS)
   3144     .Case("lo", ARMCC::LO)
   3145     .Case("cc", ARMCC::LO)
   3146     .Case("mi", ARMCC::MI)
   3147     .Case("pl", ARMCC::PL)
   3148     .Case("vs", ARMCC::VS)
   3149     .Case("vc", ARMCC::VC)
   3150     .Case("hi", ARMCC::HI)
   3151     .Case("ls", ARMCC::LS)
   3152     .Case("ge", ARMCC::GE)
   3153     .Case("lt", ARMCC::LT)
   3154     .Case("gt", ARMCC::GT)
   3155     .Case("le", ARMCC::LE)
   3156     .Case("al", ARMCC::AL)
   3157     .Default(~0U);
   3158   if (CC == ~0U)
   3159     return MatchOperand_NoMatch;
   3160   Parser.Lex(); // Eat the token.
   3161 
   3162   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
   3163 
   3164   return MatchOperand_Success;
   3165 }
   3166 
   3167 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
   3168 /// token must be an Identifier when called, and if it is a coprocessor
   3169 /// number, the token is eaten and the operand is added to the operand list.
   3170 ARMAsmParser::OperandMatchResultTy
   3171 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
   3172   SMLoc S = Parser.getTok().getLoc();
   3173   const AsmToken &Tok = Parser.getTok();
   3174   if (Tok.isNot(AsmToken::Identifier))
   3175     return MatchOperand_NoMatch;
   3176 
   3177   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
   3178   if (Num == -1)
   3179     return MatchOperand_NoMatch;
   3180 
   3181   Parser.Lex(); // Eat identifier token.
   3182   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
   3183   return MatchOperand_Success;
   3184 }
   3185 
   3186 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
   3187 /// token must be an Identifier when called, and if it is a coprocessor
   3188 /// number, the token is eaten and the operand is added to the operand list.
   3189 ARMAsmParser::OperandMatchResultTy
   3190 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
   3191   SMLoc S = Parser.getTok().getLoc();
   3192   const AsmToken &Tok = Parser.getTok();
   3193   if (Tok.isNot(AsmToken::Identifier))
   3194     return MatchOperand_NoMatch;
   3195 
   3196   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
   3197   if (Reg == -1)
   3198     return MatchOperand_NoMatch;
   3199 
   3200   Parser.Lex(); // Eat identifier token.
   3201   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
   3202   return MatchOperand_Success;
   3203 }
   3204 
   3205 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
   3206 /// coproc_option : '{' imm0_255 '}'
   3207 ARMAsmParser::OperandMatchResultTy
   3208 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
   3209   SMLoc S = Parser.getTok().getLoc();
   3210 
   3211   // If this isn't a '{', this isn't a coprocessor immediate operand.
   3212   if (Parser.getTok().isNot(AsmToken::LCurly))
   3213     return MatchOperand_NoMatch;
   3214   Parser.Lex(); // Eat the '{'
   3215 
   3216   const MCExpr *Expr;
   3217   SMLoc Loc = Parser.getTok().getLoc();
   3218   if (getParser().parseExpression(Expr)) {
   3219     Error(Loc, "illegal expression");
   3220     return MatchOperand_ParseFail;
   3221   }
   3222   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
   3223   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
   3224     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
   3225     return MatchOperand_ParseFail;
   3226   }
   3227   int Val = CE->getValue();
   3228 
   3229   // Check for and consume the closing '}'
   3230   if (Parser.getTok().isNot(AsmToken::RCurly))
   3231     return MatchOperand_ParseFail;
   3232   SMLoc E = Parser.getTok().getEndLoc();
   3233   Parser.Lex(); // Eat the '}'
   3234 
   3235   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
   3236   return MatchOperand_Success;
   3237 }
   3238 
   3239 // For register list parsing, we need to map from raw GPR register numbering
   3240 // to the enumeration values. The enumeration values aren't sorted by
   3241 // register number due to our using "sp", "lr" and "pc" as canonical names.
   3242 static unsigned getNextRegister(unsigned Reg) {
   3243   // If this is a GPR, we need to do it manually, otherwise we can rely
   3244   // on the sort ordering of the enumeration since the other reg-classes
   3245   // are sane.
   3246   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
   3247     return Reg + 1;
   3248   switch(Reg) {
   3249   default: llvm_unreachable("Invalid GPR number!");
   3250   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
   3251   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
   3252   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
   3253   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
   3254   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
   3255   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
   3256   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
   3257   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
   3258   }
   3259 }
   3260 
   3261 // Return the low-subreg of a given Q register.
   3262 static unsigned getDRegFromQReg(unsigned QReg) {
   3263   switch (QReg) {
   3264   default: llvm_unreachable("expected a Q register!");
   3265   case ARM::Q0:  return ARM::D0;
   3266   case ARM::Q1:  return ARM::D2;
   3267   case ARM::Q2:  return ARM::D4;
   3268   case ARM::Q3:  return ARM::D6;
   3269   case ARM::Q4:  return ARM::D8;
   3270   case ARM::Q5:  return ARM::D10;
   3271   case ARM::Q6:  return ARM::D12;
   3272   case ARM::Q7:  return ARM::D14;
   3273   case ARM::Q8:  return ARM::D16;
   3274   case ARM::Q9:  return ARM::D18;
   3275   case ARM::Q10: return ARM::D20;
   3276   case ARM::Q11: return ARM::D22;
   3277   case ARM::Q12: return ARM::D24;
   3278   case ARM::Q13: return ARM::D26;
   3279   case ARM::Q14: return ARM::D28;
   3280   case ARM::Q15: return ARM::D30;
   3281   }
   3282 }
   3283 
   3284 /// Parse a register list.
   3285 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
   3286   assert(Parser.getTok().is(AsmToken::LCurly) &&
   3287          "Token is not a Left Curly Brace");
   3288   SMLoc S = Parser.getTok().getLoc();
   3289   Parser.Lex(); // Eat '{' token.
   3290   SMLoc RegLoc = Parser.getTok().getLoc();
   3291 
   3292   // Check the first register in the list to see what register class
   3293   // this is a list of.
   3294   int Reg = tryParseRegister();
   3295   if (Reg == -1)
   3296     return Error(RegLoc, "register expected");
   3297 
   3298   // The reglist instructions have at most 16 registers, so reserve
   3299   // space for that many.
   3300   int EReg = 0;
   3301   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
   3302 
   3303   // Allow Q regs and just interpret them as the two D sub-registers.
   3304   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
   3305     Reg = getDRegFromQReg(Reg);
   3306     EReg = MRI->getEncodingValue(Reg);
   3307     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
   3308     ++Reg;
   3309   }
   3310   const MCRegisterClass *RC;
   3311   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
   3312     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
   3313   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
   3314     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
   3315   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
   3316     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
   3317   else
   3318     return Error(RegLoc, "invalid register in register list");
   3319 
   3320   // Store the register.
   3321   EReg = MRI->getEncodingValue(Reg);
   3322   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
   3323 
   3324   // This starts immediately after the first register token in the list,
   3325   // so we can see either a comma or a minus (range separator) as a legal
   3326   // next token.
   3327   while (Parser.getTok().is(AsmToken::Comma) ||
   3328          Parser.getTok().is(AsmToken::Minus)) {
   3329     if (Parser.getTok().is(AsmToken::Minus)) {
   3330       Parser.Lex(); // Eat the minus.
   3331       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
   3332       int EndReg = tryParseRegister();
   3333       if (EndReg == -1)
   3334         return Error(AfterMinusLoc, "register expected");
   3335       // Allow Q regs and just interpret them as the two D sub-registers.
   3336       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
   3337         EndReg = getDRegFromQReg(EndReg) + 1;
   3338       // If the register is the same as the start reg, there's nothing
   3339       // more to do.
   3340       if (Reg == EndReg)
   3341         continue;
   3342       // The register must be in the same register class as the first.
   3343       if (!RC->contains(EndReg))
   3344         return Error(AfterMinusLoc, "invalid register in register list");
   3345       // Ranges must go from low to high.
   3346       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
   3347         return Error(AfterMinusLoc, "bad range in register list");
   3348 
   3349       // Add all the registers in the range to the register list.
   3350       while (Reg != EndReg) {
   3351         Reg = getNextRegister(Reg);
   3352         EReg = MRI->getEncodingValue(Reg);
   3353         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
   3354       }
   3355       continue;
   3356     }
   3357     Parser.Lex(); // Eat the comma.
   3358     RegLoc = Parser.getTok().getLoc();
   3359     int OldReg = Reg;
   3360     const AsmToken RegTok = Parser.getTok();
   3361     Reg = tryParseRegister();
   3362     if (Reg == -1)
   3363       return Error(RegLoc, "register expected");
   3364     // Allow Q regs and just interpret them as the two D sub-registers.
   3365     bool isQReg = false;
   3366     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
   3367       Reg = getDRegFromQReg(Reg);
   3368       isQReg = true;
   3369     }
   3370     // The register must be in the same register class as the first.
   3371     if (!RC->contains(Reg))
   3372       return Error(RegLoc, "invalid register in register list");
   3373     // List must be monotonically increasing.
   3374     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
   3375       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
   3376         Warning(RegLoc, "register list not in ascending order");
   3377       else
   3378         return Error(RegLoc, "register list not in ascending order");
   3379     }
   3380     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
   3381       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
   3382               ") in register list");
   3383       continue;
   3384     }
   3385     // VFP register lists must also be contiguous.
   3386     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
   3387         Reg != OldReg + 1)
   3388       return Error(RegLoc, "non-contiguous register range");
   3389     EReg = MRI->getEncodingValue(Reg);
   3390     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
   3391     if (isQReg) {
   3392       EReg = MRI->getEncodingValue(++Reg);
   3393       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
   3394     }
   3395   }
   3396 
   3397   if (Parser.getTok().isNot(AsmToken::RCurly))
   3398     return Error(Parser.getTok().getLoc(), "'}' expected");
   3399   SMLoc E = Parser.getTok().getEndLoc();
   3400   Parser.Lex(); // Eat '}' token.
   3401 
   3402   // Push the register list operand.
   3403   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
   3404 
   3405   // The ARM system instruction variants for LDM/STM have a '^' token here.
   3406   if (Parser.getTok().is(AsmToken::Caret)) {
   3407     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
   3408     Parser.Lex(); // Eat '^' token.
   3409   }
   3410 
   3411   return false;
   3412 }
   3413 
   3414 // Helper function to parse the lane index for vector lists.
   3415 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
   3416 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
   3417   Index = 0; // Always return a defined index value.
   3418   if (Parser.getTok().is(AsmToken::LBrac)) {
   3419     Parser.Lex(); // Eat the '['.
   3420     if (Parser.getTok().is(AsmToken::RBrac)) {
   3421       // "Dn[]" is the 'all lanes' syntax.
   3422       LaneKind = AllLanes;
   3423       EndLoc = Parser.getTok().getEndLoc();
   3424       Parser.Lex(); // Eat the ']'.
   3425       return MatchOperand_Success;
   3426     }
   3427 
   3428     // There's an optional '#' token here. Normally there wouldn't be, but
   3429     // inline assemble puts one in, and it's friendly to accept that.
   3430     if (Parser.getTok().is(AsmToken::Hash))
   3431       Parser.Lex(); // Eat '#' or '$'.
   3432 
   3433     const MCExpr *LaneIndex;
   3434     SMLoc Loc = Parser.getTok().getLoc();
   3435     if (getParser().parseExpression(LaneIndex)) {
   3436       Error(Loc, "illegal expression");
   3437       return MatchOperand_ParseFail;
   3438     }
   3439     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
   3440     if (!CE) {
   3441       Error(Loc, "lane index must be empty or an integer");
   3442       return MatchOperand_ParseFail;
   3443     }
   3444     if (Parser.getTok().isNot(AsmToken::RBrac)) {
   3445       Error(Parser.getTok().getLoc(), "']' expected");
   3446       return MatchOperand_ParseFail;
   3447     }
   3448     EndLoc = Parser.getTok().getEndLoc();
   3449     Parser.Lex(); // Eat the ']'.
   3450     int64_t Val = CE->getValue();
   3451 
   3452     // FIXME: Make this range check context sensitive for .8, .16, .32.
   3453     if (Val < 0 || Val > 7) {
   3454       Error(Parser.getTok().getLoc(), "lane index out of range");
   3455       return MatchOperand_ParseFail;
   3456     }
   3457     Index = Val;
   3458     LaneKind = IndexedLane;
   3459     return MatchOperand_Success;
   3460   }
   3461   LaneKind = NoLanes;
   3462   return MatchOperand_Success;
   3463 }
   3464 
   3465 // parse a vector register list
   3466 ARMAsmParser::OperandMatchResultTy
   3467 ARMAsmParser::parseVectorList(OperandVector &Operands) {
   3468   VectorLaneTy LaneKind;
   3469   unsigned LaneIndex;
   3470   SMLoc S = Parser.getTok().getLoc();
   3471   // As an extension (to match gas), support a plain D register or Q register
   3472   // (without encosing curly braces) as a single or double entry list,
   3473   // respectively.
   3474   if (Parser.getTok().is(AsmToken::Identifier)) {
   3475     SMLoc E = Parser.getTok().getEndLoc();
   3476     int Reg = tryParseRegister();
   3477     if (Reg == -1)
   3478       return MatchOperand_NoMatch;
   3479     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
   3480       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
   3481       if (Res != MatchOperand_Success)
   3482         return Res;
   3483       switch (LaneKind) {
   3484       case NoLanes:
   3485         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
   3486         break;
   3487       case AllLanes:
   3488         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
   3489                                                                 S, E));
   3490         break;
   3491       case IndexedLane:
   3492         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
   3493                                                                LaneIndex,
   3494                                                                false, S, E));
   3495         break;
   3496       }
   3497       return MatchOperand_Success;
   3498     }
   3499     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
   3500       Reg = getDRegFromQReg(Reg);
   3501       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
   3502       if (Res != MatchOperand_Success)
   3503         return Res;
   3504       switch (LaneKind) {
   3505       case NoLanes:
   3506         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
   3507                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
   3508         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
   3509         break;
   3510       case AllLanes:
   3511         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
   3512                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
   3513         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
   3514                                                                 S, E));
   3515         break;
   3516       case IndexedLane:
   3517         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
   3518                                                                LaneIndex,
   3519                                                                false, S, E));
   3520         break;
   3521       }
   3522       return MatchOperand_Success;
   3523     }
   3524     Error(S, "vector register expected");
   3525     return MatchOperand_ParseFail;
   3526   }
   3527 
   3528   if (Parser.getTok().isNot(AsmToken::LCurly))
   3529     return MatchOperand_NoMatch;
   3530 
   3531   Parser.Lex(); // Eat '{' token.
   3532   SMLoc RegLoc = Parser.getTok().getLoc();
   3533 
   3534   int Reg = tryParseRegister();
   3535   if (Reg == -1) {
   3536     Error(RegLoc, "register expected");
   3537     return MatchOperand_ParseFail;
   3538   }
   3539   unsigned Count = 1;
   3540   int Spacing = 0;
   3541   unsigned FirstReg = Reg;
   3542   // The list is of D registers, but we also allow Q regs and just interpret
   3543   // them as the two D sub-registers.
   3544   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
   3545     FirstReg = Reg = getDRegFromQReg(Reg);
   3546     Spacing = 1; // double-spacing requires explicit D registers, otherwise
   3547                  // it's ambiguous with four-register single spaced.
   3548     ++Reg;
   3549     ++Count;
   3550   }
   3551 
   3552   SMLoc E;
   3553   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
   3554     return MatchOperand_ParseFail;
   3555 
   3556   while (Parser.getTok().is(AsmToken::Comma) ||
   3557          Parser.getTok().is(AsmToken::Minus)) {
   3558     if (Parser.getTok().is(AsmToken::Minus)) {
   3559       if (!Spacing)
   3560         Spacing = 1; // Register range implies a single spaced list.
   3561       else if (Spacing == 2) {
   3562         Error(Parser.getTok().getLoc(),
   3563               "sequential registers in double spaced list");
   3564         return MatchOperand_ParseFail;
   3565       }
   3566       Parser.Lex(); // Eat the minus.
   3567       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
   3568       int EndReg = tryParseRegister();
   3569       if (EndReg == -1) {
   3570         Error(AfterMinusLoc, "register expected");
   3571         return MatchOperand_ParseFail;
   3572       }
   3573       // Allow Q regs and just interpret them as the two D sub-registers.
   3574       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
   3575         EndReg = getDRegFromQReg(EndReg) + 1;
   3576       // If the register is the same as the start reg, there's nothing
   3577       // more to do.
   3578       if (Reg == EndReg)
   3579         continue;
   3580       // The register must be in the same register class as the first.
   3581       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
   3582         Error(AfterMinusLoc, "invalid register in register list");
   3583         return MatchOperand_ParseFail;
   3584       }
   3585       // Ranges must go from low to high.
   3586       if (Reg > EndReg) {
   3587         Error(AfterMinusLoc, "bad range in register list");
   3588         return MatchOperand_ParseFail;
   3589       }
   3590       // Parse the lane specifier if present.
   3591       VectorLaneTy NextLaneKind;
   3592       unsigned NextLaneIndex;
   3593       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
   3594           MatchOperand_Success)
   3595         return MatchOperand_ParseFail;
   3596       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
   3597         Error(AfterMinusLoc, "mismatched lane index in register list");
   3598         return MatchOperand_ParseFail;
   3599       }
   3600 
   3601       // Add all the registers in the range to the register list.
   3602       Count += EndReg - Reg;
   3603       Reg = EndReg;
   3604       continue;
   3605     }
   3606     Parser.Lex(); // Eat the comma.
   3607     RegLoc = Parser.getTok().getLoc();
   3608     int OldReg = Reg;
   3609     Reg = tryParseRegister();
   3610     if (Reg == -1) {
   3611       Error(RegLoc, "register expected");
   3612       return MatchOperand_ParseFail;
   3613     }
   3614     // vector register lists must be contiguous.
   3615     // It's OK to use the enumeration values directly here rather, as the
   3616     // VFP register classes have the enum sorted properly.
   3617     //
   3618     // The list is of D registers, but we also allow Q regs and just interpret
   3619     // them as the two D sub-registers.
   3620     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
   3621       if (!Spacing)
   3622         Spacing = 1; // Register range implies a single spaced list.
   3623       else if (Spacing == 2) {
   3624         Error(RegLoc,
   3625               "invalid register in double-spaced list (must be 'D' register')");
   3626         return MatchOperand_ParseFail;
   3627       }
   3628       Reg = getDRegFromQReg(Reg);
   3629       if (Reg != OldReg + 1) {
   3630         Error(RegLoc, "non-contiguous register range");
   3631         return MatchOperand_ParseFail;
   3632       }
   3633       ++Reg;
   3634       Count += 2;
   3635       // Parse the lane specifier if present.
   3636       VectorLaneTy NextLaneKind;
   3637       unsigned NextLaneIndex;
   3638       SMLoc LaneLoc = Parser.getTok().getLoc();
   3639       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
   3640           MatchOperand_Success)
   3641         return MatchOperand_ParseFail;
   3642       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
   3643         Error(LaneLoc, "mismatched lane index in register list");
   3644         return MatchOperand_ParseFail;
   3645       }
   3646       continue;
   3647     }
   3648     // Normal D register.
   3649     // Figure out the register spacing (single or double) of the list if
   3650     // we don't know it already.
   3651     if (!Spacing)
   3652       Spacing = 1 + (Reg == OldReg + 2);
   3653 
   3654     // Just check that it's contiguous and keep going.
   3655     if (Reg != OldReg + Spacing) {
   3656       Error(RegLoc, "non-contiguous register range");
   3657       return MatchOperand_ParseFail;
   3658     }
   3659     ++Count;
   3660     // Parse the lane specifier if present.
   3661     VectorLaneTy NextLaneKind;
   3662     unsigned NextLaneIndex;
   3663     SMLoc EndLoc = Parser.getTok().getLoc();
   3664     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
   3665       return MatchOperand_ParseFail;
   3666     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
   3667       Error(EndLoc, "mismatched lane index in register list");
   3668       return MatchOperand_ParseFail;
   3669     }
   3670   }
   3671 
   3672   if (Parser.getTok().isNot(AsmToken::RCurly)) {
   3673     Error(Parser.getTok().getLoc(), "'}' expected");
   3674     return MatchOperand_ParseFail;
   3675   }
   3676   E = Parser.getTok().getEndLoc();
   3677   Parser.Lex(); // Eat '}' token.
   3678 
   3679   switch (LaneKind) {
   3680   case NoLanes:
   3681     // Two-register operands have been converted to the
   3682     // composite register classes.
   3683     if (Count == 2) {
   3684       const MCRegisterClass *RC = (Spacing == 1) ?
   3685         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
   3686         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
   3687       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
   3688     }
   3689 
   3690     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
   3691                                                     (Spacing == 2), S, E));
   3692     break;
   3693   case AllLanes:
   3694     // Two-register operands have been converted to the
   3695     // composite register classes.
   3696     if (Count == 2) {
   3697       const MCRegisterClass *RC = (Spacing == 1) ?
   3698         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
   3699         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
   3700       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
   3701     }
   3702     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
   3703                                                             (Spacing == 2),
   3704                                                             S, E));
   3705     break;
   3706   case IndexedLane:
   3707     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
   3708                                                            LaneIndex,
   3709                                                            (Spacing == 2),
   3710                                                            S, E));
   3711     break;
   3712   }
   3713   return MatchOperand_Success;
   3714 }
   3715 
   3716 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
   3717 ARMAsmParser::OperandMatchResultTy
   3718 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
   3719   SMLoc S = Parser.getTok().getLoc();
   3720   const AsmToken &Tok = Parser.getTok();
   3721   unsigned Opt;
   3722 
   3723   if (Tok.is(AsmToken::Identifier)) {
   3724     StringRef OptStr = Tok.getString();
   3725 
   3726     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
   3727       .Case("sy",    ARM_MB::SY)
   3728       .Case("st",    ARM_MB::ST)
   3729       .Case("ld",    ARM_MB::LD)
   3730       .Case("sh",    ARM_MB::ISH)
   3731       .Case("ish",   ARM_MB::ISH)
   3732       .Case("shst",  ARM_MB::ISHST)
   3733       .Case("ishst", ARM_MB::ISHST)
   3734       .Case("ishld", ARM_MB::ISHLD)
   3735       .Case("nsh",   ARM_MB::NSH)
   3736       .Case("un",    ARM_MB::NSH)
   3737       .Case("nshst", ARM_MB::NSHST)
   3738       .Case("nshld", ARM_MB::NSHLD)
   3739       .Case("unst",  ARM_MB::NSHST)
   3740       .Case("osh",   ARM_MB::OSH)
   3741       .Case("oshst", ARM_MB::OSHST)
   3742       .Case("oshld", ARM_MB::OSHLD)
   3743       .Default(~0U);
   3744 
   3745     // ishld, oshld, nshld and ld are only available from ARMv8.
   3746     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
   3747                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
   3748       Opt = ~0U;
   3749 
   3750     if (Opt == ~0U)
   3751       return MatchOperand_NoMatch;
   3752 
   3753     Parser.Lex(); // Eat identifier token.
   3754   } else if (Tok.is(AsmToken::Hash) ||
   3755              Tok.is(AsmToken::Dollar) ||
   3756              Tok.is(AsmToken::Integer)) {
   3757     if (Parser.getTok().isNot(AsmToken::Integer))
   3758       Parser.Lex(); // Eat '#' or '$'.
   3759     SMLoc Loc = Parser.getTok().getLoc();
   3760 
   3761     const MCExpr *MemBarrierID;
   3762     if (getParser().parseExpression(MemBarrierID)) {
   3763       Error(Loc, "illegal expression");
   3764       return MatchOperand_ParseFail;
   3765     }
   3766 
   3767     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
   3768     if (!CE) {
   3769       Error(Loc, "constant expression expected");
   3770       return MatchOperand_ParseFail;
   3771     }
   3772 
   3773     int Val = CE->getValue();
   3774     if (Val & ~0xf) {
   3775       Error(Loc, "immediate value out of range");
   3776       return MatchOperand_ParseFail;
   3777     }
   3778 
   3779     Opt = ARM_MB::RESERVED_0 + Val;
   3780   } else
   3781     return MatchOperand_ParseFail;
   3782 
   3783   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
   3784   return MatchOperand_Success;
   3785 }
   3786 
   3787 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
   3788 ARMAsmParser::OperandMatchResultTy
   3789 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
   3790   SMLoc S = Parser.getTok().getLoc();
   3791   const AsmToken &Tok = Parser.getTok();
   3792   unsigned Opt;
   3793 
   3794   if (Tok.is(AsmToken::Identifier)) {
   3795     StringRef OptStr = Tok.getString();
   3796 
   3797     if (OptStr.equals_lower("sy"))
   3798       Opt = ARM_ISB::SY;
   3799     else
   3800       return MatchOperand_NoMatch;
   3801 
   3802     Parser.Lex(); // Eat identifier token.
   3803   } else if (Tok.is(AsmToken::Hash) ||
   3804              Tok.is(AsmToken::Dollar) ||
   3805              Tok.is(AsmToken::Integer)) {
   3806     if (Parser.getTok().isNot(AsmToken::Integer))
   3807       Parser.Lex(); // Eat '#' or '$'.
   3808     SMLoc Loc = Parser.getTok().getLoc();
   3809 
   3810     const MCExpr *ISBarrierID;
   3811     if (getParser().parseExpression(ISBarrierID)) {
   3812       Error(Loc, "illegal expression");
   3813       return MatchOperand_ParseFail;
   3814     }
   3815 
   3816     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
   3817     if (!CE) {
   3818       Error(Loc, "constant expression expected");
   3819       return MatchOperand_ParseFail;
   3820     }
   3821 
   3822     int Val = CE->getValue();
   3823     if (Val & ~0xf) {
   3824       Error(Loc, "immediate value out of range");
   3825       return MatchOperand_ParseFail;
   3826     }
   3827 
   3828     Opt = ARM_ISB::RESERVED_0 + Val;
   3829   } else
   3830     return MatchOperand_ParseFail;
   3831 
   3832   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
   3833           (ARM_ISB::InstSyncBOpt)Opt, S));
   3834   return MatchOperand_Success;
   3835 }
   3836 
   3837 
   3838 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
   3839 ARMAsmParser::OperandMatchResultTy
   3840 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
   3841   SMLoc S = Parser.getTok().getLoc();
   3842   const AsmToken &Tok = Parser.getTok();
   3843   if (!Tok.is(AsmToken::Identifier))
   3844     return MatchOperand_NoMatch;
   3845   StringRef IFlagsStr = Tok.getString();
   3846 
   3847   // An iflags string of "none" is interpreted to mean that none of the AIF
   3848   // bits are set.  Not a terribly useful instruction, but a valid encoding.
   3849   unsigned IFlags = 0;
   3850   if (IFlagsStr != "none") {
   3851         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
   3852       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
   3853         .Case("a", ARM_PROC::A)
   3854         .Case("i", ARM_PROC::I)
   3855         .Case("f", ARM_PROC::F)
   3856         .Default(~0U);
   3857 
   3858       // If some specific iflag is already set, it means that some letter is
   3859       // present more than once, this is not acceptable.
   3860       if (Flag == ~0U || (IFlags & Flag))
   3861         return MatchOperand_NoMatch;
   3862 
   3863       IFlags |= Flag;
   3864     }
   3865   }
   3866 
   3867   Parser.Lex(); // Eat identifier token.
   3868   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
   3869   return MatchOperand_Success;
   3870 }
   3871 
   3872 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
   3873 ARMAsmParser::OperandMatchResultTy
   3874 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
   3875   SMLoc S = Parser.getTok().getLoc();
   3876   const AsmToken &Tok = Parser.getTok();
   3877   if (!Tok.is(AsmToken::Identifier))
   3878     return MatchOperand_NoMatch;
   3879   StringRef Mask = Tok.getString();
   3880 
   3881   if (isMClass()) {
   3882     // See ARMv6-M 10.1.1
   3883     std::string Name = Mask.lower();
   3884     unsigned FlagsVal = StringSwitch<unsigned>(Name)
   3885       // Note: in the documentation:
   3886       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
   3887       //  for MSR APSR_nzcvq.
   3888       // but we do make it an alias here.  This is so to get the "mask encoding"
   3889       // bits correct on MSR APSR writes.
   3890       //
   3891       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
   3892       // should really only be allowed when writing a special register.  Note
   3893       // they get dropped in the MRS instruction reading a special register as
   3894       // the SYSm field is only 8 bits.
   3895       //
   3896       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
   3897       // includes the DSP extension but that is not checked.
   3898       .Case("apsr", 0x800)
   3899       .Case("apsr_nzcvq", 0x800)
   3900       .Case("apsr_g", 0x400)
   3901       .Case("apsr_nzcvqg", 0xc00)
   3902       .Case("iapsr", 0x801)
   3903       .Case("iapsr_nzcvq", 0x801)
   3904       .Case("iapsr_g", 0x401)
   3905       .Case("iapsr_nzcvqg", 0xc01)
   3906       .Case("eapsr", 0x802)
   3907       .Case("eapsr_nzcvq", 0x802)
   3908       .Case("eapsr_g", 0x402)
   3909       .Case("eapsr_nzcvqg", 0xc02)
   3910       .Case("xpsr", 0x803)
   3911       .Case("xpsr_nzcvq", 0x803)
   3912       .Case("xpsr_g", 0x403)
   3913       .Case("xpsr_nzcvqg", 0xc03)
   3914       .Case("ipsr", 0x805)
   3915       .Case("epsr", 0x806)
   3916       .Case("iepsr", 0x807)
   3917       .Case("msp", 0x808)
   3918       .Case("psp", 0x809)
   3919       .Case("primask", 0x810)
   3920       .Case("basepri", 0x811)
   3921       .Case("basepri_max", 0x812)
   3922       .Case("faultmask", 0x813)
   3923       .Case("control", 0x814)
   3924       .Default(~0U);
   3925 
   3926     if (FlagsVal == ~0U)
   3927       return MatchOperand_NoMatch;
   3928 
   3929     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
   3930       // basepri, basepri_max and faultmask only valid for V7m.
   3931       return MatchOperand_NoMatch;
   3932 
   3933     Parser.Lex(); // Eat identifier token.
   3934     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
   3935     return MatchOperand_Success;
   3936   }
   3937 
   3938   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
   3939   size_t Start = 0, Next = Mask.find('_');
   3940   StringRef Flags = "";
   3941   std::string SpecReg = Mask.slice(Start, Next).lower();
   3942   if (Next != StringRef::npos)
   3943     Flags = Mask.slice(Next+1, Mask.size());
   3944 
   3945   // FlagsVal contains the complete mask:
   3946   // 3-0: Mask
   3947   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
   3948   unsigned FlagsVal = 0;
   3949 
   3950   if (SpecReg == "apsr") {
   3951     FlagsVal = StringSwitch<unsigned>(Flags)
   3952     .Case("nzcvq",  0x8) // same as CPSR_f
   3953     .Case("g",      0x4) // same as CPSR_s
   3954     .Case("nzcvqg", 0xc) // same as CPSR_fs
   3955     .Default(~0U);
   3956 
   3957     if (FlagsVal == ~0U) {
   3958       if (!Flags.empty())
   3959         return MatchOperand_NoMatch;
   3960       else
   3961         FlagsVal = 8; // No flag
   3962     }
   3963   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
   3964     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
   3965     if (Flags == "all" || Flags == "")
   3966       Flags = "fc";
   3967     for (int i = 0, e = Flags.size(); i != e; ++i) {
   3968       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
   3969       .Case("c", 1)
   3970       .Case("x", 2)
   3971       .Case("s", 4)
   3972       .Case("f", 8)
   3973       .Default(~0U);
   3974 
   3975       // If some specific flag is already set, it means that some letter is
   3976       // present more than once, this is not acceptable.
   3977       if (FlagsVal == ~0U || (FlagsVal & Flag))
   3978         return MatchOperand_NoMatch;
   3979       FlagsVal |= Flag;
   3980     }
   3981   } else // No match for special register.
   3982     return MatchOperand_NoMatch;
   3983 
   3984   // Special register without flags is NOT equivalent to "fc" flags.
   3985   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
   3986   // two lines would enable gas compatibility at the expense of breaking
   3987   // round-tripping.
   3988   //
   3989   // if (!FlagsVal)
   3990   //  FlagsVal = 0x9;
   3991 
   3992   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
   3993   if (SpecReg == "spsr")
   3994     FlagsVal |= 16;
   3995 
   3996   Parser.Lex(); // Eat identifier token.
   3997   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
   3998   return MatchOperand_Success;
   3999 }
   4000 
   4001 ARMAsmParser::OperandMatchResultTy
   4002 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
   4003                           int High) {
   4004   const AsmToken &Tok = Parser.getTok();
   4005   if (Tok.isNot(AsmToken::Identifier)) {
   4006     Error(Parser.getTok().getLoc(), Op + " operand expected.");
   4007     return MatchOperand_ParseFail;
   4008   }
   4009   StringRef ShiftName = Tok.getString();
   4010   std::string LowerOp = Op.lower();
   4011   std::string UpperOp = Op.upper();
   4012   if (ShiftName != LowerOp && ShiftName != UpperOp) {
   4013     Error(Parser.getTok().getLoc(), Op + " operand expected.");
   4014     return MatchOperand_ParseFail;
   4015   }
   4016   Parser.Lex(); // Eat shift type token.
   4017 
   4018   // There must be a '#' and a shift amount.
   4019   if (Parser.getTok().isNot(AsmToken::Hash) &&
   4020       Parser.getTok().isNot(AsmToken::Dollar)) {
   4021     Error(Parser.getTok().getLoc(), "'#' expected");
   4022     return MatchOperand_ParseFail;
   4023   }
   4024   Parser.Lex(); // Eat hash token.
   4025 
   4026   const MCExpr *ShiftAmount;
   4027   SMLoc Loc = Parser.getTok().getLoc();
   4028   SMLoc EndLoc;
   4029   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
   4030     Error(Loc, "illegal expression");
   4031     return MatchOperand_ParseFail;
   4032   }
   4033   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
   4034   if (!CE) {
   4035     Error(Loc, "constant expression expected");
   4036     return MatchOperand_ParseFail;
   4037   }
   4038   int Val = CE->getValue();
   4039   if (Val < Low || Val > High) {
   4040     Error(Loc, "immediate value out of range");
   4041     return MatchOperand_ParseFail;
   4042   }
   4043 
   4044   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
   4045 
   4046   return MatchOperand_Success;
   4047 }
   4048 
   4049 ARMAsmParser::OperandMatchResultTy
   4050 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
   4051   const AsmToken &Tok = Parser.getTok();
   4052   SMLoc S = Tok.getLoc();
   4053   if (Tok.isNot(AsmToken::Identifier)) {
   4054     Error(S, "'be' or 'le' operand expected");
   4055     return MatchOperand_ParseFail;
   4056   }
   4057   int Val = StringSwitch<int>(Tok.getString().lower())
   4058     .Case("be", 1)
   4059     .Case("le", 0)
   4060     .Default(-1);
   4061   Parser.Lex(); // Eat the token.
   4062 
   4063   if (Val == -1) {
   4064     Error(S, "'be' or 'le' operand expected");
   4065     return MatchOperand_ParseFail;
   4066   }
   4067   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
   4068                                                                   getContext()),
   4069                                            S, Tok.getEndLoc()));
   4070   return MatchOperand_Success;
   4071 }
   4072 
   4073 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
   4074 /// instructions. Legal values are:
   4075 ///     lsl #n  'n' in [0,31]
   4076 ///     asr #n  'n' in [1,32]
   4077 ///             n == 32 encoded as n == 0.
   4078 ARMAsmParser::OperandMatchResultTy
   4079 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
   4080   const AsmToken &Tok = Parser.getTok();
   4081   SMLoc S = Tok.getLoc();
   4082   if (Tok.isNot(AsmToken::Identifier)) {
   4083     Error(S, "shift operator 'asr' or 'lsl' expected");
   4084     return MatchOperand_ParseFail;
   4085   }
   4086   StringRef ShiftName = Tok.getString();
   4087   bool isASR;
   4088   if (ShiftName == "lsl" || ShiftName == "LSL")
   4089     isASR = false;
   4090   else if (ShiftName == "asr" || ShiftName == "ASR")
   4091     isASR = true;
   4092   else {
   4093     Error(S, "shift operator 'asr' or 'lsl' expected");
   4094     return MatchOperand_ParseFail;
   4095   }
   4096   Parser.Lex(); // Eat the operator.
   4097 
   4098   // A '#' and a shift amount.
   4099   if (Parser.getTok().isNot(AsmToken::Hash) &&
   4100       Parser.getTok().isNot(AsmToken::Dollar)) {
   4101     Error(Parser.getTok().getLoc(), "'#' expected");
   4102     return MatchOperand_ParseFail;
   4103   }
   4104   Parser.Lex(); // Eat hash token.
   4105   SMLoc ExLoc = Parser.getTok().getLoc();
   4106 
   4107   const MCExpr *ShiftAmount;
   4108   SMLoc EndLoc;
   4109   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
   4110     Error(ExLoc, "malformed shift expression");
   4111     return MatchOperand_ParseFail;
   4112   }
   4113   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
   4114   if (!CE) {
   4115     Error(ExLoc, "shift amount must be an immediate");
   4116     return MatchOperand_ParseFail;
   4117   }
   4118 
   4119   int64_t Val = CE->getValue();
   4120   if (isASR) {
   4121     // Shift amount must be in [1,32]
   4122     if (Val < 1 || Val > 32) {
   4123       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
   4124       return MatchOperand_ParseFail;
   4125     }
   4126     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
   4127     if (isThumb() && Val == 32) {
   4128       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
   4129       return MatchOperand_ParseFail;
   4130     }
   4131     if (Val == 32) Val = 0;
   4132   } else {
   4133     // Shift amount must be in [1,32]
   4134     if (Val < 0 || Val > 31) {
   4135       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
   4136       return MatchOperand_ParseFail;
   4137     }
   4138   }
   4139 
   4140   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
   4141 
   4142   return MatchOperand_Success;
   4143 }
   4144 
   4145 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
   4146 /// of instructions. Legal values are:
   4147 ///     ror #n  'n' in {0, 8, 16, 24}
   4148 ARMAsmParser::OperandMatchResultTy
   4149 ARMAsmParser::parseRotImm(OperandVector &Operands) {
   4150   const AsmToken &Tok = Parser.getTok();
   4151   SMLoc S = Tok.getLoc();
   4152   if (Tok.isNot(AsmToken::Identifier))
   4153     return MatchOperand_NoMatch;
   4154   StringRef ShiftName = Tok.getString();
   4155   if (ShiftName != "ror" && ShiftName != "ROR")
   4156     return MatchOperand_NoMatch;
   4157   Parser.Lex(); // Eat the operator.
   4158 
   4159   // A '#' and a rotate amount.
   4160   if (Parser.getTok().isNot(AsmToken::Hash) &&
   4161       Parser.getTok().isNot(AsmToken::Dollar)) {
   4162     Error(Parser.getTok().getLoc(), "'#' expected");
   4163     return MatchOperand_ParseFail;
   4164   }
   4165   Parser.Lex(); // Eat hash token.
   4166   SMLoc ExLoc = Parser.getTok().getLoc();
   4167 
   4168   const MCExpr *ShiftAmount;
   4169   SMLoc EndLoc;
   4170   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
   4171     Error(ExLoc, "malformed rotate expression");
   4172     return MatchOperand_ParseFail;
   4173   }
   4174   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
   4175   if (!CE) {
   4176     Error(ExLoc, "rotate amount must be an immediate");
   4177     return MatchOperand_ParseFail;
   4178   }
   4179 
   4180   int64_t Val = CE->getValue();
   4181   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
   4182   // normally, zero is represented in asm by omitting the rotate operand
   4183   // entirely.
   4184   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
   4185     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
   4186     return MatchOperand_ParseFail;
   4187   }
   4188 
   4189   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
   4190 
   4191   return MatchOperand_Success;
   4192 }
   4193 
   4194 ARMAsmParser::OperandMatchResultTy
   4195 ARMAsmParser::parseBitfield(OperandVector &Operands) {
   4196   SMLoc S = Parser.getTok().getLoc();
   4197   // The bitfield descriptor is really two operands, the LSB and the width.
   4198   if (Parser.getTok().isNot(AsmToken::Hash) &&
   4199       Parser.getTok().isNot(AsmToken::Dollar)) {
   4200     Error(Parser.getTok().getLoc(), "'#' expected");
   4201     return MatchOperand_ParseFail;
   4202   }
   4203   Parser.Lex(); // Eat hash token.
   4204 
   4205   const MCExpr *LSBExpr;
   4206   SMLoc E = Parser.getTok().getLoc();
   4207   if (getParser().parseExpression(LSBExpr)) {
   4208     Error(E, "malformed immediate expression");
   4209     return MatchOperand_ParseFail;
   4210   }
   4211   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
   4212   if (!CE) {
   4213     Error(E, "'lsb' operand must be an immediate");
   4214     return MatchOperand_ParseFail;
   4215   }
   4216 
   4217   int64_t LSB = CE->getValue();
   4218   // The LSB must be in the range [0,31]
   4219   if (LSB < 0 || LSB > 31) {
   4220     Error(E, "'lsb' operand must be in the range [0,31]");
   4221     return MatchOperand_ParseFail;
   4222   }
   4223   E = Parser.getTok().getLoc();
   4224 
   4225   // Expect another immediate operand.
   4226   if (Parser.getTok().isNot(AsmToken::Comma)) {
   4227     Error(Parser.getTok().getLoc(), "too few operands");
   4228     return MatchOperand_ParseFail;
   4229   }
   4230   Parser.Lex(); // Eat hash token.
   4231   if (Parser.getTok().isNot(AsmToken::Hash) &&
   4232       Parser.getTok().isNot(AsmToken::Dollar)) {
   4233     Error(Parser.getTok().getLoc(), "'#' expected");
   4234     return MatchOperand_ParseFail;
   4235   }
   4236   Parser.Lex(); // Eat hash token.
   4237 
   4238   const MCExpr *WidthExpr;
   4239   SMLoc EndLoc;
   4240   if (getParser().parseExpression(WidthExpr, EndLoc)) {
   4241     Error(E, "malformed immediate expression");
   4242     return MatchOperand_ParseFail;
   4243   }
   4244   CE = dyn_cast<MCConstantExpr>(WidthExpr);
   4245   if (!CE) {
   4246     Error(E, "'width' operand must be an immediate");
   4247     return MatchOperand_ParseFail;
   4248   }
   4249 
   4250   int64_t Width = CE->getValue();
   4251   // The LSB must be in the range [1,32-lsb]
   4252   if (Width < 1 || Width > 32 - LSB) {
   4253     Error(E, "'width' operand must be in the range [1,32-lsb]");
   4254     return MatchOperand_ParseFail;
   4255   }
   4256 
   4257   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
   4258 
   4259   return MatchOperand_Success;
   4260 }
   4261 
   4262 ARMAsmParser::OperandMatchResultTy
   4263 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
   4264   // Check for a post-index addressing register operand. Specifically:
   4265   // postidx_reg := '+' register {, shift}
   4266   //              | '-' register {, shift}
   4267   //              | register {, shift}
   4268 
   4269   // This method must return MatchOperand_NoMatch without consuming any tokens
   4270   // in the case where there is no match, as other alternatives take other
   4271   // parse methods.
   4272   AsmToken Tok = Parser.getTok();
   4273   SMLoc S = Tok.getLoc();
   4274   bool haveEaten = false;
   4275   bool isAdd = true;
   4276   if (Tok.is(AsmToken::Plus)) {
   4277     Parser.Lex(); // Eat the '+' token.
   4278     haveEaten = true;
   4279   } else if (Tok.is(AsmToken::Minus)) {
   4280     Parser.Lex(); // Eat the '-' token.
   4281     isAdd = false;
   4282     haveEaten = true;
   4283   }
   4284 
   4285   SMLoc E = Parser.getTok().getEndLoc();
   4286   int Reg = tryParseRegister();
   4287   if (Reg == -1) {
   4288     if (!haveEaten)
   4289       return MatchOperand_NoMatch;
   4290     Error(Parser.getTok().getLoc(), "register expected");
   4291     return MatchOperand_ParseFail;
   4292   }
   4293 
   4294   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
   4295   unsigned ShiftImm = 0;
   4296   if (Parser.getTok().is(AsmToken::Comma)) {
   4297     Parser.Lex(); // Eat the ','.
   4298     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
   4299       return MatchOperand_ParseFail;
   4300 
   4301     // FIXME: Only approximates end...may include intervening whitespace.
   4302     E = Parser.getTok().getLoc();
   4303   }
   4304 
   4305   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
   4306                                                   ShiftImm, S, E));
   4307 
   4308   return MatchOperand_Success;
   4309 }
   4310 
   4311 ARMAsmParser::OperandMatchResultTy
   4312 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
   4313   // Check for a post-index addressing register operand. Specifically:
   4314   // am3offset := '+' register
   4315   //              | '-' register
   4316   //              | register
   4317   //              | # imm
   4318   //              | # + imm
   4319   //              | # - imm
   4320 
   4321   // This method must return MatchOperand_NoMatch without consuming any tokens
   4322   // in the case where there is no match, as other alternatives take other
   4323   // parse methods.
   4324   AsmToken Tok = Parser.getTok();
   4325   SMLoc S = Tok.getLoc();
   4326 
   4327   // Do immediates first, as we always parse those if we have a '#'.
   4328   if (Parser.getTok().is(AsmToken::Hash) ||
   4329       Parser.getTok().is(AsmToken::Dollar)) {
   4330     Parser.Lex(); // Eat '#' or '$'.
   4331     // Explicitly look for a '-', as we need to encode negative zero
   4332     // differently.
   4333     bool isNegative = Parser.getTok().is(AsmToken::Minus);
   4334     const MCExpr *Offset;
   4335     SMLoc E;
   4336     if (getParser().parseExpression(Offset, E))
   4337       return MatchOperand_ParseFail;
   4338     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
   4339     if (!CE) {
   4340       Error(S, "constant expression expected");
   4341       return MatchOperand_ParseFail;
   4342     }
   4343     // Negative zero is encoded as the flag value INT32_MIN.
   4344     int32_t Val = CE->getValue();
   4345     if (isNegative && Val == 0)
   4346       Val = INT32_MIN;
   4347 
   4348     Operands.push_back(
   4349       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
   4350 
   4351     return MatchOperand_Success;
   4352   }
   4353 
   4354 
   4355   bool haveEaten = false;
   4356   bool isAdd = true;
   4357   if (Tok.is(AsmToken::Plus)) {
   4358     Parser.Lex(); // Eat the '+' token.
   4359     haveEaten = true;
   4360   } else if (Tok.is(AsmToken::Minus)) {
   4361     Parser.Lex(); // Eat the '-' token.
   4362     isAdd = false;
   4363     haveEaten = true;
   4364   }
   4365 
   4366   Tok = Parser.getTok();
   4367   int Reg = tryParseRegister();
   4368   if (Reg == -1) {
   4369     if (!haveEaten)
   4370       return MatchOperand_NoMatch;
   4371     Error(Tok.getLoc(), "register expected");
   4372     return MatchOperand_ParseFail;
   4373   }
   4374 
   4375   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
   4376                                                   0, S, Tok.getEndLoc()));
   4377 
   4378   return MatchOperand_Success;
   4379 }
   4380 
   4381 /// Convert parsed operands to MCInst.  Needed here because this instruction
   4382 /// only has two register operands, but multiplication is commutative so
   4383 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
   4384 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
   4385                                     const OperandVector &Operands) {
   4386   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
   4387   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
   4388   // If we have a three-operand form, make sure to set Rn to be the operand
   4389   // that isn't the same as Rd.
   4390   unsigned RegOp = 4;
   4391   if (Operands.size() == 6 &&
   4392       ((ARMOperand &)*Operands[4]).getReg() ==
   4393           ((ARMOperand &)*Operands[3]).getReg())
   4394     RegOp = 5;
   4395   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
   4396   Inst.addOperand(Inst.getOperand(0));
   4397   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
   4398 }
   4399 
   4400 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
   4401                                     const OperandVector &Operands) {
   4402   int CondOp = -1, ImmOp = -1;
   4403   switch(Inst.getOpcode()) {
   4404     case ARM::tB:
   4405     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
   4406 
   4407     case ARM::t2B:
   4408     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
   4409 
   4410     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
   4411   }
   4412   // first decide whether or not the branch should be conditional
   4413   // by looking at it's location relative to an IT block
   4414   if(inITBlock()) {
   4415     // inside an IT block we cannot have any conditional branches. any
   4416     // such instructions needs to be converted to unconditional form
   4417     switch(Inst.getOpcode()) {
   4418       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
   4419       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
   4420     }
   4421   } else {
   4422     // outside IT blocks we can only have unconditional branches with AL
   4423     // condition code or conditional branches with non-AL condition code
   4424     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
   4425     switch(Inst.getOpcode()) {
   4426       case ARM::tB:
   4427       case ARM::tBcc:
   4428         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
   4429         break;
   4430       case ARM::t2B:
   4431       case ARM::t2Bcc:
   4432         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
   4433         break;
   4434     }
   4435   }
   4436 
   4437   // now decide on encoding size based on branch target range
   4438   switch(Inst.getOpcode()) {
   4439     // classify tB as either t2B or t1B based on range of immediate operand
   4440     case ARM::tB: {
   4441       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
   4442       if (!op.isSignedOffset<11, 1>() && isThumbTwo())
   4443         Inst.setOpcode(ARM::t2B);
   4444       break;
   4445     }
   4446     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
   4447     case ARM::tBcc: {
   4448       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
   4449       if (!op.isSignedOffset<8, 1>() && isThumbTwo())
   4450         Inst.setOpcode(ARM::t2Bcc);
   4451       break;
   4452     }
   4453   }
   4454   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
   4455   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
   4456 }
   4457 
   4458 /// Parse an ARM memory expression, return false if successful else return true
   4459 /// or an error.  The first token must be a '[' when called.
   4460 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
   4461   SMLoc S, E;
   4462   assert(Parser.getTok().is(AsmToken::LBrac) &&
   4463          "Token is not a Left Bracket");
   4464   S = Parser.getTok().getLoc();
   4465   Parser.Lex(); // Eat left bracket token.
   4466 
   4467   const AsmToken &BaseRegTok = Parser.getTok();
   4468   int BaseRegNum = tryParseRegister();
   4469   if (BaseRegNum == -1)
   4470     return Error(BaseRegTok.getLoc(), "register expected");
   4471 
   4472   // The next token must either be a comma, a colon or a closing bracket.
   4473   const AsmToken &Tok = Parser.getTok();
   4474   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
   4475       !Tok.is(AsmToken::RBrac))
   4476     return Error(Tok.getLoc(), "malformed memory operand");
   4477 
   4478   if (Tok.is(AsmToken::RBrac)) {
   4479     E = Tok.getEndLoc();
   4480     Parser.Lex(); // Eat right bracket token.
   4481 
   4482     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
   4483                                              ARM_AM::no_shift, 0, 0, false,
   4484                                              S, E));
   4485 
   4486     // If there's a pre-indexing writeback marker, '!', just add it as a token
   4487     // operand. It's rather odd, but syntactically valid.
   4488     if (Parser.getTok().is(AsmToken::Exclaim)) {
   4489       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
   4490       Parser.Lex(); // Eat the '!'.
   4491     }
   4492 
   4493     return false;
   4494   }
   4495 
   4496   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
   4497          "Lost colon or comma in memory operand?!");
   4498   if (Tok.is(AsmToken::Comma)) {
   4499     Parser.Lex(); // Eat the comma.
   4500   }
   4501 
   4502   // If we have a ':', it's an alignment specifier.
   4503   if (Parser.getTok().is(AsmToken::Colon)) {
   4504     Parser.Lex(); // Eat the ':'.
   4505     E = Parser.getTok().getLoc();
   4506     SMLoc AlignmentLoc = Tok.getLoc();
   4507 
   4508     const MCExpr *Expr;
   4509     if (getParser().parseExpression(Expr))
   4510      return true;
   4511 
   4512     // The expression has to be a constant. Memory references with relocations
   4513     // don't come through here, as they use the <label> forms of the relevant
   4514     // instructions.
   4515     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
   4516     if (!CE)
   4517       return Error (E, "constant expression expected");
   4518 
   4519     unsigned Align = 0;
   4520     switch (CE->getValue()) {
   4521     default:
   4522       return Error(E,
   4523                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
   4524     case 16:  Align = 2; break;
   4525     case 32:  Align = 4; break;
   4526     case 64:  Align = 8; break;
   4527     case 128: Align = 16; break;
   4528     case 256: Align = 32; break;
   4529     }
   4530 
   4531     // Now we should have the closing ']'
   4532     if (Parser.getTok().isNot(AsmToken::RBrac))
   4533       return Error(Parser.getTok().getLoc(), "']' expected");
   4534     E = Parser.getTok().getEndLoc();
   4535     Parser.Lex(); // Eat right bracket token.
   4536 
   4537     // Don't worry about range checking the value here. That's handled by
   4538     // the is*() predicates.
   4539     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
   4540                                              ARM_AM::no_shift, 0, Align,
   4541                                              false, S, E, AlignmentLoc));
   4542 
   4543     // If there's a pre-indexing writeback marker, '!', just add it as a token
   4544     // operand.
   4545     if (Parser.getTok().is(AsmToken::Exclaim)) {
   4546       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
   4547       Parser.Lex(); // Eat the '!'.
   4548     }
   4549 
   4550     return false;
   4551   }
   4552 
   4553   // If we have a '#', it's an immediate offset, else assume it's a register
   4554   // offset. Be friendly and also accept a plain integer (without a leading
   4555   // hash) for gas compatibility.
   4556   if (Parser.getTok().is(AsmToken::Hash) ||
   4557       Parser.getTok().is(AsmToken::Dollar) ||
   4558       Parser.getTok().is(AsmToken::Integer)) {
   4559     if (Parser.getTok().isNot(AsmToken::Integer))
   4560       Parser.Lex(); // Eat '#' or '$'.
   4561     E = Parser.getTok().getLoc();
   4562 
   4563     bool isNegative = getParser().getTok().is(AsmToken::Minus);
   4564     const MCExpr *Offset;
   4565     if (getParser().parseExpression(Offset))
   4566      return true;
   4567 
   4568     // The expression has to be a constant. Memory references with relocations
   4569     // don't come through here, as they use the <label> forms of the relevant
   4570     // instructions.
   4571     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
   4572     if (!CE)
   4573       return Error (E, "constant expression expected");
   4574 
   4575     // If the constant was #-0, represent it as INT32_MIN.
   4576     int32_t Val = CE->getValue();
   4577     if (isNegative && Val == 0)
   4578       CE = MCConstantExpr::Create(INT32_MIN, getContext());
   4579 
   4580     // Now we should have the closing ']'
   4581     if (Parser.getTok().isNot(AsmToken::RBrac))
   4582       return Error(Parser.getTok().getLoc(), "']' expected");
   4583     E = Parser.getTok().getEndLoc();
   4584     Parser.Lex(); // Eat right bracket token.
   4585 
   4586     // Don't worry about range checking the value here. That's handled by
   4587     // the is*() predicates.
   4588     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
   4589                                              ARM_AM::no_shift, 0, 0,
   4590                                              false, S, E));
   4591 
   4592     // If there's a pre-indexing writeback marker, '!', just add it as a token
   4593     // operand.
   4594     if (Parser.getTok().is(AsmToken::Exclaim)) {
   4595       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
   4596       Parser.Lex(); // Eat the '!'.
   4597     }
   4598 
   4599     return false;
   4600   }
   4601 
   4602   // The register offset is optionally preceded by a '+' or '-'
   4603   bool isNegative = false;
   4604   if (Parser.getTok().is(AsmToken::Minus)) {
   4605     isNegative = true;
   4606     Parser.Lex(); // Eat the '-'.
   4607   } else if (Parser.getTok().is(AsmToken::Plus)) {
   4608     // Nothing to do.
   4609     Parser.Lex(); // Eat the '+'.
   4610   }
   4611 
   4612   E = Parser.getTok().getLoc();
   4613   int OffsetRegNum = tryParseRegister();
   4614   if (OffsetRegNum == -1)
   4615     return Error(E, "register expected");
   4616 
   4617   // If there's a shift operator, handle it.
   4618   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
   4619   unsigned ShiftImm = 0;
   4620   if (Parser.getTok().is(AsmToken::Comma)) {
   4621     Parser.Lex(); // Eat the ','.
   4622     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
   4623       return true;
   4624   }
   4625 
   4626   // Now we should have the closing ']'
   4627   if (Parser.getTok().isNot(AsmToken::RBrac))
   4628     return Error(Parser.getTok().getLoc(), "']' expected");
   4629   E = Parser.getTok().getEndLoc();
   4630   Parser.Lex(); // Eat right bracket token.
   4631 
   4632   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
   4633                                            ShiftType, ShiftImm, 0, isNegative,
   4634                                            S, E));
   4635 
   4636   // If there's a pre-indexing writeback marker, '!', just add it as a token
   4637   // operand.
   4638   if (Parser.getTok().is(AsmToken::Exclaim)) {
   4639     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
   4640     Parser.Lex(); // Eat the '!'.
   4641   }
   4642 
   4643   return false;
   4644 }
   4645 
   4646 /// parseMemRegOffsetShift - one of these two:
   4647 ///   ( lsl | lsr | asr | ror ) , # shift_amount
   4648 ///   rrx
   4649 /// return true if it parses a shift otherwise it returns false.
   4650 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
   4651                                           unsigned &Amount) {
   4652   SMLoc Loc = Parser.getTok().getLoc();
   4653   const AsmToken &Tok = Parser.getTok();
   4654   if (Tok.isNot(AsmToken::Identifier))
   4655     return true;
   4656   StringRef ShiftName = Tok.getString();
   4657   if (ShiftName == "lsl" || ShiftName == "LSL" ||
   4658       ShiftName == "asl" || ShiftName == "ASL")
   4659     St = ARM_AM::lsl;
   4660   else if (ShiftName == "lsr" || ShiftName == "LSR")
   4661     St = ARM_AM::lsr;
   4662   else if (ShiftName == "asr" || ShiftName == "ASR")
   4663     St = ARM_AM::asr;
   4664   else if (ShiftName == "ror" || ShiftName == "ROR")
   4665     St = ARM_AM::ror;
   4666   else if (ShiftName == "rrx" || ShiftName == "RRX")
   4667     St = ARM_AM::rrx;
   4668   else
   4669     return Error(Loc, "illegal shift operator");
   4670   Parser.Lex(); // Eat shift type token.
   4671 
   4672   // rrx stands alone.
   4673   Amount = 0;
   4674   if (St != ARM_AM::rrx) {
   4675     Loc = Parser.getTok().getLoc();
   4676     // A '#' and a shift amount.
   4677     const AsmToken &HashTok = Parser.getTok();
   4678     if (HashTok.isNot(AsmToken::Hash) &&
   4679         HashTok.isNot(AsmToken::Dollar))
   4680       return Error(HashTok.getLoc(), "'#' expected");
   4681     Parser.Lex(); // Eat hash token.
   4682 
   4683     const MCExpr *Expr;
   4684     if (getParser().parseExpression(Expr))
   4685       return true;
   4686     // Range check the immediate.
   4687     // lsl, ror: 0 <= imm <= 31
   4688     // lsr, asr: 0 <= imm <= 32
   4689     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
   4690     if (!CE)
   4691       return Error(Loc, "shift amount must be an immediate");
   4692     int64_t Imm = CE->getValue();
   4693     if (Imm < 0 ||
   4694         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
   4695         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
   4696       return Error(Loc, "immediate shift value out of range");
   4697     // If <ShiftTy> #0, turn it into a no_shift.
   4698     if (Imm == 0)
   4699       St = ARM_AM::lsl;
   4700     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
   4701     if (Imm == 32)
   4702       Imm = 0;
   4703     Amount = Imm;
   4704   }
   4705 
   4706   return false;
   4707 }
   4708 
   4709 /// parseFPImm - A floating point immediate expression operand.
   4710 ARMAsmParser::OperandMatchResultTy
   4711 ARMAsmParser::parseFPImm(OperandVector &Operands) {
   4712   // Anything that can accept a floating point constant as an operand
   4713   // needs to go through here, as the regular parseExpression is
   4714   // integer only.
   4715   //
   4716   // This routine still creates a generic Immediate operand, containing
   4717   // a bitcast of the 64-bit floating point value. The various operands
   4718   // that accept floats can check whether the value is valid for them
   4719   // via the standard is*() predicates.
   4720 
   4721   SMLoc S = Parser.getTok().getLoc();
   4722 
   4723   if (Parser.getTok().isNot(AsmToken::Hash) &&
   4724       Parser.getTok().isNot(AsmToken::Dollar))
   4725     return MatchOperand_NoMatch;
   4726 
   4727   // Disambiguate the VMOV forms that can accept an FP immediate.
   4728   // vmov.f32 <sreg>, #imm
   4729   // vmov.f64 <dreg>, #imm
   4730   // vmov.f32 <dreg>, #imm  @ vector f32x2
   4731   // vmov.f32 <qreg>, #imm  @ vector f32x4
   4732   //
   4733   // There are also the NEON VMOV instructions which expect an
   4734   // integer constant. Make sure we don't try to parse an FPImm
   4735   // for these:
   4736   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
   4737   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
   4738   bool isVmovf = TyOp.isToken() &&
   4739                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
   4740   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
   4741   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
   4742                                          Mnemonic.getToken() == "fconsts");
   4743   if (!(isVmovf || isFconst))
   4744     return MatchOperand_NoMatch;
   4745 
   4746   Parser.Lex(); // Eat '#' or '$'.
   4747 
   4748   // Handle negation, as that still comes through as a separate token.
   4749   bool isNegative = false;
   4750   if (Parser.getTok().is(AsmToken::Minus)) {
   4751     isNegative = true;
   4752     Parser.Lex();
   4753   }
   4754   const AsmToken &Tok = Parser.getTok();
   4755   SMLoc Loc = Tok.getLoc();
   4756   if (Tok.is(AsmToken::Real) && isVmovf) {
   4757     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
   4758     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
   4759     // If we had a '-' in front, toggle the sign bit.
   4760     IntVal ^= (uint64_t)isNegative << 31;
   4761     Parser.Lex(); // Eat the token.
   4762     Operands.push_back(ARMOperand::CreateImm(
   4763           MCConstantExpr::Create(IntVal, getContext()),
   4764           S, Parser.getTok().getLoc()));
   4765     return MatchOperand_Success;
   4766   }
   4767   // Also handle plain integers. Instructions which allow floating point
   4768   // immediates also allow a raw encoded 8-bit value.
   4769   if (Tok.is(AsmToken::Integer) && isFconst) {
   4770     int64_t Val = Tok.getIntVal();
   4771     Parser.Lex(); // Eat the token.
   4772     if (Val > 255 || Val < 0) {
   4773       Error(Loc, "encoded floating point value out of range");
   4774       return MatchOperand_ParseFail;
   4775     }
   4776     float RealVal = ARM_AM::getFPImmFloat(Val);
   4777     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
   4778 
   4779     Operands.push_back(ARMOperand::CreateImm(
   4780         MCConstantExpr::Create(Val, getContext()), S,
   4781         Parser.getTok().getLoc()));
   4782     return MatchOperand_Success;
   4783   }
   4784 
   4785   Error(Loc, "invalid floating point immediate");
   4786   return MatchOperand_ParseFail;
   4787 }
   4788 
   4789 /// Parse a arm instruction operand.  For now this parses the operand regardless
   4790 /// of the mnemonic.
   4791 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   4792   SMLoc S, E;
   4793 
   4794   // Check if the current operand has a custom associated parser, if so, try to
   4795   // custom parse the operand, or fallback to the general approach.
   4796   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
   4797   if (ResTy == MatchOperand_Success)
   4798     return false;
   4799   // If there wasn't a custom match, try the generic matcher below. Otherwise,
   4800   // there was a match, but an error occurred, in which case, just return that
   4801   // the operand parsing failed.
   4802   if (ResTy == MatchOperand_ParseFail)
   4803     return true;
   4804 
   4805   switch (getLexer().getKind()) {
   4806   default:
   4807     Error(Parser.getTok().getLoc(), "unexpected token in operand");
   4808     return true;
   4809   case AsmToken::Identifier: {
   4810     // If we've seen a branch mnemonic, the next operand must be a label.  This
   4811     // is true even if the label is a register name.  So "br r1" means branch to
   4812     // label "r1".
   4813     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
   4814     if (!ExpectLabel) {
   4815       if (!tryParseRegisterWithWriteBack(Operands))
   4816         return false;
   4817       int Res = tryParseShiftRegister(Operands);
   4818       if (Res == 0) // success
   4819         return false;
   4820       else if (Res == -1) // irrecoverable error
   4821         return true;
   4822       // If this is VMRS, check for the apsr_nzcv operand.
   4823       if (Mnemonic == "vmrs" &&
   4824           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
   4825         S = Parser.getTok().getLoc();
   4826         Parser.Lex();
   4827         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
   4828         return false;
   4829       }
   4830     }
   4831 
   4832     // Fall though for the Identifier case that is not a register or a
   4833     // special name.
   4834   }
   4835   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
   4836   case AsmToken::Integer: // things like 1f and 2b as a branch targets
   4837   case AsmToken::String:  // quoted label names.
   4838   case AsmToken::Dot: {   // . as a branch target
   4839     // This was not a register so parse other operands that start with an
   4840     // identifier (like labels) as expressions and create them as immediates.
   4841     const MCExpr *IdVal;
   4842     S = Parser.getTok().getLoc();
   4843     if (getParser().parseExpression(IdVal))
   4844       return true;
   4845     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   4846     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
   4847     return false;
   4848   }
   4849   case AsmToken::LBrac:
   4850     return parseMemory(Operands);
   4851   case AsmToken::LCurly:
   4852     return parseRegisterList(Operands);
   4853   case AsmToken::Dollar:
   4854   case AsmToken::Hash: {
   4855     // #42 -> immediate.
   4856     S = Parser.getTok().getLoc();
   4857     Parser.Lex();
   4858 
   4859     if (Parser.getTok().isNot(AsmToken::Colon)) {
   4860       bool isNegative = Parser.getTok().is(AsmToken::Minus);
   4861       const MCExpr *ImmVal;
   4862       if (getParser().parseExpression(ImmVal))
   4863         return true;
   4864       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
   4865       if (CE) {
   4866         int32_t Val = CE->getValue();
   4867         if (isNegative && Val == 0)
   4868           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
   4869       }
   4870       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   4871       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
   4872 
   4873       // There can be a trailing '!' on operands that we want as a separate
   4874       // '!' Token operand. Handle that here. For example, the compatibility
   4875       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
   4876       if (Parser.getTok().is(AsmToken::Exclaim)) {
   4877         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
   4878                                                    Parser.getTok().getLoc()));
   4879         Parser.Lex(); // Eat exclaim token
   4880       }
   4881       return false;
   4882     }
   4883     // w/ a ':' after the '#', it's just like a plain ':'.
   4884     // FALLTHROUGH
   4885   }
   4886   case AsmToken::Colon: {
   4887     // ":lower16:" and ":upper16:" expression prefixes
   4888     // FIXME: Check it's an expression prefix,
   4889     // e.g. (FOO - :lower16:BAR) isn't legal.
   4890     ARMMCExpr::VariantKind RefKind;
   4891     if (parsePrefix(RefKind))
   4892       return true;
   4893 
   4894     const MCExpr *SubExprVal;
   4895     if (getParser().parseExpression(SubExprVal))
   4896       return true;
   4897 
   4898     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
   4899                                               getContext());
   4900     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   4901     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
   4902     return false;
   4903   }
   4904   case AsmToken::Equal: {
   4905     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
   4906       return Error(Parser.getTok().getLoc(), "unexpected token in operand");
   4907 
   4908     Parser.Lex(); // Eat '='
   4909     const MCExpr *SubExprVal;
   4910     if (getParser().parseExpression(SubExprVal))
   4911       return true;
   4912     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   4913 
   4914     const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
   4915     Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
   4916     return false;
   4917   }
   4918   }
   4919 }
   4920 
   4921 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
   4922 //  :lower16: and :upper16:.
   4923 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
   4924   RefKind = ARMMCExpr::VK_ARM_None;
   4925 
   4926   // consume an optional '#' (GNU compatibility)
   4927   if (getLexer().is(AsmToken::Hash))
   4928     Parser.Lex();
   4929 
   4930   // :lower16: and :upper16: modifiers
   4931   assert(getLexer().is(AsmToken::Colon) && "expected a :");
   4932   Parser.Lex(); // Eat ':'
   4933 
   4934   if (getLexer().isNot(AsmToken::Identifier)) {
   4935     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
   4936     return true;
   4937   }
   4938 
   4939   StringRef IDVal = Parser.getTok().getIdentifier();
   4940   if (IDVal == "lower16") {
   4941     RefKind = ARMMCExpr::VK_ARM_LO16;
   4942   } else if (IDVal == "upper16") {
   4943     RefKind = ARMMCExpr::VK_ARM_HI16;
   4944   } else {
   4945     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
   4946     return true;
   4947   }
   4948   Parser.Lex();
   4949 
   4950   if (getLexer().isNot(AsmToken::Colon)) {
   4951     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
   4952     return true;
   4953   }
   4954   Parser.Lex(); // Eat the last ':'
   4955   return false;
   4956 }
   4957 
   4958 /// \brief Given a mnemonic, split out possible predication code and carry
   4959 /// setting letters to form a canonical mnemonic and flags.
   4960 //
   4961 // FIXME: Would be nice to autogen this.
   4962 // FIXME: This is a bit of a maze of special cases.
   4963 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   4964                                       unsigned &PredicationCode,
   4965                                       bool &CarrySetting,
   4966                                       unsigned &ProcessorIMod,
   4967                                       StringRef &ITMask) {
   4968   PredicationCode = ARMCC::AL;
   4969   CarrySetting = false;
   4970   ProcessorIMod = 0;
   4971 
   4972   // Ignore some mnemonics we know aren't predicated forms.
   4973   //
   4974   // FIXME: Would be nice to autogen this.
   4975   if ((Mnemonic == "movs" && isThumb()) ||
   4976       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
   4977       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
   4978       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
   4979       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
   4980       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
   4981       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
   4982       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
   4983       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
   4984       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
   4985       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
   4986       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
   4987       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
   4988     return Mnemonic;
   4989 
   4990   // First, split out any predication code. Ignore mnemonics we know aren't
   4991   // predicated but do have a carry-set and so weren't caught above.
   4992   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
   4993       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
   4994       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
   4995       Mnemonic != "sbcs" && Mnemonic != "rscs") {
   4996     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
   4997       .Case("eq", ARMCC::EQ)
   4998       .Case("ne", ARMCC::NE)
   4999       .Case("hs", ARMCC::HS)
   5000       .Case("cs", ARMCC::HS)
   5001       .Case("lo", ARMCC::LO)
   5002       .Case("cc", ARMCC::LO)
   5003       .Case("mi", ARMCC::MI)
   5004       .Case("pl", ARMCC::PL)
   5005       .Case("vs", ARMCC::VS)
   5006       .Case("vc", ARMCC::VC)
   5007       .Case("hi", ARMCC::HI)
   5008       .Case("ls", ARMCC::LS)
   5009       .Case("ge", ARMCC::GE)
   5010       .Case("lt", ARMCC::LT)
   5011       .Case("gt", ARMCC::GT)
   5012       .Case("le", ARMCC::LE)
   5013       .Case("al", ARMCC::AL)
   5014       .Default(~0U);
   5015     if (CC != ~0U) {
   5016       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
   5017       PredicationCode = CC;
   5018     }
   5019   }
   5020 
   5021   // Next, determine if we have a carry setting bit. We explicitly ignore all
   5022   // the instructions we know end in 's'.
   5023   if (Mnemonic.endswith("s") &&
   5024       !(Mnemonic == "cps" || Mnemonic == "mls" ||
   5025         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
   5026         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
   5027         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
   5028         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
   5029         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
   5030         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
   5031         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
   5032         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
   5033         (Mnemonic == "movs" && isThumb()))) {
   5034     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
   5035     CarrySetting = true;
   5036   }
   5037 
   5038   // The "cps" instruction can have a interrupt mode operand which is glued into
   5039   // the mnemonic. Check if this is the case, split it and parse the imod op
   5040   if (Mnemonic.startswith("cps")) {
   5041     // Split out any imod code.
   5042     unsigned IMod =
   5043       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
   5044       .Case("ie", ARM_PROC::IE)
   5045       .Case("id", ARM_PROC::ID)
   5046       .Default(~0U);
   5047     if (IMod != ~0U) {
   5048       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
   5049       ProcessorIMod = IMod;
   5050     }
   5051   }
   5052 
   5053   // The "it" instruction has the condition mask on the end of the mnemonic.
   5054   if (Mnemonic.startswith("it")) {
   5055     ITMask = Mnemonic.slice(2, Mnemonic.size());
   5056     Mnemonic = Mnemonic.slice(0, 2);
   5057   }
   5058 
   5059   return Mnemonic;
   5060 }
   5061 
   5062 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
   5063 /// inclusion of carry set or predication code operands.
   5064 //
   5065 // FIXME: It would be nice to autogen this.
   5066 void ARMAsmParser::
   5067 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
   5068                      bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
   5069   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
   5070       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
   5071       Mnemonic == "add" || Mnemonic == "adc" ||
   5072       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
   5073       Mnemonic == "orr" || Mnemonic == "mvn" ||
   5074       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
   5075       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
   5076       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
   5077       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
   5078                       Mnemonic == "mla" || Mnemonic == "smlal" ||
   5079                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
   5080     CanAcceptCarrySet = true;
   5081   } else
   5082     CanAcceptCarrySet = false;
   5083 
   5084   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
   5085       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
   5086       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
   5087       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
   5088       Mnemonic.startswith("vsel") ||
   5089       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
   5090       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
   5091       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
   5092       Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
   5093       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
   5094       (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
   5095     // These mnemonics are never predicable
   5096     CanAcceptPredicationCode = false;
   5097   } else if (!isThumb()) {
   5098     // Some instructions are only predicable in Thumb mode
   5099     CanAcceptPredicationCode
   5100       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
   5101         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
   5102         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
   5103         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
   5104         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
   5105         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
   5106         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
   5107   } else if (isThumbOne()) {
   5108     if (hasV6MOps())
   5109       CanAcceptPredicationCode = Mnemonic != "movs";
   5110     else
   5111       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
   5112   } else
   5113     CanAcceptPredicationCode = true;
   5114 }
   5115 
   5116 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
   5117                                           OperandVector &Operands) {
   5118   // FIXME: This is all horribly hacky. We really need a better way to deal
   5119   // with optional operands like this in the matcher table.
   5120 
   5121   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
   5122   // another does not. Specifically, the MOVW instruction does not. So we
   5123   // special case it here and remove the defaulted (non-setting) cc_out
   5124   // operand if that's the instruction we're trying to match.
   5125   //
   5126   // We do this as post-processing of the explicit operands rather than just
   5127   // conditionally adding the cc_out in the first place because we need
   5128   // to check the type of the parsed immediate operand.
   5129   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
   5130       !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
   5131       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
   5132       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
   5133     return true;
   5134 
   5135   // Register-register 'add' for thumb does not have a cc_out operand
   5136   // when there are only two register operands.
   5137   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
   5138       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5139       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
   5140       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
   5141     return true;
   5142   // Register-register 'add' for thumb does not have a cc_out operand
   5143   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
   5144   // have to check the immediate range here since Thumb2 has a variant
   5145   // that can handle a different range and has a cc_out operand.
   5146   if (((isThumb() && Mnemonic == "add") ||
   5147        (isThumbTwo() && Mnemonic == "sub")) &&
   5148       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5149       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
   5150       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
   5151       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
   5152       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
   5153        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
   5154     return true;
   5155   // For Thumb2, add/sub immediate does not have a cc_out operand for the
   5156   // imm0_4095 variant. That's the least-preferred variant when
   5157   // selecting via the generic "add" mnemonic, so to know that we
   5158   // should remove the cc_out operand, we have to explicitly check that
   5159   // it's not one of the other variants. Ugh.
   5160   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
   5161       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5162       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
   5163       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
   5164     // Nest conditions rather than one big 'if' statement for readability.
   5165     //
   5166     // If both registers are low, we're in an IT block, and the immediate is
   5167     // in range, we should use encoding T1 instead, which has a cc_out.
   5168     if (inITBlock() &&
   5169         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
   5170         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
   5171         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
   5172       return false;
   5173     // Check against T3. If the second register is the PC, this is an
   5174     // alternate form of ADR, which uses encoding T4, so check for that too.
   5175     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
   5176         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
   5177       return false;
   5178 
   5179     // Otherwise, we use encoding T4, which does not have a cc_out
   5180     // operand.
   5181     return true;
   5182   }
   5183 
   5184   // The thumb2 multiply instruction doesn't have a CCOut register, so
   5185   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
   5186   // use the 16-bit encoding or not.
   5187   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
   5188       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
   5189       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5190       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
   5191       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
   5192       // If the registers aren't low regs, the destination reg isn't the
   5193       // same as one of the source regs, or the cc_out operand is zero
   5194       // outside of an IT block, we have to use the 32-bit encoding, so
   5195       // remove the cc_out operand.
   5196       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
   5197        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
   5198        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
   5199        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
   5200                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
   5201                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
   5202                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
   5203     return true;
   5204 
   5205   // Also check the 'mul' syntax variant that doesn't specify an explicit
   5206   // destination register.
   5207   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
   5208       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
   5209       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5210       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
   5211       // If the registers aren't low regs  or the cc_out operand is zero
   5212       // outside of an IT block, we have to use the 32-bit encoding, so
   5213       // remove the cc_out operand.
   5214       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
   5215        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
   5216        !inITBlock()))
   5217     return true;
   5218 
   5219 
   5220 
   5221   // Register-register 'add/sub' for thumb does not have a cc_out operand
   5222   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
   5223   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
   5224   // right, this will result in better diagnostics (which operand is off)
   5225   // anyway.
   5226   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
   5227       (Operands.size() == 5 || Operands.size() == 6) &&
   5228       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5229       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
   5230       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
   5231       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
   5232        (Operands.size() == 6 &&
   5233         static_cast<ARMOperand &>(*Operands[5]).isImm())))
   5234     return true;
   5235 
   5236   return false;
   5237 }
   5238 
   5239 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
   5240                                               OperandVector &Operands) {
   5241   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
   5242   unsigned RegIdx = 3;
   5243   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
   5244       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
   5245     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
   5246         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
   5247       RegIdx = 4;
   5248 
   5249     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
   5250         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
   5251              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
   5252          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
   5253              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
   5254       return true;
   5255   }
   5256   return false;
   5257 }
   5258 
   5259 static bool isDataTypeToken(StringRef Tok) {
   5260   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
   5261     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
   5262     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
   5263     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
   5264     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
   5265     Tok == ".f" || Tok == ".d";
   5266 }
   5267 
   5268 // FIXME: This bit should probably be handled via an explicit match class
   5269 // in the .td files that matches the suffix instead of having it be
   5270 // a literal string token the way it is now.
   5271 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
   5272   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
   5273 }
   5274 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
   5275                                  unsigned VariantID);
   5276 
   5277 static bool RequiresVFPRegListValidation(StringRef Inst,
   5278                                          bool &AcceptSinglePrecisionOnly,
   5279                                          bool &AcceptDoublePrecisionOnly) {
   5280   if (Inst.size() < 7)
   5281     return false;
   5282 
   5283   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
   5284     StringRef AddressingMode = Inst.substr(4, 2);
   5285     if (AddressingMode == "ia" || AddressingMode == "db" ||
   5286         AddressingMode == "ea" || AddressingMode == "fd") {
   5287       AcceptSinglePrecisionOnly = Inst[6] == 's';
   5288       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
   5289       return true;
   5290     }
   5291   }
   5292 
   5293   return false;
   5294 }
   5295 
   5296 /// Parse an arm instruction mnemonic followed by its operands.
   5297 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   5298                                     SMLoc NameLoc, OperandVector &Operands) {
   5299   // FIXME: Can this be done via tablegen in some fashion?
   5300   bool RequireVFPRegisterListCheck;
   5301   bool AcceptSinglePrecisionOnly;
   5302   bool AcceptDoublePrecisionOnly;
   5303   RequireVFPRegisterListCheck =
   5304     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
   5305                                  AcceptDoublePrecisionOnly);
   5306 
   5307   // Apply mnemonic aliases before doing anything else, as the destination
   5308   // mnemonic may include suffices and we want to handle them normally.
   5309   // The generic tblgen'erated code does this later, at the start of
   5310   // MatchInstructionImpl(), but that's too late for aliases that include
   5311   // any sort of suffix.
   5312   unsigned AvailableFeatures = getAvailableFeatures();
   5313   unsigned AssemblerDialect = getParser().getAssemblerDialect();
   5314   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
   5315 
   5316   // First check for the ARM-specific .req directive.
   5317   if (Parser.getTok().is(AsmToken::Identifier) &&
   5318       Parser.getTok().getIdentifier() == ".req") {
   5319     parseDirectiveReq(Name, NameLoc);
   5320     // We always return 'error' for this, as we're done with this
   5321     // statement and don't need to match the 'instruction."
   5322     return true;
   5323   }
   5324 
   5325   // Create the leading tokens for the mnemonic, split by '.' characters.
   5326   size_t Start = 0, Next = Name.find('.');
   5327   StringRef Mnemonic = Name.slice(Start, Next);
   5328 
   5329   // Split out the predication code and carry setting flag from the mnemonic.
   5330   unsigned PredicationCode;
   5331   unsigned ProcessorIMod;
   5332   bool CarrySetting;
   5333   StringRef ITMask;
   5334   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
   5335                            ProcessorIMod, ITMask);
   5336 
   5337   // In Thumb1, only the branch (B) instruction can be predicated.
   5338   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
   5339     Parser.eatToEndOfStatement();
   5340     return Error(NameLoc, "conditional execution not supported in Thumb1");
   5341   }
   5342 
   5343   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
   5344 
   5345   // Handle the IT instruction ITMask. Convert it to a bitmask. This
   5346   // is the mask as it will be for the IT encoding if the conditional
   5347   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
   5348   // where the conditional bit0 is zero, the instruction post-processing
   5349   // will adjust the mask accordingly.
   5350   if (Mnemonic == "it") {
   5351     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
   5352     if (ITMask.size() > 3) {
   5353       Parser.eatToEndOfStatement();
   5354       return Error(Loc, "too many conditions on IT instruction");
   5355     }
   5356     unsigned Mask = 8;
   5357     for (unsigned i = ITMask.size(); i != 0; --i) {
   5358       char pos = ITMask[i - 1];
   5359       if (pos != 't' && pos != 'e') {
   5360         Parser.eatToEndOfStatement();
   5361         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
   5362       }
   5363       Mask >>= 1;
   5364       if (ITMask[i - 1] == 't')
   5365         Mask |= 8;
   5366     }
   5367     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
   5368   }
   5369 
   5370   // FIXME: This is all a pretty gross hack. We should automatically handle
   5371   // optional operands like this via tblgen.
   5372 
   5373   // Next, add the CCOut and ConditionCode operands, if needed.
   5374   //
   5375   // For mnemonics which can ever incorporate a carry setting bit or predication
   5376   // code, our matching model involves us always generating CCOut and
   5377   // ConditionCode operands to match the mnemonic "as written" and then we let
   5378   // the matcher deal with finding the right instruction or generating an
   5379   // appropriate error.
   5380   bool CanAcceptCarrySet, CanAcceptPredicationCode;
   5381   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
   5382 
   5383   // If we had a carry-set on an instruction that can't do that, issue an
   5384   // error.
   5385   if (!CanAcceptCarrySet && CarrySetting) {
   5386     Parser.eatToEndOfStatement();
   5387     return Error(NameLoc, "instruction '" + Mnemonic +
   5388                  "' can not set flags, but 's' suffix specified");
   5389   }
   5390   // If we had a predication code on an instruction that can't do that, issue an
   5391   // error.
   5392   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
   5393     Parser.eatToEndOfStatement();
   5394     return Error(NameLoc, "instruction '" + Mnemonic +
   5395                  "' is not predicable, but condition code specified");
   5396   }
   5397 
   5398   // Add the carry setting operand, if necessary.
   5399   if (CanAcceptCarrySet) {
   5400     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
   5401     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
   5402                                                Loc));
   5403   }
   5404 
   5405   // Add the predication code operand, if necessary.
   5406   if (CanAcceptPredicationCode) {
   5407     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
   5408                                       CarrySetting);
   5409     Operands.push_back(ARMOperand::CreateCondCode(
   5410                          ARMCC::CondCodes(PredicationCode), Loc));
   5411   }
   5412 
   5413   // Add the processor imod operand, if necessary.
   5414   if (ProcessorIMod) {
   5415     Operands.push_back(ARMOperand::CreateImm(
   5416           MCConstantExpr::Create(ProcessorIMod, getContext()),
   5417                                  NameLoc, NameLoc));
   5418   }
   5419 
   5420   // Add the remaining tokens in the mnemonic.
   5421   while (Next != StringRef::npos) {
   5422     Start = Next;
   5423     Next = Name.find('.', Start + 1);
   5424     StringRef ExtraToken = Name.slice(Start, Next);
   5425 
   5426     // Some NEON instructions have an optional datatype suffix that is
   5427     // completely ignored. Check for that.
   5428     if (isDataTypeToken(ExtraToken) &&
   5429         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
   5430       continue;
   5431 
   5432     // For for ARM mode generate an error if the .n qualifier is used.
   5433     if (ExtraToken == ".n" && !isThumb()) {
   5434       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
   5435       Parser.eatToEndOfStatement();
   5436       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
   5437                    "arm mode");
   5438     }
   5439 
   5440     // The .n qualifier is always discarded as that is what the tables
   5441     // and matcher expect.  In ARM mode the .w qualifier has no effect,
   5442     // so discard it to avoid errors that can be caused by the matcher.
   5443     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
   5444       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
   5445       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
   5446     }
   5447   }
   5448 
   5449   // Read the remaining operands.
   5450   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   5451     // Read the first operand.
   5452     if (parseOperand(Operands, Mnemonic)) {
   5453       Parser.eatToEndOfStatement();
   5454       return true;
   5455     }
   5456 
   5457     while (getLexer().is(AsmToken::Comma)) {
   5458       Parser.Lex();  // Eat the comma.
   5459 
   5460       // Parse and remember the operand.
   5461       if (parseOperand(Operands, Mnemonic)) {
   5462         Parser.eatToEndOfStatement();
   5463         return true;
   5464       }
   5465     }
   5466   }
   5467 
   5468   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   5469     SMLoc Loc = getLexer().getLoc();
   5470     Parser.eatToEndOfStatement();
   5471     return Error(Loc, "unexpected token in argument list");
   5472   }
   5473 
   5474   Parser.Lex(); // Consume the EndOfStatement
   5475 
   5476   if (RequireVFPRegisterListCheck) {
   5477     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
   5478     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
   5479       return Error(Op.getStartLoc(),
   5480                    "VFP/Neon single precision register expected");
   5481     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
   5482       return Error(Op.getStartLoc(),
   5483                    "VFP/Neon double precision register expected");
   5484   }
   5485 
   5486   // Some instructions, mostly Thumb, have forms for the same mnemonic that
   5487   // do and don't have a cc_out optional-def operand. With some spot-checks
   5488   // of the operand list, we can figure out which variant we're trying to
   5489   // parse and adjust accordingly before actually matching. We shouldn't ever
   5490   // try to remove a cc_out operand that was explicitly set on the the
   5491   // mnemonic, of course (CarrySetting == true). Reason number #317 the
   5492   // table driven matcher doesn't fit well with the ARM instruction set.
   5493   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
   5494     Operands.erase(Operands.begin() + 1);
   5495 
   5496   // Some instructions have the same mnemonic, but don't always
   5497   // have a predicate. Distinguish them here and delete the
   5498   // predicate if needed.
   5499   if (shouldOmitPredicateOperand(Mnemonic, Operands))
   5500     Operands.erase(Operands.begin() + 1);
   5501 
   5502   // ARM mode 'blx' need special handling, as the register operand version
   5503   // is predicable, but the label operand version is not. So, we can't rely
   5504   // on the Mnemonic based checking to correctly figure out when to put
   5505   // a k_CondCode operand in the list. If we're trying to match the label
   5506   // version, remove the k_CondCode operand here.
   5507   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
   5508       static_cast<ARMOperand &>(*Operands[2]).isImm())
   5509     Operands.erase(Operands.begin() + 1);
   5510 
   5511   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
   5512   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
   5513   // a single GPRPair reg operand is used in the .td file to replace the two
   5514   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
   5515   // expressed as a GPRPair, so we have to manually merge them.
   5516   // FIXME: We would really like to be able to tablegen'erate this.
   5517   if (!isThumb() && Operands.size() > 4 &&
   5518       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
   5519        Mnemonic == "stlexd")) {
   5520     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
   5521     unsigned Idx = isLoad ? 2 : 3;
   5522     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
   5523     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
   5524 
   5525     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
   5526     // Adjust only if Op1 and Op2 are GPRs.
   5527     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
   5528         MRC.contains(Op2.getReg())) {
   5529       unsigned Reg1 = Op1.getReg();
   5530       unsigned Reg2 = Op2.getReg();
   5531       unsigned Rt = MRI->getEncodingValue(Reg1);
   5532       unsigned Rt2 = MRI->getEncodingValue(Reg2);
   5533 
   5534       // Rt2 must be Rt + 1 and Rt must be even.
   5535       if (Rt + 1 != Rt2 || (Rt & 1)) {
   5536         Error(Op2.getStartLoc(), isLoad
   5537                                      ? "destination operands must be sequential"
   5538                                      : "source operands must be sequential");
   5539         return true;
   5540       }
   5541       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
   5542           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
   5543       Operands[Idx] =
   5544           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
   5545       Operands.erase(Operands.begin() + Idx + 1);
   5546     }
   5547   }
   5548 
   5549   // GNU Assembler extension (compatibility)
   5550   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
   5551     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
   5552     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
   5553     if (Op3.isMem()) {
   5554       assert(Op2.isReg() && "expected register argument");
   5555 
   5556       unsigned SuperReg = MRI->getMatchingSuperReg(
   5557           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
   5558 
   5559       assert(SuperReg && "expected register pair");
   5560 
   5561       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
   5562 
   5563       Operands.insert(
   5564           Operands.begin() + 3,
   5565           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
   5566     }
   5567   }
   5568 
   5569   // FIXME: As said above, this is all a pretty gross hack.  This instruction
   5570   // does not fit with other "subs" and tblgen.
   5571   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
   5572   // so the Mnemonic is the original name "subs" and delete the predicate
   5573   // operand so it will match the table entry.
   5574   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
   5575       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
   5576       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
   5577       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
   5578       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
   5579       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
   5580     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
   5581     Operands.erase(Operands.begin() + 1);
   5582   }
   5583   return false;
   5584 }
   5585 
   5586 // Validate context-sensitive operand constraints.
   5587 
   5588 // return 'true' if register list contains non-low GPR registers,
   5589 // 'false' otherwise. If Reg is in the register list or is HiReg, set
   5590 // 'containsReg' to true.
   5591 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
   5592                                  unsigned HiReg, bool &containsReg) {
   5593   containsReg = false;
   5594   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
   5595     unsigned OpReg = Inst.getOperand(i).getReg();
   5596     if (OpReg == Reg)
   5597       containsReg = true;
   5598     // Anything other than a low register isn't legal here.
   5599     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
   5600       return true;
   5601   }
   5602   return false;
   5603 }
   5604 
   5605 // Check if the specified regisgter is in the register list of the inst,
   5606 // starting at the indicated operand number.
   5607 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
   5608   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
   5609     unsigned OpReg = Inst.getOperand(i).getReg();
   5610     if (OpReg == Reg)
   5611       return true;
   5612   }
   5613   return false;
   5614 }
   5615 
   5616 // Return true if instruction has the interesting property of being
   5617 // allowed in IT blocks, but not being predicable.
   5618 static bool instIsBreakpoint(const MCInst &Inst) {
   5619     return Inst.getOpcode() == ARM::tBKPT ||
   5620            Inst.getOpcode() == ARM::BKPT ||
   5621            Inst.getOpcode() == ARM::tHLT ||
   5622            Inst.getOpcode() == ARM::HLT;
   5623 
   5624 }
   5625 
   5626 // FIXME: We would really like to be able to tablegen'erate this.
   5627 bool ARMAsmParser::validateInstruction(MCInst &Inst,
   5628                                        const OperandVector &Operands) {
   5629   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   5630   SMLoc Loc = Operands[0]->getStartLoc();
   5631 
   5632   // Check the IT block state first.
   5633   // NOTE: BKPT and HLT instructions have the interesting property of being
   5634   // allowed in IT blocks, but not being predicable. They just always execute.
   5635   if (inITBlock() && !instIsBreakpoint(Inst)) {
   5636     unsigned Bit = 1;
   5637     if (ITState.FirstCond)
   5638       ITState.FirstCond = false;
   5639     else
   5640       Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
   5641     // The instruction must be predicable.
   5642     if (!MCID.isPredicable())
   5643       return Error(Loc, "instructions in IT block must be predicable");
   5644     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
   5645     unsigned ITCond = Bit ? ITState.Cond :
   5646       ARMCC::getOppositeCondition(ITState.Cond);
   5647     if (Cond != ITCond) {
   5648       // Find the condition code Operand to get its SMLoc information.
   5649       SMLoc CondLoc;
   5650       for (unsigned I = 1; I < Operands.size(); ++I)
   5651         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
   5652           CondLoc = Operands[I]->getStartLoc();
   5653       return Error(CondLoc, "incorrect condition in IT block; got '" +
   5654                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
   5655                    "', but expected '" +
   5656                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
   5657     }
   5658   // Check for non-'al' condition codes outside of the IT block.
   5659   } else if (isThumbTwo() && MCID.isPredicable() &&
   5660              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
   5661              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
   5662              Inst.getOpcode() != ARM::t2Bcc)
   5663     return Error(Loc, "predicated instructions must be in IT block");
   5664 
   5665   const unsigned Opcode = Inst.getOpcode();
   5666   switch (Opcode) {
   5667   case ARM::LDRD:
   5668   case ARM::LDRD_PRE:
   5669   case ARM::LDRD_POST: {
   5670     const unsigned RtReg = Inst.getOperand(0).getReg();
   5671 
   5672     // Rt can't be R14.
   5673     if (RtReg == ARM::LR)
   5674       return Error(Operands[3]->getStartLoc(),
   5675                    "Rt can't be R14");
   5676 
   5677     const unsigned Rt = MRI->getEncodingValue(RtReg);
   5678     // Rt must be even-numbered.
   5679     if ((Rt & 1) == 1)
   5680       return Error(Operands[3]->getStartLoc(),
   5681                    "Rt must be even-numbered");
   5682 
   5683     // Rt2 must be Rt + 1.
   5684     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
   5685     if (Rt2 != Rt + 1)
   5686       return Error(Operands[3]->getStartLoc(),
   5687                    "destination operands must be sequential");
   5688 
   5689     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
   5690       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
   5691       // For addressing modes with writeback, the base register needs to be
   5692       // different from the destination registers.
   5693       if (Rn == Rt || Rn == Rt2)
   5694         return Error(Operands[3]->getStartLoc(),
   5695                      "base register needs to be different from destination "
   5696                      "registers");
   5697     }
   5698 
   5699     return false;
   5700   }
   5701   case ARM::t2LDRDi8:
   5702   case ARM::t2LDRD_PRE:
   5703   case ARM::t2LDRD_POST: {
   5704     // Rt2 must be different from Rt.
   5705     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
   5706     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
   5707     if (Rt2 == Rt)
   5708       return Error(Operands[3]->getStartLoc(),
   5709                    "destination operands can't be identical");
   5710     return false;
   5711   }
   5712   case ARM::STRD: {
   5713     // Rt2 must be Rt + 1.
   5714     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
   5715     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
   5716     if (Rt2 != Rt + 1)
   5717       return Error(Operands[3]->getStartLoc(),
   5718                    "source operands must be sequential");
   5719     return false;
   5720   }
   5721   case ARM::STRD_PRE:
   5722   case ARM::STRD_POST: {
   5723     // Rt2 must be Rt + 1.
   5724     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
   5725     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
   5726     if (Rt2 != Rt + 1)
   5727       return Error(Operands[3]->getStartLoc(),
   5728                    "source operands must be sequential");
   5729     return false;
   5730   }
   5731   case ARM::SBFX:
   5732   case ARM::UBFX: {
   5733     // Width must be in range [1, 32-lsb].
   5734     unsigned LSB = Inst.getOperand(2).getImm();
   5735     unsigned Widthm1 = Inst.getOperand(3).getImm();
   5736     if (Widthm1 >= 32 - LSB)
   5737       return Error(Operands[5]->getStartLoc(),
   5738                    "bitfield width must be in range [1,32-lsb]");
   5739     return false;
   5740   }
   5741   // Notionally handles ARM::tLDMIA_UPD too.
   5742   case ARM::tLDMIA: {
   5743     // If we're parsing Thumb2, the .w variant is available and handles
   5744     // most cases that are normally illegal for a Thumb1 LDM instruction.
   5745     // We'll make the transformation in processInstruction() if necessary.
   5746     //
   5747     // Thumb LDM instructions are writeback iff the base register is not
   5748     // in the register list.
   5749     unsigned Rn = Inst.getOperand(0).getReg();
   5750     bool HasWritebackToken =
   5751         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
   5752          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
   5753     bool ListContainsBase;
   5754     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
   5755       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
   5756                    "registers must be in range r0-r7");
   5757     // If we should have writeback, then there should be a '!' token.
   5758     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
   5759       return Error(Operands[2]->getStartLoc(),
   5760                    "writeback operator '!' expected");
   5761     // If we should not have writeback, there must not be a '!'. This is
   5762     // true even for the 32-bit wide encodings.
   5763     if (ListContainsBase && HasWritebackToken)
   5764       return Error(Operands[3]->getStartLoc(),
   5765                    "writeback operator '!' not allowed when base register "
   5766                    "in register list");
   5767 
   5768     break;
   5769   }
   5770   case ARM::LDMIA_UPD:
   5771   case ARM::LDMDB_UPD:
   5772   case ARM::LDMIB_UPD:
   5773   case ARM::LDMDA_UPD:
   5774     // ARM variants loading and updating the same register are only officially
   5775     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
   5776     if (!hasV7Ops())
   5777       break;
   5778     // Fallthrough
   5779   case ARM::t2LDMIA_UPD:
   5780   case ARM::t2LDMDB_UPD:
   5781   case ARM::t2STMIA_UPD:
   5782   case ARM::t2STMDB_UPD: {
   5783     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
   5784       return Error(Operands.back()->getStartLoc(),
   5785                    "writeback register not allowed in register list");
   5786     break;
   5787   }
   5788   case ARM::sysLDMIA_UPD:
   5789   case ARM::sysLDMDA_UPD:
   5790   case ARM::sysLDMDB_UPD:
   5791   case ARM::sysLDMIB_UPD:
   5792     if (!listContainsReg(Inst, 3, ARM::PC))
   5793       return Error(Operands[4]->getStartLoc(),
   5794                    "writeback register only allowed on system LDM "
   5795                    "if PC in register-list");
   5796     break;
   5797   case ARM::sysSTMIA_UPD:
   5798   case ARM::sysSTMDA_UPD:
   5799   case ARM::sysSTMDB_UPD:
   5800   case ARM::sysSTMIB_UPD:
   5801     return Error(Operands[2]->getStartLoc(),
   5802                  "system STM cannot have writeback register");
   5803   case ARM::tMUL: {
   5804     // The second source operand must be the same register as the destination
   5805     // operand.
   5806     //
   5807     // In this case, we must directly check the parsed operands because the
   5808     // cvtThumbMultiply() function is written in such a way that it guarantees
   5809     // this first statement is always true for the new Inst.  Essentially, the
   5810     // destination is unconditionally copied into the second source operand
   5811     // without checking to see if it matches what we actually parsed.
   5812     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
   5813                                  ((ARMOperand &)*Operands[5]).getReg()) &&
   5814         (((ARMOperand &)*Operands[3]).getReg() !=
   5815          ((ARMOperand &)*Operands[4]).getReg())) {
   5816       return Error(Operands[3]->getStartLoc(),
   5817                    "destination register must match source register");
   5818     }
   5819     break;
   5820   }
   5821   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
   5822   // so only issue a diagnostic for thumb1. The instructions will be
   5823   // switched to the t2 encodings in processInstruction() if necessary.
   5824   case ARM::tPOP: {
   5825     bool ListContainsBase;
   5826     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
   5827         !isThumbTwo())
   5828       return Error(Operands[2]->getStartLoc(),
   5829                    "registers must be in range r0-r7 or pc");
   5830     break;
   5831   }
   5832   case ARM::tPUSH: {
   5833     bool ListContainsBase;
   5834     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
   5835         !isThumbTwo())
   5836       return Error(Operands[2]->getStartLoc(),
   5837                    "registers must be in range r0-r7 or lr");
   5838     break;
   5839   }
   5840   case ARM::tSTMIA_UPD: {
   5841     bool ListContainsBase, InvalidLowList;
   5842     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
   5843                                           0, ListContainsBase);
   5844     if (InvalidLowList && !isThumbTwo())
   5845       return Error(Operands[4]->getStartLoc(),
   5846                    "registers must be in range r0-r7");
   5847 
   5848     // This would be converted to a 32-bit stm, but that's not valid if the
   5849     // writeback register is in the list.
   5850     if (InvalidLowList && ListContainsBase)
   5851       return Error(Operands[4]->getStartLoc(),
   5852                    "writeback operator '!' not allowed when base register "
   5853                    "in register list");
   5854     break;
   5855   }
   5856   case ARM::tADDrSP: {
   5857     // If the non-SP source operand and the destination operand are not the
   5858     // same, we need thumb2 (for the wide encoding), or we have an error.
   5859     if (!isThumbTwo() &&
   5860         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
   5861       return Error(Operands[4]->getStartLoc(),
   5862                    "source register must be the same as destination");
   5863     }
   5864     break;
   5865   }
   5866   // Final range checking for Thumb unconditional branch instructions.
   5867   case ARM::tB:
   5868     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
   5869       return Error(Operands[2]->getStartLoc(), "branch target out of range");
   5870     break;
   5871   case ARM::t2B: {
   5872     int op = (Operands[2]->isImm()) ? 2 : 3;
   5873     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
   5874       return Error(Operands[op]->getStartLoc(), "branch target out of range");
   5875     break;
   5876   }
   5877   // Final range checking for Thumb conditional branch instructions.
   5878   case ARM::tBcc:
   5879     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
   5880       return Error(Operands[2]->getStartLoc(), "branch target out of range");
   5881     break;
   5882   case ARM::t2Bcc: {
   5883     int Op = (Operands[2]->isImm()) ? 2 : 3;
   5884     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
   5885       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
   5886     break;
   5887   }
   5888   case ARM::MOVi16:
   5889   case ARM::t2MOVi16:
   5890   case ARM::t2MOVTi16:
   5891     {
   5892     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
   5893     // especially when we turn it into a movw and the expression <symbol> does
   5894     // not have a :lower16: or :upper16 as part of the expression.  We don't
   5895     // want the behavior of silently truncating, which can be unexpected and
   5896     // lead to bugs that are difficult to find since this is an easy mistake
   5897     // to make.
   5898     int i = (Operands[3]->isImm()) ? 3 : 4;
   5899     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
   5900     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
   5901     if (CE) break;
   5902     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
   5903     if (!E) break;
   5904     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
   5905     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
   5906                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
   5907       return Error(
   5908           Op.getStartLoc(),
   5909           "immediate expression for mov requires :lower16: or :upper16");
   5910     break;
   5911   }
   5912   }
   5913 
   5914   return false;
   5915 }
   5916 
   5917 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
   5918   switch(Opc) {
   5919   default: llvm_unreachable("unexpected opcode!");
   5920   // VST1LN
   5921   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
   5922   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
   5923   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
   5924   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
   5925   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
   5926   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
   5927   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
   5928   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
   5929   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
   5930 
   5931   // VST2LN
   5932   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
   5933   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
   5934   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
   5935   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
   5936   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
   5937 
   5938   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
   5939   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
   5940   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
   5941   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
   5942   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
   5943 
   5944   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
   5945   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
   5946   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
   5947   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
   5948   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
   5949 
   5950   // VST3LN
   5951   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
   5952   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
   5953   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
   5954   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
   5955   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
   5956   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
   5957   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
   5958   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
   5959   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
   5960   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
   5961   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
   5962   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
   5963   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
   5964   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
   5965   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
   5966 
   5967   // VST3
   5968   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
   5969   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
   5970   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
   5971   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
   5972   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
   5973   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
   5974   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
   5975   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
   5976   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
   5977   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
   5978   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
   5979   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
   5980   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
   5981   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
   5982   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
   5983   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
   5984   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
   5985   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
   5986 
   5987   // VST4LN
   5988   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
   5989   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
   5990   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
   5991   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
   5992   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
   5993   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
   5994   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
   5995   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
   5996   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
   5997   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
   5998   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
   5999   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
   6000   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
   6001   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
   6002   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
   6003 
   6004   // VST4
   6005   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
   6006   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
   6007   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
   6008   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
   6009   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
   6010   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
   6011   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
   6012   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
   6013   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
   6014   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
   6015   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
   6016   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
   6017   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
   6018   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
   6019   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
   6020   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
   6021   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
   6022   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
   6023   }
   6024 }
   6025 
   6026 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
   6027   switch(Opc) {
   6028   default: llvm_unreachable("unexpected opcode!");
   6029   // VLD1LN
   6030   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
   6031   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
   6032   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
   6033   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
   6034   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
   6035   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
   6036   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
   6037   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
   6038   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
   6039 
   6040   // VLD2LN
   6041   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
   6042   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
   6043   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
   6044   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
   6045   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
   6046   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
   6047   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
   6048   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
   6049   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
   6050   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
   6051   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
   6052   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
   6053   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
   6054   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
   6055   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
   6056 
   6057   // VLD3DUP
   6058   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
   6059   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
   6060   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
   6061   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
   6062   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
   6063   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
   6064   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
   6065   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
   6066   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
   6067   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
   6068   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
   6069   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
   6070   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
   6071   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
   6072   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
   6073   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
   6074   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
   6075   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
   6076 
   6077   // VLD3LN
   6078   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
   6079   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
   6080   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
   6081   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
   6082   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
   6083   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
   6084   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
   6085   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
   6086   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
   6087   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
   6088   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
   6089   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
   6090   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
   6091   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
   6092   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
   6093 
   6094   // VLD3
   6095   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
   6096   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
   6097   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
   6098   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
   6099   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
   6100   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
   6101   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
   6102   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
   6103   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
   6104   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
   6105   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
   6106   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
   6107   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
   6108   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
   6109   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
   6110   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
   6111   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
   6112   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
   6113 
   6114   // VLD4LN
   6115   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
   6116   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
   6117   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
   6118   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
   6119   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
   6120   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
   6121   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
   6122   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
   6123   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
   6124   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
   6125   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
   6126   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
   6127   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
   6128   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
   6129   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
   6130 
   6131   // VLD4DUP
   6132   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
   6133   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
   6134   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
   6135   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
   6136   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
   6137   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
   6138   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
   6139   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
   6140   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
   6141   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
   6142   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
   6143   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
   6144   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
   6145   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
   6146   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
   6147   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
   6148   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
   6149   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
   6150 
   6151   // VLD4
   6152   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
   6153   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
   6154   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
   6155   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
   6156   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
   6157   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
   6158   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
   6159   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
   6160   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
   6161   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
   6162   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
   6163   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
   6164   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
   6165   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
   6166   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
   6167   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
   6168   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
   6169   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
   6170   }
   6171 }
   6172 
   6173 bool ARMAsmParser::processInstruction(MCInst &Inst,
   6174                                       const OperandVector &Operands) {
   6175   switch (Inst.getOpcode()) {
   6176   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
   6177   case ARM::LDRT_POST:
   6178   case ARM::LDRBT_POST: {
   6179     const unsigned Opcode =
   6180       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
   6181                                            : ARM::LDRBT_POST_IMM;
   6182     MCInst TmpInst;
   6183     TmpInst.setOpcode(Opcode);
   6184     TmpInst.addOperand(Inst.getOperand(0));
   6185     TmpInst.addOperand(Inst.getOperand(1));
   6186     TmpInst.addOperand(Inst.getOperand(1));
   6187     TmpInst.addOperand(MCOperand::CreateReg(0));
   6188     TmpInst.addOperand(MCOperand::CreateImm(0));
   6189     TmpInst.addOperand(Inst.getOperand(2));
   6190     TmpInst.addOperand(Inst.getOperand(3));
   6191     Inst = TmpInst;
   6192     return true;
   6193   }
   6194   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
   6195   case ARM::STRT_POST:
   6196   case ARM::STRBT_POST: {
   6197     const unsigned Opcode =
   6198       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
   6199                                            : ARM::STRBT_POST_IMM;
   6200     MCInst TmpInst;
   6201     TmpInst.setOpcode(Opcode);
   6202     TmpInst.addOperand(Inst.getOperand(1));
   6203     TmpInst.addOperand(Inst.getOperand(0));
   6204     TmpInst.addOperand(Inst.getOperand(1));
   6205     TmpInst.addOperand(MCOperand::CreateReg(0));
   6206     TmpInst.addOperand(MCOperand::CreateImm(0));
   6207     TmpInst.addOperand(Inst.getOperand(2));
   6208     TmpInst.addOperand(Inst.getOperand(3));
   6209     Inst = TmpInst;
   6210     return true;
   6211   }
   6212   // Alias for alternate form of 'ADR Rd, #imm' instruction.
   6213   case ARM::ADDri: {
   6214     if (Inst.getOperand(1).getReg() != ARM::PC ||
   6215         Inst.getOperand(5).getReg() != 0)
   6216       return false;
   6217     MCInst TmpInst;
   6218     TmpInst.setOpcode(ARM::ADR);
   6219     TmpInst.addOperand(Inst.getOperand(0));
   6220     TmpInst.addOperand(Inst.getOperand(2));
   6221     TmpInst.addOperand(Inst.getOperand(3));
   6222     TmpInst.addOperand(Inst.getOperand(4));
   6223     Inst = TmpInst;
   6224     return true;
   6225   }
   6226   // Aliases for alternate PC+imm syntax of LDR instructions.
   6227   case ARM::t2LDRpcrel:
   6228     // Select the narrow version if the immediate will fit.
   6229     if (Inst.getOperand(1).getImm() > 0 &&
   6230         Inst.getOperand(1).getImm() <= 0xff &&
   6231         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
   6232           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
   6233       Inst.setOpcode(ARM::tLDRpci);
   6234     else
   6235       Inst.setOpcode(ARM::t2LDRpci);
   6236     return true;
   6237   case ARM::t2LDRBpcrel:
   6238     Inst.setOpcode(ARM::t2LDRBpci);
   6239     return true;
   6240   case ARM::t2LDRHpcrel:
   6241     Inst.setOpcode(ARM::t2LDRHpci);
   6242     return true;
   6243   case ARM::t2LDRSBpcrel:
   6244     Inst.setOpcode(ARM::t2LDRSBpci);
   6245     return true;
   6246   case ARM::t2LDRSHpcrel:
   6247     Inst.setOpcode(ARM::t2LDRSHpci);
   6248     return true;
   6249   // Handle NEON VST complex aliases.
   6250   case ARM::VST1LNdWB_register_Asm_8:
   6251   case ARM::VST1LNdWB_register_Asm_16:
   6252   case ARM::VST1LNdWB_register_Asm_32: {
   6253     MCInst TmpInst;
   6254     // Shuffle the operands around so the lane index operand is in the
   6255     // right place.
   6256     unsigned Spacing;
   6257     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6258     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6259     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6260     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6261     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6262     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6263     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6264     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6265     TmpInst.addOperand(Inst.getOperand(6));
   6266     Inst = TmpInst;
   6267     return true;
   6268   }
   6269 
   6270   case ARM::VST2LNdWB_register_Asm_8:
   6271   case ARM::VST2LNdWB_register_Asm_16:
   6272   case ARM::VST2LNdWB_register_Asm_32:
   6273   case ARM::VST2LNqWB_register_Asm_16:
   6274   case ARM::VST2LNqWB_register_Asm_32: {
   6275     MCInst TmpInst;
   6276     // Shuffle the operands around so the lane index operand is in the
   6277     // right place.
   6278     unsigned Spacing;
   6279     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6280     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6281     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6282     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6283     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6284     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6285     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6286                                             Spacing));
   6287     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6288     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6289     TmpInst.addOperand(Inst.getOperand(6));
   6290     Inst = TmpInst;
   6291     return true;
   6292   }
   6293 
   6294   case ARM::VST3LNdWB_register_Asm_8:
   6295   case ARM::VST3LNdWB_register_Asm_16:
   6296   case ARM::VST3LNdWB_register_Asm_32:
   6297   case ARM::VST3LNqWB_register_Asm_16:
   6298   case ARM::VST3LNqWB_register_Asm_32: {
   6299     MCInst TmpInst;
   6300     // Shuffle the operands around so the lane index operand is in the
   6301     // right place.
   6302     unsigned Spacing;
   6303     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6304     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6305     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6306     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6307     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6308     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6309     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6310                                             Spacing));
   6311     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6312                                             Spacing * 2));
   6313     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6314     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6315     TmpInst.addOperand(Inst.getOperand(6));
   6316     Inst = TmpInst;
   6317     return true;
   6318   }
   6319 
   6320   case ARM::VST4LNdWB_register_Asm_8:
   6321   case ARM::VST4LNdWB_register_Asm_16:
   6322   case ARM::VST4LNdWB_register_Asm_32:
   6323   case ARM::VST4LNqWB_register_Asm_16:
   6324   case ARM::VST4LNqWB_register_Asm_32: {
   6325     MCInst TmpInst;
   6326     // Shuffle the operands around so the lane index operand is in the
   6327     // right place.
   6328     unsigned Spacing;
   6329     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6330     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6331     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6332     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6333     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6334     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6335     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6336                                             Spacing));
   6337     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6338                                             Spacing * 2));
   6339     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6340                                             Spacing * 3));
   6341     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6342     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6343     TmpInst.addOperand(Inst.getOperand(6));
   6344     Inst = TmpInst;
   6345     return true;
   6346   }
   6347 
   6348   case ARM::VST1LNdWB_fixed_Asm_8:
   6349   case ARM::VST1LNdWB_fixed_Asm_16:
   6350   case ARM::VST1LNdWB_fixed_Asm_32: {
   6351     MCInst TmpInst;
   6352     // Shuffle the operands around so the lane index operand is in the
   6353     // right place.
   6354     unsigned Spacing;
   6355     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6356     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6357     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6358     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6359     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6360     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6361     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6362     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6363     TmpInst.addOperand(Inst.getOperand(5));
   6364     Inst = TmpInst;
   6365     return true;
   6366   }
   6367 
   6368   case ARM::VST2LNdWB_fixed_Asm_8:
   6369   case ARM::VST2LNdWB_fixed_Asm_16:
   6370   case ARM::VST2LNdWB_fixed_Asm_32:
   6371   case ARM::VST2LNqWB_fixed_Asm_16:
   6372   case ARM::VST2LNqWB_fixed_Asm_32: {
   6373     MCInst TmpInst;
   6374     // Shuffle the operands around so the lane index operand is in the
   6375     // right place.
   6376     unsigned Spacing;
   6377     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6378     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6379     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6380     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6381     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6382     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6383     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6384                                             Spacing));
   6385     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6386     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6387     TmpInst.addOperand(Inst.getOperand(5));
   6388     Inst = TmpInst;
   6389     return true;
   6390   }
   6391 
   6392   case ARM::VST3LNdWB_fixed_Asm_8:
   6393   case ARM::VST3LNdWB_fixed_Asm_16:
   6394   case ARM::VST3LNdWB_fixed_Asm_32:
   6395   case ARM::VST3LNqWB_fixed_Asm_16:
   6396   case ARM::VST3LNqWB_fixed_Asm_32: {
   6397     MCInst TmpInst;
   6398     // Shuffle the operands around so the lane index operand is in the
   6399     // right place.
   6400     unsigned Spacing;
   6401     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6402     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6403     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6404     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6405     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6406     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6407     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6408                                             Spacing));
   6409     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6410                                             Spacing * 2));
   6411     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6412     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6413     TmpInst.addOperand(Inst.getOperand(5));
   6414     Inst = TmpInst;
   6415     return true;
   6416   }
   6417 
   6418   case ARM::VST4LNdWB_fixed_Asm_8:
   6419   case ARM::VST4LNdWB_fixed_Asm_16:
   6420   case ARM::VST4LNdWB_fixed_Asm_32:
   6421   case ARM::VST4LNqWB_fixed_Asm_16:
   6422   case ARM::VST4LNqWB_fixed_Asm_32: {
   6423     MCInst TmpInst;
   6424     // Shuffle the operands around so the lane index operand is in the
   6425     // right place.
   6426     unsigned Spacing;
   6427     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6428     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6429     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6430     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6431     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6432     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6433     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6434                                             Spacing));
   6435     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6436                                             Spacing * 2));
   6437     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6438                                             Spacing * 3));
   6439     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6440     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6441     TmpInst.addOperand(Inst.getOperand(5));
   6442     Inst = TmpInst;
   6443     return true;
   6444   }
   6445 
   6446   case ARM::VST1LNdAsm_8:
   6447   case ARM::VST1LNdAsm_16:
   6448   case ARM::VST1LNdAsm_32: {
   6449     MCInst TmpInst;
   6450     // Shuffle the operands around so the lane index operand is in the
   6451     // right place.
   6452     unsigned Spacing;
   6453     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6454     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6455     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6456     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6457     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6458     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6459     TmpInst.addOperand(Inst.getOperand(5));
   6460     Inst = TmpInst;
   6461     return true;
   6462   }
   6463 
   6464   case ARM::VST2LNdAsm_8:
   6465   case ARM::VST2LNdAsm_16:
   6466   case ARM::VST2LNdAsm_32:
   6467   case ARM::VST2LNqAsm_16:
   6468   case ARM::VST2LNqAsm_32: {
   6469     MCInst TmpInst;
   6470     // Shuffle the operands around so the lane index operand is in the
   6471     // right place.
   6472     unsigned Spacing;
   6473     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6474     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6475     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6476     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6477     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6478                                             Spacing));
   6479     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6480     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6481     TmpInst.addOperand(Inst.getOperand(5));
   6482     Inst = TmpInst;
   6483     return true;
   6484   }
   6485 
   6486   case ARM::VST3LNdAsm_8:
   6487   case ARM::VST3LNdAsm_16:
   6488   case ARM::VST3LNdAsm_32:
   6489   case ARM::VST3LNqAsm_16:
   6490   case ARM::VST3LNqAsm_32: {
   6491     MCInst TmpInst;
   6492     // Shuffle the operands around so the lane index operand is in the
   6493     // right place.
   6494     unsigned Spacing;
   6495     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6496     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6497     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6498     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6499     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6500                                             Spacing));
   6501     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6502                                             Spacing * 2));
   6503     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6504     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6505     TmpInst.addOperand(Inst.getOperand(5));
   6506     Inst = TmpInst;
   6507     return true;
   6508   }
   6509 
   6510   case ARM::VST4LNdAsm_8:
   6511   case ARM::VST4LNdAsm_16:
   6512   case ARM::VST4LNdAsm_32:
   6513   case ARM::VST4LNqAsm_16:
   6514   case ARM::VST4LNqAsm_32: {
   6515     MCInst TmpInst;
   6516     // Shuffle the operands around so the lane index operand is in the
   6517     // right place.
   6518     unsigned Spacing;
   6519     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   6520     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6521     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6522     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6523     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6524                                             Spacing));
   6525     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6526                                             Spacing * 2));
   6527     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6528                                             Spacing * 3));
   6529     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6530     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6531     TmpInst.addOperand(Inst.getOperand(5));
   6532     Inst = TmpInst;
   6533     return true;
   6534   }
   6535 
   6536   // Handle NEON VLD complex aliases.
   6537   case ARM::VLD1LNdWB_register_Asm_8:
   6538   case ARM::VLD1LNdWB_register_Asm_16:
   6539   case ARM::VLD1LNdWB_register_Asm_32: {
   6540     MCInst TmpInst;
   6541     // Shuffle the operands around so the lane index operand is in the
   6542     // right place.
   6543     unsigned Spacing;
   6544     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6545     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6546     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6547     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6548     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6549     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6550     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6551     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6552     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6553     TmpInst.addOperand(Inst.getOperand(6));
   6554     Inst = TmpInst;
   6555     return true;
   6556   }
   6557 
   6558   case ARM::VLD2LNdWB_register_Asm_8:
   6559   case ARM::VLD2LNdWB_register_Asm_16:
   6560   case ARM::VLD2LNdWB_register_Asm_32:
   6561   case ARM::VLD2LNqWB_register_Asm_16:
   6562   case ARM::VLD2LNqWB_register_Asm_32: {
   6563     MCInst TmpInst;
   6564     // Shuffle the operands around so the lane index operand is in the
   6565     // right place.
   6566     unsigned Spacing;
   6567     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6568     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6569     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6570                                             Spacing));
   6571     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6572     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6573     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6574     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6575     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6576     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6577                                             Spacing));
   6578     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6579     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6580     TmpInst.addOperand(Inst.getOperand(6));
   6581     Inst = TmpInst;
   6582     return true;
   6583   }
   6584 
   6585   case ARM::VLD3LNdWB_register_Asm_8:
   6586   case ARM::VLD3LNdWB_register_Asm_16:
   6587   case ARM::VLD3LNdWB_register_Asm_32:
   6588   case ARM::VLD3LNqWB_register_Asm_16:
   6589   case ARM::VLD3LNqWB_register_Asm_32: {
   6590     MCInst TmpInst;
   6591     // Shuffle the operands around so the lane index operand is in the
   6592     // right place.
   6593     unsigned Spacing;
   6594     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6595     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6596     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6597                                             Spacing));
   6598     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6599                                             Spacing * 2));
   6600     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6601     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6602     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6603     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6604     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6605     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6606                                             Spacing));
   6607     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6608                                             Spacing * 2));
   6609     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6610     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6611     TmpInst.addOperand(Inst.getOperand(6));
   6612     Inst = TmpInst;
   6613     return true;
   6614   }
   6615 
   6616   case ARM::VLD4LNdWB_register_Asm_8:
   6617   case ARM::VLD4LNdWB_register_Asm_16:
   6618   case ARM::VLD4LNdWB_register_Asm_32:
   6619   case ARM::VLD4LNqWB_register_Asm_16:
   6620   case ARM::VLD4LNqWB_register_Asm_32: {
   6621     MCInst TmpInst;
   6622     // Shuffle the operands around so the lane index operand is in the
   6623     // right place.
   6624     unsigned Spacing;
   6625     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6626     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6627     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6628                                             Spacing));
   6629     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6630                                             Spacing * 2));
   6631     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6632                                             Spacing * 3));
   6633     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6634     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6635     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6636     TmpInst.addOperand(Inst.getOperand(4)); // Rm
   6637     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6638     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6639                                             Spacing));
   6640     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6641                                             Spacing * 2));
   6642     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6643                                             Spacing * 3));
   6644     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6645     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
   6646     TmpInst.addOperand(Inst.getOperand(6));
   6647     Inst = TmpInst;
   6648     return true;
   6649   }
   6650 
   6651   case ARM::VLD1LNdWB_fixed_Asm_8:
   6652   case ARM::VLD1LNdWB_fixed_Asm_16:
   6653   case ARM::VLD1LNdWB_fixed_Asm_32: {
   6654     MCInst TmpInst;
   6655     // Shuffle the operands around so the lane index operand is in the
   6656     // right place.
   6657     unsigned Spacing;
   6658     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6659     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6660     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6661     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6662     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6663     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6664     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6665     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6666     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6667     TmpInst.addOperand(Inst.getOperand(5));
   6668     Inst = TmpInst;
   6669     return true;
   6670   }
   6671 
   6672   case ARM::VLD2LNdWB_fixed_Asm_8:
   6673   case ARM::VLD2LNdWB_fixed_Asm_16:
   6674   case ARM::VLD2LNdWB_fixed_Asm_32:
   6675   case ARM::VLD2LNqWB_fixed_Asm_16:
   6676   case ARM::VLD2LNqWB_fixed_Asm_32: {
   6677     MCInst TmpInst;
   6678     // Shuffle the operands around so the lane index operand is in the
   6679     // right place.
   6680     unsigned Spacing;
   6681     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6682     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6683     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6684                                             Spacing));
   6685     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6686     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6687     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6688     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6689     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6690     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6691                                             Spacing));
   6692     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6693     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6694     TmpInst.addOperand(Inst.getOperand(5));
   6695     Inst = TmpInst;
   6696     return true;
   6697   }
   6698 
   6699   case ARM::VLD3LNdWB_fixed_Asm_8:
   6700   case ARM::VLD3LNdWB_fixed_Asm_16:
   6701   case ARM::VLD3LNdWB_fixed_Asm_32:
   6702   case ARM::VLD3LNqWB_fixed_Asm_16:
   6703   case ARM::VLD3LNqWB_fixed_Asm_32: {
   6704     MCInst TmpInst;
   6705     // Shuffle the operands around so the lane index operand is in the
   6706     // right place.
   6707     unsigned Spacing;
   6708     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6709     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6710     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6711                                             Spacing));
   6712     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6713                                             Spacing * 2));
   6714     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6715     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6716     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6717     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6718     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6719     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6720                                             Spacing));
   6721     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6722                                             Spacing * 2));
   6723     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6724     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6725     TmpInst.addOperand(Inst.getOperand(5));
   6726     Inst = TmpInst;
   6727     return true;
   6728   }
   6729 
   6730   case ARM::VLD4LNdWB_fixed_Asm_8:
   6731   case ARM::VLD4LNdWB_fixed_Asm_16:
   6732   case ARM::VLD4LNdWB_fixed_Asm_32:
   6733   case ARM::VLD4LNqWB_fixed_Asm_16:
   6734   case ARM::VLD4LNqWB_fixed_Asm_32: {
   6735     MCInst TmpInst;
   6736     // Shuffle the operands around so the lane index operand is in the
   6737     // right place.
   6738     unsigned Spacing;
   6739     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6740     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6741     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6742                                             Spacing));
   6743     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6744                                             Spacing * 2));
   6745     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6746                                             Spacing * 3));
   6747     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
   6748     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6749     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6750     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6751     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6752     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6753                                             Spacing));
   6754     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6755                                             Spacing * 2));
   6756     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6757                                             Spacing * 3));
   6758     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6759     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6760     TmpInst.addOperand(Inst.getOperand(5));
   6761     Inst = TmpInst;
   6762     return true;
   6763   }
   6764 
   6765   case ARM::VLD1LNdAsm_8:
   6766   case ARM::VLD1LNdAsm_16:
   6767   case ARM::VLD1LNdAsm_32: {
   6768     MCInst TmpInst;
   6769     // Shuffle the operands around so the lane index operand is in the
   6770     // right place.
   6771     unsigned Spacing;
   6772     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6773     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6774     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6775     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6776     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6777     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6778     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6779     TmpInst.addOperand(Inst.getOperand(5));
   6780     Inst = TmpInst;
   6781     return true;
   6782   }
   6783 
   6784   case ARM::VLD2LNdAsm_8:
   6785   case ARM::VLD2LNdAsm_16:
   6786   case ARM::VLD2LNdAsm_32:
   6787   case ARM::VLD2LNqAsm_16:
   6788   case ARM::VLD2LNqAsm_32: {
   6789     MCInst TmpInst;
   6790     // Shuffle the operands around so the lane index operand is in the
   6791     // right place.
   6792     unsigned Spacing;
   6793     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6794     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6795     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6796                                             Spacing));
   6797     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6798     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6799     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6800     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6801                                             Spacing));
   6802     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6803     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6804     TmpInst.addOperand(Inst.getOperand(5));
   6805     Inst = TmpInst;
   6806     return true;
   6807   }
   6808 
   6809   case ARM::VLD3LNdAsm_8:
   6810   case ARM::VLD3LNdAsm_16:
   6811   case ARM::VLD3LNdAsm_32:
   6812   case ARM::VLD3LNqAsm_16:
   6813   case ARM::VLD3LNqAsm_32: {
   6814     MCInst TmpInst;
   6815     // Shuffle the operands around so the lane index operand is in the
   6816     // right place.
   6817     unsigned Spacing;
   6818     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6819     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6820     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6821                                             Spacing));
   6822     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6823                                             Spacing * 2));
   6824     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6825     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6826     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6827     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6828                                             Spacing));
   6829     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6830                                             Spacing * 2));
   6831     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6832     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6833     TmpInst.addOperand(Inst.getOperand(5));
   6834     Inst = TmpInst;
   6835     return true;
   6836   }
   6837 
   6838   case ARM::VLD4LNdAsm_8:
   6839   case ARM::VLD4LNdAsm_16:
   6840   case ARM::VLD4LNdAsm_32:
   6841   case ARM::VLD4LNqAsm_16:
   6842   case ARM::VLD4LNqAsm_32: {
   6843     MCInst TmpInst;
   6844     // Shuffle the operands around so the lane index operand is in the
   6845     // right place.
   6846     unsigned Spacing;
   6847     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6848     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6849     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6850                                             Spacing));
   6851     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6852                                             Spacing * 2));
   6853     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6854                                             Spacing * 3));
   6855     TmpInst.addOperand(Inst.getOperand(2)); // Rn
   6856     TmpInst.addOperand(Inst.getOperand(3)); // alignment
   6857     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
   6858     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6859                                             Spacing));
   6860     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6861                                             Spacing * 2));
   6862     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6863                                             Spacing * 3));
   6864     TmpInst.addOperand(Inst.getOperand(1)); // lane
   6865     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6866     TmpInst.addOperand(Inst.getOperand(5));
   6867     Inst = TmpInst;
   6868     return true;
   6869   }
   6870 
   6871   // VLD3DUP single 3-element structure to all lanes instructions.
   6872   case ARM::VLD3DUPdAsm_8:
   6873   case ARM::VLD3DUPdAsm_16:
   6874   case ARM::VLD3DUPdAsm_32:
   6875   case ARM::VLD3DUPqAsm_8:
   6876   case ARM::VLD3DUPqAsm_16:
   6877   case ARM::VLD3DUPqAsm_32: {
   6878     MCInst TmpInst;
   6879     unsigned Spacing;
   6880     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6881     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6882     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6883                                             Spacing));
   6884     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6885                                             Spacing * 2));
   6886     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   6887     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   6888     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   6889     TmpInst.addOperand(Inst.getOperand(4));
   6890     Inst = TmpInst;
   6891     return true;
   6892   }
   6893 
   6894   case ARM::VLD3DUPdWB_fixed_Asm_8:
   6895   case ARM::VLD3DUPdWB_fixed_Asm_16:
   6896   case ARM::VLD3DUPdWB_fixed_Asm_32:
   6897   case ARM::VLD3DUPqWB_fixed_Asm_8:
   6898   case ARM::VLD3DUPqWB_fixed_Asm_16:
   6899   case ARM::VLD3DUPqWB_fixed_Asm_32: {
   6900     MCInst TmpInst;
   6901     unsigned Spacing;
   6902     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6903     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6904     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6905                                             Spacing));
   6906     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6907                                             Spacing * 2));
   6908     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   6909     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   6910     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   6911     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6912     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   6913     TmpInst.addOperand(Inst.getOperand(4));
   6914     Inst = TmpInst;
   6915     return true;
   6916   }
   6917 
   6918   case ARM::VLD3DUPdWB_register_Asm_8:
   6919   case ARM::VLD3DUPdWB_register_Asm_16:
   6920   case ARM::VLD3DUPdWB_register_Asm_32:
   6921   case ARM::VLD3DUPqWB_register_Asm_8:
   6922   case ARM::VLD3DUPqWB_register_Asm_16:
   6923   case ARM::VLD3DUPqWB_register_Asm_32: {
   6924     MCInst TmpInst;
   6925     unsigned Spacing;
   6926     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6927     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6928     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6929                                             Spacing));
   6930     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6931                                             Spacing * 2));
   6932     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   6933     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   6934     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   6935     TmpInst.addOperand(Inst.getOperand(3)); // Rm
   6936     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   6937     TmpInst.addOperand(Inst.getOperand(5));
   6938     Inst = TmpInst;
   6939     return true;
   6940   }
   6941 
   6942   // VLD3 multiple 3-element structure instructions.
   6943   case ARM::VLD3dAsm_8:
   6944   case ARM::VLD3dAsm_16:
   6945   case ARM::VLD3dAsm_32:
   6946   case ARM::VLD3qAsm_8:
   6947   case ARM::VLD3qAsm_16:
   6948   case ARM::VLD3qAsm_32: {
   6949     MCInst TmpInst;
   6950     unsigned Spacing;
   6951     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6952     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6953     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6954                                             Spacing));
   6955     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6956                                             Spacing * 2));
   6957     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   6958     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   6959     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   6960     TmpInst.addOperand(Inst.getOperand(4));
   6961     Inst = TmpInst;
   6962     return true;
   6963   }
   6964 
   6965   case ARM::VLD3dWB_fixed_Asm_8:
   6966   case ARM::VLD3dWB_fixed_Asm_16:
   6967   case ARM::VLD3dWB_fixed_Asm_32:
   6968   case ARM::VLD3qWB_fixed_Asm_8:
   6969   case ARM::VLD3qWB_fixed_Asm_16:
   6970   case ARM::VLD3qWB_fixed_Asm_32: {
   6971     MCInst TmpInst;
   6972     unsigned Spacing;
   6973     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6974     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6975     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6976                                             Spacing));
   6977     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   6978                                             Spacing * 2));
   6979     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   6980     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   6981     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   6982     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   6983     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   6984     TmpInst.addOperand(Inst.getOperand(4));
   6985     Inst = TmpInst;
   6986     return true;
   6987   }
   6988 
   6989   case ARM::VLD3dWB_register_Asm_8:
   6990   case ARM::VLD3dWB_register_Asm_16:
   6991   case ARM::VLD3dWB_register_Asm_32:
   6992   case ARM::VLD3qWB_register_Asm_8:
   6993   case ARM::VLD3qWB_register_Asm_16:
   6994   case ARM::VLD3qWB_register_Asm_32: {
   6995     MCInst TmpInst;
   6996     unsigned Spacing;
   6997     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   6998     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   6999     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7000                                             Spacing));
   7001     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7002                                             Spacing * 2));
   7003     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7004     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7005     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7006     TmpInst.addOperand(Inst.getOperand(3)); // Rm
   7007     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   7008     TmpInst.addOperand(Inst.getOperand(5));
   7009     Inst = TmpInst;
   7010     return true;
   7011   }
   7012 
   7013   // VLD4DUP single 3-element structure to all lanes instructions.
   7014   case ARM::VLD4DUPdAsm_8:
   7015   case ARM::VLD4DUPdAsm_16:
   7016   case ARM::VLD4DUPdAsm_32:
   7017   case ARM::VLD4DUPqAsm_8:
   7018   case ARM::VLD4DUPqAsm_16:
   7019   case ARM::VLD4DUPqAsm_32: {
   7020     MCInst TmpInst;
   7021     unsigned Spacing;
   7022     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   7023     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7024     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7025                                             Spacing));
   7026     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7027                                             Spacing * 2));
   7028     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7029                                             Spacing * 3));
   7030     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7031     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7032     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7033     TmpInst.addOperand(Inst.getOperand(4));
   7034     Inst = TmpInst;
   7035     return true;
   7036   }
   7037 
   7038   case ARM::VLD4DUPdWB_fixed_Asm_8:
   7039   case ARM::VLD4DUPdWB_fixed_Asm_16:
   7040   case ARM::VLD4DUPdWB_fixed_Asm_32:
   7041   case ARM::VLD4DUPqWB_fixed_Asm_8:
   7042   case ARM::VLD4DUPqWB_fixed_Asm_16:
   7043   case ARM::VLD4DUPqWB_fixed_Asm_32: {
   7044     MCInst TmpInst;
   7045     unsigned Spacing;
   7046     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   7047     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7048     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7049                                             Spacing));
   7050     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7051                                             Spacing * 2));
   7052     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7053                                             Spacing * 3));
   7054     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7055     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7056     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7057     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   7058     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7059     TmpInst.addOperand(Inst.getOperand(4));
   7060     Inst = TmpInst;
   7061     return true;
   7062   }
   7063 
   7064   case ARM::VLD4DUPdWB_register_Asm_8:
   7065   case ARM::VLD4DUPdWB_register_Asm_16:
   7066   case ARM::VLD4DUPdWB_register_Asm_32:
   7067   case ARM::VLD4DUPqWB_register_Asm_8:
   7068   case ARM::VLD4DUPqWB_register_Asm_16:
   7069   case ARM::VLD4DUPqWB_register_Asm_32: {
   7070     MCInst TmpInst;
   7071     unsigned Spacing;
   7072     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   7073     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7074     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7075                                             Spacing));
   7076     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7077                                             Spacing * 2));
   7078     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7079                                             Spacing * 3));
   7080     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7081     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7082     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7083     TmpInst.addOperand(Inst.getOperand(3)); // Rm
   7084     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   7085     TmpInst.addOperand(Inst.getOperand(5));
   7086     Inst = TmpInst;
   7087     return true;
   7088   }
   7089 
   7090   // VLD4 multiple 4-element structure instructions.
   7091   case ARM::VLD4dAsm_8:
   7092   case ARM::VLD4dAsm_16:
   7093   case ARM::VLD4dAsm_32:
   7094   case ARM::VLD4qAsm_8:
   7095   case ARM::VLD4qAsm_16:
   7096   case ARM::VLD4qAsm_32: {
   7097     MCInst TmpInst;
   7098     unsigned Spacing;
   7099     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   7100     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7101     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7102                                             Spacing));
   7103     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7104                                             Spacing * 2));
   7105     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7106                                             Spacing * 3));
   7107     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7108     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7109     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7110     TmpInst.addOperand(Inst.getOperand(4));
   7111     Inst = TmpInst;
   7112     return true;
   7113   }
   7114 
   7115   case ARM::VLD4dWB_fixed_Asm_8:
   7116   case ARM::VLD4dWB_fixed_Asm_16:
   7117   case ARM::VLD4dWB_fixed_Asm_32:
   7118   case ARM::VLD4qWB_fixed_Asm_8:
   7119   case ARM::VLD4qWB_fixed_Asm_16:
   7120   case ARM::VLD4qWB_fixed_Asm_32: {
   7121     MCInst TmpInst;
   7122     unsigned Spacing;
   7123     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   7124     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7125     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7126                                             Spacing));
   7127     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7128                                             Spacing * 2));
   7129     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7130                                             Spacing * 3));
   7131     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7132     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7133     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7134     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   7135     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7136     TmpInst.addOperand(Inst.getOperand(4));
   7137     Inst = TmpInst;
   7138     return true;
   7139   }
   7140 
   7141   case ARM::VLD4dWB_register_Asm_8:
   7142   case ARM::VLD4dWB_register_Asm_16:
   7143   case ARM::VLD4dWB_register_Asm_32:
   7144   case ARM::VLD4qWB_register_Asm_8:
   7145   case ARM::VLD4qWB_register_Asm_16:
   7146   case ARM::VLD4qWB_register_Asm_32: {
   7147     MCInst TmpInst;
   7148     unsigned Spacing;
   7149     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
   7150     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7151     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7152                                             Spacing));
   7153     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7154                                             Spacing * 2));
   7155     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7156                                             Spacing * 3));
   7157     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7158     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7159     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7160     TmpInst.addOperand(Inst.getOperand(3)); // Rm
   7161     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   7162     TmpInst.addOperand(Inst.getOperand(5));
   7163     Inst = TmpInst;
   7164     return true;
   7165   }
   7166 
   7167   // VST3 multiple 3-element structure instructions.
   7168   case ARM::VST3dAsm_8:
   7169   case ARM::VST3dAsm_16:
   7170   case ARM::VST3dAsm_32:
   7171   case ARM::VST3qAsm_8:
   7172   case ARM::VST3qAsm_16:
   7173   case ARM::VST3qAsm_32: {
   7174     MCInst TmpInst;
   7175     unsigned Spacing;
   7176     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   7177     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7178     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7179     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7180     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7181                                             Spacing));
   7182     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7183                                             Spacing * 2));
   7184     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7185     TmpInst.addOperand(Inst.getOperand(4));
   7186     Inst = TmpInst;
   7187     return true;
   7188   }
   7189 
   7190   case ARM::VST3dWB_fixed_Asm_8:
   7191   case ARM::VST3dWB_fixed_Asm_16:
   7192   case ARM::VST3dWB_fixed_Asm_32:
   7193   case ARM::VST3qWB_fixed_Asm_8:
   7194   case ARM::VST3qWB_fixed_Asm_16:
   7195   case ARM::VST3qWB_fixed_Asm_32: {
   7196     MCInst TmpInst;
   7197     unsigned Spacing;
   7198     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   7199     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7200     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7201     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7202     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   7203     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7204     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7205                                             Spacing));
   7206     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7207                                             Spacing * 2));
   7208     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7209     TmpInst.addOperand(Inst.getOperand(4));
   7210     Inst = TmpInst;
   7211     return true;
   7212   }
   7213 
   7214   case ARM::VST3dWB_register_Asm_8:
   7215   case ARM::VST3dWB_register_Asm_16:
   7216   case ARM::VST3dWB_register_Asm_32:
   7217   case ARM::VST3qWB_register_Asm_8:
   7218   case ARM::VST3qWB_register_Asm_16:
   7219   case ARM::VST3qWB_register_Asm_32: {
   7220     MCInst TmpInst;
   7221     unsigned Spacing;
   7222     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   7223     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7224     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7225     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7226     TmpInst.addOperand(Inst.getOperand(3)); // Rm
   7227     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7228     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7229                                             Spacing));
   7230     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7231                                             Spacing * 2));
   7232     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   7233     TmpInst.addOperand(Inst.getOperand(5));
   7234     Inst = TmpInst;
   7235     return true;
   7236   }
   7237 
   7238   // VST4 multiple 3-element structure instructions.
   7239   case ARM::VST4dAsm_8:
   7240   case ARM::VST4dAsm_16:
   7241   case ARM::VST4dAsm_32:
   7242   case ARM::VST4qAsm_8:
   7243   case ARM::VST4qAsm_16:
   7244   case ARM::VST4qAsm_32: {
   7245     MCInst TmpInst;
   7246     unsigned Spacing;
   7247     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   7248     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7249     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7250     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7251     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7252                                             Spacing));
   7253     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7254                                             Spacing * 2));
   7255     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7256                                             Spacing * 3));
   7257     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7258     TmpInst.addOperand(Inst.getOperand(4));
   7259     Inst = TmpInst;
   7260     return true;
   7261   }
   7262 
   7263   case ARM::VST4dWB_fixed_Asm_8:
   7264   case ARM::VST4dWB_fixed_Asm_16:
   7265   case ARM::VST4dWB_fixed_Asm_32:
   7266   case ARM::VST4qWB_fixed_Asm_8:
   7267   case ARM::VST4qWB_fixed_Asm_16:
   7268   case ARM::VST4qWB_fixed_Asm_32: {
   7269     MCInst TmpInst;
   7270     unsigned Spacing;
   7271     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   7272     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7273     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7274     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7275     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
   7276     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7277     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7278                                             Spacing));
   7279     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7280                                             Spacing * 2));
   7281     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7282                                             Spacing * 3));
   7283     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7284     TmpInst.addOperand(Inst.getOperand(4));
   7285     Inst = TmpInst;
   7286     return true;
   7287   }
   7288 
   7289   case ARM::VST4dWB_register_Asm_8:
   7290   case ARM::VST4dWB_register_Asm_16:
   7291   case ARM::VST4dWB_register_Asm_32:
   7292   case ARM::VST4qWB_register_Asm_8:
   7293   case ARM::VST4qWB_register_Asm_16:
   7294   case ARM::VST4qWB_register_Asm_32: {
   7295     MCInst TmpInst;
   7296     unsigned Spacing;
   7297     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
   7298     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7299     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
   7300     TmpInst.addOperand(Inst.getOperand(2)); // alignment
   7301     TmpInst.addOperand(Inst.getOperand(3)); // Rm
   7302     TmpInst.addOperand(Inst.getOperand(0)); // Vd
   7303     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7304                                             Spacing));
   7305     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7306                                             Spacing * 2));
   7307     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
   7308                                             Spacing * 3));
   7309     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   7310     TmpInst.addOperand(Inst.getOperand(5));
   7311     Inst = TmpInst;
   7312     return true;
   7313   }
   7314 
   7315   // Handle encoding choice for the shift-immediate instructions.
   7316   case ARM::t2LSLri:
   7317   case ARM::t2LSRri:
   7318   case ARM::t2ASRri: {
   7319     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
   7320         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
   7321         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
   7322         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
   7323           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
   7324       unsigned NewOpc;
   7325       switch (Inst.getOpcode()) {
   7326       default: llvm_unreachable("unexpected opcode");
   7327       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
   7328       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
   7329       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
   7330       }
   7331       // The Thumb1 operands aren't in the same order. Awesome, eh?
   7332       MCInst TmpInst;
   7333       TmpInst.setOpcode(NewOpc);
   7334       TmpInst.addOperand(Inst.getOperand(0));
   7335       TmpInst.addOperand(Inst.getOperand(5));
   7336       TmpInst.addOperand(Inst.getOperand(1));
   7337       TmpInst.addOperand(Inst.getOperand(2));
   7338       TmpInst.addOperand(Inst.getOperand(3));
   7339       TmpInst.addOperand(Inst.getOperand(4));
   7340       Inst = TmpInst;
   7341       return true;
   7342     }
   7343     return false;
   7344   }
   7345 
   7346   // Handle the Thumb2 mode MOV complex aliases.
   7347   case ARM::t2MOVsr:
   7348   case ARM::t2MOVSsr: {
   7349     // Which instruction to expand to depends on the CCOut operand and
   7350     // whether we're in an IT block if the register operands are low
   7351     // registers.
   7352     bool isNarrow = false;
   7353     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
   7354         isARMLowRegister(Inst.getOperand(1).getReg()) &&
   7355         isARMLowRegister(Inst.getOperand(2).getReg()) &&
   7356         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
   7357         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
   7358       isNarrow = true;
   7359     MCInst TmpInst;
   7360     unsigned newOpc;
   7361     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
   7362     default: llvm_unreachable("unexpected opcode!");
   7363     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
   7364     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
   7365     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
   7366     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
   7367     }
   7368     TmpInst.setOpcode(newOpc);
   7369     TmpInst.addOperand(Inst.getOperand(0)); // Rd
   7370     if (isNarrow)
   7371       TmpInst.addOperand(MCOperand::CreateReg(
   7372           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
   7373     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7374     TmpInst.addOperand(Inst.getOperand(2)); // Rm
   7375     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
   7376     TmpInst.addOperand(Inst.getOperand(5));
   7377     if (!isNarrow)
   7378       TmpInst.addOperand(MCOperand::CreateReg(
   7379           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
   7380     Inst = TmpInst;
   7381     return true;
   7382   }
   7383   case ARM::t2MOVsi:
   7384   case ARM::t2MOVSsi: {
   7385     // Which instruction to expand to depends on the CCOut operand and
   7386     // whether we're in an IT block if the register operands are low
   7387     // registers.
   7388     bool isNarrow = false;
   7389     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
   7390         isARMLowRegister(Inst.getOperand(1).getReg()) &&
   7391         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
   7392       isNarrow = true;
   7393     MCInst TmpInst;
   7394     unsigned newOpc;
   7395     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
   7396     default: llvm_unreachable("unexpected opcode!");
   7397     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
   7398     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
   7399     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
   7400     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
   7401     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
   7402     }
   7403     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
   7404     if (Amount == 32) Amount = 0;
   7405     TmpInst.setOpcode(newOpc);
   7406     TmpInst.addOperand(Inst.getOperand(0)); // Rd
   7407     if (isNarrow)
   7408       TmpInst.addOperand(MCOperand::CreateReg(
   7409           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
   7410     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7411     if (newOpc != ARM::t2RRX)
   7412       TmpInst.addOperand(MCOperand::CreateImm(Amount));
   7413     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7414     TmpInst.addOperand(Inst.getOperand(4));
   7415     if (!isNarrow)
   7416       TmpInst.addOperand(MCOperand::CreateReg(
   7417           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
   7418     Inst = TmpInst;
   7419     return true;
   7420   }
   7421   // Handle the ARM mode MOV complex aliases.
   7422   case ARM::ASRr:
   7423   case ARM::LSRr:
   7424   case ARM::LSLr:
   7425   case ARM::RORr: {
   7426     ARM_AM::ShiftOpc ShiftTy;
   7427     switch(Inst.getOpcode()) {
   7428     default: llvm_unreachable("unexpected opcode!");
   7429     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
   7430     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
   7431     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
   7432     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
   7433     }
   7434     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
   7435     MCInst TmpInst;
   7436     TmpInst.setOpcode(ARM::MOVsr);
   7437     TmpInst.addOperand(Inst.getOperand(0)); // Rd
   7438     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7439     TmpInst.addOperand(Inst.getOperand(2)); // Rm
   7440     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
   7441     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7442     TmpInst.addOperand(Inst.getOperand(4));
   7443     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
   7444     Inst = TmpInst;
   7445     return true;
   7446   }
   7447   case ARM::ASRi:
   7448   case ARM::LSRi:
   7449   case ARM::LSLi:
   7450   case ARM::RORi: {
   7451     ARM_AM::ShiftOpc ShiftTy;
   7452     switch(Inst.getOpcode()) {
   7453     default: llvm_unreachable("unexpected opcode!");
   7454     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
   7455     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
   7456     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
   7457     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
   7458     }
   7459     // A shift by zero is a plain MOVr, not a MOVsi.
   7460     unsigned Amt = Inst.getOperand(2).getImm();
   7461     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
   7462     // A shift by 32 should be encoded as 0 when permitted
   7463     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
   7464       Amt = 0;
   7465     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
   7466     MCInst TmpInst;
   7467     TmpInst.setOpcode(Opc);
   7468     TmpInst.addOperand(Inst.getOperand(0)); // Rd
   7469     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7470     if (Opc == ARM::MOVsi)
   7471       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
   7472     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
   7473     TmpInst.addOperand(Inst.getOperand(4));
   7474     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
   7475     Inst = TmpInst;
   7476     return true;
   7477   }
   7478   case ARM::RRXi: {
   7479     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
   7480     MCInst TmpInst;
   7481     TmpInst.setOpcode(ARM::MOVsi);
   7482     TmpInst.addOperand(Inst.getOperand(0)); // Rd
   7483     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7484     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
   7485     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
   7486     TmpInst.addOperand(Inst.getOperand(3));
   7487     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
   7488     Inst = TmpInst;
   7489     return true;
   7490   }
   7491   case ARM::t2LDMIA_UPD: {
   7492     // If this is a load of a single register, then we should use
   7493     // a post-indexed LDR instruction instead, per the ARM ARM.
   7494     if (Inst.getNumOperands() != 5)
   7495       return false;
   7496     MCInst TmpInst;
   7497     TmpInst.setOpcode(ARM::t2LDR_POST);
   7498     TmpInst.addOperand(Inst.getOperand(4)); // Rt
   7499     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
   7500     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7501     TmpInst.addOperand(MCOperand::CreateImm(4));
   7502     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
   7503     TmpInst.addOperand(Inst.getOperand(3));
   7504     Inst = TmpInst;
   7505     return true;
   7506   }
   7507   case ARM::t2STMDB_UPD: {
   7508     // If this is a store of a single register, then we should use
   7509     // a pre-indexed STR instruction instead, per the ARM ARM.
   7510     if (Inst.getNumOperands() != 5)
   7511       return false;
   7512     MCInst TmpInst;
   7513     TmpInst.setOpcode(ARM::t2STR_PRE);
   7514     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
   7515     TmpInst.addOperand(Inst.getOperand(4)); // Rt
   7516     TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7517     TmpInst.addOperand(MCOperand::CreateImm(-4));
   7518     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
   7519     TmpInst.addOperand(Inst.getOperand(3));
   7520     Inst = TmpInst;
   7521     return true;
   7522   }
   7523   case ARM::LDMIA_UPD:
   7524     // If this is a load of a single register via a 'pop', then we should use
   7525     // a post-indexed LDR instruction instead, per the ARM ARM.
   7526     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
   7527         Inst.getNumOperands() == 5) {
   7528       MCInst TmpInst;
   7529       TmpInst.setOpcode(ARM::LDR_POST_IMM);
   7530       TmpInst.addOperand(Inst.getOperand(4)); // Rt
   7531       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
   7532       TmpInst.addOperand(Inst.getOperand(1)); // Rn
   7533       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
   7534       TmpInst.addOperand(MCOperand::CreateImm(4));
   7535       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
   7536       TmpInst.addOperand(Inst.getOperand(3));
   7537       Inst = TmpInst;
   7538       return true;
   7539     }
   7540     break;
   7541   case ARM::STMDB_UPD:
   7542     // If this is a store of a single register via a 'push', then we should use
   7543     // a pre-indexed STR instruction instead, per the ARM ARM.
   7544     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
   7545         Inst.getNumOperands() == 5) {
   7546       MCInst TmpInst;
   7547       TmpInst.setOpcode(ARM::STR_PRE_IMM);
   7548       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
   7549       TmpInst.addOperand(Inst.getOperand(4)); // Rt
   7550       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
   7551       TmpInst.addOperand(MCOperand::CreateImm(-4));
   7552       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
   7553       TmpInst.addOperand(Inst.getOperand(3));
   7554       Inst = TmpInst;
   7555     }
   7556     break;
   7557   case ARM::t2ADDri12:
   7558     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
   7559     // mnemonic was used (not "addw"), encoding T3 is preferred.
   7560     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
   7561         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
   7562       break;
   7563     Inst.setOpcode(ARM::t2ADDri);
   7564     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
   7565     break;
   7566   case ARM::t2SUBri12:
   7567     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
   7568     // mnemonic was used (not "subw"), encoding T3 is preferred.
   7569     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
   7570         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
   7571       break;
   7572     Inst.setOpcode(ARM::t2SUBri);
   7573     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
   7574     break;
   7575   case ARM::tADDi8:
   7576     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
   7577     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
   7578     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
   7579     // to encoding T1 if <Rd> is omitted."
   7580     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
   7581       Inst.setOpcode(ARM::tADDi3);
   7582       return true;
   7583     }
   7584     break;
   7585   case ARM::tSUBi8:
   7586     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
   7587     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
   7588     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
   7589     // to encoding T1 if <Rd> is omitted."
   7590     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
   7591       Inst.setOpcode(ARM::tSUBi3);
   7592       return true;
   7593     }
   7594     break;
   7595   case ARM::t2ADDri:
   7596   case ARM::t2SUBri: {
   7597     // If the destination and first source operand are the same, and
   7598     // the flags are compatible with the current IT status, use encoding T2
   7599     // instead of T3. For compatibility with the system 'as'. Make sure the
   7600     // wide encoding wasn't explicit.
   7601     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
   7602         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
   7603         (unsigned)Inst.getOperand(2).getImm() > 255 ||
   7604         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
   7605          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
   7606         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
   7607          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
   7608       break;
   7609     MCInst TmpInst;
   7610     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
   7611                       ARM::tADDi8 : ARM::tSUBi8);
   7612     TmpInst.addOperand(Inst.getOperand(0));
   7613     TmpInst.addOperand(Inst.getOperand(5));
   7614     TmpInst.addOperand(Inst.getOperand(0));
   7615     TmpInst.addOperand(Inst.getOperand(2));
   7616     TmpInst.addOperand(Inst.getOperand(3));
   7617     TmpInst.addOperand(Inst.getOperand(4));
   7618     Inst = TmpInst;
   7619     return true;
   7620   }
   7621   case ARM::t2ADDrr: {
   7622     // If the destination and first source operand are the same, and
   7623     // there's no setting of the flags, use encoding T2 instead of T3.
   7624     // Note that this is only for ADD, not SUB. This mirrors the system
   7625     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
   7626     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
   7627         Inst.getOperand(5).getReg() != 0 ||
   7628         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
   7629          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
   7630       break;
   7631     MCInst TmpInst;
   7632     TmpInst.setOpcode(ARM::tADDhirr);
   7633     TmpInst.addOperand(Inst.getOperand(0));
   7634     TmpInst.addOperand(Inst.getOperand(0));
   7635     TmpInst.addOperand(Inst.getOperand(2));
   7636     TmpInst.addOperand(Inst.getOperand(3));
   7637     TmpInst.addOperand(Inst.getOperand(4));
   7638     Inst = TmpInst;
   7639     return true;
   7640   }
   7641   case ARM::tADDrSP: {
   7642     // If the non-SP source operand and the destination operand are not the
   7643     // same, we need to use the 32-bit encoding if it's available.
   7644     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
   7645       Inst.setOpcode(ARM::t2ADDrr);
   7646       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
   7647       return true;
   7648     }
   7649     break;
   7650   }
   7651   case ARM::tB:
   7652     // A Thumb conditional branch outside of an IT block is a tBcc.
   7653     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
   7654       Inst.setOpcode(ARM::tBcc);
   7655       return true;
   7656     }
   7657     break;
   7658   case ARM::t2B:
   7659     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
   7660     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
   7661       Inst.setOpcode(ARM::t2Bcc);
   7662       return true;
   7663     }
   7664     break;
   7665   case ARM::t2Bcc:
   7666     // If the conditional is AL or we're in an IT block, we really want t2B.
   7667     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
   7668       Inst.setOpcode(ARM::t2B);
   7669       return true;
   7670     }
   7671     break;
   7672   case ARM::tBcc:
   7673     // If the conditional is AL, we really want tB.
   7674     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
   7675       Inst.setOpcode(ARM::tB);
   7676       return true;
   7677     }
   7678     break;
   7679   case ARM::tLDMIA: {
   7680     // If the register list contains any high registers, or if the writeback
   7681     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
   7682     // instead if we're in Thumb2. Otherwise, this should have generated
   7683     // an error in validateInstruction().
   7684     unsigned Rn = Inst.getOperand(0).getReg();
   7685     bool hasWritebackToken =
   7686         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
   7687          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
   7688     bool listContainsBase;
   7689     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
   7690         (!listContainsBase && !hasWritebackToken) ||
   7691         (listContainsBase && hasWritebackToken)) {
   7692       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
   7693       assert (isThumbTwo());
   7694       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
   7695       // If we're switching to the updating version, we need to insert
   7696       // the writeback tied operand.
   7697       if (hasWritebackToken)
   7698         Inst.insert(Inst.begin(),
   7699                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
   7700       return true;
   7701     }
   7702     break;
   7703   }
   7704   case ARM::tSTMIA_UPD: {
   7705     // If the register list contains any high registers, we need to use
   7706     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
   7707     // should have generated an error in validateInstruction().
   7708     unsigned Rn = Inst.getOperand(0).getReg();
   7709     bool listContainsBase;
   7710     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
   7711       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
   7712       assert (isThumbTwo());
   7713       Inst.setOpcode(ARM::t2STMIA_UPD);
   7714       return true;
   7715     }
   7716     break;
   7717   }
   7718   case ARM::tPOP: {
   7719     bool listContainsBase;
   7720     // If the register list contains any high registers, we need to use
   7721     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
   7722     // should have generated an error in validateInstruction().
   7723     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
   7724       return false;
   7725     assert (isThumbTwo());
   7726     Inst.setOpcode(ARM::t2LDMIA_UPD);
   7727     // Add the base register and writeback operands.
   7728     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
   7729     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
   7730     return true;
   7731   }
   7732   case ARM::tPUSH: {
   7733     bool listContainsBase;
   7734     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
   7735       return false;
   7736     assert (isThumbTwo());
   7737     Inst.setOpcode(ARM::t2STMDB_UPD);
   7738     // Add the base register and writeback operands.
   7739     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
   7740     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
   7741     return true;
   7742   }
   7743   case ARM::t2MOVi: {
   7744     // If we can use the 16-bit encoding and the user didn't explicitly
   7745     // request the 32-bit variant, transform it here.
   7746     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
   7747         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
   7748         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
   7749           Inst.getOperand(4).getReg() == ARM::CPSR) ||
   7750          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
   7751         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
   7752          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
   7753       // The operands aren't in the same order for tMOVi8...
   7754       MCInst TmpInst;
   7755       TmpInst.setOpcode(ARM::tMOVi8);
   7756       TmpInst.addOperand(Inst.getOperand(0));
   7757       TmpInst.addOperand(Inst.getOperand(4));
   7758       TmpInst.addOperand(Inst.getOperand(1));
   7759       TmpInst.addOperand(Inst.getOperand(2));
   7760       TmpInst.addOperand(Inst.getOperand(3));
   7761       Inst = TmpInst;
   7762       return true;
   7763     }
   7764     break;
   7765   }
   7766   case ARM::t2MOVr: {
   7767     // If we can use the 16-bit encoding and the user didn't explicitly
   7768     // request the 32-bit variant, transform it here.
   7769     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
   7770         isARMLowRegister(Inst.getOperand(1).getReg()) &&
   7771         Inst.getOperand(2).getImm() == ARMCC::AL &&
   7772         Inst.getOperand(4).getReg() == ARM::CPSR &&
   7773         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
   7774          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
   7775       // The operands aren't the same for tMOV[S]r... (no cc_out)
   7776       MCInst TmpInst;
   7777       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
   7778       TmpInst.addOperand(Inst.getOperand(0));
   7779       TmpInst.addOperand(Inst.getOperand(1));
   7780       TmpInst.addOperand(Inst.getOperand(2));
   7781       TmpInst.addOperand(Inst.getOperand(3));
   7782       Inst = TmpInst;
   7783       return true;
   7784     }
   7785     break;
   7786   }
   7787   case ARM::t2SXTH:
   7788   case ARM::t2SXTB:
   7789   case ARM::t2UXTH:
   7790   case ARM::t2UXTB: {
   7791     // If we can use the 16-bit encoding and the user didn't explicitly
   7792     // request the 32-bit variant, transform it here.
   7793     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
   7794         isARMLowRegister(Inst.getOperand(1).getReg()) &&
   7795         Inst.getOperand(2).getImm() == 0 &&
   7796         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
   7797          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
   7798       unsigned NewOpc;
   7799       switch (Inst.getOpcode()) {
   7800       default: llvm_unreachable("Illegal opcode!");
   7801       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
   7802       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
   7803       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
   7804       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
   7805       }
   7806       // The operands aren't the same for thumb1 (no rotate operand).
   7807       MCInst TmpInst;
   7808       TmpInst.setOpcode(NewOpc);
   7809       TmpInst.addOperand(Inst.getOperand(0));
   7810       TmpInst.addOperand(Inst.getOperand(1));
   7811       TmpInst.addOperand(Inst.getOperand(3));
   7812       TmpInst.addOperand(Inst.getOperand(4));
   7813       Inst = TmpInst;
   7814       return true;
   7815     }
   7816     break;
   7817   }
   7818   case ARM::MOVsi: {
   7819     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
   7820     // rrx shifts and asr/lsr of #32 is encoded as 0
   7821     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
   7822       return false;
   7823     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
   7824       // Shifting by zero is accepted as a vanilla 'MOVr'
   7825       MCInst TmpInst;
   7826       TmpInst.setOpcode(ARM::MOVr);
   7827       TmpInst.addOperand(Inst.getOperand(0));
   7828       TmpInst.addOperand(Inst.getOperand(1));
   7829       TmpInst.addOperand(Inst.getOperand(3));
   7830       TmpInst.addOperand(Inst.getOperand(4));
   7831       TmpInst.addOperand(Inst.getOperand(5));
   7832       Inst = TmpInst;
   7833       return true;
   7834     }
   7835     return false;
   7836   }
   7837   case ARM::ANDrsi:
   7838   case ARM::ORRrsi:
   7839   case ARM::EORrsi:
   7840   case ARM::BICrsi:
   7841   case ARM::SUBrsi:
   7842   case ARM::ADDrsi: {
   7843     unsigned newOpc;
   7844     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
   7845     if (SOpc == ARM_AM::rrx) return false;
   7846     switch (Inst.getOpcode()) {
   7847     default: llvm_unreachable("unexpected opcode!");
   7848     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
   7849     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
   7850     case ARM::EORrsi: newOpc = ARM::EORrr; break;
   7851     case ARM::BICrsi: newOpc = ARM::BICrr; break;
   7852     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
   7853     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
   7854     }
   7855     // If the shift is by zero, use the non-shifted instruction definition.
   7856     // The exception is for right shifts, where 0 == 32
   7857     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
   7858         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
   7859       MCInst TmpInst;
   7860       TmpInst.setOpcode(newOpc);
   7861       TmpInst.addOperand(Inst.getOperand(0));
   7862       TmpInst.addOperand(Inst.getOperand(1));
   7863       TmpInst.addOperand(Inst.getOperand(2));
   7864       TmpInst.addOperand(Inst.getOperand(4));
   7865       TmpInst.addOperand(Inst.getOperand(5));
   7866       TmpInst.addOperand(Inst.getOperand(6));
   7867       Inst = TmpInst;
   7868       return true;
   7869     }
   7870     return false;
   7871   }
   7872   case ARM::ITasm:
   7873   case ARM::t2IT: {
   7874     // The mask bits for all but the first condition are represented as
   7875     // the low bit of the condition code value implies 't'. We currently
   7876     // always have 1 implies 't', so XOR toggle the bits if the low bit
   7877     // of the condition code is zero.
   7878     MCOperand &MO = Inst.getOperand(1);
   7879     unsigned Mask = MO.getImm();
   7880     unsigned OrigMask = Mask;
   7881     unsigned TZ = countTrailingZeros(Mask);
   7882     if ((Inst.getOperand(0).getImm() & 1) == 0) {
   7883       assert(Mask && TZ <= 3 && "illegal IT mask value!");
   7884       Mask ^= (0xE << TZ) & 0xF;
   7885     }
   7886     MO.setImm(Mask);
   7887 
   7888     // Set up the IT block state according to the IT instruction we just
   7889     // matched.
   7890     assert(!inITBlock() && "nested IT blocks?!");
   7891     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
   7892     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
   7893     ITState.CurPosition = 0;
   7894     ITState.FirstCond = true;
   7895     break;
   7896   }
   7897   case ARM::t2LSLrr:
   7898   case ARM::t2LSRrr:
   7899   case ARM::t2ASRrr:
   7900   case ARM::t2SBCrr:
   7901   case ARM::t2RORrr:
   7902   case ARM::t2BICrr:
   7903   {
   7904     // Assemblers should use the narrow encodings of these instructions when permissible.
   7905     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
   7906          isARMLowRegister(Inst.getOperand(2).getReg())) &&
   7907         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
   7908         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
   7909          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
   7910         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
   7911          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
   7912              ".w"))) {
   7913       unsigned NewOpc;
   7914       switch (Inst.getOpcode()) {
   7915         default: llvm_unreachable("unexpected opcode");
   7916         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
   7917         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
   7918         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
   7919         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
   7920         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
   7921         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
   7922       }
   7923       MCInst TmpInst;
   7924       TmpInst.setOpcode(NewOpc);
   7925       TmpInst.addOperand(Inst.getOperand(0));
   7926       TmpInst.addOperand(Inst.getOperand(5));
   7927       TmpInst.addOperand(Inst.getOperand(1));
   7928       TmpInst.addOperand(Inst.getOperand(2));
   7929       TmpInst.addOperand(Inst.getOperand(3));
   7930       TmpInst.addOperand(Inst.getOperand(4));
   7931       Inst = TmpInst;
   7932       return true;
   7933     }
   7934     return false;
   7935   }
   7936   case ARM::t2ANDrr:
   7937   case ARM::t2EORrr:
   7938   case ARM::t2ADCrr:
   7939   case ARM::t2ORRrr:
   7940   {
   7941     // Assemblers should use the narrow encodings of these instructions when permissible.
   7942     // These instructions are special in that they are commutable, so shorter encodings
   7943     // are available more often.
   7944     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
   7945          isARMLowRegister(Inst.getOperand(2).getReg())) &&
   7946         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
   7947          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
   7948         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
   7949          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
   7950         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
   7951          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
   7952              ".w"))) {
   7953       unsigned NewOpc;
   7954       switch (Inst.getOpcode()) {
   7955         default: llvm_unreachable("unexpected opcode");
   7956         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
   7957         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
   7958         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
   7959         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
   7960       }
   7961       MCInst TmpInst;
   7962       TmpInst.setOpcode(NewOpc);
   7963       TmpInst.addOperand(Inst.getOperand(0));
   7964       TmpInst.addOperand(Inst.getOperand(5));
   7965       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
   7966         TmpInst.addOperand(Inst.getOperand(1));
   7967         TmpInst.addOperand(Inst.getOperand(2));
   7968       } else {
   7969         TmpInst.addOperand(Inst.getOperand(2));
   7970         TmpInst.addOperand(Inst.getOperand(1));
   7971       }
   7972       TmpInst.addOperand(Inst.getOperand(3));
   7973       TmpInst.addOperand(Inst.getOperand(4));
   7974       Inst = TmpInst;
   7975       return true;
   7976     }
   7977     return false;
   7978   }
   7979   }
   7980   return false;
   7981 }
   7982 
   7983 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   7984   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
   7985   // suffix depending on whether they're in an IT block or not.
   7986   unsigned Opc = Inst.getOpcode();
   7987   const MCInstrDesc &MCID = MII.get(Opc);
   7988   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
   7989     assert(MCID.hasOptionalDef() &&
   7990            "optionally flag setting instruction missing optional def operand");
   7991     assert(MCID.NumOperands == Inst.getNumOperands() &&
   7992            "operand count mismatch!");
   7993     // Find the optional-def operand (cc_out).
   7994     unsigned OpNo;
   7995     for (OpNo = 0;
   7996          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
   7997          ++OpNo)
   7998       ;
   7999     // If we're parsing Thumb1, reject it completely.
   8000     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
   8001       return Match_MnemonicFail;
   8002     // If we're parsing Thumb2, which form is legal depends on whether we're
   8003     // in an IT block.
   8004     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
   8005         !inITBlock())
   8006       return Match_RequiresITBlock;
   8007     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
   8008         inITBlock())
   8009       return Match_RequiresNotITBlock;
   8010   }
   8011   // Some high-register supporting Thumb1 encodings only allow both registers
   8012   // to be from r0-r7 when in Thumb2.
   8013   else if (Opc == ARM::tADDhirr && isThumbOne() &&
   8014            isARMLowRegister(Inst.getOperand(1).getReg()) &&
   8015            isARMLowRegister(Inst.getOperand(2).getReg()))
   8016     return Match_RequiresThumb2;
   8017   // Others only require ARMv6 or later.
   8018   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
   8019            isARMLowRegister(Inst.getOperand(0).getReg()) &&
   8020            isARMLowRegister(Inst.getOperand(1).getReg()))
   8021     return Match_RequiresV6;
   8022   return Match_Success;
   8023 }
   8024 
   8025 namespace llvm {
   8026 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
   8027   return true; // In an assembly source, no need to second-guess
   8028 }
   8029 }
   8030 
   8031 static const char *getSubtargetFeatureName(unsigned Val);
   8032 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   8033                                            OperandVector &Operands,
   8034                                            MCStreamer &Out, unsigned &ErrorInfo,
   8035                                            bool MatchingInlineAsm) {
   8036   MCInst Inst;
   8037   unsigned MatchResult;
   8038 
   8039   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
   8040                                      MatchingInlineAsm);
   8041   switch (MatchResult) {
   8042   default: break;
   8043   case Match_Success:
   8044     // Context sensitive operand constraints aren't handled by the matcher,
   8045     // so check them here.
   8046     if (validateInstruction(Inst, Operands)) {
   8047       // Still progress the IT block, otherwise one wrong condition causes
   8048       // nasty cascading errors.
   8049       forwardITPosition();
   8050       return true;
   8051     }
   8052 
   8053     { // processInstruction() updates inITBlock state, we need to save it away
   8054       bool wasInITBlock = inITBlock();
   8055 
   8056       // Some instructions need post-processing to, for example, tweak which
   8057       // encoding is selected. Loop on it while changes happen so the
   8058       // individual transformations can chain off each other. E.g.,
   8059       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
   8060       while (processInstruction(Inst, Operands))
   8061         ;
   8062 
   8063       // Only after the instruction is fully processed, we can validate it
   8064       if (wasInITBlock && hasV8Ops() && isThumb() &&
   8065           !isV8EligibleForIT(&Inst)) {
   8066         Warning(IDLoc, "deprecated instruction in IT block");
   8067       }
   8068     }
   8069 
   8070     // Only move forward at the very end so that everything in validate
   8071     // and process gets a consistent answer about whether we're in an IT
   8072     // block.
   8073     forwardITPosition();
   8074 
   8075     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
   8076     // doesn't actually encode.
   8077     if (Inst.getOpcode() == ARM::ITasm)
   8078       return false;
   8079 
   8080     Inst.setLoc(IDLoc);
   8081     Out.EmitInstruction(Inst, STI);
   8082     return false;
   8083   case Match_MissingFeature: {
   8084     assert(ErrorInfo && "Unknown missing feature!");
   8085     // Special case the error message for the very common case where only
   8086     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
   8087     std::string Msg = "instruction requires:";
   8088     unsigned Mask = 1;
   8089     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
   8090       if (ErrorInfo & Mask) {
   8091         Msg += " ";
   8092         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
   8093       }
   8094       Mask <<= 1;
   8095     }
   8096     return Error(IDLoc, Msg);
   8097   }
   8098   case Match_InvalidOperand: {
   8099     SMLoc ErrorLoc = IDLoc;
   8100     if (ErrorInfo != ~0U) {
   8101       if (ErrorInfo >= Operands.size())
   8102         return Error(IDLoc, "too few operands for instruction");
   8103 
   8104       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
   8105       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
   8106     }
   8107 
   8108     return Error(ErrorLoc, "invalid operand for instruction");
   8109   }
   8110   case Match_MnemonicFail:
   8111     return Error(IDLoc, "invalid instruction",
   8112                  ((ARMOperand &)*Operands[0]).getLocRange());
   8113   case Match_RequiresNotITBlock:
   8114     return Error(IDLoc, "flag setting instruction only valid outside IT block");
   8115   case Match_RequiresITBlock:
   8116     return Error(IDLoc, "instruction only valid inside IT block");
   8117   case Match_RequiresV6:
   8118     return Error(IDLoc, "instruction variant requires ARMv6 or later");
   8119   case Match_RequiresThumb2:
   8120     return Error(IDLoc, "instruction variant requires Thumb2");
   8121   case Match_ImmRange0_15: {
   8122     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
   8123     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
   8124     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
   8125   }
   8126   case Match_ImmRange0_239: {
   8127     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
   8128     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
   8129     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
   8130   }
   8131   case Match_AlignedMemoryRequiresNone:
   8132   case Match_DupAlignedMemoryRequiresNone:
   8133   case Match_AlignedMemoryRequires16:
   8134   case Match_DupAlignedMemoryRequires16:
   8135   case Match_AlignedMemoryRequires32:
   8136   case Match_DupAlignedMemoryRequires32:
   8137   case Match_AlignedMemoryRequires64:
   8138   case Match_DupAlignedMemoryRequires64:
   8139   case Match_AlignedMemoryRequires64or128:
   8140   case Match_DupAlignedMemoryRequires64or128:
   8141   case Match_AlignedMemoryRequires64or128or256:
   8142   {
   8143     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
   8144     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
   8145     switch (MatchResult) {
   8146       default:
   8147         llvm_unreachable("Missing Match_Aligned type");
   8148       case Match_AlignedMemoryRequiresNone:
   8149       case Match_DupAlignedMemoryRequiresNone:
   8150         return Error(ErrorLoc, "alignment must be omitted");
   8151       case Match_AlignedMemoryRequires16:
   8152       case Match_DupAlignedMemoryRequires16:
   8153         return Error(ErrorLoc, "alignment must be 16 or omitted");
   8154       case Match_AlignedMemoryRequires32:
   8155       case Match_DupAlignedMemoryRequires32:
   8156         return Error(ErrorLoc, "alignment must be 32 or omitted");
   8157       case Match_AlignedMemoryRequires64:
   8158       case Match_DupAlignedMemoryRequires64:
   8159         return Error(ErrorLoc, "alignment must be 64 or omitted");
   8160       case Match_AlignedMemoryRequires64or128:
   8161       case Match_DupAlignedMemoryRequires64or128:
   8162         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
   8163       case Match_AlignedMemoryRequires64or128or256:
   8164         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
   8165     }
   8166   }
   8167   }
   8168 
   8169   llvm_unreachable("Implement any new match types added!");
   8170 }
   8171 
   8172 /// parseDirective parses the arm specific directives
   8173 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
   8174   const MCObjectFileInfo::Environment Format =
   8175     getContext().getObjectFileInfo()->getObjectFileType();
   8176   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
   8177 
   8178   StringRef IDVal = DirectiveID.getIdentifier();
   8179   if (IDVal == ".word")
   8180     return parseLiteralValues(4, DirectiveID.getLoc());
   8181   else if (IDVal == ".short" || IDVal == ".hword")
   8182     return parseLiteralValues(2, DirectiveID.getLoc());
   8183   else if (IDVal == ".thumb")
   8184     return parseDirectiveThumb(DirectiveID.getLoc());
   8185   else if (IDVal == ".arm")
   8186     return parseDirectiveARM(DirectiveID.getLoc());
   8187   else if (IDVal == ".thumb_func")
   8188     return parseDirectiveThumbFunc(DirectiveID.getLoc());
   8189   else if (IDVal == ".code")
   8190     return parseDirectiveCode(DirectiveID.getLoc());
   8191   else if (IDVal == ".syntax")
   8192     return parseDirectiveSyntax(DirectiveID.getLoc());
   8193   else if (IDVal == ".unreq")
   8194     return parseDirectiveUnreq(DirectiveID.getLoc());
   8195   else if (IDVal == ".fnend")
   8196     return parseDirectiveFnEnd(DirectiveID.getLoc());
   8197   else if (IDVal == ".cantunwind")
   8198     return parseDirectiveCantUnwind(DirectiveID.getLoc());
   8199   else if (IDVal == ".personality")
   8200     return parseDirectivePersonality(DirectiveID.getLoc());
   8201   else if (IDVal == ".handlerdata")
   8202     return parseDirectiveHandlerData(DirectiveID.getLoc());
   8203   else if (IDVal == ".setfp")
   8204     return parseDirectiveSetFP(DirectiveID.getLoc());
   8205   else if (IDVal == ".pad")
   8206     return parseDirectivePad(DirectiveID.getLoc());
   8207   else if (IDVal == ".save")
   8208     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
   8209   else if (IDVal == ".vsave")
   8210     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
   8211   else if (IDVal == ".ltorg" || IDVal == ".pool")
   8212     return parseDirectiveLtorg(DirectiveID.getLoc());
   8213   else if (IDVal == ".even")
   8214     return parseDirectiveEven(DirectiveID.getLoc());
   8215   else if (IDVal == ".personalityindex")
   8216     return parseDirectivePersonalityIndex(DirectiveID.getLoc());
   8217   else if (IDVal == ".unwind_raw")
   8218     return parseDirectiveUnwindRaw(DirectiveID.getLoc());
   8219   else if (IDVal == ".movsp")
   8220     return parseDirectiveMovSP(DirectiveID.getLoc());
   8221   else if (IDVal == ".arch_extension")
   8222     return parseDirectiveArchExtension(DirectiveID.getLoc());
   8223   else if (IDVal == ".align")
   8224     return parseDirectiveAlign(DirectiveID.getLoc());
   8225   else if (IDVal == ".thumb_set")
   8226     return parseDirectiveThumbSet(DirectiveID.getLoc());
   8227 
   8228   if (!IsMachO) {
   8229     if (IDVal == ".arch")
   8230       return parseDirectiveArch(DirectiveID.getLoc());
   8231     else if (IDVal == ".cpu")
   8232       return parseDirectiveCPU(DirectiveID.getLoc());
   8233     else if (IDVal == ".eabi_attribute")
   8234       return parseDirectiveEabiAttr(DirectiveID.getLoc());
   8235     else if (IDVal == ".fpu")
   8236       return parseDirectiveFPU(DirectiveID.getLoc());
   8237     else if (IDVal == ".fnstart")
   8238       return parseDirectiveFnStart(DirectiveID.getLoc());
   8239     else if (IDVal == ".inst")
   8240       return parseDirectiveInst(DirectiveID.getLoc());
   8241     else if (IDVal == ".inst.n")
   8242       return parseDirectiveInst(DirectiveID.getLoc(), 'n');
   8243     else if (IDVal == ".inst.w")
   8244       return parseDirectiveInst(DirectiveID.getLoc(), 'w');
   8245     else if (IDVal == ".object_arch")
   8246       return parseDirectiveObjectArch(DirectiveID.getLoc());
   8247     else if (IDVal == ".tlsdescseq")
   8248       return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
   8249   }
   8250 
   8251   return true;
   8252 }
   8253 
   8254 /// parseLiteralValues
   8255 ///  ::= .hword expression [, expression]*
   8256 ///  ::= .short expression [, expression]*
   8257 ///  ::= .word expression [, expression]*
   8258 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
   8259   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   8260     for (;;) {
   8261       const MCExpr *Value;
   8262       if (getParser().parseExpression(Value)) {
   8263         Parser.eatToEndOfStatement();
   8264         return false;
   8265       }
   8266 
   8267       getParser().getStreamer().EmitValue(Value, Size);
   8268 
   8269       if (getLexer().is(AsmToken::EndOfStatement))
   8270         break;
   8271 
   8272       // FIXME: Improve diagnostic.
   8273       if (getLexer().isNot(AsmToken::Comma)) {
   8274         Error(L, "unexpected token in directive");
   8275         return false;
   8276       }
   8277       Parser.Lex();
   8278     }
   8279   }
   8280 
   8281   Parser.Lex();
   8282   return false;
   8283 }
   8284 
   8285 /// parseDirectiveThumb
   8286 ///  ::= .thumb
   8287 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
   8288   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   8289     Error(L, "unexpected token in directive");
   8290     return false;
   8291   }
   8292   Parser.Lex();
   8293 
   8294   if (!hasThumb()) {
   8295     Error(L, "target does not support Thumb mode");
   8296     return false;
   8297   }
   8298 
   8299   if (!isThumb())
   8300     SwitchMode();
   8301 
   8302   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
   8303   return false;
   8304 }
   8305 
   8306 /// parseDirectiveARM
   8307 ///  ::= .arm
   8308 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
   8309   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   8310     Error(L, "unexpected token in directive");
   8311     return false;
   8312   }
   8313   Parser.Lex();
   8314 
   8315   if (!hasARM()) {
   8316     Error(L, "target does not support ARM mode");
   8317     return false;
   8318   }
   8319 
   8320   if (isThumb())
   8321     SwitchMode();
   8322 
   8323   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
   8324   return false;
   8325 }
   8326 
   8327 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
   8328   if (NextSymbolIsThumb) {
   8329     getParser().getStreamer().EmitThumbFunc(Symbol);
   8330     NextSymbolIsThumb = false;
   8331   }
   8332 }
   8333 
   8334 /// parseDirectiveThumbFunc
   8335 ///  ::= .thumbfunc symbol_name
   8336 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
   8337   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
   8338   bool isMachO = MAI->hasSubsectionsViaSymbols();
   8339 
   8340   // Darwin asm has (optionally) function name after .thumb_func direction
   8341   // ELF doesn't
   8342   if (isMachO) {
   8343     const AsmToken &Tok = Parser.getTok();
   8344     if (Tok.isNot(AsmToken::EndOfStatement)) {
   8345       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
   8346         Error(L, "unexpected token in .thumb_func directive");
   8347         return false;
   8348       }
   8349 
   8350       MCSymbol *Func =
   8351           getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
   8352       getParser().getStreamer().EmitThumbFunc(Func);
   8353       Parser.Lex(); // Consume the identifier token.
   8354       return false;
   8355     }
   8356   }
   8357 
   8358   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   8359     Error(L, "unexpected token in directive");
   8360     return false;
   8361   }
   8362 
   8363   NextSymbolIsThumb = true;
   8364   return false;
   8365 }
   8366 
   8367 /// parseDirectiveSyntax
   8368 ///  ::= .syntax unified | divided
   8369 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
   8370   const AsmToken &Tok = Parser.getTok();
   8371   if (Tok.isNot(AsmToken::Identifier)) {
   8372     Error(L, "unexpected token in .syntax directive");
   8373     return false;
   8374   }
   8375 
   8376   StringRef Mode = Tok.getString();
   8377   if (Mode == "unified" || Mode == "UNIFIED") {
   8378     Parser.Lex();
   8379   } else if (Mode == "divided" || Mode == "DIVIDED") {
   8380     Error(L, "'.syntax divided' arm asssembly not supported");
   8381     return false;
   8382   } else {
   8383     Error(L, "unrecognized syntax mode in .syntax directive");
   8384     return false;
   8385   }
   8386 
   8387   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   8388     Error(Parser.getTok().getLoc(), "unexpected token in directive");
   8389     return false;
   8390   }
   8391   Parser.Lex();
   8392 
   8393   // TODO tell the MC streamer the mode
   8394   // getParser().getStreamer().Emit???();
   8395   return false;
   8396 }
   8397 
   8398 /// parseDirectiveCode
   8399 ///  ::= .code 16 | 32
   8400 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
   8401   const AsmToken &Tok = Parser.getTok();
   8402   if (Tok.isNot(AsmToken::Integer)) {
   8403     Error(L, "unexpected token in .code directive");
   8404     return false;
   8405   }
   8406   int64_t Val = Parser.getTok().getIntVal();
   8407   if (Val != 16 && Val != 32) {
   8408     Error(L, "invalid operand to .code directive");
   8409     return false;
   8410   }
   8411   Parser.Lex();
   8412 
   8413   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   8414     Error(Parser.getTok().getLoc(), "unexpected token in directive");
   8415     return false;
   8416   }
   8417   Parser.Lex();
   8418 
   8419   if (Val == 16) {
   8420     if (!hasThumb()) {
   8421       Error(L, "target does not support Thumb mode");
   8422       return false;
   8423     }
   8424 
   8425     if (!isThumb())
   8426       SwitchMode();
   8427     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
   8428   } else {
   8429     if (!hasARM()) {
   8430       Error(L, "target does not support ARM mode");
   8431       return false;
   8432     }
   8433 
   8434     if (isThumb())
   8435       SwitchMode();
   8436     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
   8437   }
   8438 
   8439   return false;
   8440 }
   8441 
   8442 /// parseDirectiveReq
   8443 ///  ::= name .req registername
   8444 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
   8445   Parser.Lex(); // Eat the '.req' token.
   8446   unsigned Reg;
   8447   SMLoc SRegLoc, ERegLoc;
   8448   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
   8449     Parser.eatToEndOfStatement();
   8450     Error(SRegLoc, "register name expected");
   8451     return false;
   8452   }
   8453 
   8454   // Shouldn't be anything else.
   8455   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
   8456     Parser.eatToEndOfStatement();
   8457     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
   8458     return false;
   8459   }
   8460 
   8461   Parser.Lex(); // Consume the EndOfStatement
   8462 
   8463   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
   8464     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
   8465     return false;
   8466   }
   8467 
   8468   return false;
   8469 }
   8470 
   8471 /// parseDirectiveUneq
   8472 ///  ::= .unreq registername
   8473 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
   8474   if (Parser.getTok().isNot(AsmToken::Identifier)) {
   8475     Parser.eatToEndOfStatement();
   8476     Error(L, "unexpected input in .unreq directive.");
   8477     return false;
   8478   }
   8479   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
   8480   Parser.Lex(); // Eat the identifier.
   8481   return false;
   8482 }
   8483 
   8484 /// parseDirectiveArch
   8485 ///  ::= .arch token
   8486 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
   8487   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
   8488 
   8489   unsigned ID = StringSwitch<unsigned>(Arch)
   8490 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
   8491     .Case(NAME, ARM::ID)
   8492 #define ARM_ARCH_ALIAS(NAME, ID) \
   8493     .Case(NAME, ARM::ID)
   8494 #include "MCTargetDesc/ARMArchName.def"
   8495     .Default(ARM::INVALID_ARCH);
   8496 
   8497   if (ID == ARM::INVALID_ARCH) {
   8498     Error(L, "Unknown arch name");
   8499     return false;
   8500   }
   8501 
   8502   getTargetStreamer().emitArch(ID);
   8503   return false;
   8504 }
   8505 
   8506 /// parseDirectiveEabiAttr
   8507 ///  ::= .eabi_attribute int, int [, "str"]
   8508 ///  ::= .eabi_attribute Tag_name, int [, "str"]
   8509 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
   8510   int64_t Tag;
   8511   SMLoc TagLoc;
   8512   TagLoc = Parser.getTok().getLoc();
   8513   if (Parser.getTok().is(AsmToken::Identifier)) {
   8514     StringRef Name = Parser.getTok().getIdentifier();
   8515     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
   8516     if (Tag == -1) {
   8517       Error(TagLoc, "attribute name not recognised: " + Name);
   8518       Parser.eatToEndOfStatement();
   8519       return false;
   8520     }
   8521     Parser.Lex();
   8522   } else {
   8523     const MCExpr *AttrExpr;
   8524 
   8525     TagLoc = Parser.getTok().getLoc();
   8526     if (Parser.parseExpression(AttrExpr)) {
   8527       Parser.eatToEndOfStatement();
   8528       return false;
   8529     }
   8530 
   8531     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
   8532     if (!CE) {
   8533       Error(TagLoc, "expected numeric constant");
   8534       Parser.eatToEndOfStatement();
   8535       return false;
   8536     }
   8537 
   8538     Tag = CE->getValue();
   8539   }
   8540 
   8541   if (Parser.getTok().isNot(AsmToken::Comma)) {
   8542     Error(Parser.getTok().getLoc(), "comma expected");
   8543     Parser.eatToEndOfStatement();
   8544     return false;
   8545   }
   8546   Parser.Lex(); // skip comma
   8547 
   8548   StringRef StringValue = "";
   8549   bool IsStringValue = false;
   8550 
   8551   int64_t IntegerValue = 0;
   8552   bool IsIntegerValue = false;
   8553 
   8554   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
   8555     IsStringValue = true;
   8556   else if (Tag == ARMBuildAttrs::compatibility) {
   8557     IsStringValue = true;
   8558     IsIntegerValue = true;
   8559   } else if (Tag < 32 || Tag % 2 == 0)
   8560     IsIntegerValue = true;
   8561   else if (Tag % 2 == 1)
   8562     IsStringValue = true;
   8563   else
   8564     llvm_unreachable("invalid tag type");
   8565 
   8566   if (IsIntegerValue) {
   8567     const MCExpr *ValueExpr;
   8568     SMLoc ValueExprLoc = Parser.getTok().getLoc();
   8569     if (Parser.parseExpression(ValueExpr)) {
   8570       Parser.eatToEndOfStatement();
   8571       return false;
   8572     }
   8573 
   8574     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
   8575     if (!CE) {
   8576       Error(ValueExprLoc, "expected numeric constant");
   8577       Parser.eatToEndOfStatement();
   8578       return false;
   8579     }
   8580 
   8581     IntegerValue = CE->getValue();
   8582   }
   8583 
   8584   if (Tag == ARMBuildAttrs::compatibility) {
   8585     if (Parser.getTok().isNot(AsmToken::Comma))
   8586       IsStringValue = false;
   8587     else
   8588       Parser.Lex();
   8589   }
   8590 
   8591   if (IsStringValue) {
   8592     if (Parser.getTok().isNot(AsmToken::String)) {
   8593       Error(Parser.getTok().getLoc(), "bad string constant");
   8594       Parser.eatToEndOfStatement();
   8595       return false;
   8596     }
   8597 
   8598     StringValue = Parser.getTok().getStringContents();
   8599     Parser.Lex();
   8600   }
   8601 
   8602   if (IsIntegerValue && IsStringValue) {
   8603     assert(Tag == ARMBuildAttrs::compatibility);
   8604     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
   8605   } else if (IsIntegerValue)
   8606     getTargetStreamer().emitAttribute(Tag, IntegerValue);
   8607   else if (IsStringValue)
   8608     getTargetStreamer().emitTextAttribute(Tag, StringValue);
   8609   return false;
   8610 }
   8611 
   8612 /// parseDirectiveCPU
   8613 ///  ::= .cpu str
   8614 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
   8615   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
   8616   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
   8617   return false;
   8618 }
   8619 
   8620 /// parseDirectiveFPU
   8621 ///  ::= .fpu str
   8622 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
   8623   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
   8624 
   8625   unsigned ID = StringSwitch<unsigned>(FPU)
   8626 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
   8627 #include "ARMFPUName.def"
   8628     .Default(ARM::INVALID_FPU);
   8629 
   8630   if (ID == ARM::INVALID_FPU) {
   8631     Error(L, "Unknown FPU name");
   8632     return false;
   8633   }
   8634 
   8635   getTargetStreamer().emitFPU(ID);
   8636   return false;
   8637 }
   8638 
   8639 /// parseDirectiveFnStart
   8640 ///  ::= .fnstart
   8641 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
   8642   if (UC.hasFnStart()) {
   8643     Error(L, ".fnstart starts before the end of previous one");
   8644     UC.emitFnStartLocNotes();
   8645     return false;
   8646   }
   8647 
   8648   // Reset the unwind directives parser state
   8649   UC.reset();
   8650 
   8651   getTargetStreamer().emitFnStart();
   8652 
   8653   UC.recordFnStart(L);
   8654   return false;
   8655 }
   8656 
   8657 /// parseDirectiveFnEnd
   8658 ///  ::= .fnend
   8659 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
   8660   // Check the ordering of unwind directives
   8661   if (!UC.hasFnStart()) {
   8662     Error(L, ".fnstart must precede .fnend directive");
   8663     return false;
   8664   }
   8665 
   8666   // Reset the unwind directives parser state
   8667   getTargetStreamer().emitFnEnd();
   8668 
   8669   UC.reset();
   8670   return false;
   8671 }
   8672 
   8673 /// parseDirectiveCantUnwind
   8674 ///  ::= .cantunwind
   8675 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
   8676   UC.recordCantUnwind(L);
   8677 
   8678   // Check the ordering of unwind directives
   8679   if (!UC.hasFnStart()) {
   8680     Error(L, ".fnstart must precede .cantunwind directive");
   8681     return false;
   8682   }
   8683   if (UC.hasHandlerData()) {
   8684     Error(L, ".cantunwind can't be used with .handlerdata directive");
   8685     UC.emitHandlerDataLocNotes();
   8686     return false;
   8687   }
   8688   if (UC.hasPersonality()) {
   8689     Error(L, ".cantunwind can't be used with .personality directive");
   8690     UC.emitPersonalityLocNotes();
   8691     return false;
   8692   }
   8693 
   8694   getTargetStreamer().emitCantUnwind();
   8695   return false;
   8696 }
   8697 
   8698 /// parseDirectivePersonality
   8699 ///  ::= .personality name
   8700 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
   8701   bool HasExistingPersonality = UC.hasPersonality();
   8702 
   8703   UC.recordPersonality(L);
   8704 
   8705   // Check the ordering of unwind directives
   8706   if (!UC.hasFnStart()) {
   8707     Error(L, ".fnstart must precede .personality directive");
   8708     return false;
   8709   }
   8710   if (UC.cantUnwind()) {
   8711     Error(L, ".personality can't be used with .cantunwind directive");
   8712     UC.emitCantUnwindLocNotes();
   8713     return false;
   8714   }
   8715   if (UC.hasHandlerData()) {
   8716     Error(L, ".personality must precede .handlerdata directive");
   8717     UC.emitHandlerDataLocNotes();
   8718     return false;
   8719   }
   8720   if (HasExistingPersonality) {
   8721     Parser.eatToEndOfStatement();
   8722     Error(L, "multiple personality directives");
   8723     UC.emitPersonalityLocNotes();
   8724     return false;
   8725   }
   8726 
   8727   // Parse the name of the personality routine
   8728   if (Parser.getTok().isNot(AsmToken::Identifier)) {
   8729     Parser.eatToEndOfStatement();
   8730     Error(L, "unexpected input in .personality directive.");
   8731     return false;
   8732   }
   8733   StringRef Name(Parser.getTok().getIdentifier());
   8734   Parser.Lex();
   8735 
   8736   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
   8737   getTargetStreamer().emitPersonality(PR);
   8738   return false;
   8739 }
   8740 
   8741 /// parseDirectiveHandlerData
   8742 ///  ::= .handlerdata
   8743 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
   8744   UC.recordHandlerData(L);
   8745 
   8746   // Check the ordering of unwind directives
   8747   if (!UC.hasFnStart()) {
   8748     Error(L, ".fnstart must precede .personality directive");
   8749     return false;
   8750   }
   8751   if (UC.cantUnwind()) {
   8752     Error(L, ".handlerdata can't be used with .cantunwind directive");
   8753     UC.emitCantUnwindLocNotes();
   8754     return false;
   8755   }
   8756 
   8757   getTargetStreamer().emitHandlerData();
   8758   return false;
   8759 }
   8760 
   8761 /// parseDirectiveSetFP
   8762 ///  ::= .setfp fpreg, spreg [, offset]
   8763 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
   8764   // Check the ordering of unwind directives
   8765   if (!UC.hasFnStart()) {
   8766     Error(L, ".fnstart must precede .setfp directive");
   8767     return false;
   8768   }
   8769   if (UC.hasHandlerData()) {
   8770     Error(L, ".setfp must precede .handlerdata directive");
   8771     return false;
   8772   }
   8773 
   8774   // Parse fpreg
   8775   SMLoc FPRegLoc = Parser.getTok().getLoc();
   8776   int FPReg = tryParseRegister();
   8777   if (FPReg == -1) {
   8778     Error(FPRegLoc, "frame pointer register expected");
   8779     return false;
   8780   }
   8781 
   8782   // Consume comma
   8783   if (Parser.getTok().isNot(AsmToken::Comma)) {
   8784     Error(Parser.getTok().getLoc(), "comma expected");
   8785     return false;
   8786   }
   8787   Parser.Lex(); // skip comma
   8788 
   8789   // Parse spreg
   8790   SMLoc SPRegLoc = Parser.getTok().getLoc();
   8791   int SPReg = tryParseRegister();
   8792   if (SPReg == -1) {
   8793     Error(SPRegLoc, "stack pointer register expected");
   8794     return false;
   8795   }
   8796 
   8797   if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
   8798     Error(SPRegLoc, "register should be either $sp or the latest fp register");
   8799     return false;
   8800   }
   8801 
   8802   // Update the frame pointer register
   8803   UC.saveFPReg(FPReg);
   8804 
   8805   // Parse offset
   8806   int64_t Offset = 0;
   8807   if (Parser.getTok().is(AsmToken::Comma)) {
   8808     Parser.Lex(); // skip comma
   8809 
   8810     if (Parser.getTok().isNot(AsmToken::Hash) &&
   8811         Parser.getTok().isNot(AsmToken::Dollar)) {
   8812       Error(Parser.getTok().getLoc(), "'#' expected");
   8813       return false;
   8814     }
   8815     Parser.Lex(); // skip hash token.
   8816 
   8817     const MCExpr *OffsetExpr;
   8818     SMLoc ExLoc = Parser.getTok().getLoc();
   8819     SMLoc EndLoc;
   8820     if (getParser().parseExpression(OffsetExpr, EndLoc)) {
   8821       Error(ExLoc, "malformed setfp offset");
   8822       return false;
   8823     }
   8824     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
   8825     if (!CE) {
   8826       Error(ExLoc, "setfp offset must be an immediate");
   8827       return false;
   8828     }
   8829 
   8830     Offset = CE->getValue();
   8831   }
   8832 
   8833   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
   8834                                 static_cast<unsigned>(SPReg), Offset);
   8835   return false;
   8836 }
   8837 
   8838 /// parseDirective
   8839 ///  ::= .pad offset
   8840 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
   8841   // Check the ordering of unwind directives
   8842   if (!UC.hasFnStart()) {
   8843     Error(L, ".fnstart must precede .pad directive");
   8844     return false;
   8845   }
   8846   if (UC.hasHandlerData()) {
   8847     Error(L, ".pad must precede .handlerdata directive");
   8848     return false;
   8849   }
   8850 
   8851   // Parse the offset
   8852   if (Parser.getTok().isNot(AsmToken::Hash) &&
   8853       Parser.getTok().isNot(AsmToken::Dollar)) {
   8854     Error(Parser.getTok().getLoc(), "'#' expected");
   8855     return false;
   8856   }
   8857   Parser.Lex(); // skip hash token.
   8858 
   8859   const MCExpr *OffsetExpr;
   8860   SMLoc ExLoc = Parser.getTok().getLoc();
   8861   SMLoc EndLoc;
   8862   if (getParser().parseExpression(OffsetExpr, EndLoc)) {
   8863     Error(ExLoc, "malformed pad offset");
   8864     return false;
   8865   }
   8866   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
   8867   if (!CE) {
   8868     Error(ExLoc, "pad offset must be an immediate");
   8869     return false;
   8870   }
   8871 
   8872   getTargetStreamer().emitPad(CE->getValue());
   8873   return false;
   8874 }
   8875 
   8876 /// parseDirectiveRegSave
   8877 ///  ::= .save  { registers }
   8878 ///  ::= .vsave { registers }
   8879 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
   8880   // Check the ordering of unwind directives
   8881   if (!UC.hasFnStart()) {
   8882     Error(L, ".fnstart must precede .save or .vsave directives");
   8883     return false;
   8884   }
   8885   if (UC.hasHandlerData()) {
   8886     Error(L, ".save or .vsave must precede .handlerdata directive");
   8887     return false;
   8888   }
   8889 
   8890   // RAII object to make sure parsed operands are deleted.
   8891   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
   8892 
   8893   // Parse the register list
   8894   if (parseRegisterList(Operands))
   8895     return false;
   8896   ARMOperand &Op = (ARMOperand &)*Operands[0];
   8897   if (!IsVector && !Op.isRegList()) {
   8898     Error(L, ".save expects GPR registers");
   8899     return false;
   8900   }
   8901   if (IsVector && !Op.isDPRRegList()) {
   8902     Error(L, ".vsave expects DPR registers");
   8903     return false;
   8904   }
   8905 
   8906   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
   8907   return false;
   8908 }
   8909 
   8910 /// parseDirectiveInst
   8911 ///  ::= .inst opcode [, ...]
   8912 ///  ::= .inst.n opcode [, ...]
   8913 ///  ::= .inst.w opcode [, ...]
   8914 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
   8915   int Width;
   8916 
   8917   if (isThumb()) {
   8918     switch (Suffix) {
   8919     case 'n':
   8920       Width = 2;
   8921       break;
   8922     case 'w':
   8923       Width = 4;
   8924       break;
   8925     default:
   8926       Parser.eatToEndOfStatement();
   8927       Error(Loc, "cannot determine Thumb instruction size, "
   8928                  "use inst.n/inst.w instead");
   8929       return false;
   8930     }
   8931   } else {
   8932     if (Suffix) {
   8933       Parser.eatToEndOfStatement();
   8934       Error(Loc, "width suffixes are invalid in ARM mode");
   8935       return false;
   8936     }
   8937     Width = 4;
   8938   }
   8939 
   8940   if (getLexer().is(AsmToken::EndOfStatement)) {
   8941     Parser.eatToEndOfStatement();
   8942     Error(Loc, "expected expression following directive");
   8943     return false;
   8944   }
   8945 
   8946   for (;;) {
   8947     const MCExpr *Expr;
   8948 
   8949     if (getParser().parseExpression(Expr)) {
   8950       Error(Loc, "expected expression");
   8951       return false;
   8952     }
   8953 
   8954     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
   8955     if (!Value) {
   8956       Error(Loc, "expected constant expression");
   8957       return false;
   8958     }
   8959 
   8960     switch (Width) {
   8961     case 2:
   8962       if (Value->getValue() > 0xffff) {
   8963         Error(Loc, "inst.n operand is too big, use inst.w instead");
   8964         return false;
   8965       }
   8966       break;
   8967     case 4:
   8968       if (Value->getValue() > 0xffffffff) {
   8969         Error(Loc,
   8970               StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
   8971         return false;
   8972       }
   8973       break;
   8974     default:
   8975       llvm_unreachable("only supported widths are 2 and 4");
   8976     }
   8977 
   8978     getTargetStreamer().emitInst(Value->getValue(), Suffix);
   8979 
   8980     if (getLexer().is(AsmToken::EndOfStatement))
   8981       break;
   8982 
   8983     if (getLexer().isNot(AsmToken::Comma)) {
   8984       Error(Loc, "unexpected token in directive");
   8985       return false;
   8986     }
   8987 
   8988     Parser.Lex();
   8989   }
   8990 
   8991   Parser.Lex();
   8992   return false;
   8993 }
   8994 
   8995 /// parseDirectiveLtorg
   8996 ///  ::= .ltorg | .pool
   8997 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
   8998   getTargetStreamer().emitCurrentConstantPool();
   8999   return false;
   9000 }
   9001 
   9002 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
   9003   const MCSection *Section = getStreamer().getCurrentSection().first;
   9004 
   9005   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   9006     TokError("unexpected token in directive");
   9007     return false;
   9008   }
   9009 
   9010   if (!Section) {
   9011     getStreamer().InitSections();
   9012     Section = getStreamer().getCurrentSection().first;
   9013   }
   9014 
   9015   assert(Section && "must have section to emit alignment");
   9016   if (Section->UseCodeAlign())
   9017     getStreamer().EmitCodeAlignment(2);
   9018   else
   9019     getStreamer().EmitValueToAlignment(2);
   9020 
   9021   return false;
   9022 }
   9023 
   9024 /// parseDirectivePersonalityIndex
   9025 ///   ::= .personalityindex index
   9026 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
   9027   bool HasExistingPersonality = UC.hasPersonality();
   9028 
   9029   UC.recordPersonalityIndex(L);
   9030 
   9031   if (!UC.hasFnStart()) {
   9032     Parser.eatToEndOfStatement();
   9033     Error(L, ".fnstart must precede .personalityindex directive");
   9034     return false;
   9035   }
   9036   if (UC.cantUnwind()) {
   9037     Parser.eatToEndOfStatement();
   9038     Error(L, ".personalityindex cannot be used with .cantunwind");
   9039     UC.emitCantUnwindLocNotes();
   9040     return false;
   9041   }
   9042   if (UC.hasHandlerData()) {
   9043     Parser.eatToEndOfStatement();
   9044     Error(L, ".personalityindex must precede .handlerdata directive");
   9045     UC.emitHandlerDataLocNotes();
   9046     return false;
   9047   }
   9048   if (HasExistingPersonality) {
   9049     Parser.eatToEndOfStatement();
   9050     Error(L, "multiple personality directives");
   9051     UC.emitPersonalityLocNotes();
   9052     return false;
   9053   }
   9054 
   9055   const MCExpr *IndexExpression;
   9056   SMLoc IndexLoc = Parser.getTok().getLoc();
   9057   if (Parser.parseExpression(IndexExpression)) {
   9058     Parser.eatToEndOfStatement();
   9059     return false;
   9060   }
   9061 
   9062   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
   9063   if (!CE) {
   9064     Parser.eatToEndOfStatement();
   9065     Error(IndexLoc, "index must be a constant number");
   9066     return false;
   9067   }
   9068   if (CE->getValue() < 0 ||
   9069       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
   9070     Parser.eatToEndOfStatement();
   9071     Error(IndexLoc, "personality routine index should be in range [0-3]");
   9072     return false;
   9073   }
   9074 
   9075   getTargetStreamer().emitPersonalityIndex(CE->getValue());
   9076   return false;
   9077 }
   9078 
   9079 /// parseDirectiveUnwindRaw
   9080 ///   ::= .unwind_raw offset, opcode [, opcode...]
   9081 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
   9082   if (!UC.hasFnStart()) {
   9083     Parser.eatToEndOfStatement();
   9084     Error(L, ".fnstart must precede .unwind_raw directives");
   9085     return false;
   9086   }
   9087 
   9088   int64_t StackOffset;
   9089 
   9090   const MCExpr *OffsetExpr;
   9091   SMLoc OffsetLoc = getLexer().getLoc();
   9092   if (getLexer().is(AsmToken::EndOfStatement) ||
   9093       getParser().parseExpression(OffsetExpr)) {
   9094     Error(OffsetLoc, "expected expression");
   9095     Parser.eatToEndOfStatement();
   9096     return false;
   9097   }
   9098 
   9099   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
   9100   if (!CE) {
   9101     Error(OffsetLoc, "offset must be a constant");
   9102     Parser.eatToEndOfStatement();
   9103     return false;
   9104   }
   9105 
   9106   StackOffset = CE->getValue();
   9107 
   9108   if (getLexer().isNot(AsmToken::Comma)) {
   9109     Error(getLexer().getLoc(), "expected comma");
   9110     Parser.eatToEndOfStatement();
   9111     return false;
   9112   }
   9113   Parser.Lex();
   9114 
   9115   SmallVector<uint8_t, 16> Opcodes;
   9116   for (;;) {
   9117     const MCExpr *OE;
   9118 
   9119     SMLoc OpcodeLoc = getLexer().getLoc();
   9120     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
   9121       Error(OpcodeLoc, "expected opcode expression");
   9122       Parser.eatToEndOfStatement();
   9123       return false;
   9124     }
   9125 
   9126     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
   9127     if (!OC) {
   9128       Error(OpcodeLoc, "opcode value must be a constant");
   9129       Parser.eatToEndOfStatement();
   9130       return false;
   9131     }
   9132 
   9133     const int64_t Opcode = OC->getValue();
   9134     if (Opcode & ~0xff) {
   9135       Error(OpcodeLoc, "invalid opcode");
   9136       Parser.eatToEndOfStatement();
   9137       return false;
   9138     }
   9139 
   9140     Opcodes.push_back(uint8_t(Opcode));
   9141 
   9142     if (getLexer().is(AsmToken::EndOfStatement))
   9143       break;
   9144 
   9145     if (getLexer().isNot(AsmToken::Comma)) {
   9146       Error(getLexer().getLoc(), "unexpected token in directive");
   9147       Parser.eatToEndOfStatement();
   9148       return false;
   9149     }
   9150 
   9151     Parser.Lex();
   9152   }
   9153 
   9154   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
   9155 
   9156   Parser.Lex();
   9157   return false;
   9158 }
   9159 
   9160 /// parseDirectiveTLSDescSeq
   9161 ///   ::= .tlsdescseq tls-variable
   9162 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
   9163   if (getLexer().isNot(AsmToken::Identifier)) {
   9164     TokError("expected variable after '.tlsdescseq' directive");
   9165     Parser.eatToEndOfStatement();
   9166     return false;
   9167   }
   9168 
   9169   const MCSymbolRefExpr *SRE =
   9170     MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
   9171                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
   9172   Lex();
   9173 
   9174   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   9175     Error(Parser.getTok().getLoc(), "unexpected token");
   9176     Parser.eatToEndOfStatement();
   9177     return false;
   9178   }
   9179 
   9180   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
   9181   return false;
   9182 }
   9183 
   9184 /// parseDirectiveMovSP
   9185 ///  ::= .movsp reg [, #offset]
   9186 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
   9187   if (!UC.hasFnStart()) {
   9188     Parser.eatToEndOfStatement();
   9189     Error(L, ".fnstart must precede .movsp directives");
   9190     return false;
   9191   }
   9192   if (UC.getFPReg() != ARM::SP) {
   9193     Parser.eatToEndOfStatement();
   9194     Error(L, "unexpected .movsp directive");
   9195     return false;
   9196   }
   9197 
   9198   SMLoc SPRegLoc = Parser.getTok().getLoc();
   9199   int SPReg = tryParseRegister();
   9200   if (SPReg == -1) {
   9201     Parser.eatToEndOfStatement();
   9202     Error(SPRegLoc, "register expected");
   9203     return false;
   9204   }
   9205 
   9206   if (SPReg == ARM::SP || SPReg == ARM::PC) {
   9207     Parser.eatToEndOfStatement();
   9208     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
   9209     return false;
   9210   }
   9211 
   9212   int64_t Offset = 0;
   9213   if (Parser.getTok().is(AsmToken::Comma)) {
   9214     Parser.Lex();
   9215 
   9216     if (Parser.getTok().isNot(AsmToken::Hash)) {
   9217       Error(Parser.getTok().getLoc(), "expected #constant");
   9218       Parser.eatToEndOfStatement();
   9219       return false;
   9220     }
   9221     Parser.Lex();
   9222 
   9223     const MCExpr *OffsetExpr;
   9224     SMLoc OffsetLoc = Parser.getTok().getLoc();
   9225     if (Parser.parseExpression(OffsetExpr)) {
   9226       Parser.eatToEndOfStatement();
   9227       Error(OffsetLoc, "malformed offset expression");
   9228       return false;
   9229     }
   9230 
   9231     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
   9232     if (!CE) {
   9233       Parser.eatToEndOfStatement();
   9234       Error(OffsetLoc, "offset must be an immediate constant");
   9235       return false;
   9236     }
   9237 
   9238     Offset = CE->getValue();
   9239   }
   9240 
   9241   getTargetStreamer().emitMovSP(SPReg, Offset);
   9242   UC.saveFPReg(SPReg);
   9243 
   9244   return false;
   9245 }
   9246 
   9247 /// parseDirectiveObjectArch
   9248 ///   ::= .object_arch name
   9249 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
   9250   if (getLexer().isNot(AsmToken::Identifier)) {
   9251     Error(getLexer().getLoc(), "unexpected token");
   9252     Parser.eatToEndOfStatement();
   9253     return false;
   9254   }
   9255 
   9256   StringRef Arch = Parser.getTok().getString();
   9257   SMLoc ArchLoc = Parser.getTok().getLoc();
   9258   getLexer().Lex();
   9259 
   9260   unsigned ID = StringSwitch<unsigned>(Arch)
   9261 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
   9262     .Case(NAME, ARM::ID)
   9263 #define ARM_ARCH_ALIAS(NAME, ID) \
   9264     .Case(NAME, ARM::ID)
   9265 #include "MCTargetDesc/ARMArchName.def"
   9266 #undef ARM_ARCH_NAME
   9267 #undef ARM_ARCH_ALIAS
   9268     .Default(ARM::INVALID_ARCH);
   9269 
   9270   if (ID == ARM::INVALID_ARCH) {
   9271     Error(ArchLoc, "unknown architecture '" + Arch + "'");
   9272     Parser.eatToEndOfStatement();
   9273     return false;
   9274   }
   9275 
   9276   getTargetStreamer().emitObjectArch(ID);
   9277 
   9278   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   9279     Error(getLexer().getLoc(), "unexpected token");
   9280     Parser.eatToEndOfStatement();
   9281   }
   9282 
   9283   return false;
   9284 }
   9285 
   9286 /// parseDirectiveAlign
   9287 ///   ::= .align
   9288 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
   9289   // NOTE: if this is not the end of the statement, fall back to the target
   9290   // agnostic handling for this directive which will correctly handle this.
   9291   if (getLexer().isNot(AsmToken::EndOfStatement))
   9292     return true;
   9293 
   9294   // '.align' is target specifically handled to mean 2**2 byte alignment.
   9295   if (getStreamer().getCurrentSection().first->UseCodeAlign())
   9296     getStreamer().EmitCodeAlignment(4, 0);
   9297   else
   9298     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
   9299 
   9300   return false;
   9301 }
   9302 
   9303 /// parseDirectiveThumbSet
   9304 ///  ::= .thumb_set name, value
   9305 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
   9306   StringRef Name;
   9307   if (Parser.parseIdentifier(Name)) {
   9308     TokError("expected identifier after '.thumb_set'");
   9309     Parser.eatToEndOfStatement();
   9310     return false;
   9311   }
   9312 
   9313   if (getLexer().isNot(AsmToken::Comma)) {
   9314     TokError("expected comma after name '" + Name + "'");
   9315     Parser.eatToEndOfStatement();
   9316     return false;
   9317   }
   9318   Lex();
   9319 
   9320   const MCExpr *Value;
   9321   if (Parser.parseExpression(Value)) {
   9322     TokError("missing expression");
   9323     Parser.eatToEndOfStatement();
   9324     return false;
   9325   }
   9326 
   9327   if (getLexer().isNot(AsmToken::EndOfStatement)) {
   9328     TokError("unexpected token");
   9329     Parser.eatToEndOfStatement();
   9330     return false;
   9331   }
   9332   Lex();
   9333 
   9334   MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
   9335   getTargetStreamer().emitThumbSet(Alias, Value);
   9336   return false;
   9337 }
   9338 
   9339 /// Force static initialization.
   9340 extern "C" void LLVMInitializeARMAsmParser() {
   9341   RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
   9342   RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
   9343   RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
   9344   RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
   9345 }
   9346 
   9347 #define GET_REGISTER_MATCHER
   9348 #define GET_SUBTARGET_FEATURE_NAME
   9349 #define GET_MATCHER_IMPLEMENTATION
   9350 #include "ARMGenAsmMatcher.inc"
   9351 
   9352 static const struct ExtMapEntry {
   9353   const char *Extension;
   9354   const unsigned ArchCheck;
   9355   const uint64_t Features;
   9356 } Extensions[] = {
   9357   { "crc", Feature_HasV8, ARM::FeatureCRC },
   9358   { "crypto",  Feature_HasV8,
   9359     ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
   9360   { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
   9361   { "idiv", Feature_HasV7 | Feature_IsNotMClass,
   9362     ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
   9363   // FIXME: iWMMXT not supported
   9364   { "iwmmxt", Feature_None, 0 },
   9365   // FIXME: iWMMXT2 not supported
   9366   { "iwmmxt2", Feature_None, 0 },
   9367   // FIXME: Maverick not supported
   9368   { "maverick", Feature_None, 0 },
   9369   { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
   9370   // FIXME: ARMv6-m OS Extensions feature not checked
   9371   { "os", Feature_None, 0 },
   9372   // FIXME: Also available in ARMv6-K
   9373   { "sec", Feature_HasV7, ARM::FeatureTrustZone },
   9374   { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
   9375   // FIXME: Only available in A-class, isel not predicated
   9376   { "virt", Feature_HasV7, ARM::FeatureVirtualization },
   9377   // FIXME: xscale not supported
   9378   { "xscale", Feature_None, 0 },
   9379 };
   9380 
   9381 /// parseDirectiveArchExtension
   9382 ///   ::= .arch_extension [no]feature
   9383 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
   9384   if (getLexer().isNot(AsmToken::Identifier)) {
   9385     Error(getLexer().getLoc(), "unexpected token");
   9386     Parser.eatToEndOfStatement();
   9387     return false;
   9388   }
   9389 
   9390   StringRef Extension = Parser.getTok().getString();
   9391   SMLoc ExtLoc = Parser.getTok().getLoc();
   9392   getLexer().Lex();
   9393 
   9394   bool EnableFeature = true;
   9395   if (Extension.startswith_lower("no")) {
   9396     EnableFeature = false;
   9397     Extension = Extension.substr(2);
   9398   }
   9399 
   9400   for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
   9401     if (Extensions[EI].Extension != Extension)
   9402       continue;
   9403 
   9404     unsigned FB = getAvailableFeatures();
   9405     if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
   9406       Error(ExtLoc, "architectural extension '" + Extension + "' is not "
   9407             "allowed for the current base architecture");
   9408       return false;
   9409     }
   9410 
   9411     if (!Extensions[EI].Features)
   9412       report_fatal_error("unsupported architectural extension: " + Extension);
   9413 
   9414     if (EnableFeature)
   9415       FB |= ComputeAvailableFeatures(Extensions[EI].Features);
   9416     else
   9417       FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
   9418 
   9419     setAvailableFeatures(FB);
   9420     return false;
   9421   }
   9422 
   9423   Error(ExtLoc, "unknown architectural extension: " + Extension);
   9424   Parser.eatToEndOfStatement();
   9425   return false;
   9426 }
   9427 
   9428 // Define this matcher function after the auto-generated include so we
   9429 // have the match class enum definitions.
   9430 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
   9431                                                   unsigned Kind) {
   9432   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
   9433   // If the kind is a token for a literal immediate, check if our asm
   9434   // operand matches. This is for InstAliases which have a fixed-value
   9435   // immediate in the syntax.
   9436   switch (Kind) {
   9437   default: break;
   9438   case MCK__35_0:
   9439     if (Op.isImm())
   9440       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
   9441         if (CE->getValue() == 0)
   9442           return Match_Success;
   9443     break;
   9444   case MCK_ARMSOImm:
   9445     if (Op.isImm()) {
   9446       const MCExpr *SOExpr = Op.getImm();
   9447       int64_t Value;
   9448       if (!SOExpr->EvaluateAsAbsolute(Value))
   9449         return Match_Success;
   9450       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
   9451              "expression value must be representable in 32 bits");
   9452     }
   9453     break;
   9454   case MCK_GPRPair:
   9455     if (Op.isReg() &&
   9456         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
   9457       return Match_Success;
   9458     break;
   9459   }
   9460   return Match_InvalidOperand;
   9461 }
   9462