1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Base ARM implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARM.h" 15 #include "ARMBaseInstrInfo.h" 16 #include "ARMBaseRegisterInfo.h" 17 #include "ARMConstantPoolValue.h" 18 #include "ARMFeatures.h" 19 #include "ARMHazardRecognizer.h" 20 #include "ARMMachineFunctionInfo.h" 21 #include "MCTargetDesc/ARMAddressingModes.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/LiveVariables.h" 24 #include "llvm/CodeGen/MachineConstantPool.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineJumpTableInfo.h" 28 #include "llvm/CodeGen/MachineMemOperand.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/SelectionDAGNodes.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/GlobalValue.h" 34 #include "llvm/MC/MCAsmInfo.h" 35 #include "llvm/MC/MCExpr.h" 36 #include "llvm/Support/BranchProbability.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/ErrorHandling.h" 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "arm-instrinfo" 44 45 #define GET_INSTRINFO_CTOR_DTOR 46 #include "ARMGenInstrInfo.inc" 47 48 static cl::opt<bool> 49 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, 50 cl::desc("Enable ARM 2-addr to 3-addr conv")); 51 52 static cl::opt<bool> 53 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), 54 cl::desc("Widen ARM vmovs to vmovd when possible")); 55 56 static cl::opt<unsigned> 57 SwiftPartialUpdateClearance("swift-partial-update-clearance", 58 cl::Hidden, cl::init(12), 59 cl::desc("Clearance before partial register updates")); 60 61 /// ARM_MLxEntry - Record information about MLA / MLS instructions. 62 struct ARM_MLxEntry { 63 uint16_t MLxOpc; // MLA / MLS opcode 64 uint16_t MulOpc; // Expanded multiplication opcode 65 uint16_t AddSubOpc; // Expanded add / sub opcode 66 bool NegAcc; // True if the acc is negated before the add / sub. 67 bool HasLane; // True if instruction has an extra "lane" operand. 68 }; 69 70 static const ARM_MLxEntry ARM_MLxTable[] = { 71 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane 72 // fp scalar ops 73 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false }, 74 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }, 75 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false }, 76 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false }, 77 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false }, 78 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false }, 79 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false }, 80 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false }, 81 82 // fp SIMD ops 83 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false }, 84 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false }, 85 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false }, 86 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false }, 87 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true }, 88 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true }, 89 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true }, 90 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true }, 91 }; 92 93 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) 94 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 95 Subtarget(STI) { 96 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { 97 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) 98 assert(false && "Duplicated entries?"); 99 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); 100 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc); 101 } 102 } 103 104 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl 105 // currently defaults to no prepass hazard recognizer. 106 ScheduleHazardRecognizer * 107 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 108 const ScheduleDAG *DAG) const { 109 if (usePreRAHazardRecognizer()) { 110 const InstrItineraryData *II = 111 &static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData(); 112 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); 113 } 114 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG); 115 } 116 117 ScheduleHazardRecognizer *ARMBaseInstrInfo:: 118 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 119 const ScheduleDAG *DAG) const { 120 if (Subtarget.isThumb2() || Subtarget.hasVFP2()) 121 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG); 122 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG); 123 } 124 125 MachineInstr * 126 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 127 MachineBasicBlock::iterator &MBBI, 128 LiveVariables *LV) const { 129 // FIXME: Thumb2 support. 130 131 if (!EnableARM3Addr) 132 return nullptr; 133 134 MachineInstr *MI = MBBI; 135 MachineFunction &MF = *MI->getParent()->getParent(); 136 uint64_t TSFlags = MI->getDesc().TSFlags; 137 bool isPre = false; 138 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { 139 default: return nullptr; 140 case ARMII::IndexModePre: 141 isPre = true; 142 break; 143 case ARMII::IndexModePost: 144 break; 145 } 146 147 // Try splitting an indexed load/store to an un-indexed one plus an add/sub 148 // operation. 149 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); 150 if (MemOpc == 0) 151 return nullptr; 152 153 MachineInstr *UpdateMI = nullptr; 154 MachineInstr *MemMI = nullptr; 155 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 156 const MCInstrDesc &MCID = MI->getDesc(); 157 unsigned NumOps = MCID.getNumOperands(); 158 bool isLoad = !MI->mayStore(); 159 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); 160 const MachineOperand &Base = MI->getOperand(2); 161 const MachineOperand &Offset = MI->getOperand(NumOps-3); 162 unsigned WBReg = WB.getReg(); 163 unsigned BaseReg = Base.getReg(); 164 unsigned OffReg = Offset.getReg(); 165 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); 166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); 167 switch (AddrMode) { 168 default: llvm_unreachable("Unknown indexed op!"); 169 case ARMII::AddrMode2: { 170 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 171 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 172 if (OffReg == 0) { 173 if (ARM_AM::getSOImmVal(Amt) == -1) 174 // Can't encode it in a so_imm operand. This transformation will 175 // add more than 1 instruction. Abandon! 176 return nullptr; 177 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 178 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 179 .addReg(BaseReg).addImm(Amt) 180 .addImm(Pred).addReg(0).addReg(0); 181 } else if (Amt != 0) { 182 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 183 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 184 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 185 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) 186 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 187 .addImm(Pred).addReg(0).addReg(0); 188 } else 189 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 190 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 191 .addReg(BaseReg).addReg(OffReg) 192 .addImm(Pred).addReg(0).addReg(0); 193 break; 194 } 195 case ARMII::AddrMode3 : { 196 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 197 unsigned Amt = ARM_AM::getAM3Offset(OffImm); 198 if (OffReg == 0) 199 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. 200 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 201 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) 202 .addReg(BaseReg).addImm(Amt) 203 .addImm(Pred).addReg(0).addReg(0); 204 else 205 UpdateMI = BuildMI(MF, MI->getDebugLoc(), 206 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) 207 .addReg(BaseReg).addReg(OffReg) 208 .addImm(Pred).addReg(0).addReg(0); 209 break; 210 } 211 } 212 213 std::vector<MachineInstr*> NewMIs; 214 if (isPre) { 215 if (isLoad) 216 MemMI = BuildMI(MF, MI->getDebugLoc(), 217 get(MemOpc), MI->getOperand(0).getReg()) 218 .addReg(WBReg).addImm(0).addImm(Pred); 219 else 220 MemMI = BuildMI(MF, MI->getDebugLoc(), 221 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 222 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); 223 NewMIs.push_back(MemMI); 224 NewMIs.push_back(UpdateMI); 225 } else { 226 if (isLoad) 227 MemMI = BuildMI(MF, MI->getDebugLoc(), 228 get(MemOpc), MI->getOperand(0).getReg()) 229 .addReg(BaseReg).addImm(0).addImm(Pred); 230 else 231 MemMI = BuildMI(MF, MI->getDebugLoc(), 232 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 233 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); 234 if (WB.isDead()) 235 UpdateMI->getOperand(0).setIsDead(); 236 NewMIs.push_back(UpdateMI); 237 NewMIs.push_back(MemMI); 238 } 239 240 // Transfer LiveVariables states, kill / dead info. 241 if (LV) { 242 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 243 MachineOperand &MO = MI->getOperand(i); 244 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 245 unsigned Reg = MO.getReg(); 246 247 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); 248 if (MO.isDef()) { 249 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; 250 if (MO.isDead()) 251 LV->addVirtualRegisterDead(Reg, NewMI); 252 } 253 if (MO.isUse() && MO.isKill()) { 254 for (unsigned j = 0; j < 2; ++j) { 255 // Look at the two new MI's in reverse order. 256 MachineInstr *NewMI = NewMIs[j]; 257 if (!NewMI->readsRegister(Reg)) 258 continue; 259 LV->addVirtualRegisterKilled(Reg, NewMI); 260 if (VI.removeKill(MI)) 261 VI.Kills.push_back(NewMI); 262 break; 263 } 264 } 265 } 266 } 267 } 268 269 MFI->insert(MBBI, NewMIs[1]); 270 MFI->insert(MBBI, NewMIs[0]); 271 return NewMIs[0]; 272 } 273 274 // Branch analysis. 275 bool 276 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 277 MachineBasicBlock *&FBB, 278 SmallVectorImpl<MachineOperand> &Cond, 279 bool AllowModify) const { 280 TBB = nullptr; 281 FBB = nullptr; 282 283 MachineBasicBlock::iterator I = MBB.end(); 284 if (I == MBB.begin()) 285 return false; // Empty blocks are easy. 286 --I; 287 288 // Walk backwards from the end of the basic block until the branch is 289 // analyzed or we give up. 290 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) { 291 292 // Flag to be raised on unanalyzeable instructions. This is useful in cases 293 // where we want to clean up on the end of the basic block before we bail 294 // out. 295 bool CantAnalyze = false; 296 297 // Skip over DEBUG values and predicated nonterminators. 298 while (I->isDebugValue() || !I->isTerminator()) { 299 if (I == MBB.begin()) 300 return false; 301 --I; 302 } 303 304 if (isIndirectBranchOpcode(I->getOpcode()) || 305 isJumpTableBranchOpcode(I->getOpcode())) { 306 // Indirect branches and jump tables can't be analyzed, but we still want 307 // to clean up any instructions at the tail of the basic block. 308 CantAnalyze = true; 309 } else if (isUncondBranchOpcode(I->getOpcode())) { 310 TBB = I->getOperand(0).getMBB(); 311 } else if (isCondBranchOpcode(I->getOpcode())) { 312 // Bail out if we encounter multiple conditional branches. 313 if (!Cond.empty()) 314 return true; 315 316 assert(!FBB && "FBB should have been null."); 317 FBB = TBB; 318 TBB = I->getOperand(0).getMBB(); 319 Cond.push_back(I->getOperand(1)); 320 Cond.push_back(I->getOperand(2)); 321 } else if (I->isReturn()) { 322 // Returns can't be analyzed, but we should run cleanup. 323 CantAnalyze = !isPredicated(I); 324 } else { 325 // We encountered other unrecognized terminator. Bail out immediately. 326 return true; 327 } 328 329 // Cleanup code - to be run for unpredicated unconditional branches and 330 // returns. 331 if (!isPredicated(I) && 332 (isUncondBranchOpcode(I->getOpcode()) || 333 isIndirectBranchOpcode(I->getOpcode()) || 334 isJumpTableBranchOpcode(I->getOpcode()) || 335 I->isReturn())) { 336 // Forget any previous condition branch information - it no longer applies. 337 Cond.clear(); 338 FBB = nullptr; 339 340 // If we can modify the function, delete everything below this 341 // unconditional branch. 342 if (AllowModify) { 343 MachineBasicBlock::iterator DI = std::next(I); 344 while (DI != MBB.end()) { 345 MachineInstr *InstToDelete = DI; 346 ++DI; 347 InstToDelete->eraseFromParent(); 348 } 349 } 350 } 351 352 if (CantAnalyze) 353 return true; 354 355 if (I == MBB.begin()) 356 return false; 357 358 --I; 359 } 360 361 // We made it past the terminators without bailing out - we must have 362 // analyzed this branch successfully. 363 return false; 364 } 365 366 367 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 368 MachineBasicBlock::iterator I = MBB.end(); 369 if (I == MBB.begin()) return 0; 370 --I; 371 while (I->isDebugValue()) { 372 if (I == MBB.begin()) 373 return 0; 374 --I; 375 } 376 if (!isUncondBranchOpcode(I->getOpcode()) && 377 !isCondBranchOpcode(I->getOpcode())) 378 return 0; 379 380 // Remove the branch. 381 I->eraseFromParent(); 382 383 I = MBB.end(); 384 385 if (I == MBB.begin()) return 1; 386 --I; 387 if (!isCondBranchOpcode(I->getOpcode())) 388 return 1; 389 390 // Remove the branch. 391 I->eraseFromParent(); 392 return 2; 393 } 394 395 unsigned 396 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 397 MachineBasicBlock *FBB, 398 const SmallVectorImpl<MachineOperand> &Cond, 399 DebugLoc DL) const { 400 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); 401 int BOpc = !AFI->isThumbFunction() 402 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); 403 int BccOpc = !AFI->isThumbFunction() 404 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); 405 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); 406 407 // Shouldn't be a fall through. 408 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 409 assert((Cond.size() == 2 || Cond.size() == 0) && 410 "ARM branch conditions have two components!"); 411 412 if (!FBB) { 413 if (Cond.empty()) { // Unconditional branch? 414 if (isThumb) 415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 416 else 417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 418 } else 419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 420 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 421 return 1; 422 } 423 424 // Two-way conditional branch. 425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) 426 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); 427 if (isThumb) 428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0); 429 else 430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 431 return 2; 432 } 433 434 bool ARMBaseInstrInfo:: 435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); 437 Cond[0].setImm(ARMCC::getOppositeCondition(CC)); 438 return false; 439 } 440 441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { 442 if (MI->isBundle()) { 443 MachineBasicBlock::const_instr_iterator I = MI; 444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 445 while (++I != E && I->isInsideBundle()) { 446 int PIdx = I->findFirstPredOperandIdx(); 447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) 448 return true; 449 } 450 return false; 451 } 452 453 int PIdx = MI->findFirstPredOperandIdx(); 454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL; 455 } 456 457 bool ARMBaseInstrInfo:: 458 PredicateInstruction(MachineInstr *MI, 459 const SmallVectorImpl<MachineOperand> &Pred) const { 460 unsigned Opc = MI->getOpcode(); 461 if (isUncondBranchOpcode(Opc)) { 462 MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); 463 MachineInstrBuilder(*MI->getParent()->getParent(), MI) 464 .addImm(Pred[0].getImm()) 465 .addReg(Pred[1].getReg()); 466 return true; 467 } 468 469 int PIdx = MI->findFirstPredOperandIdx(); 470 if (PIdx != -1) { 471 MachineOperand &PMO = MI->getOperand(PIdx); 472 PMO.setImm(Pred[0].getImm()); 473 MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); 474 return true; 475 } 476 return false; 477 } 478 479 bool ARMBaseInstrInfo:: 480 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 481 const SmallVectorImpl<MachineOperand> &Pred2) const { 482 if (Pred1.size() > 2 || Pred2.size() > 2) 483 return false; 484 485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); 486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); 487 if (CC1 == CC2) 488 return true; 489 490 switch (CC1) { 491 default: 492 return false; 493 case ARMCC::AL: 494 return true; 495 case ARMCC::HS: 496 return CC2 == ARMCC::HI; 497 case ARMCC::LS: 498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; 499 case ARMCC::GE: 500 return CC2 == ARMCC::GT; 501 case ARMCC::LE: 502 return CC2 == ARMCC::LT; 503 } 504 } 505 506 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, 507 std::vector<MachineOperand> &Pred) const { 508 bool Found = false; 509 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 510 const MachineOperand &MO = MI->getOperand(i); 511 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || 512 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { 513 Pred.push_back(MO); 514 Found = true; 515 } 516 } 517 518 return Found; 519 } 520 521 /// isPredicable - Return true if the specified instruction can be predicated. 522 /// By default, this returns true for every instruction with a 523 /// PredicateOperand. 524 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { 525 if (!MI->isPredicable()) 526 return false; 527 528 ARMFunctionInfo *AFI = 529 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 530 531 if (AFI->isThumb2Function()) { 532 if (getSubtarget().restrictIT()) 533 return isV8EligibleForIT(MI); 534 } else { // non-Thumb 535 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) 536 return false; 537 } 538 539 return true; 540 } 541 542 namespace llvm { 543 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) { 544 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 545 const MachineOperand &MO = MI->getOperand(i); 546 if (!MO.isReg() || MO.isUndef() || MO.isUse()) 547 continue; 548 if (MO.getReg() != ARM::CPSR) 549 continue; 550 if (!MO.isDead()) 551 return false; 552 } 553 // all definitions of CPSR are dead 554 return true; 555 } 556 } 557 558 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing. 559 LLVM_ATTRIBUTE_NOINLINE 560 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 561 unsigned JTI); 562 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, 563 unsigned JTI) { 564 assert(JTI < JT.size()); 565 return JT[JTI].MBBs.size(); 566 } 567 568 /// GetInstSize - Return the size of the specified MachineInstr. 569 /// 570 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 571 const MachineBasicBlock &MBB = *MI->getParent(); 572 const MachineFunction *MF = MBB.getParent(); 573 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); 574 575 const MCInstrDesc &MCID = MI->getDesc(); 576 if (MCID.getSize()) 577 return MCID.getSize(); 578 579 // If this machine instr is an inline asm, measure it. 580 if (MI->getOpcode() == ARM::INLINEASM) 581 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); 582 unsigned Opc = MI->getOpcode(); 583 switch (Opc) { 584 default: 585 // pseudo-instruction sizes are zero. 586 return 0; 587 case TargetOpcode::BUNDLE: 588 return getInstBundleLength(MI); 589 case ARM::MOVi16_ga_pcrel: 590 case ARM::MOVTi16_ga_pcrel: 591 case ARM::t2MOVi16_ga_pcrel: 592 case ARM::t2MOVTi16_ga_pcrel: 593 return 4; 594 case ARM::MOVi32imm: 595 case ARM::t2MOVi32imm: 596 return 8; 597 case ARM::CONSTPOOL_ENTRY: 598 // If this machine instr is a constant pool entry, its size is recorded as 599 // operand #2. 600 return MI->getOperand(2).getImm(); 601 case ARM::Int_eh_sjlj_longjmp: 602 return 16; 603 case ARM::tInt_eh_sjlj_longjmp: 604 return 10; 605 case ARM::Int_eh_sjlj_setjmp: 606 case ARM::Int_eh_sjlj_setjmp_nofp: 607 return 20; 608 case ARM::tInt_eh_sjlj_setjmp: 609 case ARM::t2Int_eh_sjlj_setjmp: 610 case ARM::t2Int_eh_sjlj_setjmp_nofp: 611 return 12; 612 case ARM::BR_JTr: 613 case ARM::BR_JTm: 614 case ARM::BR_JTadd: 615 case ARM::tBR_JTr: 616 case ARM::t2BR_JT: 617 case ARM::t2TBB_JT: 618 case ARM::t2TBH_JT: { 619 // These are jumptable branches, i.e. a branch followed by an inlined 620 // jumptable. The size is 4 + 4 * number of entries. For TBB, each 621 // entry is one byte; TBH two byte each. 622 unsigned EntrySize = (Opc == ARM::t2TBB_JT) 623 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); 624 unsigned NumOps = MCID.getNumOperands(); 625 MachineOperand JTOP = 626 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2)); 627 unsigned JTI = JTOP.getIndex(); 628 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); 629 assert(MJTI != nullptr); 630 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); 631 assert(JTI < JT.size()); 632 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte 633 // 4 aligned. The assembler / linker may add 2 byte padding just before 634 // the JT entries. The size does not include this padding; the 635 // constant islands pass does separate bookkeeping for it. 636 // FIXME: If we know the size of the function is less than (1 << 16) *2 637 // bytes, we can use 16-bit entries instead. Then there won't be an 638 // alignment issue. 639 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; 640 unsigned NumEntries = getNumJTEntries(JT, JTI); 641 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)) 642 // Make sure the instruction that follows TBB is 2-byte aligned. 643 // FIXME: Constant island pass should insert an "ALIGN" instruction 644 // instead. 645 ++NumEntries; 646 return NumEntries * EntrySize + InstSize; 647 } 648 } 649 } 650 651 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const { 652 unsigned Size = 0; 653 MachineBasicBlock::const_instr_iterator I = MI; 654 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 655 while (++I != E && I->isInsideBundle()) { 656 assert(!I->isBundle() && "No nested bundle!"); 657 Size += GetInstSizeInBytes(&*I); 658 } 659 return Size; 660 } 661 662 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 663 MachineBasicBlock::iterator I, DebugLoc DL, 664 unsigned DestReg, unsigned SrcReg, 665 bool KillSrc) const { 666 bool GPRDest = ARM::GPRRegClass.contains(DestReg); 667 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); 668 669 if (GPRDest && GPRSrc) { 670 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) 671 .addReg(SrcReg, getKillRegState(KillSrc)))); 672 return; 673 } 674 675 bool SPRDest = ARM::SPRRegClass.contains(DestReg); 676 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); 677 678 unsigned Opc = 0; 679 if (SPRDest && SPRSrc) 680 Opc = ARM::VMOVS; 681 else if (GPRDest && SPRSrc) 682 Opc = ARM::VMOVRS; 683 else if (SPRDest && GPRSrc) 684 Opc = ARM::VMOVSR; 685 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) 686 Opc = ARM::VMOVD; 687 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) 688 Opc = ARM::VORRq; 689 690 if (Opc) { 691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 692 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 693 if (Opc == ARM::VORRq) 694 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 695 AddDefaultPred(MIB); 696 return; 697 } 698 699 // Handle register classes that require multiple instructions. 700 unsigned BeginIdx = 0; 701 unsigned SubRegs = 0; 702 int Spacing = 1; 703 704 // Use VORRq when possible. 705 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { 706 Opc = ARM::VORRq; 707 BeginIdx = ARM::qsub_0; 708 SubRegs = 2; 709 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { 710 Opc = ARM::VORRq; 711 BeginIdx = ARM::qsub_0; 712 SubRegs = 4; 713 // Fall back to VMOVD. 714 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { 715 Opc = ARM::VMOVD; 716 BeginIdx = ARM::dsub_0; 717 SubRegs = 2; 718 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { 719 Opc = ARM::VMOVD; 720 BeginIdx = ARM::dsub_0; 721 SubRegs = 3; 722 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { 723 Opc = ARM::VMOVD; 724 BeginIdx = ARM::dsub_0; 725 SubRegs = 4; 726 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { 727 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; 728 BeginIdx = ARM::gsub_0; 729 SubRegs = 2; 730 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { 731 Opc = ARM::VMOVD; 732 BeginIdx = ARM::dsub_0; 733 SubRegs = 2; 734 Spacing = 2; 735 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { 736 Opc = ARM::VMOVD; 737 BeginIdx = ARM::dsub_0; 738 SubRegs = 3; 739 Spacing = 2; 740 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { 741 Opc = ARM::VMOVD; 742 BeginIdx = ARM::dsub_0; 743 SubRegs = 4; 744 Spacing = 2; 745 } 746 747 assert(Opc && "Impossible reg-to-reg copy"); 748 749 const TargetRegisterInfo *TRI = &getRegisterInfo(); 750 MachineInstrBuilder Mov; 751 752 // Copy register tuples backward when the first Dest reg overlaps with SrcReg. 753 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { 754 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing); 755 Spacing = -Spacing; 756 } 757 #ifndef NDEBUG 758 SmallSet<unsigned, 4> DstRegs; 759 #endif 760 for (unsigned i = 0; i != SubRegs; ++i) { 761 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); 762 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); 763 assert(Dst && Src && "Bad sub-register"); 764 #ifndef NDEBUG 765 assert(!DstRegs.count(Src) && "destructive vector copy"); 766 DstRegs.insert(Dst); 767 #endif 768 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); 769 // VORR takes two source operands. 770 if (Opc == ARM::VORRq) 771 Mov.addReg(Src); 772 Mov = AddDefaultPred(Mov); 773 // MOVr can set CC. 774 if (Opc == ARM::MOVr) 775 Mov = AddDefaultCC(Mov); 776 } 777 // Add implicit super-register defs and kills to the last instruction. 778 Mov->addRegisterDefined(DestReg, TRI); 779 if (KillSrc) 780 Mov->addRegisterKilled(SrcReg, TRI); 781 } 782 783 const MachineInstrBuilder & 784 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 785 unsigned SubIdx, unsigned State, 786 const TargetRegisterInfo *TRI) const { 787 if (!SubIdx) 788 return MIB.addReg(Reg, State); 789 790 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 791 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 792 return MIB.addReg(Reg, State, SubIdx); 793 } 794 795 void ARMBaseInstrInfo:: 796 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 797 unsigned SrcReg, bool isKill, int FI, 798 const TargetRegisterClass *RC, 799 const TargetRegisterInfo *TRI) const { 800 DebugLoc DL; 801 if (I != MBB.end()) DL = I->getDebugLoc(); 802 MachineFunction &MF = *MBB.getParent(); 803 MachineFrameInfo &MFI = *MF.getFrameInfo(); 804 unsigned Align = MFI.getObjectAlignment(FI); 805 806 MachineMemOperand *MMO = 807 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 808 MachineMemOperand::MOStore, 809 MFI.getObjectSize(FI), 810 Align); 811 812 switch (RC->getSize()) { 813 case 4: 814 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 815 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12)) 816 .addReg(SrcReg, getKillRegState(isKill)) 817 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 818 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 819 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS)) 820 .addReg(SrcReg, getKillRegState(isKill)) 821 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 822 } else 823 llvm_unreachable("Unknown reg class!"); 824 break; 825 case 8: 826 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 827 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD)) 828 .addReg(SrcReg, getKillRegState(isKill)) 829 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 830 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 831 if (Subtarget.hasV5TEOps()) { 832 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); 833 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 834 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 835 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 836 837 AddDefaultPred(MIB); 838 } else { 839 // Fallback to STM instruction, which has existed since the dawn of 840 // time. 841 MachineInstrBuilder MIB = 842 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA)) 843 .addFrameIndex(FI).addMemOperand(MMO)); 844 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); 845 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); 846 } 847 } else 848 llvm_unreachable("Unknown reg class!"); 849 break; 850 case 16: 851 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 852 // Use aligned spills if the stack can be realigned. 853 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 854 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64)) 855 .addFrameIndex(FI).addImm(16) 856 .addReg(SrcReg, getKillRegState(isKill)) 857 .addMemOperand(MMO)); 858 } else { 859 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA)) 860 .addReg(SrcReg, getKillRegState(isKill)) 861 .addFrameIndex(FI) 862 .addMemOperand(MMO)); 863 } 864 } else 865 llvm_unreachable("Unknown reg class!"); 866 break; 867 case 24: 868 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 869 // Use aligned spills if the stack can be realigned. 870 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 871 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo)) 872 .addFrameIndex(FI).addImm(16) 873 .addReg(SrcReg, getKillRegState(isKill)) 874 .addMemOperand(MMO)); 875 } else { 876 MachineInstrBuilder MIB = 877 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 878 .addFrameIndex(FI)) 879 .addMemOperand(MMO); 880 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 881 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 882 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 883 } 884 } else 885 llvm_unreachable("Unknown reg class!"); 886 break; 887 case 32: 888 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 889 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 890 // FIXME: It's possible to only store part of the QQ register if the 891 // spilled def has a sub-register index. 892 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo)) 893 .addFrameIndex(FI).addImm(16) 894 .addReg(SrcReg, getKillRegState(isKill)) 895 .addMemOperand(MMO)); 896 } else { 897 MachineInstrBuilder MIB = 898 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 899 .addFrameIndex(FI)) 900 .addMemOperand(MMO); 901 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 902 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 903 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 904 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 905 } 906 } else 907 llvm_unreachable("Unknown reg class!"); 908 break; 909 case 64: 910 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 911 MachineInstrBuilder MIB = 912 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA)) 913 .addFrameIndex(FI)) 914 .addMemOperand(MMO); 915 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); 916 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); 917 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); 918 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); 919 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); 920 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); 921 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); 922 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); 923 } else 924 llvm_unreachable("Unknown reg class!"); 925 break; 926 default: 927 llvm_unreachable("Unknown reg class!"); 928 } 929 } 930 931 unsigned 932 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 933 int &FrameIndex) const { 934 switch (MI->getOpcode()) { 935 default: break; 936 case ARM::STRrs: 937 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. 938 if (MI->getOperand(1).isFI() && 939 MI->getOperand(2).isReg() && 940 MI->getOperand(3).isImm() && 941 MI->getOperand(2).getReg() == 0 && 942 MI->getOperand(3).getImm() == 0) { 943 FrameIndex = MI->getOperand(1).getIndex(); 944 return MI->getOperand(0).getReg(); 945 } 946 break; 947 case ARM::STRi12: 948 case ARM::t2STRi12: 949 case ARM::tSTRspi: 950 case ARM::VSTRD: 951 case ARM::VSTRS: 952 if (MI->getOperand(1).isFI() && 953 MI->getOperand(2).isImm() && 954 MI->getOperand(2).getImm() == 0) { 955 FrameIndex = MI->getOperand(1).getIndex(); 956 return MI->getOperand(0).getReg(); 957 } 958 break; 959 case ARM::VST1q64: 960 case ARM::VST1d64TPseudo: 961 case ARM::VST1d64QPseudo: 962 if (MI->getOperand(0).isFI() && 963 MI->getOperand(2).getSubReg() == 0) { 964 FrameIndex = MI->getOperand(0).getIndex(); 965 return MI->getOperand(2).getReg(); 966 } 967 break; 968 case ARM::VSTMQIA: 969 if (MI->getOperand(1).isFI() && 970 MI->getOperand(0).getSubReg() == 0) { 971 FrameIndex = MI->getOperand(1).getIndex(); 972 return MI->getOperand(0).getReg(); 973 } 974 break; 975 } 976 977 return 0; 978 } 979 980 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 981 int &FrameIndex) const { 982 const MachineMemOperand *Dummy; 983 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex); 984 } 985 986 void ARMBaseInstrInfo:: 987 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 988 unsigned DestReg, int FI, 989 const TargetRegisterClass *RC, 990 const TargetRegisterInfo *TRI) const { 991 DebugLoc DL; 992 if (I != MBB.end()) DL = I->getDebugLoc(); 993 MachineFunction &MF = *MBB.getParent(); 994 MachineFrameInfo &MFI = *MF.getFrameInfo(); 995 unsigned Align = MFI.getObjectAlignment(FI); 996 MachineMemOperand *MMO = 997 MF.getMachineMemOperand( 998 MachinePointerInfo::getFixedStack(FI), 999 MachineMemOperand::MOLoad, 1000 MFI.getObjectSize(FI), 1001 Align); 1002 1003 switch (RC->getSize()) { 1004 case 4: 1005 if (ARM::GPRRegClass.hasSubClassEq(RC)) { 1006 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) 1007 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1008 1009 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { 1010 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) 1011 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1012 } else 1013 llvm_unreachable("Unknown reg class!"); 1014 break; 1015 case 8: 1016 if (ARM::DPRRegClass.hasSubClassEq(RC)) { 1017 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) 1018 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 1019 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { 1020 MachineInstrBuilder MIB; 1021 1022 if (Subtarget.hasV5TEOps()) { 1023 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); 1024 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 1025 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1026 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); 1027 1028 AddDefaultPred(MIB); 1029 } else { 1030 // Fallback to LDM instruction, which has existed since the dawn of 1031 // time. 1032 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) 1033 .addFrameIndex(FI).addMemOperand(MMO)); 1034 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 1035 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1036 } 1037 1038 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1039 MIB.addReg(DestReg, RegState::ImplicitDefine); 1040 } else 1041 llvm_unreachable("Unknown reg class!"); 1042 break; 1043 case 16: 1044 if (ARM::DPairRegClass.hasSubClassEq(RC)) { 1045 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1046 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) 1047 .addFrameIndex(FI).addImm(16) 1048 .addMemOperand(MMO)); 1049 } else { 1050 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) 1051 .addFrameIndex(FI) 1052 .addMemOperand(MMO)); 1053 } 1054 } else 1055 llvm_unreachable("Unknown reg class!"); 1056 break; 1057 case 24: 1058 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { 1059 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1060 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) 1061 .addFrameIndex(FI).addImm(16) 1062 .addMemOperand(MMO)); 1063 } else { 1064 MachineInstrBuilder MIB = 1065 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1066 .addFrameIndex(FI) 1067 .addMemOperand(MMO)); 1068 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1069 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1070 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1071 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1072 MIB.addReg(DestReg, RegState::ImplicitDefine); 1073 } 1074 } else 1075 llvm_unreachable("Unknown reg class!"); 1076 break; 1077 case 32: 1078 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { 1079 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { 1080 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) 1081 .addFrameIndex(FI).addImm(16) 1082 .addMemOperand(MMO)); 1083 } else { 1084 MachineInstrBuilder MIB = 1085 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1086 .addFrameIndex(FI)) 1087 .addMemOperand(MMO); 1088 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1089 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1090 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1091 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1092 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1093 MIB.addReg(DestReg, RegState::ImplicitDefine); 1094 } 1095 } else 1096 llvm_unreachable("Unknown reg class!"); 1097 break; 1098 case 64: 1099 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { 1100 MachineInstrBuilder MIB = 1101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) 1102 .addFrameIndex(FI)) 1103 .addMemOperand(MMO); 1104 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1105 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1106 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1107 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 1108 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); 1109 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); 1110 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); 1111 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); 1112 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) 1113 MIB.addReg(DestReg, RegState::ImplicitDefine); 1114 } else 1115 llvm_unreachable("Unknown reg class!"); 1116 break; 1117 default: 1118 llvm_unreachable("Unknown regclass!"); 1119 } 1120 } 1121 1122 unsigned 1123 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1124 int &FrameIndex) const { 1125 switch (MI->getOpcode()) { 1126 default: break; 1127 case ARM::LDRrs: 1128 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. 1129 if (MI->getOperand(1).isFI() && 1130 MI->getOperand(2).isReg() && 1131 MI->getOperand(3).isImm() && 1132 MI->getOperand(2).getReg() == 0 && 1133 MI->getOperand(3).getImm() == 0) { 1134 FrameIndex = MI->getOperand(1).getIndex(); 1135 return MI->getOperand(0).getReg(); 1136 } 1137 break; 1138 case ARM::LDRi12: 1139 case ARM::t2LDRi12: 1140 case ARM::tLDRspi: 1141 case ARM::VLDRD: 1142 case ARM::VLDRS: 1143 if (MI->getOperand(1).isFI() && 1144 MI->getOperand(2).isImm() && 1145 MI->getOperand(2).getImm() == 0) { 1146 FrameIndex = MI->getOperand(1).getIndex(); 1147 return MI->getOperand(0).getReg(); 1148 } 1149 break; 1150 case ARM::VLD1q64: 1151 case ARM::VLD1d64TPseudo: 1152 case ARM::VLD1d64QPseudo: 1153 if (MI->getOperand(1).isFI() && 1154 MI->getOperand(0).getSubReg() == 0) { 1155 FrameIndex = MI->getOperand(1).getIndex(); 1156 return MI->getOperand(0).getReg(); 1157 } 1158 break; 1159 case ARM::VLDMQIA: 1160 if (MI->getOperand(1).isFI() && 1161 MI->getOperand(0).getSubReg() == 0) { 1162 FrameIndex = MI->getOperand(1).getIndex(); 1163 return MI->getOperand(0).getReg(); 1164 } 1165 break; 1166 } 1167 1168 return 0; 1169 } 1170 1171 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1172 int &FrameIndex) const { 1173 const MachineMemOperand *Dummy; 1174 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1175 } 1176 1177 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{ 1178 // This hook gets to expand COPY instructions before they become 1179 // copyPhysReg() calls. Look for VMOVS instructions that can legally be 1180 // widened to VMOVD. We prefer the VMOVD when possible because it may be 1181 // changed into a VORR that can go down the NEON pipeline. 1182 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15()) 1183 return false; 1184 1185 // Look for a copy between even S-registers. That is where we keep floats 1186 // when using NEON v2f32 instructions for f32 arithmetic. 1187 unsigned DstRegS = MI->getOperand(0).getReg(); 1188 unsigned SrcRegS = MI->getOperand(1).getReg(); 1189 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) 1190 return false; 1191 1192 const TargetRegisterInfo *TRI = &getRegisterInfo(); 1193 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, 1194 &ARM::DPRRegClass); 1195 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, 1196 &ARM::DPRRegClass); 1197 if (!DstRegD || !SrcRegD) 1198 return false; 1199 1200 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only 1201 // legal if the COPY already defines the full DstRegD, and it isn't a 1202 // sub-register insertion. 1203 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI)) 1204 return false; 1205 1206 // A dead copy shouldn't show up here, but reject it just in case. 1207 if (MI->getOperand(0).isDead()) 1208 return false; 1209 1210 // All clear, widen the COPY. 1211 DEBUG(dbgs() << "widening: " << *MI); 1212 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 1213 1214 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg 1215 // or some other super-register. 1216 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD); 1217 if (ImpDefIdx != -1) 1218 MI->RemoveOperand(ImpDefIdx); 1219 1220 // Change the opcode and operands. 1221 MI->setDesc(get(ARM::VMOVD)); 1222 MI->getOperand(0).setReg(DstRegD); 1223 MI->getOperand(1).setReg(SrcRegD); 1224 AddDefaultPred(MIB); 1225 1226 // We are now reading SrcRegD instead of SrcRegS. This may upset the 1227 // register scavenger and machine verifier, so we need to indicate that we 1228 // are reading an undefined value from SrcRegD, but a proper value from 1229 // SrcRegS. 1230 MI->getOperand(1).setIsUndef(); 1231 MIB.addReg(SrcRegS, RegState::Implicit); 1232 1233 // SrcRegD may actually contain an unrelated value in the ssub_1 1234 // sub-register. Don't kill it. Only kill the ssub_0 sub-register. 1235 if (MI->getOperand(1).isKill()) { 1236 MI->getOperand(1).setIsKill(false); 1237 MI->addRegisterKilled(SrcRegS, TRI, true); 1238 } 1239 1240 DEBUG(dbgs() << "replaced by: " << *MI); 1241 return true; 1242 } 1243 1244 /// Create a copy of a const pool value. Update CPI to the new index and return 1245 /// the label UID. 1246 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) { 1247 MachineConstantPool *MCP = MF.getConstantPool(); 1248 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1249 1250 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; 1251 assert(MCPE.isMachineConstantPoolEntry() && 1252 "Expecting a machine constantpool entry!"); 1253 ARMConstantPoolValue *ACPV = 1254 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 1255 1256 unsigned PCLabelId = AFI->createPICLabelUId(); 1257 ARMConstantPoolValue *NewCPV = nullptr; 1258 1259 // FIXME: The below assumes PIC relocation model and that the function 1260 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and 1261 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR 1262 // instructions, so that's probably OK, but is PIC always correct when 1263 // we get here? 1264 if (ACPV->isGlobalValue()) 1265 NewCPV = ARMConstantPoolConstant:: 1266 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, 1267 ARMCP::CPValue, 4); 1268 else if (ACPV->isExtSymbol()) 1269 NewCPV = ARMConstantPoolSymbol:: 1270 Create(MF.getFunction()->getContext(), 1271 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); 1272 else if (ACPV->isBlockAddress()) 1273 NewCPV = ARMConstantPoolConstant:: 1274 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, 1275 ARMCP::CPBlockAddress, 4); 1276 else if (ACPV->isLSDA()) 1277 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId, 1278 ARMCP::CPLSDA, 4); 1279 else if (ACPV->isMachineBasicBlock()) 1280 NewCPV = ARMConstantPoolMBB:: 1281 Create(MF.getFunction()->getContext(), 1282 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); 1283 else 1284 llvm_unreachable("Unexpected ARM constantpool value type!!"); 1285 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); 1286 return PCLabelId; 1287 } 1288 1289 void ARMBaseInstrInfo:: 1290 reMaterialize(MachineBasicBlock &MBB, 1291 MachineBasicBlock::iterator I, 1292 unsigned DestReg, unsigned SubIdx, 1293 const MachineInstr *Orig, 1294 const TargetRegisterInfo &TRI) const { 1295 unsigned Opcode = Orig->getOpcode(); 1296 switch (Opcode) { 1297 default: { 1298 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1299 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1300 MBB.insert(I, MI); 1301 break; 1302 } 1303 case ARM::tLDRpci_pic: 1304 case ARM::t2LDRpci_pic: { 1305 MachineFunction &MF = *MBB.getParent(); 1306 unsigned CPI = Orig->getOperand(1).getIndex(); 1307 unsigned PCLabelId = duplicateCPV(MF, CPI); 1308 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), 1309 DestReg) 1310 .addConstantPoolIndex(CPI).addImm(PCLabelId); 1311 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); 1312 break; 1313 } 1314 } 1315 } 1316 1317 MachineInstr * 1318 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const { 1319 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); 1320 switch(Orig->getOpcode()) { 1321 case ARM::tLDRpci_pic: 1322 case ARM::t2LDRpci_pic: { 1323 unsigned CPI = Orig->getOperand(1).getIndex(); 1324 unsigned PCLabelId = duplicateCPV(MF, CPI); 1325 Orig->getOperand(1).setIndex(CPI); 1326 Orig->getOperand(2).setImm(PCLabelId); 1327 break; 1328 } 1329 } 1330 return MI; 1331 } 1332 1333 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0, 1334 const MachineInstr *MI1, 1335 const MachineRegisterInfo *MRI) const { 1336 int Opcode = MI0->getOpcode(); 1337 if (Opcode == ARM::t2LDRpci || 1338 Opcode == ARM::t2LDRpci_pic || 1339 Opcode == ARM::tLDRpci || 1340 Opcode == ARM::tLDRpci_pic || 1341 Opcode == ARM::LDRLIT_ga_pcrel || 1342 Opcode == ARM::LDRLIT_ga_pcrel_ldr || 1343 Opcode == ARM::tLDRLIT_ga_pcrel || 1344 Opcode == ARM::MOV_ga_pcrel || 1345 Opcode == ARM::MOV_ga_pcrel_ldr || 1346 Opcode == ARM::t2MOV_ga_pcrel) { 1347 if (MI1->getOpcode() != Opcode) 1348 return false; 1349 if (MI0->getNumOperands() != MI1->getNumOperands()) 1350 return false; 1351 1352 const MachineOperand &MO0 = MI0->getOperand(1); 1353 const MachineOperand &MO1 = MI1->getOperand(1); 1354 if (MO0.getOffset() != MO1.getOffset()) 1355 return false; 1356 1357 if (Opcode == ARM::LDRLIT_ga_pcrel || 1358 Opcode == ARM::LDRLIT_ga_pcrel_ldr || 1359 Opcode == ARM::tLDRLIT_ga_pcrel || 1360 Opcode == ARM::MOV_ga_pcrel || 1361 Opcode == ARM::MOV_ga_pcrel_ldr || 1362 Opcode == ARM::t2MOV_ga_pcrel) 1363 // Ignore the PC labels. 1364 return MO0.getGlobal() == MO1.getGlobal(); 1365 1366 const MachineFunction *MF = MI0->getParent()->getParent(); 1367 const MachineConstantPool *MCP = MF->getConstantPool(); 1368 int CPI0 = MO0.getIndex(); 1369 int CPI1 = MO1.getIndex(); 1370 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; 1371 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; 1372 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry(); 1373 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry(); 1374 if (isARMCP0 && isARMCP1) { 1375 ARMConstantPoolValue *ACPV0 = 1376 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal); 1377 ARMConstantPoolValue *ACPV1 = 1378 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal); 1379 return ACPV0->hasSameValue(ACPV1); 1380 } else if (!isARMCP0 && !isARMCP1) { 1381 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal; 1382 } 1383 return false; 1384 } else if (Opcode == ARM::PICLDR) { 1385 if (MI1->getOpcode() != Opcode) 1386 return false; 1387 if (MI0->getNumOperands() != MI1->getNumOperands()) 1388 return false; 1389 1390 unsigned Addr0 = MI0->getOperand(1).getReg(); 1391 unsigned Addr1 = MI1->getOperand(1).getReg(); 1392 if (Addr0 != Addr1) { 1393 if (!MRI || 1394 !TargetRegisterInfo::isVirtualRegister(Addr0) || 1395 !TargetRegisterInfo::isVirtualRegister(Addr1)) 1396 return false; 1397 1398 // This assumes SSA form. 1399 MachineInstr *Def0 = MRI->getVRegDef(Addr0); 1400 MachineInstr *Def1 = MRI->getVRegDef(Addr1); 1401 // Check if the loaded value, e.g. a constantpool of a global address, are 1402 // the same. 1403 if (!produceSameValue(Def0, Def1, MRI)) 1404 return false; 1405 } 1406 1407 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) { 1408 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg 1409 const MachineOperand &MO0 = MI0->getOperand(i); 1410 const MachineOperand &MO1 = MI1->getOperand(i); 1411 if (!MO0.isIdenticalTo(MO1)) 1412 return false; 1413 } 1414 return true; 1415 } 1416 1417 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); 1418 } 1419 1420 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 1421 /// determine if two loads are loading from the same base address. It should 1422 /// only return true if the base pointers are the same and the only differences 1423 /// between the two addresses is the offset. It also returns the offsets by 1424 /// reference. 1425 /// 1426 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 1427 /// is permanently disabled. 1428 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 1429 int64_t &Offset1, 1430 int64_t &Offset2) const { 1431 // Don't worry about Thumb: just ARM and Thumb2. 1432 if (Subtarget.isThumb1Only()) return false; 1433 1434 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 1435 return false; 1436 1437 switch (Load1->getMachineOpcode()) { 1438 default: 1439 return false; 1440 case ARM::LDRi12: 1441 case ARM::LDRBi12: 1442 case ARM::LDRD: 1443 case ARM::LDRH: 1444 case ARM::LDRSB: 1445 case ARM::LDRSH: 1446 case ARM::VLDRD: 1447 case ARM::VLDRS: 1448 case ARM::t2LDRi8: 1449 case ARM::t2LDRBi8: 1450 case ARM::t2LDRDi8: 1451 case ARM::t2LDRSHi8: 1452 case ARM::t2LDRi12: 1453 case ARM::t2LDRBi12: 1454 case ARM::t2LDRSHi12: 1455 break; 1456 } 1457 1458 switch (Load2->getMachineOpcode()) { 1459 default: 1460 return false; 1461 case ARM::LDRi12: 1462 case ARM::LDRBi12: 1463 case ARM::LDRD: 1464 case ARM::LDRH: 1465 case ARM::LDRSB: 1466 case ARM::LDRSH: 1467 case ARM::VLDRD: 1468 case ARM::VLDRS: 1469 case ARM::t2LDRi8: 1470 case ARM::t2LDRBi8: 1471 case ARM::t2LDRSHi8: 1472 case ARM::t2LDRi12: 1473 case ARM::t2LDRBi12: 1474 case ARM::t2LDRSHi12: 1475 break; 1476 } 1477 1478 // Check if base addresses and chain operands match. 1479 if (Load1->getOperand(0) != Load2->getOperand(0) || 1480 Load1->getOperand(4) != Load2->getOperand(4)) 1481 return false; 1482 1483 // Index should be Reg0. 1484 if (Load1->getOperand(3) != Load2->getOperand(3)) 1485 return false; 1486 1487 // Determine the offsets. 1488 if (isa<ConstantSDNode>(Load1->getOperand(1)) && 1489 isa<ConstantSDNode>(Load2->getOperand(1))) { 1490 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); 1491 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); 1492 return true; 1493 } 1494 1495 return false; 1496 } 1497 1498 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 1499 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 1500 /// be scheduled togther. On some targets if two loads are loading from 1501 /// addresses in the same cache line, it's better if they are scheduled 1502 /// together. This function takes two integers that represent the load offsets 1503 /// from the common base address. It returns true if it decides it's desirable 1504 /// to schedule the two loads together. "NumLoads" is the number of loads that 1505 /// have already been scheduled after Load1. 1506 /// 1507 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched 1508 /// is permanently disabled. 1509 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 1510 int64_t Offset1, int64_t Offset2, 1511 unsigned NumLoads) const { 1512 // Don't worry about Thumb: just ARM and Thumb2. 1513 if (Subtarget.isThumb1Only()) return false; 1514 1515 assert(Offset2 > Offset1); 1516 1517 if ((Offset2 - Offset1) / 8 > 64) 1518 return false; 1519 1520 // Check if the machine opcodes are different. If they are different 1521 // then we consider them to not be of the same base address, 1522 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12. 1523 // In this case, they are considered to be the same because they are different 1524 // encoding forms of the same basic instruction. 1525 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && 1526 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && 1527 Load2->getMachineOpcode() == ARM::t2LDRBi12) || 1528 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && 1529 Load2->getMachineOpcode() == ARM::t2LDRBi8))) 1530 return false; // FIXME: overly conservative? 1531 1532 // Four loads in a row should be sufficient. 1533 if (NumLoads >= 3) 1534 return false; 1535 1536 return true; 1537 } 1538 1539 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 1540 const MachineBasicBlock *MBB, 1541 const MachineFunction &MF) const { 1542 // Debug info is never a scheduling boundary. It's necessary to be explicit 1543 // due to the special treatment of IT instructions below, otherwise a 1544 // dbg_value followed by an IT will result in the IT instruction being 1545 // considered a scheduling hazard, which is wrong. It should be the actual 1546 // instruction preceding the dbg_value instruction(s), just like it is 1547 // when debug info is not present. 1548 if (MI->isDebugValue()) 1549 return false; 1550 1551 // Terminators and labels can't be scheduled around. 1552 if (MI->isTerminator() || MI->isPosition()) 1553 return true; 1554 1555 // Treat the start of the IT block as a scheduling boundary, but schedule 1556 // t2IT along with all instructions following it. 1557 // FIXME: This is a big hammer. But the alternative is to add all potential 1558 // true and anti dependencies to IT block instructions as implicit operands 1559 // to the t2IT instruction. The added compile time and complexity does not 1560 // seem worth it. 1561 MachineBasicBlock::const_iterator I = MI; 1562 // Make sure to skip any dbg_value instructions 1563 while (++I != MBB->end() && I->isDebugValue()) 1564 ; 1565 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) 1566 return true; 1567 1568 // Don't attempt to schedule around any instruction that defines 1569 // a stack-oriented pointer, as it's unlikely to be profitable. This 1570 // saves compile time, because it doesn't require every single 1571 // stack slot reference to depend on the instruction that does the 1572 // modification. 1573 // Calls don't actually change the stack pointer, even if they have imp-defs. 1574 // No ARM calling conventions change the stack pointer. (X86 calling 1575 // conventions sometimes do). 1576 if (!MI->isCall() && MI->definesRegister(ARM::SP)) 1577 return true; 1578 1579 return false; 1580 } 1581 1582 bool ARMBaseInstrInfo:: 1583 isProfitableToIfCvt(MachineBasicBlock &MBB, 1584 unsigned NumCycles, unsigned ExtraPredCycles, 1585 const BranchProbability &Probability) const { 1586 if (!NumCycles) 1587 return false; 1588 1589 // Attempt to estimate the relative costs of predication versus branching. 1590 unsigned UnpredCost = Probability.getNumerator() * NumCycles; 1591 UnpredCost /= Probability.getDenominator(); 1592 UnpredCost += 1; // The branch itself 1593 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1594 1595 return (NumCycles + ExtraPredCycles) <= UnpredCost; 1596 } 1597 1598 bool ARMBaseInstrInfo:: 1599 isProfitableToIfCvt(MachineBasicBlock &TMBB, 1600 unsigned TCycles, unsigned TExtra, 1601 MachineBasicBlock &FMBB, 1602 unsigned FCycles, unsigned FExtra, 1603 const BranchProbability &Probability) const { 1604 if (!TCycles || !FCycles) 1605 return false; 1606 1607 // Attempt to estimate the relative costs of predication versus branching. 1608 unsigned TUnpredCost = Probability.getNumerator() * TCycles; 1609 TUnpredCost /= Probability.getDenominator(); 1610 1611 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator(); 1612 unsigned FUnpredCost = Comp * FCycles; 1613 FUnpredCost /= Probability.getDenominator(); 1614 1615 unsigned UnpredCost = TUnpredCost + FUnpredCost; 1616 UnpredCost += 1; // The branch itself 1617 UnpredCost += Subtarget.getMispredictionPenalty() / 10; 1618 1619 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost; 1620 } 1621 1622 bool 1623 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, 1624 MachineBasicBlock &FMBB) const { 1625 // Reduce false anti-dependencies to let Swift's out-of-order execution 1626 // engine do its thing. 1627 return Subtarget.isSwift(); 1628 } 1629 1630 /// getInstrPredicate - If instruction is predicated, returns its predicate 1631 /// condition, otherwise returns AL. It also returns the condition code 1632 /// register by reference. 1633 ARMCC::CondCodes 1634 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 1635 int PIdx = MI->findFirstPredOperandIdx(); 1636 if (PIdx == -1) { 1637 PredReg = 0; 1638 return ARMCC::AL; 1639 } 1640 1641 PredReg = MI->getOperand(PIdx+1).getReg(); 1642 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); 1643 } 1644 1645 1646 int llvm::getMatchingCondBranchOpcode(int Opc) { 1647 if (Opc == ARM::B) 1648 return ARM::Bcc; 1649 if (Opc == ARM::tB) 1650 return ARM::tBcc; 1651 if (Opc == ARM::t2B) 1652 return ARM::t2Bcc; 1653 1654 llvm_unreachable("Unknown unconditional branch opcode!"); 1655 } 1656 1657 /// commuteInstruction - Handle commutable instructions. 1658 MachineInstr * 1659 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1660 switch (MI->getOpcode()) { 1661 case ARM::MOVCCr: 1662 case ARM::t2MOVCCr: { 1663 // MOVCC can be commuted by inverting the condition. 1664 unsigned PredReg = 0; 1665 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); 1666 // MOVCC AL can't be inverted. Shouldn't happen. 1667 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 1668 return nullptr; 1669 MI = TargetInstrInfo::commuteInstruction(MI, NewMI); 1670 if (!MI) 1671 return nullptr; 1672 // After swapping the MOVCC operands, also invert the condition. 1673 MI->getOperand(MI->findFirstPredOperandIdx()) 1674 .setImm(ARMCC::getOppositeCondition(CC)); 1675 return MI; 1676 } 1677 } 1678 return TargetInstrInfo::commuteInstruction(MI, NewMI); 1679 } 1680 1681 /// Identify instructions that can be folded into a MOVCC instruction, and 1682 /// return the defining instruction. 1683 static MachineInstr *canFoldIntoMOVCC(unsigned Reg, 1684 const MachineRegisterInfo &MRI, 1685 const TargetInstrInfo *TII) { 1686 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 1687 return nullptr; 1688 if (!MRI.hasOneNonDBGUse(Reg)) 1689 return nullptr; 1690 MachineInstr *MI = MRI.getVRegDef(Reg); 1691 if (!MI) 1692 return nullptr; 1693 // MI is folded into the MOVCC by predicating it. 1694 if (!MI->isPredicable()) 1695 return nullptr; 1696 // Check if MI has any non-dead defs or physreg uses. This also detects 1697 // predicated instructions which will be reading CPSR. 1698 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 1699 const MachineOperand &MO = MI->getOperand(i); 1700 // Reject frame index operands, PEI can't handle the predicated pseudos. 1701 if (MO.isFI() || MO.isCPI() || MO.isJTI()) 1702 return nullptr; 1703 if (!MO.isReg()) 1704 continue; 1705 // MI can't have any tied operands, that would conflict with predication. 1706 if (MO.isTied()) 1707 return nullptr; 1708 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 1709 return nullptr; 1710 if (MO.isDef() && !MO.isDead()) 1711 return nullptr; 1712 } 1713 bool DontMoveAcrossStores = true; 1714 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr, 1715 DontMoveAcrossStores)) 1716 return nullptr; 1717 return MI; 1718 } 1719 1720 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI, 1721 SmallVectorImpl<MachineOperand> &Cond, 1722 unsigned &TrueOp, unsigned &FalseOp, 1723 bool &Optimizable) const { 1724 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1725 "Unknown select instruction"); 1726 // MOVCC operands: 1727 // 0: Def. 1728 // 1: True use. 1729 // 2: False use. 1730 // 3: Condition code. 1731 // 4: CPSR use. 1732 TrueOp = 1; 1733 FalseOp = 2; 1734 Cond.push_back(MI->getOperand(3)); 1735 Cond.push_back(MI->getOperand(4)); 1736 // We can always fold a def. 1737 Optimizable = true; 1738 return false; 1739 } 1740 1741 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI, 1742 bool PreferFalse) const { 1743 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) && 1744 "Unknown select instruction"); 1745 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 1746 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); 1747 bool Invert = !DefMI; 1748 if (!DefMI) 1749 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1750 if (!DefMI) 1751 return nullptr; 1752 1753 // Find new register class to use. 1754 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); 1755 unsigned DestReg = MI->getOperand(0).getReg(); 1756 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 1757 if (!MRI.constrainRegClass(DestReg, PreviousClass)) 1758 return nullptr; 1759 1760 // Create a new predicated version of DefMI. 1761 // Rfalse is the first use. 1762 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1763 DefMI->getDesc(), DestReg); 1764 1765 // Copy all the DefMI operands, excluding its (null) predicate. 1766 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1767 for (unsigned i = 1, e = DefDesc.getNumOperands(); 1768 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i) 1769 NewMI.addOperand(DefMI->getOperand(i)); 1770 1771 unsigned CondCode = MI->getOperand(3).getImm(); 1772 if (Invert) 1773 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1774 else 1775 NewMI.addImm(CondCode); 1776 NewMI.addOperand(MI->getOperand(4)); 1777 1778 // DefMI is not the -S version that sets CPSR, so add an optional %noreg. 1779 if (NewMI->hasOptionalDef()) 1780 AddDefaultCC(NewMI); 1781 1782 // The output register value when the predicate is false is an implicit 1783 // register operand tied to the first def. 1784 // The tie makes the register allocator ensure the FalseReg is allocated the 1785 // same register as operand 0. 1786 FalseReg.setImplicit(); 1787 NewMI.addOperand(FalseReg); 1788 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); 1789 1790 // The caller will erase MI, but not DefMI. 1791 DefMI->eraseFromParent(); 1792 return NewMI; 1793 } 1794 1795 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the 1796 /// instruction is encoded with an 'S' bit is determined by the optional CPSR 1797 /// def operand. 1798 /// 1799 /// This will go away once we can teach tblgen how to set the optional CPSR def 1800 /// operand itself. 1801 struct AddSubFlagsOpcodePair { 1802 uint16_t PseudoOpc; 1803 uint16_t MachineOpc; 1804 }; 1805 1806 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = { 1807 {ARM::ADDSri, ARM::ADDri}, 1808 {ARM::ADDSrr, ARM::ADDrr}, 1809 {ARM::ADDSrsi, ARM::ADDrsi}, 1810 {ARM::ADDSrsr, ARM::ADDrsr}, 1811 1812 {ARM::SUBSri, ARM::SUBri}, 1813 {ARM::SUBSrr, ARM::SUBrr}, 1814 {ARM::SUBSrsi, ARM::SUBrsi}, 1815 {ARM::SUBSrsr, ARM::SUBrsr}, 1816 1817 {ARM::RSBSri, ARM::RSBri}, 1818 {ARM::RSBSrsi, ARM::RSBrsi}, 1819 {ARM::RSBSrsr, ARM::RSBrsr}, 1820 1821 {ARM::t2ADDSri, ARM::t2ADDri}, 1822 {ARM::t2ADDSrr, ARM::t2ADDrr}, 1823 {ARM::t2ADDSrs, ARM::t2ADDrs}, 1824 1825 {ARM::t2SUBSri, ARM::t2SUBri}, 1826 {ARM::t2SUBSrr, ARM::t2SUBrr}, 1827 {ARM::t2SUBSrs, ARM::t2SUBrs}, 1828 1829 {ARM::t2RSBSri, ARM::t2RSBri}, 1830 {ARM::t2RSBSrs, ARM::t2RSBrs}, 1831 }; 1832 1833 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) { 1834 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i) 1835 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc) 1836 return AddSubFlagsOpcodeMap[i].MachineOpc; 1837 return 0; 1838 } 1839 1840 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, 1841 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 1842 unsigned DestReg, unsigned BaseReg, int NumBytes, 1843 ARMCC::CondCodes Pred, unsigned PredReg, 1844 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 1845 if (NumBytes == 0 && DestReg != BaseReg) { 1846 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) 1847 .addReg(BaseReg, RegState::Kill) 1848 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1849 .setMIFlags(MIFlags); 1850 return; 1851 } 1852 1853 bool isSub = NumBytes < 0; 1854 if (isSub) NumBytes = -NumBytes; 1855 1856 while (NumBytes) { 1857 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 1858 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 1859 assert(ThisVal && "Didn't extract field correctly"); 1860 1861 // We will handle these bits from offset, clear them. 1862 NumBytes &= ~ThisVal; 1863 1864 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 1865 1866 // Build the new ADD / SUB. 1867 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; 1868 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 1869 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 1870 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 1871 .setMIFlags(MIFlags); 1872 BaseReg = DestReg; 1873 } 1874 } 1875 1876 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI, 1877 MachineInstr *MI) { 1878 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true); 1879 Subreg.isValid(); ++Subreg) 1880 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) != 1881 MachineBasicBlock::LQR_Dead) 1882 return true; 1883 return false; 1884 } 1885 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 1886 MachineFunction &MF, MachineInstr *MI, 1887 unsigned NumBytes) { 1888 // This optimisation potentially adds lots of load and store 1889 // micro-operations, it's only really a great benefit to code-size. 1890 if (!MF.getFunction()->getAttributes().hasAttribute( 1891 AttributeSet::FunctionIndex, Attribute::MinSize)) 1892 return false; 1893 1894 // If only one register is pushed/popped, LLVM can use an LDR/STR 1895 // instead. We can't modify those so make sure we're dealing with an 1896 // instruction we understand. 1897 bool IsPop = isPopOpcode(MI->getOpcode()); 1898 bool IsPush = isPushOpcode(MI->getOpcode()); 1899 if (!IsPush && !IsPop) 1900 return false; 1901 1902 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || 1903 MI->getOpcode() == ARM::VLDMDIA_UPD; 1904 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || 1905 MI->getOpcode() == ARM::tPOP || 1906 MI->getOpcode() == ARM::tPOP_RET; 1907 1908 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && 1909 MI->getOperand(1).getReg() == ARM::SP)) && 1910 "trying to fold sp update into non-sp-updating push/pop"); 1911 1912 // The VFP push & pop act on D-registers, so we can only fold an adjustment 1913 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try 1914 // if this is violated. 1915 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0) 1916 return false; 1917 1918 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 1919 // pred) so the list starts at 4. Thumb1 starts after the predicate. 1920 int RegListIdx = IsT1PushPop ? 2 : 4; 1921 1922 // Calculate the space we'll need in terms of registers. 1923 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); 1924 unsigned RD0Reg, RegsNeeded; 1925 if (IsVFPPushPop) { 1926 RD0Reg = ARM::D0; 1927 RegsNeeded = NumBytes / 8; 1928 } else { 1929 RD0Reg = ARM::R0; 1930 RegsNeeded = NumBytes / 4; 1931 } 1932 1933 // We're going to have to strip all list operands off before 1934 // re-adding them since the order matters, so save the existing ones 1935 // for later. 1936 SmallVector<MachineOperand, 4> RegList; 1937 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1938 RegList.push_back(MI->getOperand(i)); 1939 1940 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); 1941 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); 1942 1943 // Now try to find enough space in the reglist to allocate NumBytes. 1944 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; 1945 --CurReg) { 1946 if (!IsPop) { 1947 // Pushing any register is completely harmless, mark the 1948 // register involved as undef since we don't care about it in 1949 // the slightest. 1950 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, 1951 false, false, true)); 1952 --RegsNeeded; 1953 continue; 1954 } 1955 1956 // However, we can only pop an extra register if it's not live. For 1957 // registers live within the function we might clobber a return value 1958 // register; the other way a register can be live here is if it's 1959 // callee-saved. 1960 // TODO: Currently, computeRegisterLiveness() does not report "live" if a 1961 // sub reg is live. When computeRegisterLiveness() works for sub reg, it 1962 // can replace isAnySubRegLive(). 1963 if (isCalleeSavedRegister(CurReg, CSRegs) || 1964 isAnySubRegLive(CurReg, TRI, MI)) { 1965 // VFP pops don't allow holes in the register list, so any skip is fatal 1966 // for our transformation. GPR pops do, so we should just keep looking. 1967 if (IsVFPPushPop) 1968 return false; 1969 else 1970 continue; 1971 } 1972 1973 // Mark the unimportant registers as <def,dead> in the POP. 1974 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, 1975 true)); 1976 --RegsNeeded; 1977 } 1978 1979 if (RegsNeeded > 0) 1980 return false; 1981 1982 // Finally we know we can profitably perform the optimisation so go 1983 // ahead: strip all existing registers off and add them back again 1984 // in the right order. 1985 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) 1986 MI->RemoveOperand(i); 1987 1988 // Add the complete list back in. 1989 MachineInstrBuilder MIB(MF, &*MI); 1990 for (int i = RegList.size() - 1; i >= 0; --i) 1991 MIB.addOperand(RegList[i]); 1992 1993 return true; 1994 } 1995 1996 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 1997 unsigned FrameReg, int &Offset, 1998 const ARMBaseInstrInfo &TII) { 1999 unsigned Opcode = MI.getOpcode(); 2000 const MCInstrDesc &Desc = MI.getDesc(); 2001 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 2002 bool isSub = false; 2003 2004 // Memory operands in inline assembly always use AddrMode2. 2005 if (Opcode == ARM::INLINEASM) 2006 AddrMode = ARMII::AddrMode2; 2007 2008 if (Opcode == ARM::ADDri) { 2009 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 2010 if (Offset == 0) { 2011 // Turn it into a move. 2012 MI.setDesc(TII.get(ARM::MOVr)); 2013 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 2014 MI.RemoveOperand(FrameRegIdx+1); 2015 Offset = 0; 2016 return true; 2017 } else if (Offset < 0) { 2018 Offset = -Offset; 2019 isSub = true; 2020 MI.setDesc(TII.get(ARM::SUBri)); 2021 } 2022 2023 // Common case: small offset, fits into instruction. 2024 if (ARM_AM::getSOImmVal(Offset) != -1) { 2025 // Replace the FrameIndex with sp / fp 2026 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 2027 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 2028 Offset = 0; 2029 return true; 2030 } 2031 2032 // Otherwise, pull as much of the immedidate into this ADDri/SUBri 2033 // as possible. 2034 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 2035 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 2036 2037 // We will handle these bits from offset, clear them. 2038 Offset &= ~ThisImmVal; 2039 2040 // Get the properly encoded SOImmVal field. 2041 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 2042 "Bit extraction didn't work?"); 2043 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 2044 } else { 2045 unsigned ImmIdx = 0; 2046 int InstrOffs = 0; 2047 unsigned NumBits = 0; 2048 unsigned Scale = 1; 2049 switch (AddrMode) { 2050 case ARMII::AddrMode_i12: { 2051 ImmIdx = FrameRegIdx + 1; 2052 InstrOffs = MI.getOperand(ImmIdx).getImm(); 2053 NumBits = 12; 2054 break; 2055 } 2056 case ARMII::AddrMode2: { 2057 ImmIdx = FrameRegIdx+2; 2058 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 2059 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 2060 InstrOffs *= -1; 2061 NumBits = 12; 2062 break; 2063 } 2064 case ARMII::AddrMode3: { 2065 ImmIdx = FrameRegIdx+2; 2066 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 2067 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 2068 InstrOffs *= -1; 2069 NumBits = 8; 2070 break; 2071 } 2072 case ARMII::AddrMode4: 2073 case ARMII::AddrMode6: 2074 // Can't fold any offset even if it's zero. 2075 return false; 2076 case ARMII::AddrMode5: { 2077 ImmIdx = FrameRegIdx+1; 2078 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 2079 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 2080 InstrOffs *= -1; 2081 NumBits = 8; 2082 Scale = 4; 2083 break; 2084 } 2085 default: 2086 llvm_unreachable("Unsupported addressing mode!"); 2087 } 2088 2089 Offset += InstrOffs * Scale; 2090 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 2091 if (Offset < 0) { 2092 Offset = -Offset; 2093 isSub = true; 2094 } 2095 2096 // Attempt to fold address comp. if opcode has offset bits 2097 if (NumBits > 0) { 2098 // Common case: small offset, fits into instruction. 2099 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 2100 int ImmedOffset = Offset / Scale; 2101 unsigned Mask = (1 << NumBits) - 1; 2102 if ((unsigned)Offset <= Mask * Scale) { 2103 // Replace the FrameIndex with sp 2104 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 2105 // FIXME: When addrmode2 goes away, this will simplify (like the 2106 // T2 version), as the LDR.i12 versions don't need the encoding 2107 // tricks for the offset value. 2108 if (isSub) { 2109 if (AddrMode == ARMII::AddrMode_i12) 2110 ImmedOffset = -ImmedOffset; 2111 else 2112 ImmedOffset |= 1 << NumBits; 2113 } 2114 ImmOp.ChangeToImmediate(ImmedOffset); 2115 Offset = 0; 2116 return true; 2117 } 2118 2119 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 2120 ImmedOffset = ImmedOffset & Mask; 2121 if (isSub) { 2122 if (AddrMode == ARMII::AddrMode_i12) 2123 ImmedOffset = -ImmedOffset; 2124 else 2125 ImmedOffset |= 1 << NumBits; 2126 } 2127 ImmOp.ChangeToImmediate(ImmedOffset); 2128 Offset &= ~(Mask*Scale); 2129 } 2130 } 2131 2132 Offset = (isSub) ? -Offset : Offset; 2133 return Offset == 0; 2134 } 2135 2136 /// analyzeCompare - For a comparison instruction, return the source registers 2137 /// in SrcReg and SrcReg2 if having two register operands, and the value it 2138 /// compares against in CmpValue. Return true if the comparison instruction 2139 /// can be analyzed. 2140 bool ARMBaseInstrInfo:: 2141 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 2142 int &CmpMask, int &CmpValue) const { 2143 switch (MI->getOpcode()) { 2144 default: break; 2145 case ARM::CMPri: 2146 case ARM::t2CMPri: 2147 SrcReg = MI->getOperand(0).getReg(); 2148 SrcReg2 = 0; 2149 CmpMask = ~0; 2150 CmpValue = MI->getOperand(1).getImm(); 2151 return true; 2152 case ARM::CMPrr: 2153 case ARM::t2CMPrr: 2154 SrcReg = MI->getOperand(0).getReg(); 2155 SrcReg2 = MI->getOperand(1).getReg(); 2156 CmpMask = ~0; 2157 CmpValue = 0; 2158 return true; 2159 case ARM::TSTri: 2160 case ARM::t2TSTri: 2161 SrcReg = MI->getOperand(0).getReg(); 2162 SrcReg2 = 0; 2163 CmpMask = MI->getOperand(1).getImm(); 2164 CmpValue = 0; 2165 return true; 2166 } 2167 2168 return false; 2169 } 2170 2171 /// isSuitableForMask - Identify a suitable 'and' instruction that 2172 /// operates on the given source register and applies the same mask 2173 /// as a 'tst' instruction. Provide a limited look-through for copies. 2174 /// When successful, MI will hold the found instruction. 2175 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, 2176 int CmpMask, bool CommonUse) { 2177 switch (MI->getOpcode()) { 2178 case ARM::ANDri: 2179 case ARM::t2ANDri: 2180 if (CmpMask != MI->getOperand(2).getImm()) 2181 return false; 2182 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) 2183 return true; 2184 break; 2185 case ARM::COPY: { 2186 // Walk down one instruction which is potentially an 'and'. 2187 const MachineInstr &Copy = *MI; 2188 MachineBasicBlock::iterator AND( 2189 std::next(MachineBasicBlock::iterator(MI))); 2190 if (AND == MI->getParent()->end()) return false; 2191 MI = AND; 2192 return isSuitableForMask(MI, Copy.getOperand(0).getReg(), 2193 CmpMask, true); 2194 } 2195 } 2196 2197 return false; 2198 } 2199 2200 /// getSwappedCondition - assume the flags are set by MI(a,b), return 2201 /// the condition code if we modify the instructions such that flags are 2202 /// set by MI(b,a). 2203 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { 2204 switch (CC) { 2205 default: return ARMCC::AL; 2206 case ARMCC::EQ: return ARMCC::EQ; 2207 case ARMCC::NE: return ARMCC::NE; 2208 case ARMCC::HS: return ARMCC::LS; 2209 case ARMCC::LO: return ARMCC::HI; 2210 case ARMCC::HI: return ARMCC::LO; 2211 case ARMCC::LS: return ARMCC::HS; 2212 case ARMCC::GE: return ARMCC::LE; 2213 case ARMCC::LT: return ARMCC::GT; 2214 case ARMCC::GT: return ARMCC::LT; 2215 case ARMCC::LE: return ARMCC::GE; 2216 } 2217 } 2218 2219 /// isRedundantFlagInstr - check whether the first instruction, whose only 2220 /// purpose is to update flags, can be made redundant. 2221 /// CMPrr can be made redundant by SUBrr if the operands are the same. 2222 /// CMPri can be made redundant by SUBri if the operands are the same. 2223 /// This function can be extended later on. 2224 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, 2225 unsigned SrcReg2, int ImmValue, 2226 MachineInstr *OI) { 2227 if ((CmpI->getOpcode() == ARM::CMPrr || 2228 CmpI->getOpcode() == ARM::t2CMPrr) && 2229 (OI->getOpcode() == ARM::SUBrr || 2230 OI->getOpcode() == ARM::t2SUBrr) && 2231 ((OI->getOperand(1).getReg() == SrcReg && 2232 OI->getOperand(2).getReg() == SrcReg2) || 2233 (OI->getOperand(1).getReg() == SrcReg2 && 2234 OI->getOperand(2).getReg() == SrcReg))) 2235 return true; 2236 2237 if ((CmpI->getOpcode() == ARM::CMPri || 2238 CmpI->getOpcode() == ARM::t2CMPri) && 2239 (OI->getOpcode() == ARM::SUBri || 2240 OI->getOpcode() == ARM::t2SUBri) && 2241 OI->getOperand(1).getReg() == SrcReg && 2242 OI->getOperand(2).getImm() == ImmValue) 2243 return true; 2244 return false; 2245 } 2246 2247 /// optimizeCompareInstr - Convert the instruction supplying the argument to the 2248 /// comparison into one that sets the zero bit in the flags register; 2249 /// Remove a redundant Compare instruction if an earlier instruction can set the 2250 /// flags in the same way as Compare. 2251 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two 2252 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the 2253 /// condition code of instructions which use the flags. 2254 bool ARMBaseInstrInfo:: 2255 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 2256 int CmpMask, int CmpValue, 2257 const MachineRegisterInfo *MRI) const { 2258 // Get the unique definition of SrcReg. 2259 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 2260 if (!MI) return false; 2261 2262 // Masked compares sometimes use the same register as the corresponding 'and'. 2263 if (CmpMask != ~0) { 2264 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { 2265 MI = nullptr; 2266 for (MachineRegisterInfo::use_instr_iterator 2267 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end(); 2268 UI != UE; ++UI) { 2269 if (UI->getParent() != CmpInstr->getParent()) continue; 2270 MachineInstr *PotentialAND = &*UI; 2271 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || 2272 isPredicated(PotentialAND)) 2273 continue; 2274 MI = PotentialAND; 2275 break; 2276 } 2277 if (!MI) return false; 2278 } 2279 } 2280 2281 // Get ready to iterate backward from CmpInstr. 2282 MachineBasicBlock::iterator I = CmpInstr, E = MI, 2283 B = CmpInstr->getParent()->begin(); 2284 2285 // Early exit if CmpInstr is at the beginning of the BB. 2286 if (I == B) return false; 2287 2288 // There are two possible candidates which can be changed to set CPSR: 2289 // One is MI, the other is a SUB instruction. 2290 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1). 2291 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue). 2292 MachineInstr *Sub = nullptr; 2293 if (SrcReg2 != 0) 2294 // MI is not a candidate for CMPrr. 2295 MI = nullptr; 2296 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { 2297 // Conservatively refuse to convert an instruction which isn't in the same 2298 // BB as the comparison. 2299 // For CMPri, we need to check Sub, thus we can't return here. 2300 if (CmpInstr->getOpcode() == ARM::CMPri || 2301 CmpInstr->getOpcode() == ARM::t2CMPri) 2302 MI = nullptr; 2303 else 2304 return false; 2305 } 2306 2307 // Check that CPSR isn't set between the comparison instruction and the one we 2308 // want to change. At the same time, search for Sub. 2309 const TargetRegisterInfo *TRI = &getRegisterInfo(); 2310 --I; 2311 for (; I != E; --I) { 2312 const MachineInstr &Instr = *I; 2313 2314 if (Instr.modifiesRegister(ARM::CPSR, TRI) || 2315 Instr.readsRegister(ARM::CPSR, TRI)) 2316 // This instruction modifies or uses CPSR after the one we want to 2317 // change. We can't do this transformation. 2318 return false; 2319 2320 // Check whether CmpInstr can be made redundant by the current instruction. 2321 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { 2322 Sub = &*I; 2323 break; 2324 } 2325 2326 if (I == B) 2327 // The 'and' is below the comparison instruction. 2328 return false; 2329 } 2330 2331 // Return false if no candidates exist. 2332 if (!MI && !Sub) 2333 return false; 2334 2335 // The single candidate is called MI. 2336 if (!MI) MI = Sub; 2337 2338 // We can't use a predicated instruction - it doesn't always write the flags. 2339 if (isPredicated(MI)) 2340 return false; 2341 2342 switch (MI->getOpcode()) { 2343 default: break; 2344 case ARM::RSBrr: 2345 case ARM::RSBri: 2346 case ARM::RSCrr: 2347 case ARM::RSCri: 2348 case ARM::ADDrr: 2349 case ARM::ADDri: 2350 case ARM::ADCrr: 2351 case ARM::ADCri: 2352 case ARM::SUBrr: 2353 case ARM::SUBri: 2354 case ARM::SBCrr: 2355 case ARM::SBCri: 2356 case ARM::t2RSBri: 2357 case ARM::t2ADDrr: 2358 case ARM::t2ADDri: 2359 case ARM::t2ADCrr: 2360 case ARM::t2ADCri: 2361 case ARM::t2SUBrr: 2362 case ARM::t2SUBri: 2363 case ARM::t2SBCrr: 2364 case ARM::t2SBCri: 2365 case ARM::ANDrr: 2366 case ARM::ANDri: 2367 case ARM::t2ANDrr: 2368 case ARM::t2ANDri: 2369 case ARM::ORRrr: 2370 case ARM::ORRri: 2371 case ARM::t2ORRrr: 2372 case ARM::t2ORRri: 2373 case ARM::EORrr: 2374 case ARM::EORri: 2375 case ARM::t2EORrr: 2376 case ARM::t2EORri: { 2377 // Scan forward for the use of CPSR 2378 // When checking against MI: if it's a conditional code requires 2379 // checking of V bit, then this is not safe to do. 2380 // It is safe to remove CmpInstr if CPSR is redefined or killed. 2381 // If we are done with the basic block, we need to check whether CPSR is 2382 // live-out. 2383 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> 2384 OperandsToUpdate; 2385 bool isSafe = false; 2386 I = CmpInstr; 2387 E = CmpInstr->getParent()->end(); 2388 while (!isSafe && ++I != E) { 2389 const MachineInstr &Instr = *I; 2390 for (unsigned IO = 0, EO = Instr.getNumOperands(); 2391 !isSafe && IO != EO; ++IO) { 2392 const MachineOperand &MO = Instr.getOperand(IO); 2393 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { 2394 isSafe = true; 2395 break; 2396 } 2397 if (!MO.isReg() || MO.getReg() != ARM::CPSR) 2398 continue; 2399 if (MO.isDef()) { 2400 isSafe = true; 2401 break; 2402 } 2403 // Condition code is after the operand before CPSR except for VSELs. 2404 ARMCC::CondCodes CC; 2405 bool IsInstrVSel = true; 2406 switch (Instr.getOpcode()) { 2407 default: 2408 IsInstrVSel = false; 2409 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm(); 2410 break; 2411 case ARM::VSELEQD: 2412 case ARM::VSELEQS: 2413 CC = ARMCC::EQ; 2414 break; 2415 case ARM::VSELGTD: 2416 case ARM::VSELGTS: 2417 CC = ARMCC::GT; 2418 break; 2419 case ARM::VSELGED: 2420 case ARM::VSELGES: 2421 CC = ARMCC::GE; 2422 break; 2423 case ARM::VSELVSS: 2424 case ARM::VSELVSD: 2425 CC = ARMCC::VS; 2426 break; 2427 } 2428 2429 if (Sub) { 2430 ARMCC::CondCodes NewCC = getSwappedCondition(CC); 2431 if (NewCC == ARMCC::AL) 2432 return false; 2433 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based 2434 // on CMP needs to be updated to be based on SUB. 2435 // Push the condition code operands to OperandsToUpdate. 2436 // If it is safe to remove CmpInstr, the condition code of these 2437 // operands will be modified. 2438 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 2439 Sub->getOperand(2).getReg() == SrcReg) { 2440 // VSel doesn't support condition code update. 2441 if (IsInstrVSel) 2442 return false; 2443 OperandsToUpdate.push_back( 2444 std::make_pair(&((*I).getOperand(IO - 1)), NewCC)); 2445 } 2446 } else 2447 switch (CC) { 2448 default: 2449 // CPSR can be used multiple times, we should continue. 2450 break; 2451 case ARMCC::VS: 2452 case ARMCC::VC: 2453 case ARMCC::GE: 2454 case ARMCC::LT: 2455 case ARMCC::GT: 2456 case ARMCC::LE: 2457 return false; 2458 } 2459 } 2460 } 2461 2462 // If CPSR is not killed nor re-defined, we should check whether it is 2463 // live-out. If it is live-out, do not optimize. 2464 if (!isSafe) { 2465 MachineBasicBlock *MBB = CmpInstr->getParent(); 2466 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 2467 SE = MBB->succ_end(); SI != SE; ++SI) 2468 if ((*SI)->isLiveIn(ARM::CPSR)) 2469 return false; 2470 } 2471 2472 // Toggle the optional operand to CPSR. 2473 MI->getOperand(5).setReg(ARM::CPSR); 2474 MI->getOperand(5).setIsDef(true); 2475 assert(!isPredicated(MI) && "Can't use flags from predicated instruction"); 2476 CmpInstr->eraseFromParent(); 2477 2478 // Modify the condition code of operands in OperandsToUpdate. 2479 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to 2480 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 2481 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) 2482 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); 2483 return true; 2484 } 2485 } 2486 2487 return false; 2488 } 2489 2490 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, 2491 MachineInstr *DefMI, unsigned Reg, 2492 MachineRegisterInfo *MRI) const { 2493 // Fold large immediates into add, sub, or, xor. 2494 unsigned DefOpc = DefMI->getOpcode(); 2495 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) 2496 return false; 2497 if (!DefMI->getOperand(1).isImm()) 2498 // Could be t2MOVi32imm <ga:xx> 2499 return false; 2500 2501 if (!MRI->hasOneNonDBGUse(Reg)) 2502 return false; 2503 2504 const MCInstrDesc &DefMCID = DefMI->getDesc(); 2505 if (DefMCID.hasOptionalDef()) { 2506 unsigned NumOps = DefMCID.getNumOperands(); 2507 const MachineOperand &MO = DefMI->getOperand(NumOps-1); 2508 if (MO.getReg() == ARM::CPSR && !MO.isDead()) 2509 // If DefMI defines CPSR and it is not dead, it's obviously not safe 2510 // to delete DefMI. 2511 return false; 2512 } 2513 2514 const MCInstrDesc &UseMCID = UseMI->getDesc(); 2515 if (UseMCID.hasOptionalDef()) { 2516 unsigned NumOps = UseMCID.getNumOperands(); 2517 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR) 2518 // If the instruction sets the flag, do not attempt this optimization 2519 // since it may change the semantics of the code. 2520 return false; 2521 } 2522 2523 unsigned UseOpc = UseMI->getOpcode(); 2524 unsigned NewUseOpc = 0; 2525 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm(); 2526 uint32_t SOImmValV1 = 0, SOImmValV2 = 0; 2527 bool Commute = false; 2528 switch (UseOpc) { 2529 default: return false; 2530 case ARM::SUBrr: 2531 case ARM::ADDrr: 2532 case ARM::ORRrr: 2533 case ARM::EORrr: 2534 case ARM::t2SUBrr: 2535 case ARM::t2ADDrr: 2536 case ARM::t2ORRrr: 2537 case ARM::t2EORrr: { 2538 Commute = UseMI->getOperand(2).getReg() != Reg; 2539 switch (UseOpc) { 2540 default: break; 2541 case ARM::SUBrr: { 2542 if (Commute) 2543 return false; 2544 ImmVal = -ImmVal; 2545 NewUseOpc = ARM::SUBri; 2546 // Fallthrough 2547 } 2548 case ARM::ADDrr: 2549 case ARM::ORRrr: 2550 case ARM::EORrr: { 2551 if (!ARM_AM::isSOImmTwoPartVal(ImmVal)) 2552 return false; 2553 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal); 2554 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal); 2555 switch (UseOpc) { 2556 default: break; 2557 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; 2558 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; 2559 case ARM::EORrr: NewUseOpc = ARM::EORri; break; 2560 } 2561 break; 2562 } 2563 case ARM::t2SUBrr: { 2564 if (Commute) 2565 return false; 2566 ImmVal = -ImmVal; 2567 NewUseOpc = ARM::t2SUBri; 2568 // Fallthrough 2569 } 2570 case ARM::t2ADDrr: 2571 case ARM::t2ORRrr: 2572 case ARM::t2EORrr: { 2573 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal)) 2574 return false; 2575 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal); 2576 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal); 2577 switch (UseOpc) { 2578 default: break; 2579 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break; 2580 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; 2581 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; 2582 } 2583 break; 2584 } 2585 } 2586 } 2587 } 2588 2589 unsigned OpIdx = Commute ? 2 : 1; 2590 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2591 bool isKill = UseMI->getOperand(OpIdx).isKill(); 2592 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); 2593 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), 2594 UseMI, UseMI->getDebugLoc(), 2595 get(NewUseOpc), NewReg) 2596 .addReg(Reg1, getKillRegState(isKill)) 2597 .addImm(SOImmValV1))); 2598 UseMI->setDesc(get(NewUseOpc)); 2599 UseMI->getOperand(1).setReg(NewReg); 2600 UseMI->getOperand(1).setIsKill(); 2601 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2); 2602 DefMI->eraseFromParent(); 2603 return true; 2604 } 2605 2606 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, 2607 const MachineInstr *MI) { 2608 switch (MI->getOpcode()) { 2609 default: { 2610 const MCInstrDesc &Desc = MI->getDesc(); 2611 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); 2612 assert(UOps >= 0 && "bad # UOps"); 2613 return UOps; 2614 } 2615 2616 case ARM::LDRrs: 2617 case ARM::LDRBrs: 2618 case ARM::STRrs: 2619 case ARM::STRBrs: { 2620 unsigned ShOpVal = MI->getOperand(3).getImm(); 2621 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2622 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2623 if (!isSub && 2624 (ShImm == 0 || 2625 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2626 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2627 return 1; 2628 return 2; 2629 } 2630 2631 case ARM::LDRH: 2632 case ARM::STRH: { 2633 if (!MI->getOperand(2).getReg()) 2634 return 1; 2635 2636 unsigned ShOpVal = MI->getOperand(3).getImm(); 2637 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2638 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2639 if (!isSub && 2640 (ShImm == 0 || 2641 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2642 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2643 return 1; 2644 return 2; 2645 } 2646 2647 case ARM::LDRSB: 2648 case ARM::LDRSH: 2649 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2; 2650 2651 case ARM::LDRSB_POST: 2652 case ARM::LDRSH_POST: { 2653 unsigned Rt = MI->getOperand(0).getReg(); 2654 unsigned Rm = MI->getOperand(3).getReg(); 2655 return (Rt == Rm) ? 4 : 3; 2656 } 2657 2658 case ARM::LDR_PRE_REG: 2659 case ARM::LDRB_PRE_REG: { 2660 unsigned Rt = MI->getOperand(0).getReg(); 2661 unsigned Rm = MI->getOperand(3).getReg(); 2662 if (Rt == Rm) 2663 return 3; 2664 unsigned ShOpVal = MI->getOperand(4).getImm(); 2665 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2666 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2667 if (!isSub && 2668 (ShImm == 0 || 2669 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2670 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2671 return 2; 2672 return 3; 2673 } 2674 2675 case ARM::STR_PRE_REG: 2676 case ARM::STRB_PRE_REG: { 2677 unsigned ShOpVal = MI->getOperand(4).getImm(); 2678 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2679 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2680 if (!isSub && 2681 (ShImm == 0 || 2682 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2683 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2684 return 2; 2685 return 3; 2686 } 2687 2688 case ARM::LDRH_PRE: 2689 case ARM::STRH_PRE: { 2690 unsigned Rt = MI->getOperand(0).getReg(); 2691 unsigned Rm = MI->getOperand(3).getReg(); 2692 if (!Rm) 2693 return 2; 2694 if (Rt == Rm) 2695 return 3; 2696 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) 2697 ? 3 : 2; 2698 } 2699 2700 case ARM::LDR_POST_REG: 2701 case ARM::LDRB_POST_REG: 2702 case ARM::LDRH_POST: { 2703 unsigned Rt = MI->getOperand(0).getReg(); 2704 unsigned Rm = MI->getOperand(3).getReg(); 2705 return (Rt == Rm) ? 3 : 2; 2706 } 2707 2708 case ARM::LDR_PRE_IMM: 2709 case ARM::LDRB_PRE_IMM: 2710 case ARM::LDR_POST_IMM: 2711 case ARM::LDRB_POST_IMM: 2712 case ARM::STRB_POST_IMM: 2713 case ARM::STRB_POST_REG: 2714 case ARM::STRB_PRE_IMM: 2715 case ARM::STRH_POST: 2716 case ARM::STR_POST_IMM: 2717 case ARM::STR_POST_REG: 2718 case ARM::STR_PRE_IMM: 2719 return 2; 2720 2721 case ARM::LDRSB_PRE: 2722 case ARM::LDRSH_PRE: { 2723 unsigned Rm = MI->getOperand(3).getReg(); 2724 if (Rm == 0) 2725 return 3; 2726 unsigned Rt = MI->getOperand(0).getReg(); 2727 if (Rt == Rm) 2728 return 4; 2729 unsigned ShOpVal = MI->getOperand(4).getImm(); 2730 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 2731 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 2732 if (!isSub && 2733 (ShImm == 0 || 2734 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 2735 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 2736 return 3; 2737 return 4; 2738 } 2739 2740 case ARM::LDRD: { 2741 unsigned Rt = MI->getOperand(0).getReg(); 2742 unsigned Rn = MI->getOperand(2).getReg(); 2743 unsigned Rm = MI->getOperand(3).getReg(); 2744 if (Rm) 2745 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2746 return (Rt == Rn) ? 3 : 2; 2747 } 2748 2749 case ARM::STRD: { 2750 unsigned Rm = MI->getOperand(3).getReg(); 2751 if (Rm) 2752 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3; 2753 return 2; 2754 } 2755 2756 case ARM::LDRD_POST: 2757 case ARM::t2LDRD_POST: 2758 return 3; 2759 2760 case ARM::STRD_POST: 2761 case ARM::t2STRD_POST: 2762 return 4; 2763 2764 case ARM::LDRD_PRE: { 2765 unsigned Rt = MI->getOperand(0).getReg(); 2766 unsigned Rn = MI->getOperand(3).getReg(); 2767 unsigned Rm = MI->getOperand(4).getReg(); 2768 if (Rm) 2769 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2770 return (Rt == Rn) ? 4 : 3; 2771 } 2772 2773 case ARM::t2LDRD_PRE: { 2774 unsigned Rt = MI->getOperand(0).getReg(); 2775 unsigned Rn = MI->getOperand(3).getReg(); 2776 return (Rt == Rn) ? 4 : 3; 2777 } 2778 2779 case ARM::STRD_PRE: { 2780 unsigned Rm = MI->getOperand(4).getReg(); 2781 if (Rm) 2782 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4; 2783 return 3; 2784 } 2785 2786 case ARM::t2STRD_PRE: 2787 return 3; 2788 2789 case ARM::t2LDR_POST: 2790 case ARM::t2LDRB_POST: 2791 case ARM::t2LDRB_PRE: 2792 case ARM::t2LDRSBi12: 2793 case ARM::t2LDRSBi8: 2794 case ARM::t2LDRSBpci: 2795 case ARM::t2LDRSBs: 2796 case ARM::t2LDRH_POST: 2797 case ARM::t2LDRH_PRE: 2798 case ARM::t2LDRSBT: 2799 case ARM::t2LDRSB_POST: 2800 case ARM::t2LDRSB_PRE: 2801 case ARM::t2LDRSH_POST: 2802 case ARM::t2LDRSH_PRE: 2803 case ARM::t2LDRSHi12: 2804 case ARM::t2LDRSHi8: 2805 case ARM::t2LDRSHpci: 2806 case ARM::t2LDRSHs: 2807 return 2; 2808 2809 case ARM::t2LDRDi8: { 2810 unsigned Rt = MI->getOperand(0).getReg(); 2811 unsigned Rn = MI->getOperand(2).getReg(); 2812 return (Rt == Rn) ? 3 : 2; 2813 } 2814 2815 case ARM::t2STRB_POST: 2816 case ARM::t2STRB_PRE: 2817 case ARM::t2STRBs: 2818 case ARM::t2STRDi8: 2819 case ARM::t2STRH_POST: 2820 case ARM::t2STRH_PRE: 2821 case ARM::t2STRHs: 2822 case ARM::t2STR_POST: 2823 case ARM::t2STR_PRE: 2824 case ARM::t2STRs: 2825 return 2; 2826 } 2827 } 2828 2829 // Return the number of 32-bit words loaded by LDM or stored by STM. If this 2830 // can't be easily determined return 0 (missing MachineMemOperand). 2831 // 2832 // FIXME: The current MachineInstr design does not support relying on machine 2833 // mem operands to determine the width of a memory access. Instead, we expect 2834 // the target to provide this information based on the instruction opcode and 2835 // operands. However, using MachineMemOperand is a the best solution now for 2836 // two reasons: 2837 // 2838 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI 2839 // operands. This is much more dangerous than using the MachineMemOperand 2840 // sizes because CodeGen passes can insert/remove optional machine operands. In 2841 // fact, it's totally incorrect for preRA passes and appears to be wrong for 2842 // postRA passes as well. 2843 // 2844 // 2) getNumLDMAddresses is only used by the scheduling machine model and any 2845 // machine model that calls this should handle the unknown (zero size) case. 2846 // 2847 // Long term, we should require a target hook that verifies MachineMemOperand 2848 // sizes during MC lowering. That target hook should be local to MC lowering 2849 // because we can't ensure that it is aware of other MI forms. Doing this will 2850 // ensure that MachineMemOperands are correctly propagated through all passes. 2851 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const { 2852 unsigned Size = 0; 2853 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 2854 E = MI->memoperands_end(); I != E; ++I) { 2855 Size += (*I)->getSize(); 2856 } 2857 return Size / 4; 2858 } 2859 2860 unsigned 2861 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, 2862 const MachineInstr *MI) const { 2863 if (!ItinData || ItinData->isEmpty()) 2864 return 1; 2865 2866 const MCInstrDesc &Desc = MI->getDesc(); 2867 unsigned Class = Desc.getSchedClass(); 2868 int ItinUOps = ItinData->getNumMicroOps(Class); 2869 if (ItinUOps >= 0) { 2870 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore())) 2871 return getNumMicroOpsSwiftLdSt(ItinData, MI); 2872 2873 return ItinUOps; 2874 } 2875 2876 unsigned Opc = MI->getOpcode(); 2877 switch (Opc) { 2878 default: 2879 llvm_unreachable("Unexpected multi-uops instruction!"); 2880 case ARM::VLDMQIA: 2881 case ARM::VSTMQIA: 2882 return 2; 2883 2884 // The number of uOps for load / store multiple are determined by the number 2885 // registers. 2886 // 2887 // On Cortex-A8, each pair of register loads / stores can be scheduled on the 2888 // same cycle. The scheduling for the first load / store must be done 2889 // separately by assuming the address is not 64-bit aligned. 2890 // 2891 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address 2892 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON 2893 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. 2894 case ARM::VLDMDIA: 2895 case ARM::VLDMDIA_UPD: 2896 case ARM::VLDMDDB_UPD: 2897 case ARM::VLDMSIA: 2898 case ARM::VLDMSIA_UPD: 2899 case ARM::VLDMSDB_UPD: 2900 case ARM::VSTMDIA: 2901 case ARM::VSTMDIA_UPD: 2902 case ARM::VSTMDDB_UPD: 2903 case ARM::VSTMSIA: 2904 case ARM::VSTMSIA_UPD: 2905 case ARM::VSTMSDB_UPD: { 2906 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); 2907 return (NumRegs / 2) + (NumRegs % 2) + 1; 2908 } 2909 2910 case ARM::LDMIA_RET: 2911 case ARM::LDMIA: 2912 case ARM::LDMDA: 2913 case ARM::LDMDB: 2914 case ARM::LDMIB: 2915 case ARM::LDMIA_UPD: 2916 case ARM::LDMDA_UPD: 2917 case ARM::LDMDB_UPD: 2918 case ARM::LDMIB_UPD: 2919 case ARM::STMIA: 2920 case ARM::STMDA: 2921 case ARM::STMDB: 2922 case ARM::STMIB: 2923 case ARM::STMIA_UPD: 2924 case ARM::STMDA_UPD: 2925 case ARM::STMDB_UPD: 2926 case ARM::STMIB_UPD: 2927 case ARM::tLDMIA: 2928 case ARM::tLDMIA_UPD: 2929 case ARM::tSTMIA_UPD: 2930 case ARM::tPOP_RET: 2931 case ARM::tPOP: 2932 case ARM::tPUSH: 2933 case ARM::t2LDMIA_RET: 2934 case ARM::t2LDMIA: 2935 case ARM::t2LDMDB: 2936 case ARM::t2LDMIA_UPD: 2937 case ARM::t2LDMDB_UPD: 2938 case ARM::t2STMIA: 2939 case ARM::t2STMDB: 2940 case ARM::t2STMIA_UPD: 2941 case ARM::t2STMDB_UPD: { 2942 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; 2943 if (Subtarget.isSwift()) { 2944 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2945 switch (Opc) { 2946 default: break; 2947 case ARM::VLDMDIA_UPD: 2948 case ARM::VLDMDDB_UPD: 2949 case ARM::VLDMSIA_UPD: 2950 case ARM::VLDMSDB_UPD: 2951 case ARM::VSTMDIA_UPD: 2952 case ARM::VSTMDDB_UPD: 2953 case ARM::VSTMSIA_UPD: 2954 case ARM::VSTMSDB_UPD: 2955 case ARM::LDMIA_UPD: 2956 case ARM::LDMDA_UPD: 2957 case ARM::LDMDB_UPD: 2958 case ARM::LDMIB_UPD: 2959 case ARM::STMIA_UPD: 2960 case ARM::STMDA_UPD: 2961 case ARM::STMDB_UPD: 2962 case ARM::STMIB_UPD: 2963 case ARM::tLDMIA_UPD: 2964 case ARM::tSTMIA_UPD: 2965 case ARM::t2LDMIA_UPD: 2966 case ARM::t2LDMDB_UPD: 2967 case ARM::t2STMIA_UPD: 2968 case ARM::t2STMDB_UPD: 2969 ++UOps; // One for base register writeback. 2970 break; 2971 case ARM::LDMIA_RET: 2972 case ARM::tPOP_RET: 2973 case ARM::t2LDMIA_RET: 2974 UOps += 2; // One for base reg wb, one for write to pc. 2975 break; 2976 } 2977 return UOps; 2978 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 2979 if (NumRegs < 4) 2980 return 2; 2981 // 4 registers would be issued: 2, 2. 2982 // 5 registers would be issued: 2, 2, 1. 2983 int A8UOps = (NumRegs / 2); 2984 if (NumRegs % 2) 2985 ++A8UOps; 2986 return A8UOps; 2987 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 2988 int A9UOps = (NumRegs / 2); 2989 // If there are odd number of registers or if it's not 64-bit aligned, 2990 // then it takes an extra AGU (Address Generation Unit) cycle. 2991 if ((NumRegs % 2) || 2992 !MI->hasOneMemOperand() || 2993 (*MI->memoperands_begin())->getAlignment() < 8) 2994 ++A9UOps; 2995 return A9UOps; 2996 } else { 2997 // Assume the worst. 2998 return NumRegs; 2999 } 3000 } 3001 } 3002 } 3003 3004 int 3005 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, 3006 const MCInstrDesc &DefMCID, 3007 unsigned DefClass, 3008 unsigned DefIdx, unsigned DefAlign) const { 3009 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3010 if (RegNo <= 0) 3011 // Def is the address writeback. 3012 return ItinData->getOperandCycle(DefClass, DefIdx); 3013 3014 int DefCycle; 3015 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3016 // (regno / 2) + (regno % 2) + 1 3017 DefCycle = RegNo / 2 + 1; 3018 if (RegNo % 2) 3019 ++DefCycle; 3020 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3021 DefCycle = RegNo; 3022 bool isSLoad = false; 3023 3024 switch (DefMCID.getOpcode()) { 3025 default: break; 3026 case ARM::VLDMSIA: 3027 case ARM::VLDMSIA_UPD: 3028 case ARM::VLDMSDB_UPD: 3029 isSLoad = true; 3030 break; 3031 } 3032 3033 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3034 // then it takes an extra cycle. 3035 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 3036 ++DefCycle; 3037 } else { 3038 // Assume the worst. 3039 DefCycle = RegNo + 2; 3040 } 3041 3042 return DefCycle; 3043 } 3044 3045 int 3046 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, 3047 const MCInstrDesc &DefMCID, 3048 unsigned DefClass, 3049 unsigned DefIdx, unsigned DefAlign) const { 3050 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 3051 if (RegNo <= 0) 3052 // Def is the address writeback. 3053 return ItinData->getOperandCycle(DefClass, DefIdx); 3054 3055 int DefCycle; 3056 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3057 // 4 registers would be issued: 1, 2, 1. 3058 // 5 registers would be issued: 1, 2, 2. 3059 DefCycle = RegNo / 2; 3060 if (DefCycle < 1) 3061 DefCycle = 1; 3062 // Result latency is issue cycle + 2: E2. 3063 DefCycle += 2; 3064 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3065 DefCycle = (RegNo / 2); 3066 // If there are odd number of registers or if it's not 64-bit aligned, 3067 // then it takes an extra AGU (Address Generation Unit) cycle. 3068 if ((RegNo % 2) || DefAlign < 8) 3069 ++DefCycle; 3070 // Result latency is AGU cycles + 2. 3071 DefCycle += 2; 3072 } else { 3073 // Assume the worst. 3074 DefCycle = RegNo + 2; 3075 } 3076 3077 return DefCycle; 3078 } 3079 3080 int 3081 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, 3082 const MCInstrDesc &UseMCID, 3083 unsigned UseClass, 3084 unsigned UseIdx, unsigned UseAlign) const { 3085 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3086 if (RegNo <= 0) 3087 return ItinData->getOperandCycle(UseClass, UseIdx); 3088 3089 int UseCycle; 3090 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3091 // (regno / 2) + (regno % 2) + 1 3092 UseCycle = RegNo / 2 + 1; 3093 if (RegNo % 2) 3094 ++UseCycle; 3095 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3096 UseCycle = RegNo; 3097 bool isSStore = false; 3098 3099 switch (UseMCID.getOpcode()) { 3100 default: break; 3101 case ARM::VSTMSIA: 3102 case ARM::VSTMSIA_UPD: 3103 case ARM::VSTMSDB_UPD: 3104 isSStore = true; 3105 break; 3106 } 3107 3108 // If there are odd number of 'S' registers or if it's not 64-bit aligned, 3109 // then it takes an extra cycle. 3110 if ((isSStore && (RegNo % 2)) || UseAlign < 8) 3111 ++UseCycle; 3112 } else { 3113 // Assume the worst. 3114 UseCycle = RegNo + 2; 3115 } 3116 3117 return UseCycle; 3118 } 3119 3120 int 3121 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, 3122 const MCInstrDesc &UseMCID, 3123 unsigned UseClass, 3124 unsigned UseIdx, unsigned UseAlign) const { 3125 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3126 if (RegNo <= 0) 3127 return ItinData->getOperandCycle(UseClass, UseIdx); 3128 3129 int UseCycle; 3130 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) { 3131 UseCycle = RegNo / 2; 3132 if (UseCycle < 2) 3133 UseCycle = 2; 3134 // Read in E3. 3135 UseCycle += 2; 3136 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) { 3137 UseCycle = (RegNo / 2); 3138 // If there are odd number of registers or if it's not 64-bit aligned, 3139 // then it takes an extra AGU (Address Generation Unit) cycle. 3140 if ((RegNo % 2) || UseAlign < 8) 3141 ++UseCycle; 3142 } else { 3143 // Assume the worst. 3144 UseCycle = 1; 3145 } 3146 return UseCycle; 3147 } 3148 3149 int 3150 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3151 const MCInstrDesc &DefMCID, 3152 unsigned DefIdx, unsigned DefAlign, 3153 const MCInstrDesc &UseMCID, 3154 unsigned UseIdx, unsigned UseAlign) const { 3155 unsigned DefClass = DefMCID.getSchedClass(); 3156 unsigned UseClass = UseMCID.getSchedClass(); 3157 3158 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3159 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3160 3161 // This may be a def / use of a variable_ops instruction, the operand 3162 // latency might be determinable dynamically. Let the target try to 3163 // figure it out. 3164 int DefCycle = -1; 3165 bool LdmBypass = false; 3166 switch (DefMCID.getOpcode()) { 3167 default: 3168 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3169 break; 3170 3171 case ARM::VLDMDIA: 3172 case ARM::VLDMDIA_UPD: 3173 case ARM::VLDMDDB_UPD: 3174 case ARM::VLDMSIA: 3175 case ARM::VLDMSIA_UPD: 3176 case ARM::VLDMSDB_UPD: 3177 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 3178 break; 3179 3180 case ARM::LDMIA_RET: 3181 case ARM::LDMIA: 3182 case ARM::LDMDA: 3183 case ARM::LDMDB: 3184 case ARM::LDMIB: 3185 case ARM::LDMIA_UPD: 3186 case ARM::LDMDA_UPD: 3187 case ARM::LDMDB_UPD: 3188 case ARM::LDMIB_UPD: 3189 case ARM::tLDMIA: 3190 case ARM::tLDMIA_UPD: 3191 case ARM::tPUSH: 3192 case ARM::t2LDMIA_RET: 3193 case ARM::t2LDMIA: 3194 case ARM::t2LDMDB: 3195 case ARM::t2LDMIA_UPD: 3196 case ARM::t2LDMDB_UPD: 3197 LdmBypass = 1; 3198 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); 3199 break; 3200 } 3201 3202 if (DefCycle == -1) 3203 // We can't seem to determine the result latency of the def, assume it's 2. 3204 DefCycle = 2; 3205 3206 int UseCycle = -1; 3207 switch (UseMCID.getOpcode()) { 3208 default: 3209 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 3210 break; 3211 3212 case ARM::VSTMDIA: 3213 case ARM::VSTMDIA_UPD: 3214 case ARM::VSTMDDB_UPD: 3215 case ARM::VSTMSIA: 3216 case ARM::VSTMSIA_UPD: 3217 case ARM::VSTMSDB_UPD: 3218 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 3219 break; 3220 3221 case ARM::STMIA: 3222 case ARM::STMDA: 3223 case ARM::STMDB: 3224 case ARM::STMIB: 3225 case ARM::STMIA_UPD: 3226 case ARM::STMDA_UPD: 3227 case ARM::STMDB_UPD: 3228 case ARM::STMIB_UPD: 3229 case ARM::tSTMIA_UPD: 3230 case ARM::tPOP_RET: 3231 case ARM::tPOP: 3232 case ARM::t2STMIA: 3233 case ARM::t2STMDB: 3234 case ARM::t2STMIA_UPD: 3235 case ARM::t2STMDB_UPD: 3236 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); 3237 break; 3238 } 3239 3240 if (UseCycle == -1) 3241 // Assume it's read in the first stage. 3242 UseCycle = 1; 3243 3244 UseCycle = DefCycle - UseCycle + 1; 3245 if (UseCycle > 0) { 3246 if (LdmBypass) { 3247 // It's a variable_ops instruction so we can't use DefIdx here. Just use 3248 // first def operand. 3249 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, 3250 UseClass, UseIdx)) 3251 --UseCycle; 3252 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, 3253 UseClass, UseIdx)) { 3254 --UseCycle; 3255 } 3256 } 3257 3258 return UseCycle; 3259 } 3260 3261 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, 3262 const MachineInstr *MI, unsigned Reg, 3263 unsigned &DefIdx, unsigned &Dist) { 3264 Dist = 0; 3265 3266 MachineBasicBlock::const_iterator I = MI; ++I; 3267 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator()); 3268 assert(II->isInsideBundle() && "Empty bundle?"); 3269 3270 int Idx = -1; 3271 while (II->isInsideBundle()) { 3272 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); 3273 if (Idx != -1) 3274 break; 3275 --II; 3276 ++Dist; 3277 } 3278 3279 assert(Idx != -1 && "Cannot find bundled definition!"); 3280 DefIdx = Idx; 3281 return II; 3282 } 3283 3284 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, 3285 const MachineInstr *MI, unsigned Reg, 3286 unsigned &UseIdx, unsigned &Dist) { 3287 Dist = 0; 3288 3289 MachineBasicBlock::const_instr_iterator II = MI; ++II; 3290 assert(II->isInsideBundle() && "Empty bundle?"); 3291 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3292 3293 // FIXME: This doesn't properly handle multiple uses. 3294 int Idx = -1; 3295 while (II != E && II->isInsideBundle()) { 3296 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); 3297 if (Idx != -1) 3298 break; 3299 if (II->getOpcode() != ARM::t2IT) 3300 ++Dist; 3301 ++II; 3302 } 3303 3304 if (Idx == -1) { 3305 Dist = 0; 3306 return nullptr; 3307 } 3308 3309 UseIdx = Idx; 3310 return II; 3311 } 3312 3313 /// Return the number of cycles to add to (or subtract from) the static 3314 /// itinerary based on the def opcode and alignment. The caller will ensure that 3315 /// adjusted latency is at least one cycle. 3316 static int adjustDefLatency(const ARMSubtarget &Subtarget, 3317 const MachineInstr *DefMI, 3318 const MCInstrDesc *DefMCID, unsigned DefAlign) { 3319 int Adjust = 0; 3320 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) { 3321 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3322 // variants are one cycle cheaper. 3323 switch (DefMCID->getOpcode()) { 3324 default: break; 3325 case ARM::LDRrs: 3326 case ARM::LDRBrs: { 3327 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3328 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3329 if (ShImm == 0 || 3330 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3331 --Adjust; 3332 break; 3333 } 3334 case ARM::t2LDRs: 3335 case ARM::t2LDRBs: 3336 case ARM::t2LDRHs: 3337 case ARM::t2LDRSHs: { 3338 // Thumb2 mode: lsl only. 3339 unsigned ShAmt = DefMI->getOperand(3).getImm(); 3340 if (ShAmt == 0 || ShAmt == 2) 3341 --Adjust; 3342 break; 3343 } 3344 } 3345 } else if (Subtarget.isSwift()) { 3346 // FIXME: Properly handle all of the latency adjustments for address 3347 // writeback. 3348 switch (DefMCID->getOpcode()) { 3349 default: break; 3350 case ARM::LDRrs: 3351 case ARM::LDRBrs: { 3352 unsigned ShOpVal = DefMI->getOperand(3).getImm(); 3353 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; 3354 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3355 if (!isSub && 3356 (ShImm == 0 || 3357 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3358 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))) 3359 Adjust -= 2; 3360 else if (!isSub && 3361 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3362 --Adjust; 3363 break; 3364 } 3365 case ARM::t2LDRs: 3366 case ARM::t2LDRBs: 3367 case ARM::t2LDRHs: 3368 case ARM::t2LDRSHs: { 3369 // Thumb2 mode: lsl only. 3370 unsigned ShAmt = DefMI->getOperand(3).getImm(); 3371 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3) 3372 Adjust -= 2; 3373 break; 3374 } 3375 } 3376 } 3377 3378 if (DefAlign < 8 && Subtarget.isLikeA9()) { 3379 switch (DefMCID->getOpcode()) { 3380 default: break; 3381 case ARM::VLD1q8: 3382 case ARM::VLD1q16: 3383 case ARM::VLD1q32: 3384 case ARM::VLD1q64: 3385 case ARM::VLD1q8wb_fixed: 3386 case ARM::VLD1q16wb_fixed: 3387 case ARM::VLD1q32wb_fixed: 3388 case ARM::VLD1q64wb_fixed: 3389 case ARM::VLD1q8wb_register: 3390 case ARM::VLD1q16wb_register: 3391 case ARM::VLD1q32wb_register: 3392 case ARM::VLD1q64wb_register: 3393 case ARM::VLD2d8: 3394 case ARM::VLD2d16: 3395 case ARM::VLD2d32: 3396 case ARM::VLD2q8: 3397 case ARM::VLD2q16: 3398 case ARM::VLD2q32: 3399 case ARM::VLD2d8wb_fixed: 3400 case ARM::VLD2d16wb_fixed: 3401 case ARM::VLD2d32wb_fixed: 3402 case ARM::VLD2q8wb_fixed: 3403 case ARM::VLD2q16wb_fixed: 3404 case ARM::VLD2q32wb_fixed: 3405 case ARM::VLD2d8wb_register: 3406 case ARM::VLD2d16wb_register: 3407 case ARM::VLD2d32wb_register: 3408 case ARM::VLD2q8wb_register: 3409 case ARM::VLD2q16wb_register: 3410 case ARM::VLD2q32wb_register: 3411 case ARM::VLD3d8: 3412 case ARM::VLD3d16: 3413 case ARM::VLD3d32: 3414 case ARM::VLD1d64T: 3415 case ARM::VLD3d8_UPD: 3416 case ARM::VLD3d16_UPD: 3417 case ARM::VLD3d32_UPD: 3418 case ARM::VLD1d64Twb_fixed: 3419 case ARM::VLD1d64Twb_register: 3420 case ARM::VLD3q8_UPD: 3421 case ARM::VLD3q16_UPD: 3422 case ARM::VLD3q32_UPD: 3423 case ARM::VLD4d8: 3424 case ARM::VLD4d16: 3425 case ARM::VLD4d32: 3426 case ARM::VLD1d64Q: 3427 case ARM::VLD4d8_UPD: 3428 case ARM::VLD4d16_UPD: 3429 case ARM::VLD4d32_UPD: 3430 case ARM::VLD1d64Qwb_fixed: 3431 case ARM::VLD1d64Qwb_register: 3432 case ARM::VLD4q8_UPD: 3433 case ARM::VLD4q16_UPD: 3434 case ARM::VLD4q32_UPD: 3435 case ARM::VLD1DUPq8: 3436 case ARM::VLD1DUPq16: 3437 case ARM::VLD1DUPq32: 3438 case ARM::VLD1DUPq8wb_fixed: 3439 case ARM::VLD1DUPq16wb_fixed: 3440 case ARM::VLD1DUPq32wb_fixed: 3441 case ARM::VLD1DUPq8wb_register: 3442 case ARM::VLD1DUPq16wb_register: 3443 case ARM::VLD1DUPq32wb_register: 3444 case ARM::VLD2DUPd8: 3445 case ARM::VLD2DUPd16: 3446 case ARM::VLD2DUPd32: 3447 case ARM::VLD2DUPd8wb_fixed: 3448 case ARM::VLD2DUPd16wb_fixed: 3449 case ARM::VLD2DUPd32wb_fixed: 3450 case ARM::VLD2DUPd8wb_register: 3451 case ARM::VLD2DUPd16wb_register: 3452 case ARM::VLD2DUPd32wb_register: 3453 case ARM::VLD4DUPd8: 3454 case ARM::VLD4DUPd16: 3455 case ARM::VLD4DUPd32: 3456 case ARM::VLD4DUPd8_UPD: 3457 case ARM::VLD4DUPd16_UPD: 3458 case ARM::VLD4DUPd32_UPD: 3459 case ARM::VLD1LNd8: 3460 case ARM::VLD1LNd16: 3461 case ARM::VLD1LNd32: 3462 case ARM::VLD1LNd8_UPD: 3463 case ARM::VLD1LNd16_UPD: 3464 case ARM::VLD1LNd32_UPD: 3465 case ARM::VLD2LNd8: 3466 case ARM::VLD2LNd16: 3467 case ARM::VLD2LNd32: 3468 case ARM::VLD2LNq16: 3469 case ARM::VLD2LNq32: 3470 case ARM::VLD2LNd8_UPD: 3471 case ARM::VLD2LNd16_UPD: 3472 case ARM::VLD2LNd32_UPD: 3473 case ARM::VLD2LNq16_UPD: 3474 case ARM::VLD2LNq32_UPD: 3475 case ARM::VLD4LNd8: 3476 case ARM::VLD4LNd16: 3477 case ARM::VLD4LNd32: 3478 case ARM::VLD4LNq16: 3479 case ARM::VLD4LNq32: 3480 case ARM::VLD4LNd8_UPD: 3481 case ARM::VLD4LNd16_UPD: 3482 case ARM::VLD4LNd32_UPD: 3483 case ARM::VLD4LNq16_UPD: 3484 case ARM::VLD4LNq32_UPD: 3485 // If the address is not 64-bit aligned, the latencies of these 3486 // instructions increases by one. 3487 ++Adjust; 3488 break; 3489 } 3490 } 3491 return Adjust; 3492 } 3493 3494 3495 3496 int 3497 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3498 const MachineInstr *DefMI, unsigned DefIdx, 3499 const MachineInstr *UseMI, 3500 unsigned UseIdx) const { 3501 // No operand latency. The caller may fall back to getInstrLatency. 3502 if (!ItinData || ItinData->isEmpty()) 3503 return -1; 3504 3505 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); 3506 unsigned Reg = DefMO.getReg(); 3507 const MCInstrDesc *DefMCID = &DefMI->getDesc(); 3508 const MCInstrDesc *UseMCID = &UseMI->getDesc(); 3509 3510 unsigned DefAdj = 0; 3511 if (DefMI->isBundle()) { 3512 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); 3513 DefMCID = &DefMI->getDesc(); 3514 } 3515 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || 3516 DefMI->isRegSequence() || DefMI->isImplicitDef()) { 3517 return 1; 3518 } 3519 3520 unsigned UseAdj = 0; 3521 if (UseMI->isBundle()) { 3522 unsigned NewUseIdx; 3523 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI, 3524 Reg, NewUseIdx, UseAdj); 3525 if (!NewUseMI) 3526 return -1; 3527 3528 UseMI = NewUseMI; 3529 UseIdx = NewUseIdx; 3530 UseMCID = &UseMI->getDesc(); 3531 } 3532 3533 if (Reg == ARM::CPSR) { 3534 if (DefMI->getOpcode() == ARM::FMSTAT) { 3535 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) 3536 return Subtarget.isLikeA9() ? 1 : 20; 3537 } 3538 3539 // CPSR set and branch can be paired in the same cycle. 3540 if (UseMI->isBranch()) 3541 return 0; 3542 3543 // Otherwise it takes the instruction latency (generally one). 3544 unsigned Latency = getInstrLatency(ItinData, DefMI); 3545 3546 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to 3547 // its uses. Instructions which are otherwise scheduled between them may 3548 // incur a code size penalty (not able to use the CPSR setting 16-bit 3549 // instructions). 3550 if (Latency > 0 && Subtarget.isThumb2()) { 3551 const MachineFunction *MF = DefMI->getParent()->getParent(); 3552 if (MF->getFunction()->getAttributes(). 3553 hasAttribute(AttributeSet::FunctionIndex, 3554 Attribute::OptimizeForSize)) 3555 --Latency; 3556 } 3557 return Latency; 3558 } 3559 3560 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit()) 3561 return -1; 3562 3563 unsigned DefAlign = DefMI->hasOneMemOperand() 3564 ? (*DefMI->memoperands_begin())->getAlignment() : 0; 3565 unsigned UseAlign = UseMI->hasOneMemOperand() 3566 ? (*UseMI->memoperands_begin())->getAlignment() : 0; 3567 3568 // Get the itinerary's latency if possible, and handle variable_ops. 3569 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, 3570 *UseMCID, UseIdx, UseAlign); 3571 // Unable to find operand latency. The caller may resort to getInstrLatency. 3572 if (Latency < 0) 3573 return Latency; 3574 3575 // Adjust for IT block position. 3576 int Adj = DefAdj + UseAdj; 3577 3578 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3579 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign); 3580 if (Adj >= 0 || (int)Latency > -Adj) { 3581 return Latency + Adj; 3582 } 3583 // Return the itinerary latency, which may be zero but not less than zero. 3584 return Latency; 3585 } 3586 3587 int 3588 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, 3589 SDNode *DefNode, unsigned DefIdx, 3590 SDNode *UseNode, unsigned UseIdx) const { 3591 if (!DefNode->isMachineOpcode()) 3592 return 1; 3593 3594 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); 3595 3596 if (isZeroCost(DefMCID.Opcode)) 3597 return 0; 3598 3599 if (!ItinData || ItinData->isEmpty()) 3600 return DefMCID.mayLoad() ? 3 : 1; 3601 3602 if (!UseNode->isMachineOpcode()) { 3603 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); 3604 if (Subtarget.isLikeA9() || Subtarget.isSwift()) 3605 return Latency <= 2 ? 1 : Latency - 1; 3606 else 3607 return Latency <= 3 ? 1 : Latency - 2; 3608 } 3609 3610 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); 3611 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode); 3612 unsigned DefAlign = !DefMN->memoperands_empty() 3613 ? (*DefMN->memoperands_begin())->getAlignment() : 0; 3614 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode); 3615 unsigned UseAlign = !UseMN->memoperands_empty() 3616 ? (*UseMN->memoperands_begin())->getAlignment() : 0; 3617 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, 3618 UseMCID, UseIdx, UseAlign); 3619 3620 if (Latency > 1 && 3621 (Subtarget.isCortexA8() || Subtarget.isLikeA9() || 3622 Subtarget.isCortexA7())) { 3623 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] 3624 // variants are one cycle cheaper. 3625 switch (DefMCID.getOpcode()) { 3626 default: break; 3627 case ARM::LDRrs: 3628 case ARM::LDRBrs: { 3629 unsigned ShOpVal = 3630 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3631 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3632 if (ShImm == 0 || 3633 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3634 --Latency; 3635 break; 3636 } 3637 case ARM::t2LDRs: 3638 case ARM::t2LDRBs: 3639 case ARM::t2LDRHs: 3640 case ARM::t2LDRSHs: { 3641 // Thumb2 mode: lsl only. 3642 unsigned ShAmt = 3643 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3644 if (ShAmt == 0 || ShAmt == 2) 3645 --Latency; 3646 break; 3647 } 3648 } 3649 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) { 3650 // FIXME: Properly handle all of the latency adjustments for address 3651 // writeback. 3652 switch (DefMCID.getOpcode()) { 3653 default: break; 3654 case ARM::LDRrs: 3655 case ARM::LDRBrs: { 3656 unsigned ShOpVal = 3657 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); 3658 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); 3659 if (ShImm == 0 || 3660 ((ShImm == 1 || ShImm == 2 || ShImm == 3) && 3661 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)) 3662 Latency -= 2; 3663 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr) 3664 --Latency; 3665 break; 3666 } 3667 case ARM::t2LDRs: 3668 case ARM::t2LDRBs: 3669 case ARM::t2LDRHs: 3670 case ARM::t2LDRSHs: { 3671 // Thumb2 mode: lsl 0-3 only. 3672 Latency -= 2; 3673 break; 3674 } 3675 } 3676 } 3677 3678 if (DefAlign < 8 && Subtarget.isLikeA9()) 3679 switch (DefMCID.getOpcode()) { 3680 default: break; 3681 case ARM::VLD1q8: 3682 case ARM::VLD1q16: 3683 case ARM::VLD1q32: 3684 case ARM::VLD1q64: 3685 case ARM::VLD1q8wb_register: 3686 case ARM::VLD1q16wb_register: 3687 case ARM::VLD1q32wb_register: 3688 case ARM::VLD1q64wb_register: 3689 case ARM::VLD1q8wb_fixed: 3690 case ARM::VLD1q16wb_fixed: 3691 case ARM::VLD1q32wb_fixed: 3692 case ARM::VLD1q64wb_fixed: 3693 case ARM::VLD2d8: 3694 case ARM::VLD2d16: 3695 case ARM::VLD2d32: 3696 case ARM::VLD2q8Pseudo: 3697 case ARM::VLD2q16Pseudo: 3698 case ARM::VLD2q32Pseudo: 3699 case ARM::VLD2d8wb_fixed: 3700 case ARM::VLD2d16wb_fixed: 3701 case ARM::VLD2d32wb_fixed: 3702 case ARM::VLD2q8PseudoWB_fixed: 3703 case ARM::VLD2q16PseudoWB_fixed: 3704 case ARM::VLD2q32PseudoWB_fixed: 3705 case ARM::VLD2d8wb_register: 3706 case ARM::VLD2d16wb_register: 3707 case ARM::VLD2d32wb_register: 3708 case ARM::VLD2q8PseudoWB_register: 3709 case ARM::VLD2q16PseudoWB_register: 3710 case ARM::VLD2q32PseudoWB_register: 3711 case ARM::VLD3d8Pseudo: 3712 case ARM::VLD3d16Pseudo: 3713 case ARM::VLD3d32Pseudo: 3714 case ARM::VLD1d64TPseudo: 3715 case ARM::VLD1d64TPseudoWB_fixed: 3716 case ARM::VLD3d8Pseudo_UPD: 3717 case ARM::VLD3d16Pseudo_UPD: 3718 case ARM::VLD3d32Pseudo_UPD: 3719 case ARM::VLD3q8Pseudo_UPD: 3720 case ARM::VLD3q16Pseudo_UPD: 3721 case ARM::VLD3q32Pseudo_UPD: 3722 case ARM::VLD3q8oddPseudo: 3723 case ARM::VLD3q16oddPseudo: 3724 case ARM::VLD3q32oddPseudo: 3725 case ARM::VLD3q8oddPseudo_UPD: 3726 case ARM::VLD3q16oddPseudo_UPD: 3727 case ARM::VLD3q32oddPseudo_UPD: 3728 case ARM::VLD4d8Pseudo: 3729 case ARM::VLD4d16Pseudo: 3730 case ARM::VLD4d32Pseudo: 3731 case ARM::VLD1d64QPseudo: 3732 case ARM::VLD1d64QPseudoWB_fixed: 3733 case ARM::VLD4d8Pseudo_UPD: 3734 case ARM::VLD4d16Pseudo_UPD: 3735 case ARM::VLD4d32Pseudo_UPD: 3736 case ARM::VLD4q8Pseudo_UPD: 3737 case ARM::VLD4q16Pseudo_UPD: 3738 case ARM::VLD4q32Pseudo_UPD: 3739 case ARM::VLD4q8oddPseudo: 3740 case ARM::VLD4q16oddPseudo: 3741 case ARM::VLD4q32oddPseudo: 3742 case ARM::VLD4q8oddPseudo_UPD: 3743 case ARM::VLD4q16oddPseudo_UPD: 3744 case ARM::VLD4q32oddPseudo_UPD: 3745 case ARM::VLD1DUPq8: 3746 case ARM::VLD1DUPq16: 3747 case ARM::VLD1DUPq32: 3748 case ARM::VLD1DUPq8wb_fixed: 3749 case ARM::VLD1DUPq16wb_fixed: 3750 case ARM::VLD1DUPq32wb_fixed: 3751 case ARM::VLD1DUPq8wb_register: 3752 case ARM::VLD1DUPq16wb_register: 3753 case ARM::VLD1DUPq32wb_register: 3754 case ARM::VLD2DUPd8: 3755 case ARM::VLD2DUPd16: 3756 case ARM::VLD2DUPd32: 3757 case ARM::VLD2DUPd8wb_fixed: 3758 case ARM::VLD2DUPd16wb_fixed: 3759 case ARM::VLD2DUPd32wb_fixed: 3760 case ARM::VLD2DUPd8wb_register: 3761 case ARM::VLD2DUPd16wb_register: 3762 case ARM::VLD2DUPd32wb_register: 3763 case ARM::VLD4DUPd8Pseudo: 3764 case ARM::VLD4DUPd16Pseudo: 3765 case ARM::VLD4DUPd32Pseudo: 3766 case ARM::VLD4DUPd8Pseudo_UPD: 3767 case ARM::VLD4DUPd16Pseudo_UPD: 3768 case ARM::VLD4DUPd32Pseudo_UPD: 3769 case ARM::VLD1LNq8Pseudo: 3770 case ARM::VLD1LNq16Pseudo: 3771 case ARM::VLD1LNq32Pseudo: 3772 case ARM::VLD1LNq8Pseudo_UPD: 3773 case ARM::VLD1LNq16Pseudo_UPD: 3774 case ARM::VLD1LNq32Pseudo_UPD: 3775 case ARM::VLD2LNd8Pseudo: 3776 case ARM::VLD2LNd16Pseudo: 3777 case ARM::VLD2LNd32Pseudo: 3778 case ARM::VLD2LNq16Pseudo: 3779 case ARM::VLD2LNq32Pseudo: 3780 case ARM::VLD2LNd8Pseudo_UPD: 3781 case ARM::VLD2LNd16Pseudo_UPD: 3782 case ARM::VLD2LNd32Pseudo_UPD: 3783 case ARM::VLD2LNq16Pseudo_UPD: 3784 case ARM::VLD2LNq32Pseudo_UPD: 3785 case ARM::VLD4LNd8Pseudo: 3786 case ARM::VLD4LNd16Pseudo: 3787 case ARM::VLD4LNd32Pseudo: 3788 case ARM::VLD4LNq16Pseudo: 3789 case ARM::VLD4LNq32Pseudo: 3790 case ARM::VLD4LNd8Pseudo_UPD: 3791 case ARM::VLD4LNd16Pseudo_UPD: 3792 case ARM::VLD4LNd32Pseudo_UPD: 3793 case ARM::VLD4LNq16Pseudo_UPD: 3794 case ARM::VLD4LNq32Pseudo_UPD: 3795 // If the address is not 64-bit aligned, the latencies of these 3796 // instructions increases by one. 3797 ++Latency; 3798 break; 3799 } 3800 3801 return Latency; 3802 } 3803 3804 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const { 3805 if (MI->isCopyLike() || MI->isInsertSubreg() || 3806 MI->isRegSequence() || MI->isImplicitDef()) 3807 return 0; 3808 3809 if (MI->isBundle()) 3810 return 0; 3811 3812 const MCInstrDesc &MCID = MI->getDesc(); 3813 3814 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) { 3815 // When predicated, CPSR is an additional source operand for CPSR updating 3816 // instructions, this apparently increases their latencies. 3817 return 1; 3818 } 3819 return 0; 3820 } 3821 3822 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3823 const MachineInstr *MI, 3824 unsigned *PredCost) const { 3825 if (MI->isCopyLike() || MI->isInsertSubreg() || 3826 MI->isRegSequence() || MI->isImplicitDef()) 3827 return 1; 3828 3829 // An instruction scheduler typically runs on unbundled instructions, however 3830 // other passes may query the latency of a bundled instruction. 3831 if (MI->isBundle()) { 3832 unsigned Latency = 0; 3833 MachineBasicBlock::const_instr_iterator I = MI; 3834 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 3835 while (++I != E && I->isInsideBundle()) { 3836 if (I->getOpcode() != ARM::t2IT) 3837 Latency += getInstrLatency(ItinData, I, PredCost); 3838 } 3839 return Latency; 3840 } 3841 3842 const MCInstrDesc &MCID = MI->getDesc(); 3843 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) { 3844 // When predicated, CPSR is an additional source operand for CPSR updating 3845 // instructions, this apparently increases their latencies. 3846 *PredCost = 1; 3847 } 3848 // Be sure to call getStageLatency for an empty itinerary in case it has a 3849 // valid MinLatency property. 3850 if (!ItinData) 3851 return MI->mayLoad() ? 3 : 1; 3852 3853 unsigned Class = MCID.getSchedClass(); 3854 3855 // For instructions with variable uops, use uops as latency. 3856 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) 3857 return getNumMicroOps(ItinData, MI); 3858 3859 // For the common case, fall back on the itinerary's latency. 3860 unsigned Latency = ItinData->getStageLatency(Class); 3861 3862 // Adjust for dynamic def-side opcode variants not captured by the itinerary. 3863 unsigned DefAlign = MI->hasOneMemOperand() 3864 ? (*MI->memoperands_begin())->getAlignment() : 0; 3865 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign); 3866 if (Adj >= 0 || (int)Latency > -Adj) { 3867 return Latency + Adj; 3868 } 3869 return Latency; 3870 } 3871 3872 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, 3873 SDNode *Node) const { 3874 if (!Node->isMachineOpcode()) 3875 return 1; 3876 3877 if (!ItinData || ItinData->isEmpty()) 3878 return 1; 3879 3880 unsigned Opcode = Node->getMachineOpcode(); 3881 switch (Opcode) { 3882 default: 3883 return ItinData->getStageLatency(get(Opcode).getSchedClass()); 3884 case ARM::VLDMQIA: 3885 case ARM::VSTMQIA: 3886 return 2; 3887 } 3888 } 3889 3890 bool ARMBaseInstrInfo:: 3891 hasHighOperandLatency(const InstrItineraryData *ItinData, 3892 const MachineRegisterInfo *MRI, 3893 const MachineInstr *DefMI, unsigned DefIdx, 3894 const MachineInstr *UseMI, unsigned UseIdx) const { 3895 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3896 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask; 3897 if (Subtarget.isCortexA8() && 3898 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP)) 3899 // CortexA8 VFP instructions are not pipelined. 3900 return true; 3901 3902 // Hoist VFP / NEON instructions with 4 or higher latency. 3903 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); 3904 if (Latency < 0) 3905 Latency = getInstrLatency(ItinData, DefMI); 3906 if (Latency <= 3) 3907 return false; 3908 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON || 3909 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON; 3910 } 3911 3912 bool ARMBaseInstrInfo:: 3913 hasLowDefLatency(const InstrItineraryData *ItinData, 3914 const MachineInstr *DefMI, unsigned DefIdx) const { 3915 if (!ItinData || ItinData->isEmpty()) 3916 return false; 3917 3918 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; 3919 if (DDomain == ARMII::DomainGeneral) { 3920 unsigned DefClass = DefMI->getDesc().getSchedClass(); 3921 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 3922 return (DefCycle != -1 && DefCycle <= 2); 3923 } 3924 return false; 3925 } 3926 3927 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI, 3928 StringRef &ErrInfo) const { 3929 if (convertAddSubFlagsOpcode(MI->getOpcode())) { 3930 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; 3931 return false; 3932 } 3933 return true; 3934 } 3935 3936 bool 3937 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 3938 unsigned &AddSubOpc, 3939 bool &NegAcc, bool &HasLane) const { 3940 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode); 3941 if (I == MLxEntryMap.end()) 3942 return false; 3943 3944 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; 3945 MulOpc = Entry.MulOpc; 3946 AddSubOpc = Entry.AddSubOpc; 3947 NegAcc = Entry.NegAcc; 3948 HasLane = Entry.HasLane; 3949 return true; 3950 } 3951 3952 //===----------------------------------------------------------------------===// 3953 // Execution domains. 3954 //===----------------------------------------------------------------------===// 3955 // 3956 // Some instructions go down the NEON pipeline, some go down the VFP pipeline, 3957 // and some can go down both. The vmov instructions go down the VFP pipeline, 3958 // but they can be changed to vorr equivalents that are executed by the NEON 3959 // pipeline. 3960 // 3961 // We use the following execution domain numbering: 3962 // 3963 enum ARMExeDomain { 3964 ExeGeneric = 0, 3965 ExeVFP = 1, 3966 ExeNEON = 2 3967 }; 3968 // 3969 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h 3970 // 3971 std::pair<uint16_t, uint16_t> 3972 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { 3973 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON 3974 // if they are not predicated. 3975 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) 3976 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3977 3978 // CortexA9 is particularly picky about mixing the two and wants these 3979 // converted. 3980 if (Subtarget.isCortexA9() && !isPredicated(MI) && 3981 (MI->getOpcode() == ARM::VMOVRS || 3982 MI->getOpcode() == ARM::VMOVSR || 3983 MI->getOpcode() == ARM::VMOVS)) 3984 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); 3985 3986 // No other instructions can be swizzled, so just determine their domain. 3987 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; 3988 3989 if (Domain & ARMII::DomainNEON) 3990 return std::make_pair(ExeNEON, 0); 3991 3992 // Certain instructions can go either way on Cortex-A8. 3993 // Treat them as NEON instructions. 3994 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) 3995 return std::make_pair(ExeNEON, 0); 3996 3997 if (Domain & ARMII::DomainVFP) 3998 return std::make_pair(ExeVFP, 0); 3999 4000 return std::make_pair(ExeGeneric, 0); 4001 } 4002 4003 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, 4004 unsigned SReg, unsigned &Lane) { 4005 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); 4006 Lane = 0; 4007 4008 if (DReg != ARM::NoRegister) 4009 return DReg; 4010 4011 Lane = 1; 4012 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); 4013 4014 assert(DReg && "S-register with no D super-register?"); 4015 return DReg; 4016 } 4017 4018 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, 4019 /// set ImplicitSReg to a register number that must be marked as implicit-use or 4020 /// zero if no register needs to be defined as implicit-use. 4021 /// 4022 /// If the function cannot determine if an SPR should be marked implicit use or 4023 /// not, it returns false. 4024 /// 4025 /// This function handles cases where an instruction is being modified from taking 4026 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict 4027 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other 4028 /// lane of the DPR). 4029 /// 4030 /// If the other SPR is defined, an implicit-use of it should be added. Else, 4031 /// (including the case where the DPR itself is defined), it should not. 4032 /// 4033 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, 4034 MachineInstr *MI, 4035 unsigned DReg, unsigned Lane, 4036 unsigned &ImplicitSReg) { 4037 // If the DPR is defined or used already, the other SPR lane will be chained 4038 // correctly, so there is nothing to be done. 4039 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) { 4040 ImplicitSReg = 0; 4041 return true; 4042 } 4043 4044 // Otherwise we need to go searching to see if the SPR is set explicitly. 4045 ImplicitSReg = TRI->getSubReg(DReg, 4046 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); 4047 MachineBasicBlock::LivenessQueryResult LQR = 4048 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); 4049 4050 if (LQR == MachineBasicBlock::LQR_Live) 4051 return true; 4052 else if (LQR == MachineBasicBlock::LQR_Unknown) 4053 return false; 4054 4055 // If the register is known not to be live, there is no need to add an 4056 // implicit-use. 4057 ImplicitSReg = 0; 4058 return true; 4059 } 4060 4061 void 4062 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4063 unsigned DstReg, SrcReg, DReg; 4064 unsigned Lane; 4065 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 4066 const TargetRegisterInfo *TRI = &getRegisterInfo(); 4067 switch (MI->getOpcode()) { 4068 default: 4069 llvm_unreachable("cannot handle opcode!"); 4070 break; 4071 case ARM::VMOVD: 4072 if (Domain != ExeNEON) 4073 break; 4074 4075 // Zap the predicate operands. 4076 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); 4077 4078 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) 4079 DstReg = MI->getOperand(0).getReg(); 4080 SrcReg = MI->getOperand(1).getReg(); 4081 4082 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4083 MI->RemoveOperand(i-1); 4084 4085 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) 4086 MI->setDesc(get(ARM::VORRd)); 4087 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 4088 .addReg(SrcReg) 4089 .addReg(SrcReg)); 4090 break; 4091 case ARM::VMOVRS: 4092 if (Domain != ExeNEON) 4093 break; 4094 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); 4095 4096 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) 4097 DstReg = MI->getOperand(0).getReg(); 4098 SrcReg = MI->getOperand(1).getReg(); 4099 4100 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4101 MI->RemoveOperand(i-1); 4102 4103 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); 4104 4105 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) 4106 // Note that DSrc has been widened and the other lane may be undef, which 4107 // contaminates the entire register. 4108 MI->setDesc(get(ARM::VGETLNi32)); 4109 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 4110 .addReg(DReg, RegState::Undef) 4111 .addImm(Lane)); 4112 4113 // The old source should be an implicit use, otherwise we might think it 4114 // was dead before here. 4115 MIB.addReg(SrcReg, RegState::Implicit); 4116 break; 4117 case ARM::VMOVSR: { 4118 if (Domain != ExeNEON) 4119 break; 4120 assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); 4121 4122 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) 4123 DstReg = MI->getOperand(0).getReg(); 4124 SrcReg = MI->getOperand(1).getReg(); 4125 4126 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 4127 4128 unsigned ImplicitSReg; 4129 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) 4130 break; 4131 4132 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4133 MI->RemoveOperand(i-1); 4134 4135 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) 4136 // Again DDst may be undefined at the beginning of this instruction. 4137 MI->setDesc(get(ARM::VSETLNi32)); 4138 MIB.addReg(DReg, RegState::Define) 4139 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI))) 4140 .addReg(SrcReg) 4141 .addImm(Lane); 4142 AddDefaultPred(MIB); 4143 4144 // The narrower destination must be marked as set to keep previous chains 4145 // in place. 4146 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 4147 if (ImplicitSReg != 0) 4148 MIB.addReg(ImplicitSReg, RegState::Implicit); 4149 break; 4150 } 4151 case ARM::VMOVS: { 4152 if (Domain != ExeNEON) 4153 break; 4154 4155 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) 4156 DstReg = MI->getOperand(0).getReg(); 4157 SrcReg = MI->getOperand(1).getReg(); 4158 4159 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; 4160 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); 4161 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); 4162 4163 unsigned ImplicitSReg; 4164 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) 4165 break; 4166 4167 for (unsigned i = MI->getDesc().getNumOperands(); i; --i) 4168 MI->RemoveOperand(i-1); 4169 4170 if (DSrc == DDst) { 4171 // Destination can be: 4172 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) 4173 MI->setDesc(get(ARM::VDUPLN32d)); 4174 MIB.addReg(DDst, RegState::Define) 4175 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI))) 4176 .addImm(SrcLane); 4177 AddDefaultPred(MIB); 4178 4179 // Neither the source or the destination are naturally represented any 4180 // more, so add them in manually. 4181 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); 4182 MIB.addReg(SrcReg, RegState::Implicit); 4183 if (ImplicitSReg != 0) 4184 MIB.addReg(ImplicitSReg, RegState::Implicit); 4185 break; 4186 } 4187 4188 // In general there's no single instruction that can perform an S <-> S 4189 // move in NEON space, but a pair of VEXT instructions *can* do the 4190 // job. It turns out that the VEXTs needed will only use DSrc once, with 4191 // the position based purely on the combination of lane-0 and lane-1 4192 // involved. For example 4193 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 4194 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 4195 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 4196 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 4197 // 4198 // Pattern of the MachineInstrs is: 4199 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) 4200 MachineInstrBuilder NewMIB; 4201 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4202 get(ARM::VEXTd32), DDst); 4203 4204 // On the first instruction, both DSrc and DDst may be <undef> if present. 4205 // Specifically when the original instruction didn't have them as an 4206 // <imp-use>. 4207 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; 4208 bool CurUndef = !MI->readsRegister(CurReg, TRI); 4209 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 4210 4211 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; 4212 CurUndef = !MI->readsRegister(CurReg, TRI); 4213 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); 4214 4215 NewMIB.addImm(1); 4216 AddDefaultPred(NewMIB); 4217 4218 if (SrcLane == DstLane) 4219 NewMIB.addReg(SrcReg, RegState::Implicit); 4220 4221 MI->setDesc(get(ARM::VEXTd32)); 4222 MIB.addReg(DDst, RegState::Define); 4223 4224 // On the second instruction, DDst has definitely been defined above, so 4225 // it is not <undef>. DSrc, if present, can be <undef> as above. 4226 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; 4227 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 4228 MIB.addReg(CurReg, getUndefRegState(CurUndef)); 4229 4230 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; 4231 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI); 4232 MIB.addReg(CurReg, getUndefRegState(CurUndef)); 4233 4234 MIB.addImm(1); 4235 AddDefaultPred(MIB); 4236 4237 if (SrcLane != DstLane) 4238 MIB.addReg(SrcReg, RegState::Implicit); 4239 4240 // As before, the original destination is no longer represented, add it 4241 // implicitly. 4242 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 4243 if (ImplicitSReg != 0) 4244 MIB.addReg(ImplicitSReg, RegState::Implicit); 4245 break; 4246 } 4247 } 4248 4249 } 4250 4251 //===----------------------------------------------------------------------===// 4252 // Partial register updates 4253 //===----------------------------------------------------------------------===// 4254 // 4255 // Swift renames NEON registers with 64-bit granularity. That means any 4256 // instruction writing an S-reg implicitly reads the containing D-reg. The 4257 // problem is mostly avoided by translating f32 operations to v2f32 operations 4258 // on D-registers, but f32 loads are still a problem. 4259 // 4260 // These instructions can load an f32 into a NEON register: 4261 // 4262 // VLDRS - Only writes S, partial D update. 4263 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops. 4264 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops. 4265 // 4266 // FCONSTD can be used as a dependency-breaking instruction. 4267 unsigned ARMBaseInstrInfo:: 4268 getPartialRegUpdateClearance(const MachineInstr *MI, 4269 unsigned OpNum, 4270 const TargetRegisterInfo *TRI) const { 4271 if (!SwiftPartialUpdateClearance || 4272 !(Subtarget.isSwift() || Subtarget.isCortexA15())) 4273 return 0; 4274 4275 assert(TRI && "Need TRI instance"); 4276 4277 const MachineOperand &MO = MI->getOperand(OpNum); 4278 if (MO.readsReg()) 4279 return 0; 4280 unsigned Reg = MO.getReg(); 4281 int UseOp = -1; 4282 4283 switch(MI->getOpcode()) { 4284 // Normal instructions writing only an S-register. 4285 case ARM::VLDRS: 4286 case ARM::FCONSTS: 4287 case ARM::VMOVSR: 4288 case ARM::VMOVv8i8: 4289 case ARM::VMOVv4i16: 4290 case ARM::VMOVv2i32: 4291 case ARM::VMOVv2f32: 4292 case ARM::VMOVv1i64: 4293 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI); 4294 break; 4295 4296 // Explicitly reads the dependency. 4297 case ARM::VLD1LNd32: 4298 UseOp = 3; 4299 break; 4300 default: 4301 return 0; 4302 } 4303 4304 // If this instruction actually reads a value from Reg, there is no unwanted 4305 // dependency. 4306 if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) 4307 return 0; 4308 4309 // We must be able to clobber the whole D-reg. 4310 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4311 // Virtual register must be a foo:ssub_0<def,undef> operand. 4312 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg)) 4313 return 0; 4314 } else if (ARM::SPRRegClass.contains(Reg)) { 4315 // Physical register: MI must define the full D-reg. 4316 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, 4317 &ARM::DPRRegClass); 4318 if (!DReg || !MI->definesRegister(DReg, TRI)) 4319 return 0; 4320 } 4321 4322 // MI has an unwanted D-register dependency. 4323 // Avoid defs in the previous N instructrions. 4324 return SwiftPartialUpdateClearance; 4325 } 4326 4327 // Break a partial register dependency after getPartialRegUpdateClearance 4328 // returned non-zero. 4329 void ARMBaseInstrInfo:: 4330 breakPartialRegDependency(MachineBasicBlock::iterator MI, 4331 unsigned OpNum, 4332 const TargetRegisterInfo *TRI) const { 4333 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def"); 4334 assert(TRI && "Need TRI instance"); 4335 4336 const MachineOperand &MO = MI->getOperand(OpNum); 4337 unsigned Reg = MO.getReg(); 4338 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 4339 "Can't break virtual register dependencies."); 4340 unsigned DReg = Reg; 4341 4342 // If MI defines an S-reg, find the corresponding D super-register. 4343 if (ARM::SPRRegClass.contains(Reg)) { 4344 DReg = ARM::D0 + (Reg - ARM::S0) / 2; 4345 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); 4346 } 4347 4348 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); 4349 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); 4350 4351 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines 4352 // the full D-register by loading the same value to both lanes. The 4353 // instruction is micro-coded with 2 uops, so don't do this until we can 4354 // properly schedule micro-coded instructions. The dispatcher stalls cause 4355 // too big regressions. 4356 4357 // Insert the dependency-breaking FCONSTD before MI. 4358 // 96 is the encoding of 0.5, but the actual value doesn't matter here. 4359 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 4360 get(ARM::FCONSTD), DReg).addImm(96)); 4361 MI->addRegisterKilled(DReg, TRI, true); 4362 } 4363 4364 void ARMBaseInstrInfo::getUnconditionalBranch( 4365 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const { 4366 if (Subtarget.isThumb()) 4367 Branch.setOpcode(ARM::tB); 4368 else if (Subtarget.isThumb2()) 4369 Branch.setOpcode(ARM::t2B); 4370 else 4371 Branch.setOpcode(ARM::Bcc); 4372 4373 Branch.addOperand(MCOperand::CreateExpr(BranchTarget)); 4374 Branch.addOperand(MCOperand::CreateImm(ARMCC::AL)); 4375 Branch.addOperand(MCOperand::CreateReg(0)); 4376 } 4377 4378 void ARMBaseInstrInfo::getTrap(MCInst &MI) const { 4379 if (Subtarget.isThumb()) 4380 MI.setOpcode(ARM::tTRAP); 4381 else if (Subtarget.useNaClTrap()) 4382 MI.setOpcode(ARM::TRAPNaCl); 4383 else 4384 MI.setOpcode(ARM::TRAP); 4385 } 4386 4387 bool ARMBaseInstrInfo::hasNOP() const { 4388 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0; 4389 } 4390 4391 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const { 4392 if (MI->getNumOperands() < 4) 4393 return true; 4394 unsigned ShOpVal = MI->getOperand(3).getImm(); 4395 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal); 4396 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1. 4397 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) || 4398 ((ShImm == 1 || ShImm == 2) && 4399 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl)) 4400 return true; 4401 4402 return false; 4403 } 4404